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-rw-r--r--drivers/ide/pci/aec62xx.c116
-rw-r--r--drivers/ide/pci/alim15x3.c121
-rw-r--r--drivers/ide/pci/amd74xx.c44
-rw-r--r--drivers/ide/pci/atiixp.c24
-rw-r--r--drivers/ide/pci/cmd640.c42
-rw-r--r--drivers/ide/pci/cmd64x.c89
-rw-r--r--drivers/ide/pci/cs5520.c57
-rw-r--r--drivers/ide/pci/cs5530.c28
-rw-r--r--drivers/ide/pci/cs5535.c17
-rw-r--r--drivers/ide/pci/cy82c693.c22
-rw-r--r--drivers/ide/pci/delkin_cb.c2
-rw-r--r--drivers/ide/pci/generic.c167
-rw-r--r--drivers/ide/pci/hpt34x.c56
-rw-r--r--drivers/ide/pci/hpt366.c376
-rw-r--r--drivers/ide/pci/it8213.c18
-rw-r--r--drivers/ide/pci/it821x.c28
-rw-r--r--drivers/ide/pci/jmicron.c14
-rw-r--r--drivers/ide/pci/ns87415.c8
-rw-r--r--drivers/ide/pci/opti621.c34
-rw-r--r--drivers/ide/pci/pdc202xx_new.c201
-rw-r--r--drivers/ide/pci/pdc202xx_old.c145
-rw-r--r--drivers/ide/pci/piix.c173
-rw-r--r--drivers/ide/pci/rz1000.c10
-rw-r--r--drivers/ide/pci/sc1200.c21
-rw-r--r--drivers/ide/pci/scc_pata.c33
-rw-r--r--drivers/ide/pci/serverworks.c95
-rw-r--r--drivers/ide/pci/sgiioc4.c27
-rw-r--r--drivers/ide/pci/siimage.c125
-rw-r--r--drivers/ide/pci/sis5513.c18
-rw-r--r--drivers/ide/pci/sl82c105.c24
-rw-r--r--drivers/ide/pci/slc90e66.c27
-rw-r--r--drivers/ide/pci/tc86c001.c28
-rw-r--r--drivers/ide/pci/triflex.c14
-rw-r--r--drivers/ide/pci/trm290.c13
-rw-r--r--drivers/ide/pci/via82cxxx.c83
35 files changed, 870 insertions, 1430 deletions
diff --git a/drivers/ide/pci/aec62xx.c b/drivers/ide/pci/aec62xx.c
index 3a4c2c26a77e..19ec421f7b9f 100644
--- a/drivers/ide/pci/aec62xx.c
+++ b/drivers/ide/pci/aec62xx.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/aec62xx.c Version 0.25 Aug 1, 2007 2 * linux/drivers/ide/pci/aec62xx.c Version 0.27 Sep 16, 2007
3 * 3 *
4 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> 5 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
@@ -141,19 +141,6 @@ static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio)
141 drive->hwif->set_dma_mode(drive, pio + XFER_PIO_0); 141 drive->hwif->set_dma_mode(drive, pio + XFER_PIO_0);
142} 142}
143 143
144static void aec62xx_dma_lost_irq (ide_drive_t *drive)
145{
146 switch (HWIF(drive)->pci_dev->device) {
147 case PCI_DEVICE_ID_ARTOP_ATP860:
148 case PCI_DEVICE_ID_ARTOP_ATP860R:
149 case PCI_DEVICE_ID_ARTOP_ATP865:
150 case PCI_DEVICE_ID_ARTOP_ATP865R:
151 printk(" AEC62XX time out ");
152 default:
153 break;
154 }
155}
156
157static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name) 144static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
158{ 145{
159 int bus_speed = system_bus_clock(); 146 int bus_speed = system_bus_clock();
@@ -184,34 +171,21 @@ static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const ch
184static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif) 171static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
185{ 172{
186 struct pci_dev *dev = hwif->pci_dev; 173 struct pci_dev *dev = hwif->pci_dev;
187 u8 reg54 = 0, mask = hwif->channel ? 0xf0 : 0x0f;
188 unsigned long flags;
189 174
190 hwif->set_pio_mode = &aec_set_pio_mode; 175 hwif->set_pio_mode = &aec_set_pio_mode;
191 176
192 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) { 177 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
193 if(hwif->mate)
194 hwif->mate->serialized = hwif->serialized = 1;
195 hwif->set_dma_mode = &aec6210_set_mode; 178 hwif->set_dma_mode = &aec6210_set_mode;
196 } else 179 else
197 hwif->set_dma_mode = &aec6260_set_mode; 180 hwif->set_dma_mode = &aec6260_set_mode;
198 181
199 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
200
201 if (hwif->dma_base == 0) 182 if (hwif->dma_base == 0)
202 return; 183 return;
203 184
204 hwif->ultra_mask = hwif->cds->udma_mask; 185 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
205 hwif->mwdma_mask = 0x07; 186 return;
206
207 hwif->dma_lost_irq = &aec62xx_dma_lost_irq;
208 187
209 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) { 188 if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
210 spin_lock_irqsave(&ide_lock, flags);
211 pci_read_config_byte (dev, 0x54, &reg54);
212 pci_write_config_byte(dev, 0x54, (reg54 & ~mask));
213 spin_unlock_irqrestore(&ide_lock, flags);
214 } else if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
215 u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01; 189 u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
216 190
217 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66); 191 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
@@ -220,73 +194,53 @@ static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
220 } 194 }
221} 195}
222 196
223static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d) 197static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
224{
225 return ide_setup_pci_device(dev, d);
226}
227
228static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
229{
230 unsigned long dma_base = pci_resource_start(dev, 4);
231
232 if (inb(dma_base + 2) & 0x10) {
233 d->name = (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R) ?
234 "AEC6880R" : "AEC6880";
235 d->udma_mask = 0x7f; /* udma0-6 */
236 }
237
238 return ide_setup_pci_device(dev, d);
239}
240
241static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
242 { /* 0 */ 198 { /* 0 */
243 .name = "AEC6210", 199 .name = "AEC6210",
244 .init_setup = init_setup_aec62xx,
245 .init_chipset = init_chipset_aec62xx, 200 .init_chipset = init_chipset_aec62xx,
246 .init_hwif = init_hwif_aec62xx, 201 .init_hwif = init_hwif_aec62xx,
247 .autodma = AUTODMA,
248 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 202 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
249 .bootable = OFF_BOARD, 203 .host_flags = IDE_HFLAG_SERIALIZE |
204 IDE_HFLAG_NO_ATAPI_DMA |
205 IDE_HFLAG_OFF_BOARD,
250 .pio_mask = ATA_PIO4, 206 .pio_mask = ATA_PIO4,
251 .udma_mask = 0x07, /* udma0-2 */ 207 .mwdma_mask = ATA_MWDMA2,
208 .udma_mask = ATA_UDMA2,
252 },{ /* 1 */ 209 },{ /* 1 */
253 .name = "AEC6260", 210 .name = "AEC6260",
254 .init_setup = init_setup_aec62xx,
255 .init_chipset = init_chipset_aec62xx, 211 .init_chipset = init_chipset_aec62xx,
256 .init_hwif = init_hwif_aec62xx, 212 .init_hwif = init_hwif_aec62xx,
257 .autodma = NOAUTODMA, 213 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
258 .bootable = OFF_BOARD, 214 IDE_HFLAG_OFF_BOARD,
259 .pio_mask = ATA_PIO4, 215 .pio_mask = ATA_PIO4,
260 .udma_mask = 0x1f, /* udma0-4 */ 216 .mwdma_mask = ATA_MWDMA2,
217 .udma_mask = ATA_UDMA4,
261 },{ /* 2 */ 218 },{ /* 2 */
262 .name = "AEC6260R", 219 .name = "AEC6260R",
263 .init_setup = init_setup_aec62xx,
264 .init_chipset = init_chipset_aec62xx, 220 .init_chipset = init_chipset_aec62xx,
265 .init_hwif = init_hwif_aec62xx, 221 .init_hwif = init_hwif_aec62xx,
266 .autodma = AUTODMA,
267 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 222 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
268 .bootable = NEVER_BOARD, 223 .host_flags = IDE_HFLAG_NO_ATAPI_DMA,
269 .pio_mask = ATA_PIO4, 224 .pio_mask = ATA_PIO4,
270 .udma_mask = 0x1f, /* udma0-4 */ 225 .mwdma_mask = ATA_MWDMA2,
226 .udma_mask = ATA_UDMA4,
271 },{ /* 3 */ 227 },{ /* 3 */
272 .name = "AEC6280", 228 .name = "AEC6280",
273 .init_setup = init_setup_aec6x80,
274 .init_chipset = init_chipset_aec62xx, 229 .init_chipset = init_chipset_aec62xx,
275 .init_hwif = init_hwif_aec62xx, 230 .init_hwif = init_hwif_aec62xx,
276 .autodma = AUTODMA, 231 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
277 .bootable = OFF_BOARD,
278 .pio_mask = ATA_PIO4, 232 .pio_mask = ATA_PIO4,
279 .udma_mask = 0x3f, /* udma0-5 */ 233 .mwdma_mask = ATA_MWDMA2,
234 .udma_mask = ATA_UDMA5,
280 },{ /* 4 */ 235 },{ /* 4 */
281 .name = "AEC6280R", 236 .name = "AEC6280R",
282 .init_setup = init_setup_aec6x80,
283 .init_chipset = init_chipset_aec62xx, 237 .init_chipset = init_chipset_aec62xx,
284 .init_hwif = init_hwif_aec62xx, 238 .init_hwif = init_hwif_aec62xx,
285 .autodma = AUTODMA,
286 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 239 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
287 .bootable = OFF_BOARD, 240 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
288 .pio_mask = ATA_PIO4, 241 .pio_mask = ATA_PIO4,
289 .udma_mask = 0x3f, /* udma0-5 */ 242 .mwdma_mask = ATA_MWDMA2,
243 .udma_mask = ATA_UDMA5,
290 } 244 }
291}; 245};
292 246
@@ -299,14 +253,26 @@ static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
299 * finds a device matching our IDE device tables. 253 * finds a device matching our IDE device tables.
300 * 254 *
301 * NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R] 255 * NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
302 * chips, pass a local copy of 'struct pci_device_id' down the call chain. 256 * chips, pass a local copy of 'struct ide_port_info' down the call chain.
303 */ 257 */
304 258
305static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) 259static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
306{ 260{
307 ide_pci_device_t d = aec62xx_chipsets[id->driver_data]; 261 struct ide_port_info d;
262 u8 idx = id->driver_data;
263
264 d = aec62xx_chipsets[idx];
265
266 if (idx == 3 || idx == 4) {
267 unsigned long dma_base = pci_resource_start(dev, 4);
268
269 if (inb(dma_base + 2) & 0x10) {
270 d.name = (idx == 4) ? "AEC6880R" : "AEC6880";
271 d.udma_mask = ATA_UDMA6;
272 }
273 }
308 274
309 return d.init_setup(dev, &d); 275 return ide_setup_pci_device(dev, &d);
310} 276}
311 277
312static const struct pci_device_id aec62xx_pci_tbl[] = { 278static const struct pci_device_id aec62xx_pci_tbl[] = {
diff --git a/drivers/ide/pci/alim15x3.c b/drivers/ide/pci/alim15x3.c
index 31d4e50647d5..a607dd31a64c 100644
--- a/drivers/ide/pci/alim15x3.c
+++ b/drivers/ide/pci/alim15x3.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/alim15x3.c Version 0.26 Jul 14 2007 2 * linux/drivers/ide/pci/alim15x3.c Version 0.29 Sep 16 2007
3 * 3 *
4 * Copyright (C) 1998-2000 Michel Aubry, Maintainer 4 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer 5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
@@ -492,6 +492,13 @@ static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const c
492 * clear bit 7 492 * clear bit 7
493 */ 493 */
494 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F); 494 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
495 /*
496 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
497 */
498 if (m5229_revision >= 0x20 && isa_dev) {
499 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
500 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
501 }
495 goto out; 502 goto out;
496 } 503 }
497 504
@@ -537,7 +544,30 @@ static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const c
537 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02); 544 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
538 } 545 }
539 } 546 }
547
540out: 548out:
549 /*
550 * CD_ROM DMA on (m5229, 0x53, bit0)
551 * Enable this bit even if we want to use PIO.
552 * PIO FIFO off (m5229, 0x53, bit1)
553 * The hardware will use 0x54h and 0x55h to control PIO FIFO.
554 * (Not on later devices it seems)
555 *
556 * 0x53 changes meaning on later revs - we must no touch
557 * bit 1 on them. Need to check if 0x20 is the right break.
558 */
559 if (m5229_revision >= 0x20) {
560 pci_read_config_byte(dev, 0x53, &tmpbyte);
561
562 if (m5229_revision <= 0x20)
563 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
564 else if (m5229_revision == 0xc7 || m5229_revision == 0xc8)
565 tmpbyte |= 0x03;
566 else
567 tmpbyte |= 0x01;
568
569 pci_write_config_byte(dev, 0x53, tmpbyte);
570 }
541 pci_dev_put(north); 571 pci_dev_put(north);
542 pci_dev_put(isa_dev); 572 pci_dev_put(isa_dev);
543 local_irq_restore(flags); 573 local_irq_restore(flags);
@@ -616,36 +646,8 @@ static u8 __devinit ata66_ali15x3(ide_hwif_t *hwif)
616 if ((tmpbyte & (1 << hwif->channel)) == 0) 646 if ((tmpbyte & (1 << hwif->channel)) == 0)
617 cbl = ATA_CBL_PATA80; 647 cbl = ATA_CBL_PATA80;
618 } 648 }
619 } else {
620 /*
621 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
622 */
623 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
624 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
625 } 649 }
626 650
627 /*
628 * CD_ROM DMA on (m5229, 0x53, bit0)
629 * Enable this bit even if we want to use PIO
630 * PIO FIFO off (m5229, 0x53, bit1)
631 * The hardware will use 0x54h and 0x55h to control PIO FIFO
632 * (Not on later devices it seems)
633 *
634 * 0x53 changes meaning on later revs - we must no touch
635 * bit 1 on them. Need to check if 0x20 is the right break
636 */
637
638 pci_read_config_byte(dev, 0x53, &tmpbyte);
639
640 if(m5229_revision <= 0x20)
641 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
642 else if (m5229_revision == 0xc7 || m5229_revision == 0xc8)
643 tmpbyte |= 0x03;
644 else
645 tmpbyte |= 0x01;
646
647 pci_write_config_byte(dev, 0x53, tmpbyte);
648
649 local_irq_restore(flags); 651 local_irq_restore(flags);
650 652
651 return cbl; 653 return cbl;
@@ -664,35 +666,8 @@ static void __devinit init_hwif_common_ali15x3 (ide_hwif_t *hwif)
664 hwif->set_dma_mode = &ali_set_dma_mode; 666 hwif->set_dma_mode = &ali_set_dma_mode;
665 hwif->udma_filter = &ali_udma_filter; 667 hwif->udma_filter = &ali_udma_filter;
666 668
667 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */ 669 if (hwif->dma_base == 0)
668 hwif->no_lba48_dma = (m5229_revision <= 0xC4) ? 1 : 0;
669
670 if (!hwif->dma_base) {
671 hwif->drives[0].autotune = 1;
672 hwif->drives[1].autotune = 1;
673 return; 670 return;
674 }
675
676 /*
677 * check in ->init_dma guarantees m5229_revision >= 0x20 here
678 */
679
680 if (m5229_revision > 0x20)
681 hwif->atapi_dma = 1;
682
683 if (m5229_revision <= 0x20)
684 hwif->ultra_mask = 0x00; /* no udma */
685 else if (m5229_revision < 0xC2)
686 hwif->ultra_mask = 0x07; /* udma0-2 */
687 else if (m5229_revision == 0xC2 || m5229_revision == 0xC3)
688 hwif->ultra_mask = 0x1f; /* udma0-4 */
689 else if (m5229_revision == 0xC4)
690 hwif->ultra_mask = 0x3f; /* udma0-5 */
691 else
692 hwif->ultra_mask = 0x7f; /* udma0-6 */
693
694 hwif->mwdma_mask = 0x07;
695 hwif->swdma_mask = 0x07;
696 671
697 hwif->dma_setup = &ali15x3_dma_setup; 672 hwif->dma_setup = &ali15x3_dma_setup;
698 673
@@ -771,14 +746,15 @@ static void __devinit init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
771 ide_setup_dma(hwif, dmabase, 8); 746 ide_setup_dma(hwif, dmabase, 8);
772} 747}
773 748
774static ide_pci_device_t ali15x3_chipset __devinitdata = { 749static const struct ide_port_info ali15x3_chipset __devinitdata = {
775 .name = "ALI15X3", 750 .name = "ALI15X3",
776 .init_chipset = init_chipset_ali15x3, 751 .init_chipset = init_chipset_ali15x3,
777 .init_hwif = init_hwif_ali15x3, 752 .init_hwif = init_hwif_ali15x3,
778 .init_dma = init_dma_ali15x3, 753 .init_dma = init_dma_ali15x3,
779 .autodma = AUTODMA, 754 .host_flags = IDE_HFLAG_BOOTABLE,
780 .bootable = ON_BOARD,
781 .pio_mask = ATA_PIO5, 755 .pio_mask = ATA_PIO5,
756 .swdma_mask = ATA_SWDMA2,
757 .mwdma_mask = ATA_MWDMA2,
782}; 758};
783 759
784/** 760/**
@@ -796,15 +772,34 @@ static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_dev
796 { }, 772 { },
797 }; 773 };
798 774
799 ide_pci_device_t *d = &ali15x3_chipset; 775 struct ide_port_info d = ali15x3_chipset;
776 u8 rev = dev->revision;
800 777
801 if (pci_dev_present(ati_rs100)) 778 if (pci_dev_present(ati_rs100))
802 printk(KERN_WARNING "alim15x3: ATI Radeon IGP Northbridge is not yet fully tested.\n"); 779 printk(KERN_WARNING "alim15x3: ATI Radeon IGP Northbridge is not yet fully tested.\n");
803 780
781 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
782 if (rev <= 0xC4)
783 d.host_flags |= IDE_HFLAG_NO_LBA48_DMA;
784
785 if (rev >= 0x20) {
786 if (rev == 0x20)
787 d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
788
789 if (rev < 0xC2)
790 d.udma_mask = ATA_UDMA2;
791 else if (rev == 0xC2 || rev == 0xC3)
792 d.udma_mask = ATA_UDMA4;
793 else if (rev == 0xC4)
794 d.udma_mask = ATA_UDMA5;
795 else
796 d.udma_mask = ATA_UDMA6;
797 }
798
804#if defined(CONFIG_SPARC64) 799#if defined(CONFIG_SPARC64)
805 d->init_hwif = init_hwif_common_ali15x3; 800 d.init_hwif = init_hwif_common_ali15x3;
806#endif /* CONFIG_SPARC64 */ 801#endif /* CONFIG_SPARC64 */
807 return ide_setup_pci_device(dev, d); 802 return ide_setup_pci_device(dev, &d);
808} 803}
809 804
810 805
diff --git a/drivers/ide/pci/amd74xx.c b/drivers/ide/pci/amd74xx.c
index 3bf3d931eea1..8d4125ec252c 100644
--- a/drivers/ide/pci/amd74xx.c
+++ b/drivers/ide/pci/amd74xx.c
@@ -77,7 +77,7 @@ static struct amd_ide_chip {
77}; 77};
78 78
79static struct amd_ide_chip *amd_config; 79static struct amd_ide_chip *amd_config;
80static ide_pci_device_t *amd_chipset; 80static const struct ide_port_info *amd_chipset;
81static unsigned int amd_80w; 81static unsigned int amd_80w;
82static unsigned int amd_clock; 82static unsigned int amd_clock;
83 83
@@ -233,7 +233,6 @@ static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const ch
233 * Print the boot message. 233 * Print the boot message.
234 */ 234 */
235 235
236 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
237 printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n", 236 printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n",
238 amd_chipset->name, pci_name(dev), dev->revision, 237 amd_chipset->name, pci_name(dev), dev->revision,
239 amd_dma[fls(amd_config->udma_mask) - 1]); 238 amd_dma[fls(amd_config->udma_mask) - 1]);
@@ -243,29 +242,18 @@ static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const ch
243 242
244static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif) 243static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
245{ 244{
246 int i;
247
248 if (hwif->irq == 0) /* 0 is bogus but will do for now */ 245 if (hwif->irq == 0) /* 0 is bogus but will do for now */
249 hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel); 246 hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel);
250 247
251 hwif->set_pio_mode = &amd_set_pio_mode; 248 hwif->set_pio_mode = &amd_set_pio_mode;
252 hwif->set_dma_mode = &amd_set_drive; 249 hwif->set_dma_mode = &amd_set_drive;
253 250
254 for (i = 0; i < 2; i++) {
255 hwif->drives[i].io_32bit = 1;
256 hwif->drives[i].unmask = 1;
257 hwif->drives[i].autotune = 1;
258 }
259
260 if (!hwif->dma_base) 251 if (!hwif->dma_base)
261 return; 252 return;
262 253
263 hwif->atapi_dma = 1;
264
265 hwif->ultra_mask = amd_config->udma_mask; 254 hwif->ultra_mask = amd_config->udma_mask;
266 hwif->mwdma_mask = 0x07; 255 if (amd_config->flags & AMD_BAD_SWDMA)
267 if ((amd_config->flags & AMD_BAD_SWDMA) == 0) 256 hwif->swdma_mask = 0x00;
268 hwif->swdma_mask = 0x07;
269 257
270 if (hwif->cbl != ATA_CBL_PATA40_SHORT) { 258 if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
271 if ((amd_80w >> hwif->channel) & 1) 259 if ((amd_80w >> hwif->channel) & 1)
@@ -275,18 +263,24 @@ static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
275 } 263 }
276} 264}
277 265
266#define IDE_HFLAGS_AMD \
267 (IDE_HFLAG_PIO_NO_BLACKLIST | \
268 IDE_HFLAG_PIO_NO_DOWNGRADE | \
269 IDE_HFLAG_POST_SET_MODE | \
270 IDE_HFLAG_IO_32BIT | \
271 IDE_HFLAG_UNMASK_IRQS | \
272 IDE_HFLAG_BOOTABLE)
273
278#define DECLARE_AMD_DEV(name_str) \ 274#define DECLARE_AMD_DEV(name_str) \
279 { \ 275 { \
280 .name = name_str, \ 276 .name = name_str, \
281 .init_chipset = init_chipset_amd74xx, \ 277 .init_chipset = init_chipset_amd74xx, \
282 .init_hwif = init_hwif_amd74xx, \ 278 .init_hwif = init_hwif_amd74xx, \
283 .autodma = AUTODMA, \
284 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \ 279 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
285 .bootable = ON_BOARD, \ 280 .host_flags = IDE_HFLAGS_AMD, \
286 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST \
287 | IDE_HFLAG_PIO_NO_DOWNGRADE \
288 | IDE_HFLAG_POST_SET_MODE, \
289 .pio_mask = ATA_PIO5, \ 281 .pio_mask = ATA_PIO5, \
282 .swdma_mask = ATA_SWDMA2, \
283 .mwdma_mask = ATA_MWDMA2, \
290 } 284 }
291 285
292#define DECLARE_NV_DEV(name_str) \ 286#define DECLARE_NV_DEV(name_str) \
@@ -294,16 +288,14 @@ static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
294 .name = name_str, \ 288 .name = name_str, \
295 .init_chipset = init_chipset_amd74xx, \ 289 .init_chipset = init_chipset_amd74xx, \
296 .init_hwif = init_hwif_amd74xx, \ 290 .init_hwif = init_hwif_amd74xx, \
297 .autodma = AUTODMA, \
298 .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \ 291 .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
299 .bootable = ON_BOARD, \ 292 .host_flags = IDE_HFLAGS_AMD, \
300 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST \
301 | IDE_HFLAG_PIO_NO_DOWNGRADE \
302 | IDE_HFLAG_POST_SET_MODE, \
303 .pio_mask = ATA_PIO5, \ 293 .pio_mask = ATA_PIO5, \
294 .swdma_mask = ATA_SWDMA2, \
295 .mwdma_mask = ATA_MWDMA2, \
304 } 296 }
305 297
306static ide_pci_device_t amd74xx_chipsets[] __devinitdata = { 298static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
307 /* 0 */ DECLARE_AMD_DEV("AMD7401"), 299 /* 0 */ DECLARE_AMD_DEV("AMD7401"),
308 /* 1 */ DECLARE_AMD_DEV("AMD7409"), 300 /* 1 */ DECLARE_AMD_DEV("AMD7409"),
309 /* 2 */ DECLARE_AMD_DEV("AMD7411"), 301 /* 2 */ DECLARE_AMD_DEV("AMD7411"),
diff --git a/drivers/ide/pci/atiixp.c b/drivers/ide/pci/atiixp.c
index 446900da1329..ef8e0164ef7a 100644
--- a/drivers/ide/pci/atiixp.c
+++ b/drivers/ide/pci/atiixp.c
@@ -172,21 +172,12 @@ static void __devinit init_hwif_atiixp(ide_hwif_t *hwif)
172 u8 ch = hwif->channel; 172 u8 ch = hwif->channel;
173 struct pci_dev *pdev = hwif->pci_dev; 173 struct pci_dev *pdev = hwif->pci_dev;
174 174
175 if (!hwif->irq)
176 hwif->irq = ch ? 15 : 14;
177
178 hwif->set_pio_mode = &atiixp_set_pio_mode; 175 hwif->set_pio_mode = &atiixp_set_pio_mode;
179 hwif->set_dma_mode = &atiixp_set_dma_mode; 176 hwif->set_dma_mode = &atiixp_set_dma_mode;
180 hwif->drives[0].autotune = 1;
181 hwif->drives[1].autotune = 1;
182 177
183 if (!hwif->dma_base) 178 if (!hwif->dma_base)
184 return; 179 return;
185 180
186 hwif->atapi_dma = 1;
187 hwif->ultra_mask = 0x3f;
188 hwif->mwdma_mask = 0x07;
189
190 pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode); 181 pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
191 182
192 if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40) 183 if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
@@ -198,23 +189,24 @@ static void __devinit init_hwif_atiixp(ide_hwif_t *hwif)
198 hwif->dma_host_off = &atiixp_dma_host_off; 189 hwif->dma_host_off = &atiixp_dma_host_off;
199} 190}
200 191
201 192static const struct ide_port_info atiixp_pci_info[] __devinitdata = {
202static ide_pci_device_t atiixp_pci_info[] __devinitdata = {
203 { /* 0 */ 193 { /* 0 */
204 .name = "ATIIXP", 194 .name = "ATIIXP",
205 .init_hwif = init_hwif_atiixp, 195 .init_hwif = init_hwif_atiixp,
206 .autodma = AUTODMA,
207 .enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}}, 196 .enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
208 .bootable = ON_BOARD, 197 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
209 .pio_mask = ATA_PIO4, 198 .pio_mask = ATA_PIO4,
199 .mwdma_mask = ATA_MWDMA2,
200 .udma_mask = ATA_UDMA5,
210 },{ /* 1 */ 201 },{ /* 1 */
211 .name = "SB600_PATA", 202 .name = "SB600_PATA",
212 .init_hwif = init_hwif_atiixp, 203 .init_hwif = init_hwif_atiixp,
213 .autodma = AUTODMA,
214 .enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}}, 204 .enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
215 .bootable = ON_BOARD, 205 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_LEGACY_IRQS |
216 .host_flags = IDE_HFLAG_SINGLE, 206 IDE_HFLAG_BOOTABLE,
217 .pio_mask = ATA_PIO4, 207 .pio_mask = ATA_PIO4,
208 .mwdma_mask = ATA_MWDMA2,
209 .udma_mask = ATA_UDMA5,
218 }, 210 },
219}; 211};
220 212
diff --git a/drivers/ide/pci/cmd640.c b/drivers/ide/pci/cmd640.c
index f369645e4d16..4aa48104e0c1 100644
--- a/drivers/ide/pci/cmd640.c
+++ b/drivers/ide/pci/cmd640.c
@@ -185,6 +185,8 @@ static u8 recovery_counts[4] = {16, 16, 16, 16}; /* Recovery count (encoded) */
185 185
186#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */ 186#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
187 187
188static DEFINE_SPINLOCK(cmd640_lock);
189
188/* 190/*
189 * These are initialized to point at the devices we control 191 * These are initialized to point at the devices we control
190 */ 192 */
@@ -258,12 +260,12 @@ static u8 get_cmd640_reg_vlb (u16 reg)
258 260
259static u8 get_cmd640_reg(u16 reg) 261static u8 get_cmd640_reg(u16 reg)
260{ 262{
261 u8 b;
262 unsigned long flags; 263 unsigned long flags;
264 u8 b;
263 265
264 spin_lock_irqsave(&ide_lock, flags); 266 spin_lock_irqsave(&cmd640_lock, flags);
265 b = __get_cmd640_reg(reg); 267 b = __get_cmd640_reg(reg);
266 spin_unlock_irqrestore(&ide_lock, flags); 268 spin_unlock_irqrestore(&cmd640_lock, flags);
267 return b; 269 return b;
268} 270}
269 271
@@ -271,9 +273,9 @@ static void put_cmd640_reg(u16 reg, u8 val)
271{ 273{
272 unsigned long flags; 274 unsigned long flags;
273 275
274 spin_lock_irqsave(&ide_lock, flags); 276 spin_lock_irqsave(&cmd640_lock, flags);
275 __put_cmd640_reg(reg,val); 277 __put_cmd640_reg(reg,val);
276 spin_unlock_irqrestore(&ide_lock, flags); 278 spin_unlock_irqrestore(&cmd640_lock, flags);
277} 279}
278 280
279static int __init match_pci_cmd640_device (void) 281static int __init match_pci_cmd640_device (void)
@@ -351,7 +353,7 @@ static int __init secondary_port_responding (void)
351{ 353{
352 unsigned long flags; 354 unsigned long flags;
353 355
354 spin_lock_irqsave(&ide_lock, flags); 356 spin_lock_irqsave(&cmd640_lock, flags);
355 357
356 outb_p(0x0a, 0x170 + IDE_SELECT_OFFSET); /* select drive0 */ 358 outb_p(0x0a, 0x170 + IDE_SELECT_OFFSET); /* select drive0 */
357 udelay(100); 359 udelay(100);
@@ -359,11 +361,11 @@ static int __init secondary_port_responding (void)
359 outb_p(0x1a, 0x170 + IDE_SELECT_OFFSET); /* select drive1 */ 361 outb_p(0x1a, 0x170 + IDE_SELECT_OFFSET); /* select drive1 */
360 udelay(100); 362 udelay(100);
361 if ((inb_p(0x170 + IDE_SELECT_OFFSET) & 0x1f) != 0x1a) { 363 if ((inb_p(0x170 + IDE_SELECT_OFFSET) & 0x1f) != 0x1a) {
362 spin_unlock_irqrestore(&ide_lock, flags); 364 spin_unlock_irqrestore(&cmd640_lock, flags);
363 return 0; /* nothing responded */ 365 return 0; /* nothing responded */
364 } 366 }
365 } 367 }
366 spin_unlock_irqrestore(&ide_lock, flags); 368 spin_unlock_irqrestore(&cmd640_lock, flags);
367 return 1; /* success */ 369 return 1; /* success */
368} 370}
369 371
@@ -440,11 +442,11 @@ static void __init setup_device_ptrs (void)
440static void set_prefetch_mode (unsigned int index, int mode) 442static void set_prefetch_mode (unsigned int index, int mode)
441{ 443{
442 ide_drive_t *drive = cmd_drives[index]; 444 ide_drive_t *drive = cmd_drives[index];
445 unsigned long flags;
443 int reg = prefetch_regs[index]; 446 int reg = prefetch_regs[index];
444 u8 b; 447 u8 b;
445 unsigned long flags;
446 448
447 spin_lock_irqsave(&ide_lock, flags); 449 spin_lock_irqsave(&cmd640_lock, flags);
448 b = __get_cmd640_reg(reg); 450 b = __get_cmd640_reg(reg);
449 if (mode) { /* want prefetch on? */ 451 if (mode) { /* want prefetch on? */
450#if CMD640_PREFETCH_MASKS 452#if CMD640_PREFETCH_MASKS
@@ -460,7 +462,7 @@ static void set_prefetch_mode (unsigned int index, int mode)
460 b |= prefetch_masks[index]; /* disable prefetch */ 462 b |= prefetch_masks[index]; /* disable prefetch */
461 } 463 }
462 __put_cmd640_reg(reg, b); 464 __put_cmd640_reg(reg, b);
463 spin_unlock_irqrestore(&ide_lock, flags); 465 spin_unlock_irqrestore(&cmd640_lock, flags);
464} 466}
465 467
466/* 468/*
@@ -561,7 +563,7 @@ static void program_drive_counts (unsigned int index)
561 /* 563 /*
562 * Now that everything is ready, program the new timings 564 * Now that everything is ready, program the new timings
563 */ 565 */
564 spin_lock_irqsave(&ide_lock, flags); 566 spin_lock_irqsave(&cmd640_lock, flags);
565 /* 567 /*
566 * Program the address_setup clocks into ARTTIM reg, 568 * Program the address_setup clocks into ARTTIM reg,
567 * and then the active/recovery counts into the DRWTIM reg 569 * and then the active/recovery counts into the DRWTIM reg
@@ -570,7 +572,7 @@ static void program_drive_counts (unsigned int index)
570 setup_count |= __get_cmd640_reg(arttim_regs[index]) & 0x3f; 572 setup_count |= __get_cmd640_reg(arttim_regs[index]) & 0x3f;
571 __put_cmd640_reg(arttim_regs[index], setup_count); 573 __put_cmd640_reg(arttim_regs[index], setup_count);
572 __put_cmd640_reg(drwtim_regs[index], pack_nibbles(active_count, recovery_count)); 574 __put_cmd640_reg(drwtim_regs[index], pack_nibbles(active_count, recovery_count));
573 spin_unlock_irqrestore(&ide_lock, flags); 575 spin_unlock_irqrestore(&cmd640_lock, flags);
574} 576}
575 577
576/* 578/*
@@ -670,20 +672,20 @@ static void cmd640_set_pio_mode(ide_drive_t *drive, const u8 pio)
670 672
671static int pci_conf1(void) 673static int pci_conf1(void)
672{ 674{
673 u32 tmp;
674 unsigned long flags; 675 unsigned long flags;
676 u32 tmp;
675 677
676 spin_lock_irqsave(&ide_lock, flags); 678 spin_lock_irqsave(&cmd640_lock, flags);
677 outb(0x01, 0xCFB); 679 outb(0x01, 0xCFB);
678 tmp = inl(0xCF8); 680 tmp = inl(0xCF8);
679 outl(0x80000000, 0xCF8); 681 outl(0x80000000, 0xCF8);
680 if (inl(0xCF8) == 0x80000000) { 682 if (inl(0xCF8) == 0x80000000) {
681 outl(tmp, 0xCF8); 683 outl(tmp, 0xCF8);
682 spin_unlock_irqrestore(&ide_lock, flags); 684 spin_unlock_irqrestore(&cmd640_lock, flags);
683 return 1; 685 return 1;
684 } 686 }
685 outl(tmp, 0xCF8); 687 outl(tmp, 0xCF8);
686 spin_unlock_irqrestore(&ide_lock, flags); 688 spin_unlock_irqrestore(&cmd640_lock, flags);
687 return 0; 689 return 0;
688} 690}
689 691
@@ -691,15 +693,15 @@ static int pci_conf2(void)
691{ 693{
692 unsigned long flags; 694 unsigned long flags;
693 695
694 spin_lock_irqsave(&ide_lock, flags); 696 spin_lock_irqsave(&cmd640_lock, flags);
695 outb(0x00, 0xCFB); 697 outb(0x00, 0xCFB);
696 outb(0x00, 0xCF8); 698 outb(0x00, 0xCF8);
697 outb(0x00, 0xCFA); 699 outb(0x00, 0xCFA);
698 if (inb(0xCF8) == 0x00 && inb(0xCF8) == 0x00) { 700 if (inb(0xCF8) == 0x00 && inb(0xCF8) == 0x00) {
699 spin_unlock_irqrestore(&ide_lock, flags); 701 spin_unlock_irqrestore(&cmd640_lock, flags);
700 return 1; 702 return 1;
701 } 703 }
702 spin_unlock_irqrestore(&ide_lock, flags); 704 spin_unlock_irqrestore(&cmd640_lock, flags);
703 return 0; 705 return 0;
704} 706}
705 707
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c
index f3d3bde8daba..ea0143ef5fe5 100644
--- a/drivers/ide/pci/cmd64x.c
+++ b/drivers/ide/pci/cmd64x.c
@@ -439,11 +439,8 @@ static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const cha
439 u8 mrdmode = 0; 439 u8 mrdmode = 0;
440 440
441 if (dev->device == PCI_DEVICE_ID_CMD_646) { 441 if (dev->device == PCI_DEVICE_ID_CMD_646) {
442 u8 rev = 0;
443 442
444 pci_read_config_byte(dev, PCI_REVISION_ID, &rev); 443 switch (dev->revision) {
445
446 switch (rev) {
447 case 0x07: 444 case 0x07:
448 case 0x05: 445 case 0x05:
449 printk("%s: UltraDMA capable\n", name); 446 printk("%s: UltraDMA capable\n", name);
@@ -505,22 +502,13 @@ static u8 __devinit ata66_cmd64x(ide_hwif_t *hwif)
505static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif) 502static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
506{ 503{
507 struct pci_dev *dev = hwif->pci_dev; 504 struct pci_dev *dev = hwif->pci_dev;
508 u8 rev = 0;
509
510 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
511 505
512 hwif->set_pio_mode = &cmd64x_set_pio_mode; 506 hwif->set_pio_mode = &cmd64x_set_pio_mode;
513 hwif->set_dma_mode = &cmd64x_set_dma_mode; 507 hwif->set_dma_mode = &cmd64x_set_dma_mode;
514 508
515 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
516
517 if (!hwif->dma_base) 509 if (!hwif->dma_base)
518 return; 510 return;
519 511
520 hwif->atapi_dma = 1;
521 hwif->mwdma_mask = 0x07;
522 hwif->ultra_mask = hwif->cds->udma_mask;
523
524 /* 512 /*
525 * UltraDMA only supported on PCI646U and PCI646U2, which 513 * UltraDMA only supported on PCI646U and PCI646U2, which
526 * correspond to revisions 0x03, 0x05 and 0x07 respectively. 514 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
@@ -533,7 +521,7 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
533 * 521 *
534 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets. 522 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
535 */ 523 */
536 if (dev->device == PCI_DEVICE_ID_CMD_646 && rev < 5) 524 if (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 5)
537 hwif->ultra_mask = 0x00; 525 hwif->ultra_mask = 0x00;
538 526
539 if (hwif->cbl != ATA_CBL_PATA40_SHORT) 527 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
@@ -547,11 +535,10 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
547 hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq; 535 hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq;
548 break; 536 break;
549 case PCI_DEVICE_ID_CMD_646: 537 case PCI_DEVICE_ID_CMD_646:
550 hwif->chipset = ide_cmd646; 538 if (dev->revision == 0x01) {
551 if (rev == 0x01) {
552 hwif->ide_dma_end = &cmd646_1_ide_dma_end; 539 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
553 break; 540 break;
554 } else if (rev >= 0x03) 541 } else if (dev->revision >= 0x03)
555 goto alt_irq_bits; 542 goto alt_irq_bits;
556 /* fall thru */ 543 /* fall thru */
557 default: 544 default:
@@ -561,80 +548,62 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
561 } 548 }
562} 549}
563 550
564static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d) 551static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
565{
566 return ide_setup_pci_device(dev, d);
567}
568
569static int __devinit init_setup_cmd646(struct pci_dev *dev, ide_pci_device_t *d)
570{
571 /*
572 * The original PCI0646 didn't have the primary channel enable bit,
573 * it appeared starting with PCI0646U (i.e. revision ID 3).
574 */
575 if (dev->revision < 3)
576 d->enablebits[0].reg = 0;
577
578 return ide_setup_pci_device(dev, d);
579}
580
581static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
582 { /* 0 */ 552 { /* 0 */
583 .name = "CMD643", 553 .name = "CMD643",
584 .init_setup = init_setup_cmd64x,
585 .init_chipset = init_chipset_cmd64x, 554 .init_chipset = init_chipset_cmd64x,
586 .init_hwif = init_hwif_cmd64x, 555 .init_hwif = init_hwif_cmd64x,
587 .autodma = AUTODMA,
588 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}}, 556 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
589 .bootable = ON_BOARD, 557 .host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
590 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
591 .pio_mask = ATA_PIO5, 558 .pio_mask = ATA_PIO5,
559 .mwdma_mask = ATA_MWDMA2,
592 .udma_mask = 0x00, /* no udma */ 560 .udma_mask = 0x00, /* no udma */
593 },{ /* 1 */ 561 },{ /* 1 */
594 .name = "CMD646", 562 .name = "CMD646",
595 .init_setup = init_setup_cmd646,
596 .init_chipset = init_chipset_cmd64x, 563 .init_chipset = init_chipset_cmd64x,
597 .init_hwif = init_hwif_cmd64x, 564 .init_hwif = init_hwif_cmd64x,
598 .autodma = AUTODMA,
599 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, 565 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
600 .bootable = ON_BOARD, 566 .host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
601 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
602 .pio_mask = ATA_PIO5, 567 .pio_mask = ATA_PIO5,
603 .udma_mask = 0x07, /* udma0-2 */ 568 .mwdma_mask = ATA_MWDMA2,
569 .udma_mask = ATA_UDMA2,
604 },{ /* 2 */ 570 },{ /* 2 */
605 .name = "CMD648", 571 .name = "CMD648",
606 .init_setup = init_setup_cmd64x,
607 .init_chipset = init_chipset_cmd64x, 572 .init_chipset = init_chipset_cmd64x,
608 .init_hwif = init_hwif_cmd64x, 573 .init_hwif = init_hwif_cmd64x,
609 .autodma = AUTODMA,
610 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, 574 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
611 .bootable = ON_BOARD, 575 .chipset = ide_cmd646,
612 .host_flags = IDE_HFLAG_ABUSE_PREFETCH, 576 .host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
613 .pio_mask = ATA_PIO5, 577 .pio_mask = ATA_PIO5,
614 .udma_mask = 0x1f, /* udma0-4 */ 578 .mwdma_mask = ATA_MWDMA2,
579 .udma_mask = ATA_UDMA4,
615 },{ /* 3 */ 580 },{ /* 3 */
616 .name = "CMD649", 581 .name = "CMD649",
617 .init_setup = init_setup_cmd64x,
618 .init_chipset = init_chipset_cmd64x, 582 .init_chipset = init_chipset_cmd64x,
619 .init_hwif = init_hwif_cmd64x, 583 .init_hwif = init_hwif_cmd64x,
620 .autodma = AUTODMA,
621 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, 584 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
622 .bootable = ON_BOARD, 585 .host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
623 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
624 .pio_mask = ATA_PIO5, 586 .pio_mask = ATA_PIO5,
625 .udma_mask = 0x3f, /* udma0-5 */ 587 .mwdma_mask = ATA_MWDMA2,
588 .udma_mask = ATA_UDMA5,
626 } 589 }
627}; 590};
628 591
629/*
630 * We may have to modify enablebits for PCI0646, so we'd better pass
631 * a local copy of the ide_pci_device_t structure down the call chain...
632 */
633static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id) 592static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
634{ 593{
635 ide_pci_device_t d = cmd64x_chipsets[id->driver_data]; 594 struct ide_port_info d;
595 u8 idx = id->driver_data;
596
597 d = cmd64x_chipsets[idx];
598
599 /*
600 * The original PCI0646 didn't have the primary channel enable bit,
601 * it appeared starting with PCI0646U (i.e. revision ID 3).
602 */
603 if (idx == 1 && dev->revision < 3)
604 d.enablebits[0].reg = 0;
636 605
637 return d.init_setup(dev, &d); 606 return ide_setup_pci_device(dev, &d);
638} 607}
639 608
640static const struct pci_device_id cmd64x_pci_tbl[] = { 609static const struct pci_device_id cmd64x_pci_tbl[] = {
diff --git a/drivers/ide/pci/cs5520.c b/drivers/ide/pci/cs5520.c
index a8bf4940ca9c..0466462fd21b 100644
--- a/drivers/ide/pci/cs5520.c
+++ b/drivers/ide/pci/cs5520.c
@@ -106,18 +106,6 @@ static void cs5520_set_dma_mode(ide_drive_t *drive, const u8 speed)
106} 106}
107 107
108/* 108/*
109 * We provide a callback for our nonstandard DMA location
110 */
111
112static void __devinit cs5520_init_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
113{
114 unsigned long bmide = pci_resource_start(dev, 2); /* Not the usual 4 */
115 if(hwif->mate && hwif->mate->dma_base) /* Second channel at primary + 8 */
116 bmide += 8;
117 ide_setup_dma(hwif, bmide, 8);
118}
119
120/*
121 * We wrap the DMA activate to set the vdma flag. This is needed 109 * We wrap the DMA activate to set the vdma flag. This is needed
122 * so that the IDE DMA layer issues PIO not DMA commands over the 110 * so that the IDE DMA layer issues PIO not DMA commands over the
123 * DMA channel 111 * DMA channel
@@ -125,6 +113,7 @@ static void __devinit cs5520_init_setup_dma(struct pci_dev *dev, ide_pci_device_
125 113
126static int cs5520_dma_on(ide_drive_t *drive) 114static int cs5520_dma_on(ide_drive_t *drive)
127{ 115{
116 /* ATAPI is harder so leave it for now */
128 drive->vdma = 1; 117 drive->vdma = 1;
129 return 0; 118 return 0;
130} 119}
@@ -134,33 +123,25 @@ static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
134 hwif->set_pio_mode = &cs5520_set_pio_mode; 123 hwif->set_pio_mode = &cs5520_set_pio_mode;
135 hwif->set_dma_mode = &cs5520_set_dma_mode; 124 hwif->set_dma_mode = &cs5520_set_dma_mode;
136 125
137 if (hwif->dma_base == 0) { 126 if (hwif->dma_base == 0)
138 hwif->drives[1].autotune = hwif->drives[0].autotune = 1;
139 return; 127 return;
140 }
141 128
142 hwif->ide_dma_on = &cs5520_dma_on; 129 hwif->ide_dma_on = &cs5520_dma_on;
143
144 /* ATAPI is harder so leave it for now */
145 hwif->atapi_dma = 0;
146 hwif->ultra_mask = 0;
147 hwif->swdma_mask = 0;
148 hwif->mwdma_mask = 0;
149} 130}
150 131
151#define DECLARE_CS_DEV(name_str) \ 132#define DECLARE_CS_DEV(name_str) \
152 { \ 133 { \
153 .name = name_str, \ 134 .name = name_str, \
154 .init_setup_dma = cs5520_init_setup_dma, \
155 .init_hwif = init_hwif_cs5520, \ 135 .init_hwif = init_hwif_cs5520, \
156 .autodma = AUTODMA, \
157 .bootable = ON_BOARD, \
158 .host_flags = IDE_HFLAG_ISA_PORTS | \ 136 .host_flags = IDE_HFLAG_ISA_PORTS | \
159 IDE_HFLAG_VDMA, \ 137 IDE_HFLAG_CS5520 | \
138 IDE_HFLAG_VDMA | \
139 IDE_HFLAG_NO_ATAPI_DMA | \
140 IDE_HFLAG_BOOTABLE, \
160 .pio_mask = ATA_PIO4, \ 141 .pio_mask = ATA_PIO4, \
161 } 142 }
162 143
163static ide_pci_device_t cyrix_chipsets[] __devinitdata = { 144static const struct ide_port_info cyrix_chipsets[] __devinitdata = {
164 /* 0 */ DECLARE_CS_DEV("Cyrix 5510"), 145 /* 0 */ DECLARE_CS_DEV("Cyrix 5510"),
165 /* 1 */ DECLARE_CS_DEV("Cyrix 5520") 146 /* 1 */ DECLARE_CS_DEV("Cyrix 5520")
166}; 147};
@@ -173,9 +154,8 @@ static ide_pci_device_t cyrix_chipsets[] __devinitdata = {
173 154
174static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id) 155static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
175{ 156{
176 ide_hwif_t *hwif = NULL, *mate = NULL; 157 const struct ide_port_info *d = &cyrix_chipsets[id->driver_data];
177 ata_index_t index; 158 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
178 ide_pci_device_t *d = &cyrix_chipsets[id->driver_data];
179 159
180 ide_setup_pci_noise(dev, d); 160 ide_setup_pci_noise(dev, d);
181 161
@@ -191,29 +171,14 @@ static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_devic
191 return -ENODEV; 171 return -ENODEV;
192 } 172 }
193 173
194 index.all = 0xf0f0;
195
196 /* 174 /*
197 * Now the chipset is configured we can let the core 175 * Now the chipset is configured we can let the core
198 * do all the device setup for us 176 * do all the device setup for us
199 */ 177 */
200 178
201 ide_pci_setup_ports(dev, d, 14, &index); 179 ide_pci_setup_ports(dev, d, 14, &idx[0]);
202
203 if ((index.b.low & 0xf0) != 0xf0)
204 hwif = &ide_hwifs[index.b.low];
205 if ((index.b.high & 0xf0) != 0xf0)
206 mate = &ide_hwifs[index.b.high];
207
208 if (hwif)
209 probe_hwif_init(hwif);
210 if (mate)
211 probe_hwif_init(mate);
212 180
213 if (hwif) 181 ide_device_add(idx);
214 ide_proc_register_port(hwif);
215 if (mate)
216 ide_proc_register_port(mate);
217 182
218 return 0; 183 return 0;
219} 184}
diff --git a/drivers/ide/pci/cs5530.c b/drivers/ide/pci/cs5530.c
index 0d23b8aabe9c..599408952bd4 100644
--- a/drivers/ide/pci/cs5530.c
+++ b/drivers/ide/pci/cs5530.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/cs5530.c Version 0.76 Aug 3 2007 2 * linux/drivers/ide/pci/cs5530.c Version 0.77 Sep 24 2007
3 * 3 *
4 * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2000 Mark Lord <mlord@pobox.com> 5 * Copyright (C) 2000 Mark Lord <mlord@pobox.com>
@@ -146,7 +146,6 @@ static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
146static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const char *name) 146static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const char *name)
147{ 147{
148 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL; 148 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
149 unsigned long flags;
150 149
151 if (pci_resource_start(dev, 4) == 0) 150 if (pci_resource_start(dev, 4) == 0)
152 return -EFAULT; 151 return -EFAULT;
@@ -171,9 +170,6 @@ static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const ch
171 goto out; 170 goto out;
172 } 171 }
173 172
174 spin_lock_irqsave(&ide_lock, flags);
175 /* all CPUs (there should only be one CPU with this chipset) */
176
177 /* 173 /*
178 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530: 174 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
179 * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530 175 * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
@@ -224,8 +220,6 @@ static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const ch
224 pci_write_config_byte(master_0, 0x42, 0x00); 220 pci_write_config_byte(master_0, 0x42, 0x00);
225 pci_write_config_byte(master_0, 0x43, 0xc1); 221 pci_write_config_byte(master_0, 0x43, 0xc1);
226 222
227 spin_unlock_irqrestore(&ide_lock, flags);
228
229out: 223out:
230 pci_dev_put(master_0); 224 pci_dev_put(master_0);
231 pci_dev_put(cs5530_0); 225 pci_dev_put(cs5530_0);
@@ -245,9 +239,6 @@ static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
245 unsigned long basereg; 239 unsigned long basereg;
246 u32 d0_timings; 240 u32 d0_timings;
247 241
248 if (hwif->mate)
249 hwif->serialized = hwif->mate->serialized = 1;
250
251 hwif->set_pio_mode = &cs5530_set_pio_mode; 242 hwif->set_pio_mode = &cs5530_set_pio_mode;
252 hwif->set_dma_mode = &cs5530_set_dma_mode; 243 hwif->set_dma_mode = &cs5530_set_dma_mode;
253 244
@@ -258,27 +249,22 @@ static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
258 if (CS5530_BAD_PIO(inl(basereg + 8))) 249 if (CS5530_BAD_PIO(inl(basereg + 8)))
259 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8); 250 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
260 251
261 hwif->drives[0].autotune = 1;
262 hwif->drives[1].autotune = 1;
263
264 if (hwif->dma_base == 0) 252 if (hwif->dma_base == 0)
265 return; 253 return;
266 254
267 hwif->atapi_dma = 1;
268 hwif->ultra_mask = 0x07;
269 hwif->mwdma_mask = 0x07;
270
271 hwif->udma_filter = cs5530_udma_filter; 255 hwif->udma_filter = cs5530_udma_filter;
272} 256}
273 257
274static ide_pci_device_t cs5530_chipset __devinitdata = { 258static const struct ide_port_info cs5530_chipset __devinitdata = {
275 .name = "CS5530", 259 .name = "CS5530",
276 .init_chipset = init_chipset_cs5530, 260 .init_chipset = init_chipset_cs5530,
277 .init_hwif = init_hwif_cs5530, 261 .init_hwif = init_hwif_cs5530,
278 .autodma = AUTODMA, 262 .host_flags = IDE_HFLAG_SERIALIZE |
279 .bootable = ON_BOARD, 263 IDE_HFLAG_POST_SET_MODE |
264 IDE_HFLAG_BOOTABLE,
280 .pio_mask = ATA_PIO4, 265 .pio_mask = ATA_PIO4,
281 .host_flags = IDE_HFLAG_POST_SET_MODE, 266 .mwdma_mask = ATA_MWDMA2,
267 .udma_mask = ATA_UDMA2,
282}; 268};
283 269
284static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id) 270static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
diff --git a/drivers/ide/pci/cs5535.c b/drivers/ide/pci/cs5535.c
index e4891a16afef..9094916e3780 100644
--- a/drivers/ide/pci/cs5535.c
+++ b/drivers/ide/pci/cs5535.c
@@ -84,7 +84,7 @@ static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
84 84
85 /* Set the PIO timings */ 85 /* Set the PIO timings */
86 if ((speed & XFER_MODE) == XFER_PIO) { 86 if ((speed & XFER_MODE) == XFER_PIO) {
87 ide_drive_t *pair = &drive->hwif->drives[drive->dn ^ 1]; 87 ide_drive_t *pair = ide_get_paired_drive(drive);
88 u8 cmd, pioa; 88 u8 cmd, pioa;
89 89
90 cmd = pioa = speed - XFER_PIO_0; 90 cmd = pioa = speed - XFER_PIO_0;
@@ -180,25 +180,20 @@ static void __devinit init_hwif_cs5535(ide_hwif_t *hwif)
180 hwif->set_pio_mode = &cs5535_set_pio_mode; 180 hwif->set_pio_mode = &cs5535_set_pio_mode;
181 hwif->set_dma_mode = &cs5535_set_dma_mode; 181 hwif->set_dma_mode = &cs5535_set_dma_mode;
182 182
183 hwif->drives[1].autotune = hwif->drives[0].autotune = 1;
184
185 if (hwif->dma_base == 0) 183 if (hwif->dma_base == 0)
186 return; 184 return;
187 185
188 hwif->atapi_dma = 1;
189 hwif->ultra_mask = 0x1F;
190 hwif->mwdma_mask = 0x07;
191
192 hwif->cbl = cs5535_cable_detect(hwif->pci_dev); 186 hwif->cbl = cs5535_cable_detect(hwif->pci_dev);
193} 187}
194 188
195static ide_pci_device_t cs5535_chipset __devinitdata = { 189static const struct ide_port_info cs5535_chipset __devinitdata = {
196 .name = "CS5535", 190 .name = "CS5535",
197 .init_hwif = init_hwif_cs5535, 191 .init_hwif = init_hwif_cs5535,
198 .autodma = AUTODMA, 192 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE |
199 .bootable = ON_BOARD, 193 IDE_HFLAG_BOOTABLE,
200 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE,
201 .pio_mask = ATA_PIO4, 194 .pio_mask = ATA_PIO4,
195 .mwdma_mask = ATA_MWDMA2,
196 .udma_mask = ATA_UDMA4,
202}; 197};
203 198
204static int __devinit cs5535_init_one(struct pci_dev *dev, 199static int __devinit cs5535_init_one(struct pci_dev *dev,
diff --git a/drivers/ide/pci/cy82c693.c b/drivers/ide/pci/cy82c693.c
index c498ecfd7fcb..3ef4fc10fe2c 100644
--- a/drivers/ide/pci/cy82c693.c
+++ b/drivers/ide/pci/cy82c693.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/cy82c693.c Version 0.40 Sep. 10, 2002 2 * linux/drivers/ide/pci/cy82c693.c Version 0.41 Aug 27, 2007
3 * 3 *
4 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer 4 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
5 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator 5 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
@@ -428,18 +428,10 @@ static unsigned int __devinit init_chipset_cy82c693(struct pci_dev *dev, const c
428 */ 428 */
429static void __devinit init_hwif_cy82c693(ide_hwif_t *hwif) 429static void __devinit init_hwif_cy82c693(ide_hwif_t *hwif)
430{ 430{
431 hwif->chipset = ide_cy82c693;
432 hwif->set_pio_mode = &cy82c693_set_pio_mode; 431 hwif->set_pio_mode = &cy82c693_set_pio_mode;
433 432
434 if (!hwif->dma_base) { 433 if (hwif->dma_base == 0)
435 hwif->drives[0].autotune = 1;
436 hwif->drives[1].autotune = 1;
437 return; 434 return;
438 }
439
440 hwif->atapi_dma = 1;
441 hwif->mwdma_mask = 0x04;
442 hwif->swdma_mask = 0x04;
443 435
444 hwif->ide_dma_on = &cy82c693_ide_dma_on; 436 hwif->ide_dma_on = &cy82c693_ide_dma_on;
445} 437}
@@ -456,15 +448,17 @@ static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
456 } 448 }
457} 449}
458 450
459static ide_pci_device_t cy82c693_chipset __devinitdata = { 451static const struct ide_port_info cy82c693_chipset __devinitdata = {
460 .name = "CY82C693", 452 .name = "CY82C693",
461 .init_chipset = init_chipset_cy82c693, 453 .init_chipset = init_chipset_cy82c693,
462 .init_iops = init_iops_cy82c693, 454 .init_iops = init_iops_cy82c693,
463 .init_hwif = init_hwif_cy82c693, 455 .init_hwif = init_hwif_cy82c693,
464 .autodma = AUTODMA, 456 .chipset = ide_cy82c693,
465 .bootable = ON_BOARD, 457 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_TRUST_BIOS_FOR_DMA |
466 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_TRUST_BIOS_FOR_DMA, 458 IDE_HFLAG_BOOTABLE,
467 .pio_mask = ATA_PIO4, 459 .pio_mask = ATA_PIO4,
460 .swdma_mask = ATA_SWDMA2_ONLY,
461 .mwdma_mask = ATA_MWDMA2_ONLY,
468}; 462};
469 463
470static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id) 464static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
diff --git a/drivers/ide/pci/delkin_cb.c b/drivers/ide/pci/delkin_cb.c
index 46f4a888c037..83829081640a 100644
--- a/drivers/ide/pci/delkin_cb.c
+++ b/drivers/ide/pci/delkin_cb.c
@@ -80,7 +80,7 @@ delkin_cb_probe (struct pci_dev *dev, const struct pci_device_id *id)
80 hw.irq = dev->irq; 80 hw.irq = dev->irq;
81 hw.chipset = ide_pci; /* this enables IRQ sharing */ 81 hw.chipset = ide_pci; /* this enables IRQ sharing */
82 82
83 rc = ide_register_hw_with_fixup(&hw, 0, &hwif, ide_undecoded_slave); 83 rc = ide_register_hw(&hw, &ide_undecoded_slave, 0, &hwif);
84 if (rc < 0) { 84 if (rc < 0) {
85 printk(KERN_ERR "delkin_cb: ide_register_hw failed (%d)\n", rc); 85 printk(KERN_ERR "delkin_cb: ide_register_hw failed (%d)\n", rc);
86 pci_disable_device(dev); 86 pci_disable_device(dev);
diff --git a/drivers/ide/pci/generic.c b/drivers/ide/pci/generic.c
index cce6311b02df..f44d70852c3c 100644
--- a/drivers/ide/pci/generic.c
+++ b/drivers/ide/pci/generic.c
@@ -54,130 +54,61 @@ __setup("all-generic-ide", ide_generic_all_on);
54module_param_named(all_generic_ide, ide_generic_all, bool, 0444); 54module_param_named(all_generic_ide, ide_generic_all, bool, 0444);
55MODULE_PARM_DESC(all_generic_ide, "IDE generic will claim all unknown PCI IDE storage controllers."); 55MODULE_PARM_DESC(all_generic_ide, "IDE generic will claim all unknown PCI IDE storage controllers.");
56 56
57static void __devinit init_hwif_generic (ide_hwif_t *hwif) 57#define IDE_HFLAGS_UMC (IDE_HFLAG_NO_DMA | IDE_HFLAG_FORCE_LEGACY_IRQS)
58{ 58
59 switch(hwif->pci_dev->device) { 59#define DECLARE_GENERIC_PCI_DEV(name_str, extra_flags) \
60 case PCI_DEVICE_ID_UMC_UM8673F: 60 { \
61 case PCI_DEVICE_ID_UMC_UM8886A: 61 .name = name_str, \
62 case PCI_DEVICE_ID_UMC_UM8886BF: 62 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA | \
63 hwif->irq = hwif->channel ? 15 : 14; 63 extra_flags | \
64 break; 64 IDE_HFLAG_BOOTABLE, \
65 default: 65 .swdma_mask = ATA_SWDMA2, \
66 break; 66 .mwdma_mask = ATA_MWDMA2, \
67 .udma_mask = ATA_UDMA6, \
67 } 68 }
68 69
69 if (!(hwif->dma_base)) 70static const struct ide_port_info generic_chipsets[] __devinitdata = {
70 return; 71 /* 0 */ DECLARE_GENERIC_PCI_DEV("Unknown", 0),
71
72 hwif->atapi_dma = 1;
73 hwif->ultra_mask = 0x7f;
74 hwif->mwdma_mask = 0x07;
75 hwif->swdma_mask = 0x07;
76}
77
78#if 0
79 /* Logic to add back later on */
80
81 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
82 ide_pci_device_t *unknown = unknown_chipset;
83 init_setup_unknown(dev, unknown);
84 return 1;
85 }
86 return 0;
87#endif
88 72
89static ide_pci_device_t generic_chipsets[] __devinitdata = { 73 { /* 1 */
90 { /* 0 */
91 .name = "Unknown",
92 .init_hwif = init_hwif_generic,
93 .autodma = AUTODMA,
94 .bootable = ON_BOARD,
95 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
96 },{ /* 1 */
97 .name = "NS87410", 74 .name = "NS87410",
98 .init_hwif = init_hwif_generic,
99 .autodma = AUTODMA,
100 .enablebits = {{0x43,0x08,0x08}, {0x47,0x08,0x08}}, 75 .enablebits = {{0x43,0x08,0x08}, {0x47,0x08,0x08}},
101 .bootable = ON_BOARD, 76 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
102 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, 77 IDE_HFLAG_BOOTABLE,
103 },{ /* 2 */ 78 .swdma_mask = ATA_SWDMA2,
104 .name = "SAMURAI", 79 .mwdma_mask = ATA_MWDMA2,
105 .init_hwif = init_hwif_generic, 80 .udma_mask = ATA_UDMA6,
106 .autodma = AUTODMA, 81 },
107 .bootable = ON_BOARD, 82
108 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, 83 /* 2 */ DECLARE_GENERIC_PCI_DEV("SAMURAI", 0),
109 },{ /* 3 */ 84 /* 3 */ DECLARE_GENERIC_PCI_DEV("HT6565", 0),
110 .name = "HT6565", 85 /* 4 */ DECLARE_GENERIC_PCI_DEV("UM8673F", IDE_HFLAGS_UMC),
111 .init_hwif = init_hwif_generic, 86 /* 5 */ DECLARE_GENERIC_PCI_DEV("UM8886A", IDE_HFLAGS_UMC),
112 .autodma = AUTODMA, 87 /* 6 */ DECLARE_GENERIC_PCI_DEV("UM8886BF", IDE_HFLAGS_UMC),
113 .bootable = ON_BOARD, 88 /* 7 */ DECLARE_GENERIC_PCI_DEV("HINT_IDE", 0),
114 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, 89 /* 8 */ DECLARE_GENERIC_PCI_DEV("VIA_IDE", IDE_HFLAG_NO_AUTODMA),
115 },{ /* 4 */ 90 /* 9 */ DECLARE_GENERIC_PCI_DEV("OPTI621V", IDE_HFLAG_NO_AUTODMA),
116 .name = "UM8673F", 91
117 .init_hwif = init_hwif_generic, 92 { /* 10 */
118 .autodma = NODMA,
119 .bootable = ON_BOARD,
120 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
121 },{ /* 5 */
122 .name = "UM8886A",
123 .init_hwif = init_hwif_generic,
124 .autodma = NODMA,
125 .bootable = ON_BOARD,
126 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
127 },{ /* 6 */
128 .name = "UM8886BF",
129 .init_hwif = init_hwif_generic,
130 .autodma = NODMA,
131 .bootable = ON_BOARD,
132 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
133 },{ /* 7 */
134 .name = "HINT_IDE",
135 .init_hwif = init_hwif_generic,
136 .autodma = AUTODMA,
137 .bootable = ON_BOARD,
138 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
139 },{ /* 8 */
140 .name = "VIA_IDE",
141 .init_hwif = init_hwif_generic,
142 .autodma = NOAUTODMA,
143 .bootable = ON_BOARD,
144 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
145 },{ /* 9 */
146 .name = "OPTI621V",
147 .init_hwif = init_hwif_generic,
148 .autodma = NOAUTODMA,
149 .bootable = ON_BOARD,
150 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
151 },{ /* 10 */
152 .name = "VIA8237SATA", 93 .name = "VIA8237SATA",
153 .init_hwif = init_hwif_generic, 94 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
154 .autodma = AUTODMA, 95 IDE_HFLAG_OFF_BOARD,
155 .bootable = OFF_BOARD, 96 .swdma_mask = ATA_SWDMA2,
156 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, 97 .mwdma_mask = ATA_MWDMA2,
157 },{ /* 11 */ 98 .udma_mask = ATA_UDMA6,
158 .name = "Piccolo0102", 99 },
159 .init_hwif = init_hwif_generic, 100
160 .autodma = NOAUTODMA, 101 /* 11 */ DECLARE_GENERIC_PCI_DEV("Piccolo0102", IDE_HFLAG_NO_AUTODMA),
161 .bootable = ON_BOARD, 102 /* 12 */ DECLARE_GENERIC_PCI_DEV("Piccolo0103", IDE_HFLAG_NO_AUTODMA),
162 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, 103 /* 13 */ DECLARE_GENERIC_PCI_DEV("Piccolo0105", IDE_HFLAG_NO_AUTODMA),
163 },{ /* 12 */ 104
164 .name = "Piccolo0103", 105 { /* 14 */
165 .init_hwif = init_hwif_generic,
166 .autodma = NOAUTODMA,
167 .bootable = ON_BOARD,
168 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
169 },{ /* 13 */
170 .name = "Piccolo0105",
171 .init_hwif = init_hwif_generic,
172 .autodma = NOAUTODMA,
173 .bootable = ON_BOARD,
174 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
175 },{ /* 14 */
176 .name = "Revolution", 106 .name = "Revolution",
177 .init_hwif = init_hwif_generic, 107 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
178 .autodma = AUTODMA, 108 IDE_HFLAG_OFF_BOARD,
179 .bootable = OFF_BOARD, 109 .swdma_mask = ATA_SWDMA2,
180 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, 110 .mwdma_mask = ATA_MWDMA2,
111 .udma_mask = ATA_UDMA6,
181 } 112 }
182}; 113};
183 114
@@ -192,7 +123,7 @@ static ide_pci_device_t generic_chipsets[] __devinitdata = {
192 123
193static int __devinit generic_init_one(struct pci_dev *dev, const struct pci_device_id *id) 124static int __devinit generic_init_one(struct pci_dev *dev, const struct pci_device_id *id)
194{ 125{
195 ide_pci_device_t *d = &generic_chipsets[id->driver_data]; 126 const struct ide_port_info *d = &generic_chipsets[id->driver_data];
196 int ret = -ENODEV; 127 int ret = -ENODEV;
197 128
198 /* Don't use the generic entry unless instructed to do so */ 129 /* Don't use the generic entry unless instructed to do so */
diff --git a/drivers/ide/pci/hpt34x.c b/drivers/ide/pci/hpt34x.c
index 44ac0e2f7a09..ae6307fae4f9 100644
--- a/drivers/ide/pci/hpt34x.c
+++ b/drivers/ide/pci/hpt34x.c
@@ -125,49 +125,45 @@ static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const cha
125 125
126static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif) 126static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
127{ 127{
128 u16 pcicmd = 0;
129
130 hwif->set_pio_mode = &hpt34x_set_pio_mode; 128 hwif->set_pio_mode = &hpt34x_set_pio_mode;
131 hwif->set_dma_mode = &hpt34x_set_mode; 129 hwif->set_dma_mode = &hpt34x_set_mode;
130}
132 131
133 hwif->drives[0].autotune = 1; 132static const struct ide_port_info hpt34x_chipsets[] __devinitdata = {
134 hwif->drives[1].autotune = 1; 133 { /* 0 */
135 134 .name = "HPT343",
136 pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd); 135 .init_chipset = init_chipset_hpt34x,
137 136 .init_hwif = init_hwif_hpt34x,
138 if (!hwif->dma_base) 137 .extra = 16,
139 return; 138 .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
140 139 IDE_HFLAG_NO_AUTODMA,
140 .pio_mask = ATA_PIO5,
141 },
142 { /* 1 */
143 .name = "HPT345",
144 .init_chipset = init_chipset_hpt34x,
145 .init_hwif = init_hwif_hpt34x,
146 .extra = 16,
147 .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
148 IDE_HFLAG_NO_AUTODMA |
149 IDE_HFLAG_OFF_BOARD,
150 .pio_mask = ATA_PIO5,
141#ifdef CONFIG_HPT34X_AUTODMA 151#ifdef CONFIG_HPT34X_AUTODMA
142 if ((pcicmd & PCI_COMMAND_MEMORY) == 0) 152 .swdma_mask = ATA_SWDMA2,
143 return; 153 .mwdma_mask = ATA_MWDMA2,
144 154 .udma_mask = ATA_UDMA2,
145 hwif->ultra_mask = 0x07;
146 hwif->mwdma_mask = 0x07;
147 hwif->swdma_mask = 0x07;
148#endif 155#endif
149} 156 }
150
151static ide_pci_device_t hpt34x_chipset __devinitdata = {
152 .name = "HPT34X",
153 .init_chipset = init_chipset_hpt34x,
154 .init_hwif = init_hwif_hpt34x,
155 .autodma = NOAUTODMA,
156 .bootable = NEVER_BOARD,
157 .extra = 16,
158 .pio_mask = ATA_PIO5,
159}; 157};
160 158
161static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id) 159static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
162{ 160{
163 ide_pci_device_t *d = &hpt34x_chipset; 161 const struct ide_port_info *d;
164 static char *chipset_names[] = {"HPT343", "HPT345"};
165 u16 pcicmd = 0; 162 u16 pcicmd = 0;
166 163
167 pci_read_config_word(dev, PCI_COMMAND, &pcicmd); 164 pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
168 165
169 d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0]; 166 d = &hpt34x_chipsets[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
170 d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
171 167
172 return ide_setup_pci_device(dev, d); 168 return ide_setup_pci_device(dev, d);
173} 169}
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index fcb21ddab2cc..612b795241bf 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -1,9 +1,10 @@
1/* 1/*
2 * linux/drivers/ide/pci/hpt366.c Version 1.14 Oct 1, 2007 2 * linux/drivers/ide/pci/hpt366.c Version 1.20 Oct 1, 2007
3 * 3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc 6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
7 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc. 8 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
8 * 9 *
9 * Thanks to HighPoint Technologies for their assistance, and hardware. 10 * Thanks to HighPoint Technologies for their assistance, and hardware.
@@ -393,8 +394,9 @@ enum ata_clock {
393 */ 394 */
394 395
395struct hpt_info { 396struct hpt_info {
397 char *chip_name; /* Chip name */
396 u8 chip_type; /* Chip type */ 398 u8 chip_type; /* Chip type */
397 u8 max_ultra; /* Max. UltraDMA mode allowed */ 399 u8 udma_mask; /* Allowed UltraDMA modes mask. */
398 u8 dpll_clk; /* DPLL clock in MHz */ 400 u8 dpll_clk; /* DPLL clock in MHz */
399 u8 pci_clk; /* PCI clock in MHz */ 401 u8 pci_clk; /* PCI clock in MHz */
400 u32 **settings; /* Chipset settings table */ 402 u32 **settings; /* Chipset settings table */
@@ -432,78 +434,89 @@ static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
432}; 434};
433 435
434static struct hpt_info hpt36x __devinitdata = { 436static struct hpt_info hpt36x __devinitdata = {
437 .chip_name = "HPT36x",
435 .chip_type = HPT36x, 438 .chip_type = HPT36x,
436 .max_ultra = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? 4 : 3) : 2, 439 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
437 .dpll_clk = 0, /* no DPLL */ 440 .dpll_clk = 0, /* no DPLL */
438 .settings = hpt36x_settings 441 .settings = hpt36x_settings
439}; 442};
440 443
441static struct hpt_info hpt370 __devinitdata = { 444static struct hpt_info hpt370 __devinitdata = {
445 .chip_name = "HPT370",
442 .chip_type = HPT370, 446 .chip_type = HPT370,
443 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4, 447 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
444 .dpll_clk = 48, 448 .dpll_clk = 48,
445 .settings = hpt37x_settings 449 .settings = hpt37x_settings
446}; 450};
447 451
448static struct hpt_info hpt370a __devinitdata = { 452static struct hpt_info hpt370a __devinitdata = {
453 .chip_name = "HPT370A",
449 .chip_type = HPT370A, 454 .chip_type = HPT370A,
450 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4, 455 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
451 .dpll_clk = 48, 456 .dpll_clk = 48,
452 .settings = hpt37x_settings 457 .settings = hpt37x_settings
453}; 458};
454 459
455static struct hpt_info hpt374 __devinitdata = { 460static struct hpt_info hpt374 __devinitdata = {
461 .chip_name = "HPT374",
456 .chip_type = HPT374, 462 .chip_type = HPT374,
457 .max_ultra = 5, 463 .udma_mask = ATA_UDMA5,
458 .dpll_clk = 48, 464 .dpll_clk = 48,
459 .settings = hpt37x_settings 465 .settings = hpt37x_settings
460}; 466};
461 467
462static struct hpt_info hpt372 __devinitdata = { 468static struct hpt_info hpt372 __devinitdata = {
469 .chip_name = "HPT372",
463 .chip_type = HPT372, 470 .chip_type = HPT372,
464 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5, 471 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
465 .dpll_clk = 55, 472 .dpll_clk = 55,
466 .settings = hpt37x_settings 473 .settings = hpt37x_settings
467}; 474};
468 475
469static struct hpt_info hpt372a __devinitdata = { 476static struct hpt_info hpt372a __devinitdata = {
477 .chip_name = "HPT372A",
470 .chip_type = HPT372A, 478 .chip_type = HPT372A,
471 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5, 479 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
472 .dpll_clk = 66, 480 .dpll_clk = 66,
473 .settings = hpt37x_settings 481 .settings = hpt37x_settings
474}; 482};
475 483
476static struct hpt_info hpt302 __devinitdata = { 484static struct hpt_info hpt302 __devinitdata = {
485 .chip_name = "HPT302",
477 .chip_type = HPT302, 486 .chip_type = HPT302,
478 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5, 487 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
479 .dpll_clk = 66, 488 .dpll_clk = 66,
480 .settings = hpt37x_settings 489 .settings = hpt37x_settings
481}; 490};
482 491
483static struct hpt_info hpt371 __devinitdata = { 492static struct hpt_info hpt371 __devinitdata = {
493 .chip_name = "HPT371",
484 .chip_type = HPT371, 494 .chip_type = HPT371,
485 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5, 495 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
486 .dpll_clk = 66, 496 .dpll_clk = 66,
487 .settings = hpt37x_settings 497 .settings = hpt37x_settings
488}; 498};
489 499
490static struct hpt_info hpt372n __devinitdata = { 500static struct hpt_info hpt372n __devinitdata = {
501 .chip_name = "HPT372N",
491 .chip_type = HPT372N, 502 .chip_type = HPT372N,
492 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5, 503 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
493 .dpll_clk = 77, 504 .dpll_clk = 77,
494 .settings = hpt37x_settings 505 .settings = hpt37x_settings
495}; 506};
496 507
497static struct hpt_info hpt302n __devinitdata = { 508static struct hpt_info hpt302n __devinitdata = {
509 .chip_name = "HPT302N",
498 .chip_type = HPT302N, 510 .chip_type = HPT302N,
499 .max_ultra = HPT302_ALLOW_ATA133_6 ? 6 : 5, 511 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
500 .dpll_clk = 77, 512 .dpll_clk = 77,
501 .settings = hpt37x_settings 513 .settings = hpt37x_settings
502}; 514};
503 515
504static struct hpt_info hpt371n __devinitdata = { 516static struct hpt_info hpt371n __devinitdata = {
517 .chip_name = "HPT371N",
505 .chip_type = HPT371N, 518 .chip_type = HPT371N,
506 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5, 519 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
507 .dpll_clk = 77, 520 .dpll_clk = 77,
508 .settings = hpt37x_settings 521 .settings = hpt37x_settings
509}; 522};
@@ -676,12 +689,11 @@ static int hpt3xx_quirkproc(ide_drive_t *drive)
676 689
677static void hpt3xx_intrproc(ide_drive_t *drive) 690static void hpt3xx_intrproc(ide_drive_t *drive)
678{ 691{
679 ide_hwif_t *hwif = HWIF(drive);
680
681 if (drive->quirk_list) 692 if (drive->quirk_list)
682 return; 693 return;
694
683 /* drives in the quirk_list may not like intr setups/cleanups */ 695 /* drives in the quirk_list may not like intr setups/cleanups */
684 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG); 696 outb(drive->ctl | 2, IDE_CONTROL_REG);
685} 697}
686 698
687static void hpt3xx_maskproc(ide_drive_t *drive, int mask) 699static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
@@ -709,8 +721,8 @@ static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
709 enable_irq (hwif->irq); 721 enable_irq (hwif->irq);
710 } 722 }
711 } else 723 } else
712 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2), 724 outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
713 IDE_CONTROL_REG); 725 IDE_CONTROL_REG);
714} 726}
715 727
716/* 728/*
@@ -750,9 +762,9 @@ static void hpt370_irq_timeout(ide_drive_t *drive)
750 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff); 762 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
751 763
752 /* get DMA command mode */ 764 /* get DMA command mode */
753 dma_cmd = hwif->INB(hwif->dma_command); 765 dma_cmd = inb(hwif->dma_command);
754 /* stop DMA */ 766 /* stop DMA */
755 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command); 767 outb(dma_cmd & ~0x1, hwif->dma_command);
756 hpt370_clear_engine(drive); 768 hpt370_clear_engine(drive);
757} 769}
758 770
@@ -767,12 +779,12 @@ static void hpt370_ide_dma_start(ide_drive_t *drive)
767static int hpt370_ide_dma_end(ide_drive_t *drive) 779static int hpt370_ide_dma_end(ide_drive_t *drive)
768{ 780{
769 ide_hwif_t *hwif = HWIF(drive); 781 ide_hwif_t *hwif = HWIF(drive);
770 u8 dma_stat = hwif->INB(hwif->dma_status); 782 u8 dma_stat = inb(hwif->dma_status);
771 783
772 if (dma_stat & 0x01) { 784 if (dma_stat & 0x01) {
773 /* wait a little */ 785 /* wait a little */
774 udelay(20); 786 udelay(20);
775 dma_stat = hwif->INB(hwif->dma_status); 787 dma_stat = inb(hwif->dma_status);
776 if (dma_stat & 0x01) 788 if (dma_stat & 0x01)
777 hpt370_irq_timeout(drive); 789 hpt370_irq_timeout(drive);
778 } 790 }
@@ -833,34 +845,32 @@ static int hpt374_ide_dma_end(ide_drive_t *drive)
833 845
834static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode) 846static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
835{ 847{
836 u8 scr2 = hwif->INB(hwif->dma_master + 0x7b); 848 u8 scr2 = inb(hwif->dma_master + 0x7b);
837 849
838 if ((scr2 & 0x7f) == mode) 850 if ((scr2 & 0x7f) == mode)
839 return; 851 return;
840 852
841 /* Tristate the bus */ 853 /* Tristate the bus */
842 hwif->OUTB(0x80, hwif->dma_master + 0x73); 854 outb(0x80, hwif->dma_master + 0x73);
843 hwif->OUTB(0x80, hwif->dma_master + 0x77); 855 outb(0x80, hwif->dma_master + 0x77);
844 856
845 /* Switch clock and reset channels */ 857 /* Switch clock and reset channels */
846 hwif->OUTB(mode, hwif->dma_master + 0x7b); 858 outb(mode, hwif->dma_master + 0x7b);
847 hwif->OUTB(0xc0, hwif->dma_master + 0x79); 859 outb(0xc0, hwif->dma_master + 0x79);
848 860
849 /* 861 /*
850 * Reset the state machines. 862 * Reset the state machines.
851 * NOTE: avoid accidentally enabling the disabled channels. 863 * NOTE: avoid accidentally enabling the disabled channels.
852 */ 864 */
853 hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32, 865 outb(inb(hwif->dma_master + 0x70) | 0x32, hwif->dma_master + 0x70);
854 hwif->dma_master + 0x70); 866 outb(inb(hwif->dma_master + 0x74) | 0x32, hwif->dma_master + 0x74);
855 hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
856 hwif->dma_master + 0x74);
857 867
858 /* Complete reset */ 868 /* Complete reset */
859 hwif->OUTB(0x00, hwif->dma_master + 0x79); 869 outb(0x00, hwif->dma_master + 0x79);
860 870
861 /* Reconnect channels to bus */ 871 /* Reconnect channels to bus */
862 hwif->OUTB(0x00, hwif->dma_master + 0x73); 872 outb(0x00, hwif->dma_master + 0x73);
863 hwif->OUTB(0x00, hwif->dma_master + 0x77); 873 outb(0x00, hwif->dma_master + 0x77);
864} 874}
865 875
866/** 876/**
@@ -1139,7 +1149,7 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
1139 * Select 66 MHz DPLL clock only if UltraATA/133 mode is 1149 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1140 * supported/enabled, use 50 MHz DPLL clock otherwise... 1150 * supported/enabled, use 50 MHz DPLL clock otherwise...
1141 */ 1151 */
1142 if (info->max_ultra == 6) { 1152 if (info->udma_mask == ATA_UDMA6) {
1143 dpll_clk = 66; 1153 dpll_clk = 66;
1144 clock = ATA_CLOCK_66MHZ; 1154 clock = ATA_CLOCK_66MHZ;
1145 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */ 1155 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
@@ -1291,14 +1301,9 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1291 if (new_mcr != old_mcr) 1301 if (new_mcr != old_mcr)
1292 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr); 1302 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1293 1303
1294 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1295
1296 if (hwif->dma_base == 0) 1304 if (hwif->dma_base == 0)
1297 return; 1305 return;
1298 1306
1299 hwif->ultra_mask = hwif->cds->udma_mask;
1300 hwif->mwdma_mask = 0x07;
1301
1302 /* 1307 /*
1303 * The HPT37x uses the CBLID pins as outputs for MA15/MA16 1308 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1304 * address lines to access an external EEPROM. To read valid 1309 * address lines to access an external EEPROM. To read valid
@@ -1354,7 +1359,7 @@ static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1354 u8 dma_new = 0, dma_old = 0; 1359 u8 dma_new = 0, dma_old = 0;
1355 unsigned long flags; 1360 unsigned long flags;
1356 1361
1357 dma_old = hwif->INB(dmabase + 2); 1362 dma_old = inb(dmabase + 2);
1358 1363
1359 local_irq_save(flags); 1364 local_irq_save(flags);
1360 1365
@@ -1365,60 +1370,26 @@ static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1365 if (masterdma & 0x30) dma_new |= 0x20; 1370 if (masterdma & 0x30) dma_new |= 0x20;
1366 if ( slavedma & 0x30) dma_new |= 0x40; 1371 if ( slavedma & 0x30) dma_new |= 0x40;
1367 if (dma_new != dma_old) 1372 if (dma_new != dma_old)
1368 hwif->OUTB(dma_new, dmabase + 2); 1373 outb(dma_new, dmabase + 2);
1369 1374
1370 local_irq_restore(flags); 1375 local_irq_restore(flags);
1371 1376
1372 ide_setup_dma(hwif, dmabase, 8); 1377 ide_setup_dma(hwif, dmabase, 8);
1373} 1378}
1374 1379
1375static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d) 1380static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
1376{ 1381{
1377 struct pci_dev *dev2; 1382 if (dev2->irq != dev->irq) {
1378 1383 /* FIXME: we need a core pci_set_interrupt() */
1379 if (PCI_FUNC(dev->devfn) & 1) 1384 dev2->irq = dev->irq;
1380 return -ENODEV; 1385 printk(KERN_INFO "HPT374: PCI config space interrupt fixed\n");
1381
1382 pci_set_drvdata(dev, &hpt374);
1383
1384 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1385 int ret;
1386
1387 pci_set_drvdata(dev2, &hpt374);
1388
1389 if (dev2->irq != dev->irq) {
1390 /* FIXME: we need a core pci_set_interrupt() */
1391 dev2->irq = dev->irq;
1392 printk(KERN_WARNING "%s: PCI config space interrupt "
1393 "fixed.\n", d->name);
1394 }
1395 ret = ide_setup_pci_devices(dev, dev2, d);
1396 if (ret < 0)
1397 pci_dev_put(dev2);
1398 return ret;
1399 } 1386 }
1400 return ide_setup_pci_device(dev, d);
1401}
1402
1403static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1404{
1405 pci_set_drvdata(dev, &hpt372n);
1406
1407 return ide_setup_pci_device(dev, d);
1408} 1387}
1409 1388
1410static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d) 1389static void __devinit hpt371_init(struct pci_dev *dev)
1411{ 1390{
1412 struct hpt_info *info;
1413 u8 mcr1 = 0; 1391 u8 mcr1 = 0;
1414 1392
1415 if (dev->revision > 1) {
1416 d->name = "HPT371N";
1417
1418 info = &hpt371n;
1419 } else
1420 info = &hpt371;
1421
1422 /* 1393 /*
1423 * HPT371 chips physically have only one channel, the secondary one, 1394 * HPT371 chips physically have only one channel, the secondary one,
1424 * but the primary channel registers do exist! Go figure... 1395 * but the primary channel registers do exist! Go figure...
@@ -1428,194 +1399,102 @@ static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1428 pci_read_config_byte(dev, 0x50, &mcr1); 1399 pci_read_config_byte(dev, 0x50, &mcr1);
1429 if (mcr1 & 0x04) 1400 if (mcr1 & 0x04)
1430 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04); 1401 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1431
1432 pci_set_drvdata(dev, info);
1433
1434 return ide_setup_pci_device(dev, d);
1435} 1402}
1436 1403
1437static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d) 1404static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
1438{ 1405{
1439 struct hpt_info *info; 1406 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1440
1441 if (dev->revision > 1) {
1442 d->name = "HPT372N";
1443 1407
1444 info = &hpt372n; 1408 /*
1445 } else 1409 * Now we'll have to force both channels enabled if
1446 info = &hpt372a; 1410 * at least one of them has been enabled by BIOS...
1447 pci_set_drvdata(dev, info); 1411 */
1448 1412 pci_read_config_byte(dev, 0x50, &mcr1);
1449 return ide_setup_pci_device(dev, d); 1413 if (mcr1 & 0x30)
1450} 1414 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1451
1452static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1453{
1454 struct hpt_info *info;
1455 1415
1456 if (dev->revision > 1) { 1416 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1457 d->name = "HPT302N"; 1417 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1458 1418
1459 info = &hpt302n; 1419 if (pin1 != pin2 && dev->irq == dev2->irq) {
1460 } else 1420 printk(KERN_INFO "HPT36x: onboard version of chipset, "
1461 info = &hpt302; 1421 "pin1=%d pin2=%d\n", pin1, pin2);
1462 pci_set_drvdata(dev, info); 1422 return 1;
1423 }
1463 1424
1464 return ide_setup_pci_device(dev, d); 1425 return 0;
1465} 1426}
1466 1427
1467static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d) 1428static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1468{ 1429 { /* 0 */
1469 struct pci_dev *dev2; 1430 .name = "HPT36x",
1470 u8 rev = dev->revision; 1431 .init_chipset = init_chipset_hpt366,
1471 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368", 1432 .init_hwif = init_hwif_hpt366,
1472 "HPT370", "HPT370A", "HPT372", 1433 .init_dma = init_dma_hpt366,
1473 "HPT372N" };
1474 static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x,
1475 &hpt370, &hpt370a, &hpt372,
1476 &hpt372n };
1477
1478 if (PCI_FUNC(dev->devfn) & 1)
1479 return -ENODEV;
1480
1481 switch (rev) {
1482 case 0:
1483 case 1:
1484 case 2:
1485 /* 1434 /*
1486 * HPT36x chips have one channel per function and have 1435 * HPT36x chips have one channel per function and have
1487 * both channel enable bits located differently and visible 1436 * both channel enable bits located differently and visible
1488 * to both functions -- really stupid design decision... :-( 1437 * to both functions -- really stupid design decision... :-(
1489 * Bit 4 is for the primary channel, bit 5 for the secondary. 1438 * Bit 4 is for the primary channel, bit 5 for the secondary.
1490 */ 1439 */
1491 d->host_flags |= IDE_HFLAG_SINGLE; 1440 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1492 d->enablebits[0].mask = d->enablebits[0].val = 0x10;
1493
1494 d->udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ?
1495 ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2;
1496 break;
1497 case 3:
1498 case 4:
1499 d->udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4;
1500 break;
1501 default:
1502 rev = 6;
1503 /* fall thru */
1504 case 5:
1505 case 6:
1506 d->udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5;
1507 break;
1508 }
1509
1510 d->name = chipset_names[rev];
1511
1512 pci_set_drvdata(dev, info[rev]);
1513
1514 if (rev > 2)
1515 goto init_single;
1516
1517 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1518 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1519 int ret;
1520
1521 pci_set_drvdata(dev2, info[rev]);
1522
1523 /*
1524 * Now we'll have to force both channels enabled if
1525 * at least one of them has been enabled by BIOS...
1526 */
1527 pci_read_config_byte(dev, 0x50, &mcr1);
1528 if (mcr1 & 0x30)
1529 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1530
1531 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1532 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1533 if (pin1 != pin2 && dev->irq == dev2->irq) {
1534 d->bootable = ON_BOARD;
1535 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1536 d->name, pin1, pin2);
1537 }
1538 ret = ide_setup_pci_devices(dev, dev2, d);
1539 if (ret < 0)
1540 pci_dev_put(dev2);
1541 return ret;
1542 }
1543init_single:
1544 return ide_setup_pci_device(dev, d);
1545}
1546
1547static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1548 { /* 0 */
1549 .name = "HPT366",
1550 .init_setup = init_setup_hpt366,
1551 .init_chipset = init_chipset_hpt366,
1552 .init_hwif = init_hwif_hpt366,
1553 .init_dma = init_dma_hpt366,
1554 .autodma = AUTODMA,
1555 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1556 .bootable = OFF_BOARD,
1557 .extra = 240, 1441 .extra = 240,
1442 .host_flags = IDE_HFLAG_SINGLE |
1443 IDE_HFLAG_NO_ATAPI_DMA |
1444 IDE_HFLAG_OFF_BOARD,
1558 .pio_mask = ATA_PIO4, 1445 .pio_mask = ATA_PIO4,
1446 .mwdma_mask = ATA_MWDMA2,
1559 },{ /* 1 */ 1447 },{ /* 1 */
1560 .name = "HPT372A", 1448 .name = "HPT372A",
1561 .init_setup = init_setup_hpt372a,
1562 .init_chipset = init_chipset_hpt366, 1449 .init_chipset = init_chipset_hpt366,
1563 .init_hwif = init_hwif_hpt366, 1450 .init_hwif = init_hwif_hpt366,
1564 .init_dma = init_dma_hpt366, 1451 .init_dma = init_dma_hpt366,
1565 .autodma = AUTODMA,
1566 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1452 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1567 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1568 .bootable = OFF_BOARD,
1569 .extra = 240, 1453 .extra = 240,
1454 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
1570 .pio_mask = ATA_PIO4, 1455 .pio_mask = ATA_PIO4,
1456 .mwdma_mask = ATA_MWDMA2,
1571 },{ /* 2 */ 1457 },{ /* 2 */
1572 .name = "HPT302", 1458 .name = "HPT302",
1573 .init_setup = init_setup_hpt302,
1574 .init_chipset = init_chipset_hpt366, 1459 .init_chipset = init_chipset_hpt366,
1575 .init_hwif = init_hwif_hpt366, 1460 .init_hwif = init_hwif_hpt366,
1576 .init_dma = init_dma_hpt366, 1461 .init_dma = init_dma_hpt366,
1577 .autodma = AUTODMA,
1578 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1462 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1579 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1580 .bootable = OFF_BOARD,
1581 .extra = 240, 1463 .extra = 240,
1464 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
1582 .pio_mask = ATA_PIO4, 1465 .pio_mask = ATA_PIO4,
1466 .mwdma_mask = ATA_MWDMA2,
1583 },{ /* 3 */ 1467 },{ /* 3 */
1584 .name = "HPT371", 1468 .name = "HPT371",
1585 .init_setup = init_setup_hpt371,
1586 .init_chipset = init_chipset_hpt366, 1469 .init_chipset = init_chipset_hpt366,
1587 .init_hwif = init_hwif_hpt366, 1470 .init_hwif = init_hwif_hpt366,
1588 .init_dma = init_dma_hpt366, 1471 .init_dma = init_dma_hpt366,
1589 .autodma = AUTODMA,
1590 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1472 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1591 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1592 .bootable = OFF_BOARD,
1593 .extra = 240, 1473 .extra = 240,
1474 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
1594 .pio_mask = ATA_PIO4, 1475 .pio_mask = ATA_PIO4,
1476 .mwdma_mask = ATA_MWDMA2,
1595 },{ /* 4 */ 1477 },{ /* 4 */
1596 .name = "HPT374", 1478 .name = "HPT374",
1597 .init_setup = init_setup_hpt374,
1598 .init_chipset = init_chipset_hpt366, 1479 .init_chipset = init_chipset_hpt366,
1599 .init_hwif = init_hwif_hpt366, 1480 .init_hwif = init_hwif_hpt366,
1600 .init_dma = init_dma_hpt366, 1481 .init_dma = init_dma_hpt366,
1601 .autodma = AUTODMA,
1602 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1482 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1603 .udma_mask = ATA_UDMA5, 1483 .udma_mask = ATA_UDMA5,
1604 .bootable = OFF_BOARD,
1605 .extra = 240, 1484 .extra = 240,
1485 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
1606 .pio_mask = ATA_PIO4, 1486 .pio_mask = ATA_PIO4,
1487 .mwdma_mask = ATA_MWDMA2,
1607 },{ /* 5 */ 1488 },{ /* 5 */
1608 .name = "HPT372N", 1489 .name = "HPT372N",
1609 .init_setup = init_setup_hpt372n,
1610 .init_chipset = init_chipset_hpt366, 1490 .init_chipset = init_chipset_hpt366,
1611 .init_hwif = init_hwif_hpt366, 1491 .init_hwif = init_hwif_hpt366,
1612 .init_dma = init_dma_hpt366, 1492 .init_dma = init_dma_hpt366,
1613 .autodma = AUTODMA,
1614 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1493 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1615 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1616 .bootable = OFF_BOARD,
1617 .extra = 240, 1494 .extra = 240,
1495 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
1618 .pio_mask = ATA_PIO4, 1496 .pio_mask = ATA_PIO4,
1497 .mwdma_mask = ATA_MWDMA2,
1619 } 1498 }
1620}; 1499};
1621 1500
@@ -1626,16 +1505,77 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1626 * 1505 *
1627 * Called when the PCI registration layer (or the IDE initialization) 1506 * Called when the PCI registration layer (or the IDE initialization)
1628 * finds a device matching our IDE device tables. 1507 * finds a device matching our IDE device tables.
1629 *
1630 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1631 * structure depending on the chip's revision, we'd better pass a local
1632 * copy down the call chain...
1633 */ 1508 */
1634static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id) 1509static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1635{ 1510{
1636 ide_pci_device_t d = hpt366_chipsets[id->driver_data]; 1511 struct hpt_info *info = NULL;
1512 struct pci_dev *dev2 = NULL;
1513 struct ide_port_info d;
1514 u8 idx = id->driver_data;
1515 u8 rev = dev->revision;
1516
1517 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1518 return -ENODEV;
1519
1520 switch (idx) {
1521 case 0:
1522 if (rev < 3)
1523 info = &hpt36x;
1524 else {
1525 static struct hpt_info *hpt37x_info[] =
1526 { &hpt370, &hpt370a, &hpt372, &hpt372n };
1527
1528 info = hpt37x_info[min_t(u8, rev, 6) - 3];
1529 idx++;
1530 }
1531 break;
1532 case 1:
1533 info = (rev > 1) ? &hpt372n : &hpt372a;
1534 break;
1535 case 2:
1536 info = (rev > 1) ? &hpt302n : &hpt302;
1537 break;
1538 case 3:
1539 hpt371_init(dev);
1540 info = (rev > 1) ? &hpt371n : &hpt371;
1541 break;
1542 case 4:
1543 info = &hpt374;
1544 break;
1545 case 5:
1546 info = &hpt372n;
1547 break;
1548 }
1549
1550 d = hpt366_chipsets[idx];
1551
1552 d.name = info->chip_name;
1553 d.udma_mask = info->udma_mask;
1554
1555 pci_set_drvdata(dev, info);
1556
1557 if (info == &hpt36x || info == &hpt374)
1558 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1559
1560 if (dev2) {
1561 int ret;
1562
1563 pci_set_drvdata(dev2, info);
1564
1565 if (info == &hpt374)
1566 hpt374_init(dev, dev2);
1567 else {
1568 if (hpt36x_init(dev, dev2))
1569 d.host_flags |= IDE_HFLAG_BOOTABLE;
1570 }
1571
1572 ret = ide_setup_pci_devices(dev, dev2, &d);
1573 if (ret < 0)
1574 pci_dev_put(dev2);
1575 return ret;
1576 }
1637 1577
1638 return d.init_setup(dev, &d); 1578 return ide_setup_pci_device(dev, &d);
1639} 1579}
1640 1580
1641static const struct pci_device_id hpt366_pci_tbl[] = { 1581static const struct pci_device_id hpt366_pci_tbl[] = {
diff --git a/drivers/ide/pci/it8213.c b/drivers/ide/pci/it8213.c
index 24a71d03744a..90b52ed37bfc 100644
--- a/drivers/ide/pci/it8213.c
+++ b/drivers/ide/pci/it8213.c
@@ -170,17 +170,9 @@ static void __devinit init_hwif_it8213(ide_hwif_t *hwif)
170 hwif->set_dma_mode = &it8213_set_dma_mode; 170 hwif->set_dma_mode = &it8213_set_dma_mode;
171 hwif->set_pio_mode = &it8213_set_pio_mode; 171 hwif->set_pio_mode = &it8213_set_pio_mode;
172 172
173 hwif->drives[0].autotune = 1;
174 hwif->drives[1].autotune = 1;
175
176 if (!hwif->dma_base) 173 if (!hwif->dma_base)
177 return; 174 return;
178 175
179 hwif->atapi_dma = 1;
180 hwif->ultra_mask = 0x7f;
181 hwif->mwdma_mask = 0x06;
182 hwif->swdma_mask = 0x04;
183
184 pci_read_config_byte(hwif->pci_dev, 0x42, &reg42h); 176 pci_read_config_byte(hwif->pci_dev, 0x42, &reg42h);
185 177
186 if (hwif->cbl != ATA_CBL_PATA40_SHORT) 178 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
@@ -192,14 +184,16 @@ static void __devinit init_hwif_it8213(ide_hwif_t *hwif)
192 { \ 184 { \
193 .name = name_str, \ 185 .name = name_str, \
194 .init_hwif = init_hwif_it8213, \ 186 .init_hwif = init_hwif_it8213, \
195 .autodma = AUTODMA, \
196 .enablebits = {{0x41,0x80,0x80}}, \ 187 .enablebits = {{0x41,0x80,0x80}}, \
197 .bootable = ON_BOARD, \ 188 .host_flags = IDE_HFLAG_SINGLE | \
198 .host_flags = IDE_HFLAG_SINGLE, \ 189 IDE_HFLAG_BOOTABLE, \
199 .pio_mask = ATA_PIO4, \ 190 .pio_mask = ATA_PIO4, \
191 .swdma_mask = ATA_SWDMA2_ONLY, \
192 .mwdma_mask = ATA_MWDMA12_ONLY, \
193 .udma_mask = ATA_UDMA6, \
200 } 194 }
201 195
202static ide_pci_device_t it8213_chipsets[] __devinitdata = { 196static const struct ide_port_info it8213_chipsets[] __devinitdata = {
203 /* 0 */ DECLARE_ITE_DEV("IT8213"), 197 /* 0 */ DECLARE_ITE_DEV("IT8213"),
204}; 198};
205 199
diff --git a/drivers/ide/pci/it821x.c b/drivers/ide/pci/it821x.c
index f3391a8698ac..5c9975435319 100644
--- a/drivers/ide/pci/it821x.c
+++ b/drivers/ide/pci/it821x.c
@@ -95,7 +95,7 @@ struct it821x_dev
95 95
96/* 96/*
97 * We allow users to force the card into non raid mode without 97 * We allow users to force the card into non raid mode without
98 * flashing the alternative BIOS. This is also neccessary right now 98 * flashing the alternative BIOS. This is also necessary right now
99 * for embedded platforms that cannot run a PC BIOS but are using this 99 * for embedded platforms that cannot run a PC BIOS but are using this
100 * device. 100 * device.
101 */ 101 */
@@ -544,12 +544,10 @@ static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
544 544
545 ide_set_hwifdata(hwif, idev); 545 ide_set_hwifdata(hwif, idev);
546 546
547 hwif->atapi_dma = 1;
548
549 pci_read_config_byte(hwif->pci_dev, 0x50, &conf); 547 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
550 if(conf & 1) { 548 if (conf & 1) {
551 idev->smart = 1; 549 idev->smart = 1;
552 hwif->atapi_dma = 0; 550 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
553 /* Long I/O's although allowed in LBA48 space cause the 551 /* Long I/O's although allowed in LBA48 space cause the
554 onboard firmware to enter the twighlight zone */ 552 onboard firmware to enter the twighlight zone */
555 hwif->rqsize = 256; 553 hwif->rqsize = 256;
@@ -566,14 +564,14 @@ static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
566 564
567 /* 565 /*
568 * Not in the docs but according to the reference driver 566 * Not in the docs but according to the reference driver
569 * this is neccessary. 567 * this is necessary.
570 */ 568 */
571 569
572 pci_read_config_byte(hwif->pci_dev, 0x08, &conf); 570 pci_read_config_byte(hwif->pci_dev, 0x08, &conf);
573 if(conf == 0x10) { 571 if (conf == 0x10) {
574 idev->timing10 = 1; 572 idev->timing10 = 1;
575 hwif->atapi_dma = 0; 573 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
576 if(!idev->smart) 574 if (idev->smart == 0)
577 printk(KERN_WARNING "it821x: Revision 0x10, workarounds activated.\n"); 575 printk(KERN_WARNING "it821x: Revision 0x10, workarounds activated.\n");
578 } 576 }
579 577
@@ -587,14 +585,11 @@ static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
587 } else 585 } else
588 hwif->host_flags |= IDE_HFLAG_NO_SET_MODE; 586 hwif->host_flags |= IDE_HFLAG_NO_SET_MODE;
589 587
590 hwif->drives[0].autotune = 1;
591 hwif->drives[1].autotune = 1;
592
593 if (hwif->dma_base == 0) 588 if (hwif->dma_base == 0)
594 return; 589 return;
595 590
596 hwif->ultra_mask = 0x7f; 591 hwif->ultra_mask = ATA_UDMA6;
597 hwif->mwdma_mask = 0x07; 592 hwif->mwdma_mask = ATA_MWDMA2;
598 593
599 if (hwif->cbl != ATA_CBL_PATA40_SHORT) 594 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
600 hwif->cbl = ata66_it821x(hwif); 595 hwif->cbl = ata66_it821x(hwif);
@@ -638,13 +633,12 @@ static unsigned int __devinit init_chipset_it821x(struct pci_dev *dev, const cha
638 .name = name_str, \ 633 .name = name_str, \
639 .init_chipset = init_chipset_it821x, \ 634 .init_chipset = init_chipset_it821x, \
640 .init_hwif = init_hwif_it821x, \ 635 .init_hwif = init_hwif_it821x, \
641 .autodma = AUTODMA, \
642 .bootable = ON_BOARD, \
643 .fixup = it821x_fixups, \ 636 .fixup = it821x_fixups, \
637 .host_flags = IDE_HFLAG_BOOTABLE, \
644 .pio_mask = ATA_PIO4, \ 638 .pio_mask = ATA_PIO4, \
645 } 639 }
646 640
647static ide_pci_device_t it821x_chipsets[] __devinitdata = { 641static const struct ide_port_info it821x_chipsets[] __devinitdata = {
648 /* 0 */ DECLARE_ITE_DEV("IT8212"), 642 /* 0 */ DECLARE_ITE_DEV("IT8212"),
649}; 643};
650 644
diff --git a/drivers/ide/pci/jmicron.c b/drivers/ide/pci/jmicron.c
index bb893ffcc987..bdf64d997708 100644
--- a/drivers/ide/pci/jmicron.c
+++ b/drivers/ide/pci/jmicron.c
@@ -111,27 +111,21 @@ static void __devinit init_hwif_jmicron(ide_hwif_t *hwif)
111 hwif->set_pio_mode = &jmicron_set_pio_mode; 111 hwif->set_pio_mode = &jmicron_set_pio_mode;
112 hwif->set_dma_mode = &jmicron_set_dma_mode; 112 hwif->set_dma_mode = &jmicron_set_dma_mode;
113 113
114 hwif->drives[0].autotune = 1;
115 hwif->drives[1].autotune = 1;
116
117 if (hwif->dma_base == 0) 114 if (hwif->dma_base == 0)
118 return; 115 return;
119 116
120 hwif->atapi_dma = 1;
121 hwif->ultra_mask = 0x7f;
122 hwif->mwdma_mask = 0x07;
123
124 if (hwif->cbl != ATA_CBL_PATA40_SHORT) 117 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
125 hwif->cbl = ata66_jmicron(hwif); 118 hwif->cbl = ata66_jmicron(hwif);
126} 119}
127 120
128static ide_pci_device_t jmicron_chipset __devinitdata = { 121static const struct ide_port_info jmicron_chipset __devinitdata = {
129 .name = "JMB", 122 .name = "JMB",
130 .init_hwif = init_hwif_jmicron, 123 .init_hwif = init_hwif_jmicron,
131 .autodma = AUTODMA, 124 .host_flags = IDE_HFLAG_BOOTABLE,
132 .bootable = ON_BOARD,
133 .enablebits = { { 0x40, 0x01, 0x01 }, { 0x40, 0x10, 0x10 } }, 125 .enablebits = { { 0x40, 0x01, 0x01 }, { 0x40, 0x10, 0x10 } },
134 .pio_mask = ATA_PIO5, 126 .pio_mask = ATA_PIO5,
127 .mwdma_mask = ATA_MWDMA2,
128 .udma_mask = ATA_UDMA6,
135}; 129};
136 130
137/** 131/**
diff --git a/drivers/ide/pci/ns87415.c b/drivers/ide/pci/ns87415.c
index a8cd50ab62fb..d4df4642dbb5 100644
--- a/drivers/ide/pci/ns87415.c
+++ b/drivers/ide/pci/ns87415.c
@@ -260,15 +260,15 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
260 hwif->ide_dma_end = &ns87415_ide_dma_end; 260 hwif->ide_dma_end = &ns87415_ide_dma_end;
261} 261}
262 262
263static ide_pci_device_t ns87415_chipset __devinitdata = { 263static const struct ide_port_info ns87415_chipset __devinitdata = {
264 .name = "NS87415", 264 .name = "NS87415",
265#ifdef CONFIG_SUPERIO 265#ifdef CONFIG_SUPERIO
266 .init_iops = init_iops_ns87415, 266 .init_iops = init_iops_ns87415,
267#endif 267#endif
268 .init_hwif = init_hwif_ns87415, 268 .init_hwif = init_hwif_ns87415,
269 .autodma = AUTODMA, 269 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
270 .bootable = ON_BOARD, 270 IDE_HFLAG_NO_ATAPI_DMA |
271 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, 271 IDE_HFLAG_BOOTABLE,
272}; 272};
273 273
274static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id) 274static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
diff --git a/drivers/ide/pci/opti621.c b/drivers/ide/pci/opti621.c
index 250662ea18ad..8953d9c3926f 100644
--- a/drivers/ide/pci/opti621.c
+++ b/drivers/ide/pci/opti621.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/opti621.c Version 0.7 Sept 10, 2002 2 * linux/drivers/ide/pci/opti621.c Version 0.9 Sep 24, 2007
3 * 3 *
4 * Copyright (C) 1996-1998 Linus Torvalds & authors (see below) 4 * Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
5 */ 5 */
@@ -57,9 +57,6 @@
57 * There is a 25/33MHz switch in configuration 57 * There is a 25/33MHz switch in configuration
58 * register, but driver is written for use at any frequency which get 58 * register, but driver is written for use at any frequency which get
59 * (use idebus=xx to select PCI bus speed). 59 * (use idebus=xx to select PCI bus speed).
60 * Use hda=autotune and hdb=autotune for automatical tune of the PIO modes.
61 * If you get strange results, do not use this and set PIO manually
62 * by hdparm.
63 * 60 *
64 * Version 0.1, Nov 8, 1996 61 * Version 0.1, Nov 8, 1996
65 * by Jaromir Koutek, for 2.1.8. 62 * by Jaromir Koutek, for 2.1.8.
@@ -136,6 +133,8 @@ static int reg_base;
136#define PIO_NOT_EXIST 254 133#define PIO_NOT_EXIST 254
137#define PIO_DONT_KNOW 255 134#define PIO_DONT_KNOW 255
138 135
136static DEFINE_SPINLOCK(opti621_lock);
137
139/* there are stored pio numbers from other calls of opti621_set_pio_mode */ 138/* there are stored pio numbers from other calls of opti621_set_pio_mode */
140static void compute_pios(ide_drive_t *drive, const u8 pio) 139static void compute_pios(ide_drive_t *drive, const u8 pio)
141/* Store values into drive->drive_data 140/* Store values into drive->drive_data
@@ -281,7 +280,7 @@ static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
281 second.recovery_time, drdy); 280 second.recovery_time, drdy);
282#endif 281#endif
283 282
284 spin_lock_irqsave(&ide_lock, flags); 283 spin_lock_irqsave(&opti621_lock, flags);
285 284
286 reg_base = hwif->io_ports[IDE_DATA_OFFSET]; 285 reg_base = hwif->io_ports[IDE_DATA_OFFSET];
287 286
@@ -320,7 +319,7 @@ static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
320 /* and read prefetch for both drives */ 319 /* and read prefetch for both drives */
321 write_reg(misc, MISC_REG); 320 write_reg(misc, MISC_REG);
322 321
323 spin_unlock_irqrestore(&ide_lock, flags); 322 spin_unlock_irqrestore(&opti621_lock, flags);
324} 323}
325 324
326/* 325/*
@@ -332,32 +331,27 @@ static void __devinit init_hwif_opti621 (ide_hwif_t *hwif)
332 hwif->drives[1].drive_data = PIO_DONT_KNOW; 331 hwif->drives[1].drive_data = PIO_DONT_KNOW;
333 332
334 hwif->set_pio_mode = &opti621_set_pio_mode; 333 hwif->set_pio_mode = &opti621_set_pio_mode;
335
336 if (!(hwif->dma_base))
337 return;
338
339 hwif->atapi_dma = 1;
340 hwif->mwdma_mask = 0x07;
341 hwif->swdma_mask = 0x07;
342} 334}
343 335
344static ide_pci_device_t opti621_chipsets[] __devinitdata = { 336static const struct ide_port_info opti621_chipsets[] __devinitdata = {
345 { /* 0 */ 337 { /* 0 */
346 .name = "OPTI621", 338 .name = "OPTI621",
347 .init_hwif = init_hwif_opti621, 339 .init_hwif = init_hwif_opti621,
348 .autodma = AUTODMA,
349 .enablebits = {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, 340 .enablebits = {{0x45,0x80,0x00}, {0x40,0x08,0x00}},
350 .bootable = ON_BOARD, 341 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
342 IDE_HFLAG_BOOTABLE,
351 .pio_mask = ATA_PIO3, 343 .pio_mask = ATA_PIO3,
352 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, 344 .swdma_mask = ATA_SWDMA2,
345 .mwdma_mask = ATA_MWDMA2,
353 },{ /* 1 */ 346 },{ /* 1 */
354 .name = "OPTI621X", 347 .name = "OPTI621X",
355 .init_hwif = init_hwif_opti621, 348 .init_hwif = init_hwif_opti621,
356 .autodma = AUTODMA,
357 .enablebits = {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, 349 .enablebits = {{0x45,0x80,0x00}, {0x40,0x08,0x00}},
358 .bootable = ON_BOARD, 350 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
351 IDE_HFLAG_BOOTABLE,
359 .pio_mask = ATA_PIO3, 352 .pio_mask = ATA_PIO3,
360 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, 353 .swdma_mask = ATA_SWDMA2,
354 .mwdma_mask = ATA_MWDMA2,
361 } 355 }
362}; 356};
363 357
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
index 8704b6f33312..4234efeba606 100644
--- a/drivers/ide/pci/pdc202xx_new.c
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -332,16 +332,12 @@ static long __devinit detect_pll_input_clock(unsigned long dma_base)
332static void __devinit apple_kiwi_init(struct pci_dev *pdev) 332static void __devinit apple_kiwi_init(struct pci_dev *pdev)
333{ 333{
334 struct device_node *np = pci_device_to_OF_node(pdev); 334 struct device_node *np = pci_device_to_OF_node(pdev);
335 unsigned int class_rev = 0;
336 u8 conf; 335 u8 conf;
337 336
338 if (np == NULL || !of_device_is_compatible(np, "kiwi-root")) 337 if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
339 return; 338 return;
340 339
341 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev); 340 if (pdev->revision >= 0x03) {
342 class_rev &= 0xff;
343
344 if (class_rev >= 0x03) {
345 /* Setup chip magic config stuff (from darwin) */ 341 /* Setup chip magic config stuff (from darwin) */
346 pci_read_config_byte (pdev, 0x40, &conf); 342 pci_read_config_byte (pdev, 0x40, &conf);
347 pci_write_config_byte(pdev, 0x40, (conf | 0x01)); 343 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
@@ -475,32 +471,76 @@ static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
475 hwif->quirkproc = &pdcnew_quirkproc; 471 hwif->quirkproc = &pdcnew_quirkproc;
476 hwif->resetproc = &pdcnew_reset; 472 hwif->resetproc = &pdcnew_reset;
477 473
478 hwif->err_stops_fifo = 1;
479
480 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
481
482 if (hwif->dma_base == 0) 474 if (hwif->dma_base == 0)
483 return; 475 return;
484 476
485 hwif->atapi_dma = 1;
486
487 hwif->ultra_mask = hwif->cds->udma_mask;
488 hwif->mwdma_mask = 0x07;
489
490 if (hwif->cbl != ATA_CBL_PATA40_SHORT) 477 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
491 hwif->cbl = pdcnew_cable_detect(hwif); 478 hwif->cbl = pdcnew_cable_detect(hwif);
492} 479}
493 480
494static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d) 481static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
495{ 482{
496 return ide_setup_pci_device(dev, d); 483 struct pci_dev *dev2;
484
485 dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 2,
486 PCI_FUNC(dev->devfn)));
487 if (dev2 &&
488 dev2->vendor == dev->vendor &&
489 dev2->device == dev->device) {
490
491 if (dev2->irq != dev->irq) {
492 dev2->irq = dev->irq;
493 printk(KERN_INFO "PDC20270: PCI config space "
494 "interrupt fixed\n");
495 }
496
497 return dev2;
498 }
499
500 return NULL;
497} 501}
498 502
499static int __devinit init_setup_pdc20270(struct pci_dev *dev, ide_pci_device_t *d) 503#define DECLARE_PDCNEW_DEV(name_str, udma) \
504 { \
505 .name = name_str, \
506 .init_chipset = init_chipset_pdcnew, \
507 .init_hwif = init_hwif_pdc202new, \
508 .host_flags = IDE_HFLAG_POST_SET_MODE | \
509 IDE_HFLAG_ERROR_STOPS_FIFO | \
510 IDE_HFLAG_OFF_BOARD, \
511 .pio_mask = ATA_PIO4, \
512 .mwdma_mask = ATA_MWDMA2, \
513 .udma_mask = udma, \
514 }
515
516static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
517 /* 0 */ DECLARE_PDCNEW_DEV("PDC20268", ATA_UDMA5),
518 /* 1 */ DECLARE_PDCNEW_DEV("PDC20269", ATA_UDMA6),
519 /* 2 */ DECLARE_PDCNEW_DEV("PDC20270", ATA_UDMA5),
520 /* 3 */ DECLARE_PDCNEW_DEV("PDC20271", ATA_UDMA6),
521 /* 4 */ DECLARE_PDCNEW_DEV("PDC20275", ATA_UDMA6),
522 /* 5 */ DECLARE_PDCNEW_DEV("PDC20276", ATA_UDMA6),
523 /* 6 */ DECLARE_PDCNEW_DEV("PDC20277", ATA_UDMA6),
524};
525
526/**
527 * pdc202new_init_one - called when a pdc202xx is found
528 * @dev: the pdc202new device
529 * @id: the matching pci id
530 *
531 * Called when the PCI registration layer (or the IDE initialization)
532 * finds a device matching our IDE device tables.
533 */
534
535static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
500{ 536{
537 const struct ide_port_info *d;
501 struct pci_dev *bridge = dev->bus->self; 538 struct pci_dev *bridge = dev->bus->self;
539 u8 idx = id->driver_data;
540
541 d = &pdcnew_chipsets[idx];
502 542
503 if (bridge != NULL && 543 if (idx == 2 && bridge &&
504 bridge->vendor == PCI_VENDOR_ID_DEC && 544 bridge->vendor == PCI_VENDOR_ID_DEC &&
505 bridge->device == PCI_DEVICE_ID_DEC_21150) { 545 bridge->device == PCI_DEVICE_ID_DEC_21150) {
506 struct pci_dev *dev2; 546 struct pci_dev *dev2;
@@ -508,133 +548,26 @@ static int __devinit init_setup_pdc20270(struct pci_dev *dev, ide_pci_device_t *
508 if (PCI_SLOT(dev->devfn) & 2) 548 if (PCI_SLOT(dev->devfn) & 2)
509 return -ENODEV; 549 return -ENODEV;
510 550
511 dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 2, 551 dev2 = pdc20270_get_dev2(dev);
512 PCI_FUNC(dev->devfn)));
513 if (dev2 != NULL &&
514 dev2->vendor == dev->vendor &&
515 dev2->device == dev->device) {
516 int ret;
517
518 if (dev2->irq != dev->irq) {
519 dev2->irq = dev->irq;
520 552
521 printk(KERN_WARNING "%s: PCI config space " 553 if (dev2) {
522 "interrupt fixed.\n", d->name); 554 int ret = ide_setup_pci_devices(dev, dev2, d);
523 }
524
525 ret = ide_setup_pci_devices(dev, dev2, d);
526 if (ret < 0) 555 if (ret < 0)
527 pci_dev_put(dev2); 556 pci_dev_put(dev2);
528 return ret; 557 return ret;
529 } 558 }
530 } 559 }
531 return ide_setup_pci_device(dev, d);
532}
533 560
534static int __devinit init_setup_pdc20276(struct pci_dev *dev, ide_pci_device_t *d) 561 if (idx == 5 && bridge &&
535{
536 struct pci_dev *bridge = dev->bus->self;
537
538 if (bridge != NULL &&
539 bridge->vendor == PCI_VENDOR_ID_INTEL && 562 bridge->vendor == PCI_VENDOR_ID_INTEL &&
540 (bridge->device == PCI_DEVICE_ID_INTEL_I960 || 563 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
541 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) { 564 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
542 565 printk(KERN_INFO "PDC20276: attached to I2O RAID controller, "
543 printk(KERN_INFO "%s: attached to I2O RAID controller, " 566 "skipping\n");
544 "skipping.\n", d->name);
545 return -ENODEV; 567 return -ENODEV;
546 } 568 }
547 return ide_setup_pci_device(dev, d);
548}
549
550static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
551 { /* 0 */
552 .name = "PDC20268",
553 .init_setup = init_setup_pdcnew,
554 .init_chipset = init_chipset_pdcnew,
555 .init_hwif = init_hwif_pdc202new,
556 .autodma = AUTODMA,
557 .bootable = OFF_BOARD,
558 .pio_mask = ATA_PIO4,
559 .udma_mask = 0x3f, /* udma0-5 */
560 .host_flags = IDE_HFLAG_POST_SET_MODE,
561 },{ /* 1 */
562 .name = "PDC20269",
563 .init_setup = init_setup_pdcnew,
564 .init_chipset = init_chipset_pdcnew,
565 .init_hwif = init_hwif_pdc202new,
566 .autodma = AUTODMA,
567 .bootable = OFF_BOARD,
568 .pio_mask = ATA_PIO4,
569 .udma_mask = 0x7f, /* udma0-6*/
570 .host_flags = IDE_HFLAG_POST_SET_MODE,
571 },{ /* 2 */
572 .name = "PDC20270",
573 .init_setup = init_setup_pdc20270,
574 .init_chipset = init_chipset_pdcnew,
575 .init_hwif = init_hwif_pdc202new,
576 .autodma = AUTODMA,
577 .bootable = OFF_BOARD,
578 .pio_mask = ATA_PIO4,
579 .udma_mask = 0x3f, /* udma0-5 */
580 .host_flags = IDE_HFLAG_POST_SET_MODE,
581 },{ /* 3 */
582 .name = "PDC20271",
583 .init_setup = init_setup_pdcnew,
584 .init_chipset = init_chipset_pdcnew,
585 .init_hwif = init_hwif_pdc202new,
586 .autodma = AUTODMA,
587 .bootable = OFF_BOARD,
588 .pio_mask = ATA_PIO4,
589 .udma_mask = 0x7f, /* udma0-6*/
590 .host_flags = IDE_HFLAG_POST_SET_MODE,
591 },{ /* 4 */
592 .name = "PDC20275",
593 .init_setup = init_setup_pdcnew,
594 .init_chipset = init_chipset_pdcnew,
595 .init_hwif = init_hwif_pdc202new,
596 .autodma = AUTODMA,
597 .bootable = OFF_BOARD,
598 .pio_mask = ATA_PIO4,
599 .udma_mask = 0x7f, /* udma0-6*/
600 .host_flags = IDE_HFLAG_POST_SET_MODE,
601 },{ /* 5 */
602 .name = "PDC20276",
603 .init_setup = init_setup_pdc20276,
604 .init_chipset = init_chipset_pdcnew,
605 .init_hwif = init_hwif_pdc202new,
606 .autodma = AUTODMA,
607 .bootable = OFF_BOARD,
608 .pio_mask = ATA_PIO4,
609 .udma_mask = 0x7f, /* udma0-6*/
610 .host_flags = IDE_HFLAG_POST_SET_MODE,
611 },{ /* 6 */
612 .name = "PDC20277",
613 .init_setup = init_setup_pdcnew,
614 .init_chipset = init_chipset_pdcnew,
615 .init_hwif = init_hwif_pdc202new,
616 .autodma = AUTODMA,
617 .bootable = OFF_BOARD,
618 .pio_mask = ATA_PIO4,
619 .udma_mask = 0x7f, /* udma0-6*/
620 .host_flags = IDE_HFLAG_POST_SET_MODE,
621 }
622};
623 569
624/** 570 return ide_setup_pci_device(dev, d);
625 * pdc202new_init_one - called when a pdc202xx is found
626 * @dev: the pdc202new device
627 * @id: the matching pci id
628 *
629 * Called when the PCI registration layer (or the IDE initialization)
630 * finds a device matching our IDE device tables.
631 */
632
633static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
634{
635 ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
636
637 return d->init_setup(dev, d);
638} 571}
639 572
640static const struct pci_device_id pdc202new_pci_tbl[] = { 573static const struct pci_device_id pdc202new_pci_tbl[] = {
diff --git a/drivers/ide/pci/pdc202xx_old.c b/drivers/ide/pci/pdc202xx_old.c
index e1d2337a9f1d..e09742e2ba59 100644
--- a/drivers/ide/pci/pdc202xx_old.c
+++ b/drivers/ide/pci/pdc202xx_old.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/pdc202xx_old.c Version 0.51 Jul 27, 2007 2 * linux/drivers/ide/pci/pdc202xx_old.c Version 0.52 Aug 27, 2007
3 * 3 *
4 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2006-2007 MontaVista Software, Inc. 5 * Copyright (C) 2006-2007 MontaVista Software, Inc.
@@ -97,9 +97,6 @@ static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
97 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break; 97 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
98 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break; 98 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
99 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break; 99 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
100 case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break;
101 case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break;
102 case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break;
103 case XFER_PIO_4: TA = 0x01; TB = 0x04; break; 100 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
104 case XFER_PIO_3: TA = 0x02; TB = 0x06; break; 101 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
105 case XFER_PIO_2: TA = 0x03; TB = 0x08; break; 102 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
@@ -305,13 +302,6 @@ static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
305 302
306static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif) 303static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
307{ 304{
308 struct pci_dev *dev = hwif->pci_dev;
309
310 /* PDC20265 has problems with large LBA48 requests */
311 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
312 (dev->device == PCI_DEVICE_ID_PROMISE_20265))
313 hwif->rqsize = 256;
314
315 hwif->set_pio_mode = &pdc202xx_set_pio_mode; 305 hwif->set_pio_mode = &pdc202xx_set_pio_mode;
316 hwif->set_dma_mode = &pdc202xx_set_mode; 306 hwif->set_dma_mode = &pdc202xx_set_mode;
317 307
@@ -320,18 +310,9 @@ static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
320 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) 310 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
321 hwif->resetproc = &pdc202xx_reset; 311 hwif->resetproc = &pdc202xx_reset;
322 312
323 hwif->err_stops_fifo = 1;
324
325 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
326
327 if (hwif->dma_base == 0) 313 if (hwif->dma_base == 0)
328 return; 314 return;
329 315
330 hwif->ultra_mask = hwif->cds->udma_mask;
331 hwif->mwdma_mask = 0x07;
332 hwif->swdma_mask = 0x07;
333 hwif->atapi_dma = 1;
334
335 hwif->dma_lost_irq = &pdc202xx_dma_lost_irq; 316 hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
336 hwif->dma_timeout = &pdc202xx_dma_timeout; 317 hwif->dma_timeout = &pdc202xx_dma_timeout;
337 318
@@ -377,8 +358,8 @@ static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
377 ide_setup_dma(hwif, dmabase, 8); 358 ide_setup_dma(hwif, dmabase, 8);
378} 359}
379 360
380static int __devinit init_setup_pdc202ata4(struct pci_dev *dev, 361static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
381 ide_pci_device_t *d) 362 const char *name)
382{ 363{
383 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) { 364 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
384 u8 irq = 0, irq2 = 0; 365 u8 irq = 0, irq2 = 0;
@@ -388,90 +369,45 @@ static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
388 if (irq != irq2) { 369 if (irq != irq2) {
389 pci_write_config_byte(dev, 370 pci_write_config_byte(dev,
390 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */ 371 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
391 printk(KERN_INFO "%s: pci-config space interrupt " 372 printk(KERN_INFO "%s: PCI config space interrupt "
392 "mirror fixed.\n", d->name); 373 "mirror fixed\n", name);
393 } 374 }
394 } 375 }
395 return ide_setup_pci_device(dev, d);
396} 376}
397 377
398static int __devinit init_setup_pdc20265(struct pci_dev *dev, 378#define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
399 ide_pci_device_t *d) 379 { \
400{ 380 .name = name_str, \
401 if ((dev->bus->self) && 381 .init_chipset = init_chipset_pdc202xx, \
402 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) && 382 .init_hwif = init_hwif_pdc202xx, \
403 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) || 383 .init_dma = init_dma_pdc202xx, \
404 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) { 384 .extra = 48, \
405 printk(KERN_INFO "ide: Skipping Promise PDC20265 " 385 .host_flags = IDE_HFLAG_ERROR_STOPS_FIFO | \
406 "attached to I2O RAID controller.\n"); 386 extra_flags | \
407 return -ENODEV; 387 IDE_HFLAG_OFF_BOARD, \
388 .pio_mask = ATA_PIO4, \
389 .mwdma_mask = ATA_MWDMA2, \
390 .udma_mask = udma, \
408 } 391 }
409 return ide_setup_pci_device(dev, d);
410}
411 392
412static int __devinit init_setup_pdc202xx(struct pci_dev *dev, 393static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
413 ide_pci_device_t *d)
414{
415 return ide_setup_pci_device(dev, d);
416}
417
418static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
419 { /* 0 */ 394 { /* 0 */
420 .name = "PDC20246", 395 .name = "PDC20246",
421 .init_setup = init_setup_pdc202ata4,
422 .init_chipset = init_chipset_pdc202xx, 396 .init_chipset = init_chipset_pdc202xx,
423 .init_hwif = init_hwif_pdc202xx, 397 .init_hwif = init_hwif_pdc202xx,
424 .init_dma = init_dma_pdc202xx, 398 .init_dma = init_dma_pdc202xx,
425 .autodma = AUTODMA,
426 .bootable = OFF_BOARD,
427 .extra = 16, 399 .extra = 16,
400 .host_flags = IDE_HFLAG_ERROR_STOPS_FIFO |
401 IDE_HFLAG_OFF_BOARD,
428 .pio_mask = ATA_PIO4, 402 .pio_mask = ATA_PIO4,
429 .udma_mask = 0x07, /* udma0-2 */ 403 .mwdma_mask = ATA_MWDMA2,
430 },{ /* 1 */ 404 .udma_mask = ATA_UDMA2,
431 .name = "PDC20262", 405 },
432 .init_setup = init_setup_pdc202ata4, 406
433 .init_chipset = init_chipset_pdc202xx, 407 /* 1 */ DECLARE_PDC2026X_DEV("PDC20262", ATA_UDMA4, 0),
434 .init_hwif = init_hwif_pdc202xx, 408 /* 2 */ DECLARE_PDC2026X_DEV("PDC20263", ATA_UDMA4, 0),
435 .init_dma = init_dma_pdc202xx, 409 /* 3 */ DECLARE_PDC2026X_DEV("PDC20265", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
436 .autodma = AUTODMA, 410 /* 4 */ DECLARE_PDC2026X_DEV("PDC20267", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
437 .bootable = OFF_BOARD,
438 .extra = 48,
439 .pio_mask = ATA_PIO4,
440 .udma_mask = 0x1f, /* udma0-4 */
441 },{ /* 2 */
442 .name = "PDC20263",
443 .init_setup = init_setup_pdc202ata4,
444 .init_chipset = init_chipset_pdc202xx,
445 .init_hwif = init_hwif_pdc202xx,
446 .init_dma = init_dma_pdc202xx,
447 .autodma = AUTODMA,
448 .bootable = OFF_BOARD,
449 .extra = 48,
450 .pio_mask = ATA_PIO4,
451 .udma_mask = 0x1f, /* udma0-4 */
452 },{ /* 3 */
453 .name = "PDC20265",
454 .init_setup = init_setup_pdc20265,
455 .init_chipset = init_chipset_pdc202xx,
456 .init_hwif = init_hwif_pdc202xx,
457 .init_dma = init_dma_pdc202xx,
458 .autodma = AUTODMA,
459 .bootable = OFF_BOARD,
460 .extra = 48,
461 .pio_mask = ATA_PIO4,
462 .udma_mask = 0x3f, /* udma0-5 */
463 },{ /* 4 */
464 .name = "PDC20267",
465 .init_setup = init_setup_pdc202xx,
466 .init_chipset = init_chipset_pdc202xx,
467 .init_hwif = init_hwif_pdc202xx,
468 .init_dma = init_dma_pdc202xx,
469 .autodma = AUTODMA,
470 .bootable = OFF_BOARD,
471 .extra = 48,
472 .pio_mask = ATA_PIO4,
473 .udma_mask = 0x3f, /* udma0-5 */
474 }
475}; 411};
476 412
477/** 413/**
@@ -485,9 +421,28 @@ static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
485 421
486static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) 422static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
487{ 423{
488 ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data]; 424 const struct ide_port_info *d;
425 u8 idx = id->driver_data;
426
427 d = &pdc202xx_chipsets[idx];
428
429 if (idx < 3)
430 pdc202ata4_fixup_irq(dev, d->name);
431
432 if (idx == 3) {
433 struct pci_dev *bridge = dev->bus->self;
489 434
490 return d->init_setup(dev, d); 435 if (bridge &&
436 bridge->vendor == PCI_VENDOR_ID_INTEL &&
437 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
438 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
439 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
440 "attached to I2O RAID controller\n");
441 return -ENODEV;
442 }
443 }
444
445 return ide_setup_pci_device(dev, d);
491} 446}
492 447
493static const struct pci_device_id pdc202xx_pci_tbl[] = { 448static const struct pci_device_id pdc202xx_pci_tbl[] = {
diff --git a/drivers/ide/pci/piix.c b/drivers/ide/pci/piix.c
index a8dd0c0add35..9329d4a810e5 100644
--- a/drivers/ide/pci/piix.c
+++ b/drivers/ide/pci/piix.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/piix.c Version 0.53 Aug 9, 2007 2 * linux/drivers/ide/pci/piix.c Version 0.54 Sep 5, 2007
3 * 3 *
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
@@ -254,53 +254,20 @@ static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
254} 254}
255 255
256/** 256/**
257 * piix_is_ichx - check if ICHx 257 * init_chipset_ich - set up the ICH chipset
258 * @dev: PCI device to check
259 *
260 * returns 1 if ICHx, 0 otherwise.
261 */
262static int piix_is_ichx(struct pci_dev *dev)
263{
264 switch (dev->device) {
265 case PCI_DEVICE_ID_INTEL_82801EB_1:
266 case PCI_DEVICE_ID_INTEL_82801AA_1:
267 case PCI_DEVICE_ID_INTEL_82801AB_1:
268 case PCI_DEVICE_ID_INTEL_82801BA_8:
269 case PCI_DEVICE_ID_INTEL_82801BA_9:
270 case PCI_DEVICE_ID_INTEL_82801CA_10:
271 case PCI_DEVICE_ID_INTEL_82801CA_11:
272 case PCI_DEVICE_ID_INTEL_82801DB_1:
273 case PCI_DEVICE_ID_INTEL_82801DB_10:
274 case PCI_DEVICE_ID_INTEL_82801DB_11:
275 case PCI_DEVICE_ID_INTEL_82801EB_11:
276 case PCI_DEVICE_ID_INTEL_82801E_11:
277 case PCI_DEVICE_ID_INTEL_ESB_2:
278 case PCI_DEVICE_ID_INTEL_ICH6_19:
279 case PCI_DEVICE_ID_INTEL_ICH7_21:
280 case PCI_DEVICE_ID_INTEL_ESB2_18:
281 case PCI_DEVICE_ID_INTEL_ICH8_6:
282 return 1;
283 }
284
285 return 0;
286}
287
288/**
289 * init_chipset_piix - set up the PIIX chipset
290 * @dev: PCI device to set up 258 * @dev: PCI device to set up
291 * @name: Name of the device 259 * @name: Name of the device
292 * 260 *
293 * Initialize the PCI device as required. For the PIIX this turns 261 * Initialize the PCI device as required. For the ICH this turns
294 * out to be nice and simple 262 * out to be nice and simple.
295 */ 263 */
296 264
297static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name) 265static unsigned int __devinit init_chipset_ich(struct pci_dev *dev, const char *name)
298{ 266{
299 if (piix_is_ichx(dev)) { 267 u32 extra = 0;
300 unsigned int extra = 0; 268
301 pci_read_config_dword(dev, 0x54, &extra); 269 pci_read_config_dword(dev, 0x54, &extra);
302 pci_write_config_dword(dev, 0x54, extra|0x400); 270 pci_write_config_dword(dev, 0x54, extra | 0x400);
303 }
304 271
305 return 0; 272 return 0;
306} 273}
@@ -318,9 +285,9 @@ static void piix_dma_clear_irq(ide_drive_t *drive)
318 u8 dma_stat; 285 u8 dma_stat;
319 286
320 /* clear the INTR & ERROR bits */ 287 /* clear the INTR & ERROR bits */
321 dma_stat = hwif->INB(hwif->dma_status); 288 dma_stat = inb(hwif->dma_status);
322 /* Should we force the bit as well ? */ 289 /* Should we force the bit as well ? */
323 hwif->OUTB(dma_stat, hwif->dma_status); 290 outb(dma_stat, hwif->dma_status);
324} 291}
325 292
326struct ich_laptop { 293struct ich_laptop {
@@ -374,35 +341,12 @@ static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
374 341
375static void __devinit init_hwif_piix(ide_hwif_t *hwif) 342static void __devinit init_hwif_piix(ide_hwif_t *hwif)
376{ 343{
377#ifndef CONFIG_IA64
378 if (!hwif->irq)
379 hwif->irq = hwif->channel ? 15 : 14;
380#endif /* CONFIG_IA64 */
381
382 if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
383 /* This is a painful system best to let it self tune for now */
384 return;
385 }
386
387 hwif->set_pio_mode = &piix_set_pio_mode; 344 hwif->set_pio_mode = &piix_set_pio_mode;
388 hwif->set_dma_mode = &piix_set_dma_mode; 345 hwif->set_dma_mode = &piix_set_dma_mode;
389 346
390 hwif->drives[0].autotune = 1;
391 hwif->drives[1].autotune = 1;
392
393 if (!hwif->dma_base) 347 if (!hwif->dma_base)
394 return; 348 return;
395 349
396 /* ICHx need to clear the bmdma status for all interrupts */
397 if (piix_is_ichx(hwif->pci_dev))
398 hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
399
400 hwif->atapi_dma = 1;
401
402 hwif->ultra_mask = hwif->cds->udma_mask;
403 hwif->mwdma_mask = 0x06;
404 hwif->swdma_mask = 0x04;
405
406 if (hwif->ultra_mask & 0x78) { 350 if (hwif->ultra_mask & 0x78) {
407 if (hwif->cbl != ATA_CBL_PATA40_SHORT) 351 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
408 hwif->cbl = piix_cable_detect(hwif); 352 hwif->cbl = piix_cable_detect(hwif);
@@ -412,21 +356,49 @@ static void __devinit init_hwif_piix(ide_hwif_t *hwif)
412 hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0; 356 hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
413} 357}
414 358
359static void __devinit init_hwif_ich(ide_hwif_t *hwif)
360{
361 init_hwif_piix(hwif);
362
363 /* ICHx need to clear the BMDMA status for all interrupts */
364 if (hwif->dma_base)
365 hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
366}
367
368#ifndef CONFIG_IA64
369 #define IDE_HFLAGS_PIIX (IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE)
370#else
371 #define IDE_HFLAGS_PIIX IDE_HFLAG_BOOTABLE
372#endif
373
415#define DECLARE_PIIX_DEV(name_str, udma) \ 374#define DECLARE_PIIX_DEV(name_str, udma) \
416 { \ 375 { \
417 .name = name_str, \ 376 .name = name_str, \
418 .init_chipset = init_chipset_piix, \
419 .init_hwif = init_hwif_piix, \ 377 .init_hwif = init_hwif_piix, \
420 .autodma = AUTODMA, \
421 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ 378 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
422 .bootable = ON_BOARD, \ 379 .host_flags = IDE_HFLAGS_PIIX, \
423 .pio_mask = ATA_PIO4, \ 380 .pio_mask = ATA_PIO4, \
381 .swdma_mask = ATA_SWDMA2_ONLY, \
382 .mwdma_mask = ATA_MWDMA12_ONLY, \
424 .udma_mask = udma, \ 383 .udma_mask = udma, \
425 } 384 }
426 385
427static ide_pci_device_t piix_pci_info[] __devinitdata = { 386#define DECLARE_ICH_DEV(name_str, udma) \
428 /* 0 */ DECLARE_PIIX_DEV("PIIXa", 0x00), /* no udma */ 387 { \
429 /* 1 */ DECLARE_PIIX_DEV("PIIXb", 0x00), /* no udma */ 388 .name = name_str, \
389 .init_chipset = init_chipset_ich, \
390 .init_hwif = init_hwif_ich, \
391 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
392 .host_flags = IDE_HFLAGS_PIIX, \
393 .pio_mask = ATA_PIO4, \
394 .swdma_mask = ATA_SWDMA2_ONLY, \
395 .mwdma_mask = ATA_MWDMA12_ONLY, \
396 .udma_mask = udma, \
397 }
398
399static const struct ide_port_info piix_pci_info[] __devinitdata = {
400 /* 0 */ DECLARE_PIIX_DEV("PIIXa", 0x00), /* no udma */
401 /* 1 */ DECLARE_PIIX_DEV("PIIXb", 0x00), /* no udma */
430 402
431 /* 2 */ 403 /* 2 */
432 { /* 404 { /*
@@ -435,36 +407,35 @@ static ide_pci_device_t piix_pci_info[] __devinitdata = {
435 * of the bit 14 of the IDETIM register at offset 0x6c 407 * of the bit 14 of the IDETIM register at offset 0x6c
436 */ 408 */
437 .name = "MPIIX", 409 .name = "MPIIX",
438 .init_hwif = init_hwif_piix,
439 .autodma = NODMA,
440 .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}}, 410 .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
441 .bootable = ON_BOARD, 411 .host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA |
442 .host_flags = IDE_HFLAG_ISA_PORTS, 412 IDE_HFLAGS_PIIX,
443 .pio_mask = ATA_PIO4, 413 .pio_mask = ATA_PIO4,
414 /* This is a painful system best to let it self tune for now */
444 }, 415 },
445 416
446 /* 3 */ DECLARE_PIIX_DEV("PIIX3", 0x00), /* no udma */ 417 /* 3 */ DECLARE_PIIX_DEV("PIIX3", 0x00), /* no udma */
447 /* 4 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */ 418 /* 4 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
448 /* 5 */ DECLARE_PIIX_DEV("ICH0", 0x07), /* udma0-2 */ 419 /* 5 */ DECLARE_ICH_DEV("ICH0", ATA_UDMA2),
449 /* 6 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */ 420 /* 6 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
450 /* 7 */ DECLARE_PIIX_DEV("ICH", 0x1f), /* udma0-4 */ 421 /* 7 */ DECLARE_ICH_DEV("ICH", ATA_UDMA4),
451 /* 8 */ DECLARE_PIIX_DEV("PIIX4", 0x1f), /* udma0-4 */ 422 /* 8 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA4),
452 /* 9 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */ 423 /* 9 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
453 /* 10 */ DECLARE_PIIX_DEV("ICH2", 0x3f), /* udma0-5 */ 424 /* 10 */ DECLARE_ICH_DEV("ICH2", ATA_UDMA5),
454 /* 11 */ DECLARE_PIIX_DEV("ICH2M", 0x3f), /* udma0-5 */ 425 /* 11 */ DECLARE_ICH_DEV("ICH2M", ATA_UDMA5),
455 /* 12 */ DECLARE_PIIX_DEV("ICH3M", 0x3f), /* udma0-5 */ 426 /* 12 */ DECLARE_ICH_DEV("ICH3M", ATA_UDMA5),
456 /* 13 */ DECLARE_PIIX_DEV("ICH3", 0x3f), /* udma0-5 */ 427 /* 13 */ DECLARE_ICH_DEV("ICH3", ATA_UDMA5),
457 /* 14 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */ 428 /* 14 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
458 /* 15 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */ 429 /* 15 */ DECLARE_ICH_DEV("ICH5", ATA_UDMA5),
459 /* 16 */ DECLARE_PIIX_DEV("C-ICH", 0x3f), /* udma0-5 */ 430 /* 16 */ DECLARE_ICH_DEV("C-ICH", ATA_UDMA5),
460 /* 17 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */ 431 /* 17 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
461 /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA", 0x3f), /* udma0-5 */ 432 /* 18 */ DECLARE_ICH_DEV("ICH5-SATA", ATA_UDMA5),
462 /* 19 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */ 433 /* 19 */ DECLARE_ICH_DEV("ICH5", ATA_UDMA5),
463 /* 20 */ DECLARE_PIIX_DEV("ICH6", 0x3f), /* udma0-5 */ 434 /* 20 */ DECLARE_ICH_DEV("ICH6", ATA_UDMA5),
464 /* 21 */ DECLARE_PIIX_DEV("ICH7", 0x3f), /* udma0-5 */ 435 /* 21 */ DECLARE_ICH_DEV("ICH7", ATA_UDMA5),
465 /* 22 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */ 436 /* 22 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
466 /* 23 */ DECLARE_PIIX_DEV("ESB2", 0x3f), /* udma0-5 */ 437 /* 23 */ DECLARE_ICH_DEV("ESB2", ATA_UDMA5),
467 /* 24 */ DECLARE_PIIX_DEV("ICH8M", 0x3f), /* udma0-5 */ 438 /* 24 */ DECLARE_ICH_DEV("ICH8M", ATA_UDMA5),
468}; 439};
469 440
470/** 441/**
@@ -478,9 +449,7 @@ static ide_pci_device_t piix_pci_info[] __devinitdata = {
478 449
479static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id) 450static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
480{ 451{
481 ide_pci_device_t *d = &piix_pci_info[id->driver_data]; 452 return ide_setup_pci_device(dev, &piix_pci_info[id->driver_data]);
482
483 return ide_setup_pci_device(dev, d);
484} 453}
485 454
486/** 455/**
diff --git a/drivers/ide/pci/rz1000.c b/drivers/ide/pci/rz1000.c
index 3f506e8d44e3..6b10ae260fa2 100644
--- a/drivers/ide/pci/rz1000.c
+++ b/drivers/ide/pci/rz1000.c
@@ -35,13 +35,13 @@ static void __devinit init_hwif_rz1000 (ide_hwif_t *hwif)
35 u16 reg; 35 u16 reg;
36 struct pci_dev *dev = hwif->pci_dev; 36 struct pci_dev *dev = hwif->pci_dev;
37 37
38 hwif->chipset = ide_rz1000;
39 if (!pci_read_config_word (dev, 0x40, &reg) && 38 if (!pci_read_config_word (dev, 0x40, &reg) &&
40 !pci_write_config_word(dev, 0x40, reg & 0xdfff)) { 39 !pci_write_config_word(dev, 0x40, reg & 0xdfff)) {
41 printk(KERN_INFO "%s: disabled chipset read-ahead " 40 printk(KERN_INFO "%s: disabled chipset read-ahead "
42 "(buggy RZ1000/RZ1001)\n", hwif->name); 41 "(buggy RZ1000/RZ1001)\n", hwif->name);
43 } else { 42 } else {
44 hwif->serialized = 1; 43 if (hwif->mate)
44 hwif->mate->serialized = hwif->serialized = 1;
45 hwif->drives[0].no_unmask = 1; 45 hwif->drives[0].no_unmask = 1;
46 hwif->drives[1].no_unmask = 1; 46 hwif->drives[1].no_unmask = 1;
47 printk(KERN_INFO "%s: serialized, disabled unmasking " 47 printk(KERN_INFO "%s: serialized, disabled unmasking "
@@ -49,11 +49,11 @@ static void __devinit init_hwif_rz1000 (ide_hwif_t *hwif)
49 } 49 }
50} 50}
51 51
52static ide_pci_device_t rz1000_chipset __devinitdata = { 52static const struct ide_port_info rz1000_chipset __devinitdata = {
53 .name = "RZ100x", 53 .name = "RZ100x",
54 .init_hwif = init_hwif_rz1000, 54 .init_hwif = init_hwif_rz1000,
55 .autodma = NODMA, 55 .chipset = ide_rz1000,
56 .bootable = ON_BOARD, 56 .host_flags = IDE_HFLAG_NO_DMA | IDE_HFLAG_BOOTABLE,
57}; 57};
58 58
59static int __devinit rz1000_init_one(struct pci_dev *dev, const struct pci_device_id *id) 59static int __devinit rz1000_init_one(struct pci_dev *dev, const struct pci_device_id *id)
diff --git a/drivers/ide/pci/sc1200.c b/drivers/ide/pci/sc1200.c
index 54c5c98a2e26..d2c8b5524f28 100644
--- a/drivers/ide/pci/sc1200.c
+++ b/drivers/ide/pci/sc1200.c
@@ -362,33 +362,26 @@ static int sc1200_resume (struct pci_dev *dev)
362 */ 362 */
363static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif) 363static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif)
364{ 364{
365 if (hwif->mate)
366 hwif->serialized = hwif->mate->serialized = 1;
367
368 hwif->set_pio_mode = &sc1200_set_pio_mode; 365 hwif->set_pio_mode = &sc1200_set_pio_mode;
369 hwif->set_dma_mode = &sc1200_set_dma_mode; 366 hwif->set_dma_mode = &sc1200_set_dma_mode;
370 367
371 hwif->drives[0].autotune = 1;
372 hwif->drives[1].autotune = 1;
373
374 if (hwif->dma_base == 0) 368 if (hwif->dma_base == 0)
375 return; 369 return;
376 370
377 hwif->udma_filter = sc1200_udma_filter; 371 hwif->udma_filter = sc1200_udma_filter;
378 hwif->ide_dma_end = &sc1200_ide_dma_end; 372 hwif->ide_dma_end = &sc1200_ide_dma_end;
379
380 hwif->atapi_dma = 1;
381 hwif->ultra_mask = 0x07;
382 hwif->mwdma_mask = 0x07;
383} 373}
384 374
385static ide_pci_device_t sc1200_chipset __devinitdata = { 375static const struct ide_port_info sc1200_chipset __devinitdata = {
386 .name = "SC1200", 376 .name = "SC1200",
387 .init_hwif = init_hwif_sc1200, 377 .init_hwif = init_hwif_sc1200,
388 .autodma = AUTODMA, 378 .host_flags = IDE_HFLAG_SERIALIZE |
389 .bootable = ON_BOARD, 379 IDE_HFLAG_POST_SET_MODE |
390 .host_flags = IDE_HFLAG_ABUSE_DMA_MODES | IDE_HFLAG_POST_SET_MODE, 380 IDE_HFLAG_ABUSE_DMA_MODES |
381 IDE_HFLAG_BOOTABLE,
391 .pio_mask = ATA_PIO4, 382 .pio_mask = ATA_PIO4,
383 .mwdma_mask = ATA_MWDMA2,
384 .udma_mask = ATA_UDMA2,
392}; 385};
393 386
394static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id) 387static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
diff --git a/drivers/ide/pci/scc_pata.c b/drivers/ide/pci/scc_pata.c
index bd4c1d3070e4..ebb7132b9b84 100644
--- a/drivers/ide/pci/scc_pata.c
+++ b/drivers/ide/pci/scc_pata.c
@@ -472,7 +472,7 @@ static u8 scc_udma_filter(ide_drive_t *drive)
472 if ((drive->media != ide_disk) && (mask & 0xE0)) { 472 if ((drive->media != ide_disk) && (mask & 0xE0)) {
473 printk(KERN_INFO "%s: limit %s to UDMA4\n", 473 printk(KERN_INFO "%s: limit %s to UDMA4\n",
474 SCC_PATA_NAME, drive->name); 474 SCC_PATA_NAME, drive->name);
475 mask = 0x1F; 475 mask = ATA_UDMA4;
476 } 476 }
477 477
478 return mask; 478 return mask;
@@ -538,12 +538,13 @@ static int setup_mmio_scc (struct pci_dev *dev, const char *name)
538/** 538/**
539 * init_setup_scc - set up an SCC PATA Controller 539 * init_setup_scc - set up an SCC PATA Controller
540 * @dev: PCI device 540 * @dev: PCI device
541 * @d: IDE PCI device 541 * @d: IDE port info
542 * 542 *
543 * Perform the initial set up for this device. 543 * Perform the initial set up for this device.
544 */ 544 */
545 545
546static int __devinit init_setup_scc(struct pci_dev *dev, ide_pci_device_t *d) 546static int __devinit init_setup_scc(struct pci_dev *dev,
547 const struct ide_port_info *d)
547{ 548{
548 unsigned long ctl_base; 549 unsigned long ctl_base;
549 unsigned long dma_base; 550 unsigned long dma_base;
@@ -683,17 +684,10 @@ static void __devinit init_hwif_scc(ide_hwif_t *hwif)
683 hwif->ide_dma_test_irq = scc_dma_test_irq; 684 hwif->ide_dma_test_irq = scc_dma_test_irq;
684 hwif->udma_filter = scc_udma_filter; 685 hwif->udma_filter = scc_udma_filter;
685 686
686 hwif->drives[0].autotune = IDE_TUNE_AUTO; 687 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
687 hwif->drives[1].autotune = IDE_TUNE_AUTO; 688 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
688 689 else
689 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) { 690 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
690 hwif->ultra_mask = 0x7f; /* 133MHz */
691 } else {
692 hwif->ultra_mask = 0x3f; /* 100MHz */
693 }
694 hwif->mwdma_mask = 0x00;
695 hwif->swdma_mask = 0x00;
696 hwif->atapi_dma = 1;
697 691
698 /* we support 80c cable only. */ 692 /* we support 80c cable only. */
699 hwif->cbl = ATA_CBL_PATA80; 693 hwif->cbl = ATA_CBL_PATA80;
@@ -702,16 +696,14 @@ static void __devinit init_hwif_scc(ide_hwif_t *hwif)
702#define DECLARE_SCC_DEV(name_str) \ 696#define DECLARE_SCC_DEV(name_str) \
703 { \ 697 { \
704 .name = name_str, \ 698 .name = name_str, \
705 .init_setup = init_setup_scc, \
706 .init_iops = init_iops_scc, \ 699 .init_iops = init_iops_scc, \
707 .init_hwif = init_hwif_scc, \ 700 .init_hwif = init_hwif_scc, \
708 .autodma = AUTODMA, \ 701 .host_flags = IDE_HFLAG_SINGLE | \
709 .bootable = ON_BOARD, \ 702 IDE_HFLAG_BOOTABLE, \
710 .host_flags = IDE_HFLAG_SINGLE, \
711 .pio_mask = ATA_PIO4, \ 703 .pio_mask = ATA_PIO4, \
712 } 704 }
713 705
714static ide_pci_device_t scc_chipsets[] __devinitdata = { 706static const struct ide_port_info scc_chipsets[] __devinitdata = {
715 /* 0 */ DECLARE_SCC_DEV("sccIDE"), 707 /* 0 */ DECLARE_SCC_DEV("sccIDE"),
716}; 708};
717 709
@@ -726,8 +718,7 @@ static ide_pci_device_t scc_chipsets[] __devinitdata = {
726 718
727static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id) 719static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
728{ 720{
729 ide_pci_device_t *d = &scc_chipsets[id->driver_data]; 721 return init_setup_scc(dev, &scc_chipsets[id->driver_data]);
730 return d->init_setup(dev, d);
731} 722}
732 723
733/** 724/**
diff --git a/drivers/ide/pci/serverworks.c b/drivers/ide/pci/serverworks.c
index d3ffc52e22af..a7280311357b 100644
--- a/drivers/ide/pci/serverworks.c
+++ b/drivers/ide/pci/serverworks.c
@@ -158,13 +158,6 @@ static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed)
158 158
159 u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0; 159 u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
160 160
161 /* If we are about to put a disk into UDMA mode we screwed up.
162 Our code assumes we never _ever_ do this on an OSB4 */
163
164 if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
165 drive->media == ide_disk && speed >= XFER_UDMA_0)
166 BUG();
167
168 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing); 161 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
169 pci_read_config_byte(dev, 0x54, &ultra_enable); 162 pci_read_config_byte(dev, 0x54, &ultra_enable);
170 163
@@ -360,23 +353,10 @@ static u8 __devinit ata66_svwks(ide_hwif_t *hwif)
360 353
361static void __devinit init_hwif_svwks (ide_hwif_t *hwif) 354static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
362{ 355{
363 if (!hwif->irq)
364 hwif->irq = hwif->channel ? 15 : 14;
365
366 hwif->set_pio_mode = &svwks_set_pio_mode; 356 hwif->set_pio_mode = &svwks_set_pio_mode;
367 hwif->set_dma_mode = &svwks_set_dma_mode; 357 hwif->set_dma_mode = &svwks_set_dma_mode;
368 hwif->udma_filter = &svwks_udma_filter; 358 hwif->udma_filter = &svwks_udma_filter;
369 359
370 hwif->atapi_dma = 1;
371
372 if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
373 hwif->ultra_mask = 0x3f;
374
375 hwif->mwdma_mask = 0x07;
376
377 hwif->drives[0].autotune = 1;
378 hwif->drives[1].autotune = 1;
379
380 if (!hwif->dma_base) 360 if (!hwif->dma_base)
381 return; 361 return;
382 362
@@ -386,72 +366,49 @@ static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
386 } 366 }
387} 367}
388 368
389static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d) 369static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
390{
391 return ide_setup_pci_device(dev, d);
392}
393
394static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
395{
396 if (!(PCI_FUNC(dev->devfn) & 1)) {
397 d->bootable = NEVER_BOARD;
398 if (dev->resource[0].start == 0x01f1)
399 d->bootable = ON_BOARD;
400 }
401
402 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
403 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
404 (!(PCI_FUNC(dev->devfn) & 1)))
405 d->host_flags |= IDE_HFLAG_SINGLE;
406 else
407 d->host_flags &= ~IDE_HFLAG_SINGLE;
408
409 return ide_setup_pci_device(dev, d);
410}
411
412static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
413 { /* 0 */ 370 { /* 0 */
414 .name = "SvrWks OSB4", 371 .name = "SvrWks OSB4",
415 .init_setup = init_setup_svwks,
416 .init_chipset = init_chipset_svwks, 372 .init_chipset = init_chipset_svwks,
417 .init_hwif = init_hwif_svwks, 373 .init_hwif = init_hwif_svwks,
418 .autodma = AUTODMA, 374 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
419 .bootable = ON_BOARD,
420 .pio_mask = ATA_PIO4, 375 .pio_mask = ATA_PIO4,
376 .mwdma_mask = ATA_MWDMA2,
377 .udma_mask = 0x00, /* UDMA is problematic on OSB4 */
421 },{ /* 1 */ 378 },{ /* 1 */
422 .name = "SvrWks CSB5", 379 .name = "SvrWks CSB5",
423 .init_setup = init_setup_svwks,
424 .init_chipset = init_chipset_svwks, 380 .init_chipset = init_chipset_svwks,
425 .init_hwif = init_hwif_svwks, 381 .init_hwif = init_hwif_svwks,
426 .autodma = AUTODMA, 382 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
427 .bootable = ON_BOARD,
428 .pio_mask = ATA_PIO4, 383 .pio_mask = ATA_PIO4,
384 .mwdma_mask = ATA_MWDMA2,
385 .udma_mask = ATA_UDMA5,
429 },{ /* 2 */ 386 },{ /* 2 */
430 .name = "SvrWks CSB6", 387 .name = "SvrWks CSB6",
431 .init_setup = init_setup_csb6,
432 .init_chipset = init_chipset_svwks, 388 .init_chipset = init_chipset_svwks,
433 .init_hwif = init_hwif_svwks, 389 .init_hwif = init_hwif_svwks,
434 .autodma = AUTODMA, 390 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
435 .bootable = ON_BOARD,
436 .pio_mask = ATA_PIO4, 391 .pio_mask = ATA_PIO4,
392 .mwdma_mask = ATA_MWDMA2,
393 .udma_mask = ATA_UDMA5,
437 },{ /* 3 */ 394 },{ /* 3 */
438 .name = "SvrWks CSB6", 395 .name = "SvrWks CSB6",
439 .init_setup = init_setup_csb6,
440 .init_chipset = init_chipset_svwks, 396 .init_chipset = init_chipset_svwks,
441 .init_hwif = init_hwif_svwks, 397 .init_hwif = init_hwif_svwks,
442 .autodma = AUTODMA, 398 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_SINGLE |
443 .bootable = ON_BOARD, 399 IDE_HFLAG_BOOTABLE,
444 .host_flags = IDE_HFLAG_SINGLE,
445 .pio_mask = ATA_PIO4, 400 .pio_mask = ATA_PIO4,
401 .mwdma_mask = ATA_MWDMA2,
402 .udma_mask = ATA_UDMA5,
446 },{ /* 4 */ 403 },{ /* 4 */
447 .name = "SvrWks HT1000", 404 .name = "SvrWks HT1000",
448 .init_setup = init_setup_svwks,
449 .init_chipset = init_chipset_svwks, 405 .init_chipset = init_chipset_svwks,
450 .init_hwif = init_hwif_svwks, 406 .init_hwif = init_hwif_svwks,
451 .autodma = AUTODMA, 407 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_SINGLE |
452 .bootable = ON_BOARD, 408 IDE_HFLAG_BOOTABLE,
453 .host_flags = IDE_HFLAG_SINGLE,
454 .pio_mask = ATA_PIO4, 409 .pio_mask = ATA_PIO4,
410 .mwdma_mask = ATA_MWDMA2,
411 .udma_mask = ATA_UDMA5,
455 } 412 }
456}; 413};
457 414
@@ -466,9 +423,21 @@ static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
466 423
467static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id) 424static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
468{ 425{
469 ide_pci_device_t *d = &serverworks_chipsets[id->driver_data]; 426 struct ide_port_info d;
427 u8 idx = id->driver_data;
428
429 d = serverworks_chipsets[idx];
430
431 if (idx == 2 || idx == 3) {
432 if ((PCI_FUNC(dev->devfn) & 1) == 0) {
433 if (pci_resource_start(dev, 0) != 0x01f1)
434 d.host_flags &= ~IDE_HFLAG_BOOTABLE;
435 d.host_flags |= IDE_HFLAG_SINGLE;
436 } else
437 d.host_flags &= ~IDE_HFLAG_SINGLE;
438 }
470 439
471 return d->init_setup(dev, d); 440 return ide_setup_pci_device(dev, &d);
472} 441}
473 442
474static const struct pci_device_id svwks_pci_tbl[] = { 443static const struct pci_device_id svwks_pci_tbl[] = {
diff --git a/drivers/ide/pci/sgiioc4.c b/drivers/ide/pci/sgiioc4.c
index 9a9474f534e5..de820aa58cd0 100644
--- a/drivers/ide/pci/sgiioc4.c
+++ b/drivers/ide/pci/sgiioc4.c
@@ -592,8 +592,7 @@ ide_init_sgiioc4(ide_hwif_t * hwif)
592 if (hwif->dma_base == 0) 592 if (hwif->dma_base == 0)
593 return; 593 return;
594 594
595 hwif->atapi_dma = 1; 595 hwif->mwdma_mask = ATA_MWDMA2_ONLY;
596 hwif->mwdma_mask = 0x04;
597 596
598 hwif->dma_setup = &sgiioc4_ide_dma_setup; 597 hwif->dma_setup = &sgiioc4_ide_dma_setup;
599 hwif->dma_start = &sgiioc4_ide_dma_start; 598 hwif->dma_start = &sgiioc4_ide_dma_start;
@@ -615,6 +614,7 @@ sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
615 void __iomem *virt_base; 614 void __iomem *virt_base;
616 ide_hwif_t *hwif; 615 ide_hwif_t *hwif;
617 int h; 616 int h;
617 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
618 618
619 /* 619 /*
620 * Find an empty HWIF; if none available, return -ENOMEM. 620 * Find an empty HWIF; if none available, return -ENOMEM.
@@ -655,10 +655,12 @@ sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
655 } 655 }
656 656
657 if (hwif->io_ports[IDE_DATA_OFFSET] != cmd_base) { 657 if (hwif->io_ports[IDE_DATA_OFFSET] != cmd_base) {
658 hw_regs_t hw;
659
658 /* Initialize the IO registers */ 660 /* Initialize the IO registers */
659 sgiioc4_init_hwif_ports(&hwif->hw, cmd_base, ctl, irqport); 661 memset(&hw, 0, sizeof(hw));
660 memcpy(hwif->io_ports, hwif->hw.io_ports, 662 sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport);
661 sizeof (hwif->io_ports)); 663 memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports));
662 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET]; 664 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
663 } 665 }
664 666
@@ -680,11 +682,10 @@ sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
680 682
681 ide_init_sgiioc4(hwif); 683 ide_init_sgiioc4(hwif);
682 684
683 if (probe_hwif_init(hwif)) 685 idx[0] = hwif->index;
684 return -EIO;
685 686
686 /* Create /proc/ide entries */ 687 if (ide_device_add(idx))
687 ide_proc_register_port(hwif); 688 return -EIO;
688 689
689 return 0; 690 return 0;
690} 691}
@@ -692,14 +693,12 @@ sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
692static unsigned int __devinit 693static unsigned int __devinit
693pci_init_sgiioc4(struct pci_dev *dev) 694pci_init_sgiioc4(struct pci_dev *dev)
694{ 695{
695 unsigned int class_rev;
696 int ret; 696 int ret;
697 697
698 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
699 class_rev &= 0xff;
700 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n", 698 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
701 DRV_NAME, pci_name(dev), class_rev); 699 DRV_NAME, pci_name(dev), dev->revision);
702 if (class_rev < IOC4_SUPPORTED_FIRMWARE_REV) { 700
701 if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) {
703 printk(KERN_ERR "Skipping %s IDE controller in slot %s: " 702 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
704 "firmware is obsolete - please upgrade to " 703 "firmware is obsolete - please upgrade to "
705 "revision46 or higher\n", 704 "revision46 or higher\n",
diff --git a/drivers/ide/pci/siimage.c b/drivers/ide/pci/siimage.c
index 85d0afd00e66..6d99441c605b 100644
--- a/drivers/ide/pci/siimage.c
+++ b/drivers/ide/pci/siimage.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/siimage.c Version 1.16 Jul 13 2007 2 * linux/drivers/ide/pci/siimage.c Version 1.18 Oct 18 2007
3 * 3 *
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com> 5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
@@ -26,7 +26,7 @@
26 * 26 *
27 * If you have strange problems with nVidia chipset systems please 27 * If you have strange problems with nVidia chipset systems please
28 * see the SI support documentation and update your system BIOS 28 * see the SI support documentation and update your system BIOS
29 * if neccessary 29 * if necessary
30 * 30 *
31 * The Dell DRAC4 has some interesting features including effectively hot 31 * The Dell DRAC4 has some interesting features including effectively hot
32 * unplugging/replugging the virtual CD interface when the DRAC is reset. 32 * unplugging/replugging the virtual CD interface when the DRAC is reset.
@@ -57,8 +57,8 @@
57 57
58static int pdev_is_sata(struct pci_dev *pdev) 58static int pdev_is_sata(struct pci_dev *pdev)
59{ 59{
60 switch(pdev->device) 60#ifdef CONFIG_BLK_DEV_IDE_SATA
61 { 61 switch(pdev->device) {
62 case PCI_DEVICE_ID_SII_3112: 62 case PCI_DEVICE_ID_SII_3112:
63 case PCI_DEVICE_ID_SII_1210SA: 63 case PCI_DEVICE_ID_SII_1210SA:
64 return 1; 64 return 1;
@@ -66,9 +66,10 @@ static int pdev_is_sata(struct pci_dev *pdev)
66 return 0; 66 return 0;
67 } 67 }
68 BUG(); 68 BUG();
69#endif
69 return 0; 70 return 0;
70} 71}
71 72
72/** 73/**
73 * is_sata - check if hwif is SATA 74 * is_sata - check if hwif is SATA
74 * @hwif: interface to check 75 * @hwif: interface to check
@@ -136,7 +137,7 @@ static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
136 * SI3112 SATA controller life is a bit simpler. 137 * SI3112 SATA controller life is a bit simpler.
137 */ 138 */
138 139
139static u8 sil_udma_filter(ide_drive_t *drive) 140static u8 sil_pata_udma_filter(ide_drive_t *drive)
140{ 141{
141 ide_hwif_t *hwif = drive->hwif; 142 ide_hwif_t *hwif = drive->hwif;
142 unsigned long base = (unsigned long) hwif->hwif_data; 143 unsigned long base = (unsigned long) hwif->hwif_data;
@@ -147,23 +148,23 @@ static u8 sil_udma_filter(ide_drive_t *drive)
147 else 148 else
148 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc); 149 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
149 150
150 if (is_sata(hwif)) {
151 mask = strstr(drive->id->model, "Maxtor") ? 0x3f : 0x7f;
152 goto out;
153 }
154
155 if ((scsc & 0x30) == 0x10) /* 133 */ 151 if ((scsc & 0x30) == 0x10) /* 133 */
156 mask = 0x7f; 152 mask = ATA_UDMA6;
157 else if ((scsc & 0x30) == 0x20) /* 2xPCI */ 153 else if ((scsc & 0x30) == 0x20) /* 2xPCI */
158 mask = 0x7f; 154 mask = ATA_UDMA6;
159 else if ((scsc & 0x30) == 0x00) /* 100 */ 155 else if ((scsc & 0x30) == 0x00) /* 100 */
160 mask = 0x3f; 156 mask = ATA_UDMA5;
161 else /* Disabled ? */ 157 else /* Disabled ? */
162 BUG(); 158 BUG();
163out: 159
164 return mask; 160 return mask;
165} 161}
166 162
163static u8 sil_sata_udma_filter(ide_drive_t *drive)
164{
165 return strstr(drive->id->model, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6;
166}
167
167/** 168/**
168 * sil_set_pio_mode - set host controller for PIO mode 169 * sil_set_pio_mode - set host controller for PIO mode
169 * @drive: drive 170 * @drive: drive
@@ -180,7 +181,7 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
180 const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 181 const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
181 182
182 ide_hwif_t *hwif = HWIF(drive); 183 ide_hwif_t *hwif = HWIF(drive);
183 ide_drive_t *pair = &hwif->drives[drive->dn ^ 1]; 184 ide_drive_t *pair = ide_get_paired_drive(drive);
184 u32 speedt = 0; 185 u32 speedt = 0;
185 u16 speedp = 0; 186 u16 speedp = 0;
186 unsigned long addr = siimage_seldev(drive, 0x04); 187 unsigned long addr = siimage_seldev(drive, 0x04);
@@ -340,10 +341,11 @@ static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
340static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive) 341static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
341{ 342{
342 ide_hwif_t *hwif = HWIF(drive); 343 ide_hwif_t *hwif = HWIF(drive);
343 unsigned long base = (unsigned long)hwif->hwif_data;
344 unsigned long addr = siimage_selreg(hwif, 0x1); 344 unsigned long addr = siimage_selreg(hwif, 0x1);
345 345
346 if (SATA_ERROR_REG) { 346 if (SATA_ERROR_REG) {
347 unsigned long base = (unsigned long)hwif->hwif_data;
348
347 u32 ext_stat = readl((void __iomem *)(base + 0x10)); 349 u32 ext_stat = readl((void __iomem *)(base + 0x10));
348 u8 watchdog = 0; 350 u8 watchdog = 0;
349 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { 351 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
@@ -376,7 +378,7 @@ static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
376} 378}
377 379
378/** 380/**
379 * siimage_busproc - bus isolation ioctl 381 * sil_sata_busproc - bus isolation IOCTL
380 * @drive: drive to isolate/restore 382 * @drive: drive to isolate/restore
381 * @state: bus state to set 383 * @state: bus state to set
382 * 384 *
@@ -384,8 +386,8 @@ static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
384 * SATA controller the work required is quite limited, we 386 * SATA controller the work required is quite limited, we
385 * just have to clean up the statistics 387 * just have to clean up the statistics
386 */ 388 */
387 389
388static int siimage_busproc (ide_drive_t * drive, int state) 390static int sil_sata_busproc(ide_drive_t * drive, int state)
389{ 391{
390 ide_hwif_t *hwif = HWIF(drive); 392 ide_hwif_t *hwif = HWIF(drive);
391 u32 stat_config = 0; 393 u32 stat_config = 0;
@@ -417,14 +419,14 @@ static int siimage_busproc (ide_drive_t * drive, int state)
417} 419}
418 420
419/** 421/**
420 * siimage_reset_poll - wait for sata reset 422 * sil_sata_reset_poll - wait for SATA reset
421 * @drive: drive we are resetting 423 * @drive: drive we are resetting
422 * 424 *
423 * Poll the SATA phy and see whether it has come back from the dead 425 * Poll the SATA phy and see whether it has come back from the dead
424 * yet. 426 * yet.
425 */ 427 */
426 428
427static int siimage_reset_poll (ide_drive_t *drive) 429static int sil_sata_reset_poll(ide_drive_t *drive)
428{ 430{
429 if (SATA_STATUS_REG) { 431 if (SATA_STATUS_REG) {
430 ide_hwif_t *hwif = HWIF(drive); 432 ide_hwif_t *hwif = HWIF(drive);
@@ -436,27 +438,22 @@ static int siimage_reset_poll (ide_drive_t *drive)
436 HWGROUP(drive)->polling = 0; 438 HWGROUP(drive)->polling = 0;
437 return ide_started; 439 return ide_started;
438 } 440 }
439 return 0;
440 } else {
441 return 0;
442 } 441 }
442
443 return 0;
443} 444}
444 445
445/** 446/**
446 * siimage_pre_reset - reset hook 447 * sil_sata_pre_reset - reset hook
447 * @drive: IDE device being reset 448 * @drive: IDE device being reset
448 * 449 *
449 * For the SATA devices we need to handle recalibration/geometry 450 * For the SATA devices we need to handle recalibration/geometry
450 * differently 451 * differently
451 */ 452 */
452
453static void siimage_pre_reset (ide_drive_t *drive)
454{
455 if (drive->media != ide_disk)
456 return;
457 453
458 if (is_sata(HWIF(drive))) 454static void sil_sata_pre_reset(ide_drive_t *drive)
459 { 455{
456 if (drive->media == ide_disk) {
460 drive->special.b.set_geometry = 0; 457 drive->special.b.set_geometry = 0;
461 drive->special.b.recalibrate = 0; 458 drive->special.b.recalibrate = 0;
462 } 459 }
@@ -502,7 +499,6 @@ static void siimage_reset (ide_drive_t *drive)
502 drive->failures++; 499 drive->failures++;
503 } 500 }
504 } 501 }
505
506} 502}
507 503
508/** 504/**
@@ -640,13 +636,9 @@ static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
640 636
641static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name) 637static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
642{ 638{
643 u32 class_rev = 0; 639 u8 rev = dev->revision, tmpbyte = 0, BA5_EN = 0;
644 u8 tmpbyte = 0;
645 u8 BA5_EN = 0;
646 640
647 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 641 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
648 class_rev &= 0xff;
649 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
650 642
651 pci_read_config_byte(dev, 0x8A, &BA5_EN); 643 pci_read_config_byte(dev, 0x8A, &BA5_EN);
652 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) { 644 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
@@ -762,16 +754,11 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
762 hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148; 754 hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148;
763 } 755 }
764 756
765 hw.irq = hwif->pci_dev->irq; 757 memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports));
766
767 memcpy(&hwif->hw, &hw, sizeof(hw));
768 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
769 758
770 hwif->irq = hw.irq; 759 hwif->irq = dev->irq;
771 760
772 base = (unsigned long) addr; 761 hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
773
774 hwif->dma_base = base + (ch ? 0x08 : 0x00);
775 762
776 hwif->mmio = 1; 763 hwif->mmio = 1;
777} 764}
@@ -825,19 +812,14 @@ static void __devinit siimage_fixup(ide_hwif_t *hwif)
825 812
826static void __devinit init_iops_siimage(ide_hwif_t *hwif) 813static void __devinit init_iops_siimage(ide_hwif_t *hwif)
827{ 814{
828 struct pci_dev *dev = hwif->pci_dev;
829 u32 class_rev = 0;
830
831 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
832 class_rev &= 0xff;
833
834 hwif->hwif_data = NULL; 815 hwif->hwif_data = NULL;
835 816
836 /* Pessimal until we finish probing */ 817 /* Pessimal until we finish probing */
837 hwif->rqsize = 15; 818 hwif->rqsize = 15;
838 819
839 if (pci_get_drvdata(dev) == NULL) 820 if (pci_get_drvdata(hwif->pci_dev) == NULL)
840 return; 821 return;
822
841 init_mmio_iops_siimage(hwif); 823 init_mmio_iops_siimage(hwif);
842} 824}
843 825
@@ -873,34 +855,32 @@ static u8 __devinit ata66_siimage(ide_hwif_t *hwif)
873 855
874static void __devinit init_hwif_siimage(ide_hwif_t *hwif) 856static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
875{ 857{
858 u8 sata = is_sata(hwif);
859
876 hwif->resetproc = &siimage_reset; 860 hwif->resetproc = &siimage_reset;
877 hwif->set_pio_mode = &sil_set_pio_mode; 861 hwif->set_pio_mode = &sil_set_pio_mode;
878 hwif->set_dma_mode = &sil_set_dma_mode; 862 hwif->set_dma_mode = &sil_set_dma_mode;
879 hwif->reset_poll = &siimage_reset_poll;
880 hwif->pre_reset = &siimage_pre_reset;
881 hwif->udma_filter = &sil_udma_filter;
882 863
883 if(is_sata(hwif)) { 864 if (sata) {
884 static int first = 1; 865 static int first = 1;
885 866
886 hwif->busproc = &siimage_busproc; 867 hwif->busproc = &sil_sata_busproc;
868 hwif->reset_poll = &sil_sata_reset_poll;
869 hwif->pre_reset = &sil_sata_pre_reset;
870 hwif->udma_filter = &sil_sata_udma_filter;
887 871
888 if (first) { 872 if (first) {
889 printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n"); 873 printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n");
890 first = 0; 874 first = 0;
891 } 875 }
892 } 876 } else
893 877 hwif->udma_filter = &sil_pata_udma_filter;
894 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
895 878
896 if (hwif->dma_base == 0) 879 if (hwif->dma_base == 0)
897 return; 880 return;
898 881
899 hwif->ultra_mask = 0x7f; 882 if (sata)
900 hwif->mwdma_mask = 0x07; 883 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
901
902 if (!is_sata(hwif))
903 hwif->atapi_dma = 1;
904 884
905 if (hwif->cbl != ATA_CBL_PATA40_SHORT) 885 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
906 hwif->cbl = ata66_siimage(hwif); 886 hwif->cbl = ata66_siimage(hwif);
@@ -919,12 +899,13 @@ static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
919 .init_iops = init_iops_siimage, \ 899 .init_iops = init_iops_siimage, \
920 .init_hwif = init_hwif_siimage, \ 900 .init_hwif = init_hwif_siimage, \
921 .fixup = siimage_fixup, \ 901 .fixup = siimage_fixup, \
922 .autodma = AUTODMA, \ 902 .host_flags = IDE_HFLAG_BOOTABLE, \
923 .bootable = ON_BOARD, \
924 .pio_mask = ATA_PIO4, \ 903 .pio_mask = ATA_PIO4, \
904 .mwdma_mask = ATA_MWDMA2, \
905 .udma_mask = ATA_UDMA6, \
925 } 906 }
926 907
927static ide_pci_device_t siimage_chipsets[] __devinitdata = { 908static const struct ide_port_info siimage_chipsets[] __devinitdata = {
928 /* 0 */ DECLARE_SII_DEV("SiI680"), 909 /* 0 */ DECLARE_SII_DEV("SiI680"),
929 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"), 910 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
930 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA") 911 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
diff --git a/drivers/ide/pci/sis5513.c b/drivers/ide/pci/sis5513.c
index 5a54e2e20b3c..6b7bb53acefd 100644
--- a/drivers/ide/pci/sis5513.c
+++ b/drivers/ide/pci/sis5513.c
@@ -264,7 +264,7 @@ static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode)
264 if (mode >= XFER_MW_DMA_0) { 264 if (mode >= XFER_MW_DMA_0) {
265 t1 &= ~0x04; /* disable UDMA */ 265 t1 &= ~0x04; /* disable UDMA */
266 idx = mode - XFER_MW_DMA_0 + 5; 266 idx = mode - XFER_MW_DMA_0 + 5;
267 } 267 } else
268 idx = mode - XFER_PIO_0; 268 idx = mode - XFER_PIO_0;
269 t1 |= ini_time_value[clk][idx] << 12; 269 t1 |= ini_time_value[clk][idx] << 12;
270 t1 |= act_time_value[clk][idx] << 16; 270 t1 |= act_time_value[clk][idx] << 16;
@@ -564,38 +564,30 @@ static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
564{ 564{
565 u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f }; 565 u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
566 566
567 if (!hwif->irq)
568 hwif->irq = hwif->channel ? 15 : 14;
569
570 hwif->set_pio_mode = &sis_set_pio_mode; 567 hwif->set_pio_mode = &sis_set_pio_mode;
571 hwif->set_dma_mode = &sis_set_dma_mode; 568 hwif->set_dma_mode = &sis_set_dma_mode;
572 569
573 if (chipset_family >= ATA_133) 570 if (chipset_family >= ATA_133)
574 hwif->udma_filter = sis5513_ata133_udma_filter; 571 hwif->udma_filter = sis5513_ata133_udma_filter;
575 572
576 hwif->drives[0].autotune = 1;
577 hwif->drives[1].autotune = 1;
578
579 if (hwif->dma_base == 0) 573 if (hwif->dma_base == 0)
580 return; 574 return;
581 575
582 hwif->atapi_dma = 1;
583
584 hwif->ultra_mask = udma_rates[chipset_family]; 576 hwif->ultra_mask = udma_rates[chipset_family];
585 hwif->mwdma_mask = 0x07;
586 577
587 if (hwif->cbl != ATA_CBL_PATA40_SHORT) 578 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
588 hwif->cbl = ata66_sis5513(hwif); 579 hwif->cbl = ata66_sis5513(hwif);
589} 580}
590 581
591static ide_pci_device_t sis5513_chipset __devinitdata = { 582static const struct ide_port_info sis5513_chipset __devinitdata = {
592 .name = "SIS5513", 583 .name = "SIS5513",
593 .init_chipset = init_chipset_sis5513, 584 .init_chipset = init_chipset_sis5513,
594 .init_hwif = init_hwif_sis5513, 585 .init_hwif = init_hwif_sis5513,
595 .autodma = NOAUTODMA,
596 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 586 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
597 .bootable = ON_BOARD, 587 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA |
588 IDE_HFLAG_BOOTABLE,
598 .pio_mask = ATA_PIO4, 589 .pio_mask = ATA_PIO4,
590 .mwdma_mask = ATA_MWDMA2,
599}; 591};
600 592
601static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id) 593static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
diff --git a/drivers/ide/pci/sl82c105.c b/drivers/ide/pci/sl82c105.c
index 771efb8884c8..147d783f7529 100644
--- a/drivers/ide/pci/sl82c105.c
+++ b/drivers/ide/pci/sl82c105.c
@@ -361,19 +361,6 @@ static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
361 hwif->selectproc = &sl82c105_selectproc; 361 hwif->selectproc = &sl82c105_selectproc;
362 hwif->resetproc = &sl82c105_resetproc; 362 hwif->resetproc = &sl82c105_resetproc;
363 363
364 /*
365 * We support 32-bit I/O on this interface, and
366 * it doesn't have problems with interrupts.
367 */
368 hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1;
369 hwif->drives[0].unmask = hwif->drives[1].unmask = 1;
370
371 /*
372 * We always autotune PIO, this is done before DMA is checked,
373 * so there's no risk of accidentally disabling DMA
374 */
375 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
376
377 if (!hwif->dma_base) 364 if (!hwif->dma_base)
378 return; 365 return;
379 366
@@ -388,8 +375,7 @@ static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
388 return; 375 return;
389 } 376 }
390 377
391 hwif->atapi_dma = 1; 378 hwif->mwdma_mask = ATA_MWDMA2;
392 hwif->mwdma_mask = 0x07;
393 379
394 hwif->ide_dma_on = &sl82c105_ide_dma_on; 380 hwif->ide_dma_on = &sl82c105_ide_dma_on;
395 hwif->dma_off_quietly = &sl82c105_dma_off_quietly; 381 hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
@@ -401,13 +387,15 @@ static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
401 hwif->serialized = hwif->mate->serialized = 1; 387 hwif->serialized = hwif->mate->serialized = 1;
402} 388}
403 389
404static ide_pci_device_t sl82c105_chipset __devinitdata = { 390static const struct ide_port_info sl82c105_chipset __devinitdata = {
405 .name = "W82C105", 391 .name = "W82C105",
406 .init_chipset = init_chipset_sl82c105, 392 .init_chipset = init_chipset_sl82c105,
407 .init_hwif = init_hwif_sl82c105, 393 .init_hwif = init_hwif_sl82c105,
408 .autodma = NOAUTODMA,
409 .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, 394 .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
410 .bootable = ON_BOARD, 395 .host_flags = IDE_HFLAG_IO_32BIT |
396 IDE_HFLAG_UNMASK_IRQS |
397 IDE_HFLAG_NO_AUTODMA |
398 IDE_HFLAG_BOOTABLE,
411 .pio_mask = ATA_PIO5, 399 .pio_mask = ATA_PIO5,
412}; 400};
413 401
diff --git a/drivers/ide/pci/slc90e66.c b/drivers/ide/pci/slc90e66.c
index fa8df6d43832..eb4445b229ed 100644
--- a/drivers/ide/pci/slc90e66.c
+++ b/drivers/ide/pci/slc90e66.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/slc90e66.c Version 0.18 Aug 9, 2007 2 * linux/drivers/ide/pci/slc90e66.c Version 0.19 Sep 24, 2007
3 * 3 *
4 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> 5 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
@@ -21,6 +21,8 @@
21 21
22#include <asm/io.h> 22#include <asm/io.h>
23 23
24static DEFINE_SPINLOCK(slc90e66_lock);
25
24static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio) 26static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
25{ 27{
26 ide_hwif_t *hwif = HWIF(drive); 28 ide_hwif_t *hwif = HWIF(drive);
@@ -40,7 +42,7 @@ static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
40 { 2, 1 }, 42 { 2, 1 },
41 { 2, 3 }, }; 43 { 2, 3 }, };
42 44
43 spin_lock_irqsave(&ide_lock, flags); 45 spin_lock_irqsave(&slc90e66_lock, flags);
44 pci_read_config_word(dev, master_port, &master_data); 46 pci_read_config_word(dev, master_port, &master_data);
45 47
46 if (pio > 1) 48 if (pio > 1)
@@ -71,7 +73,7 @@ static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
71 pci_write_config_word(dev, master_port, master_data); 73 pci_write_config_word(dev, master_port, master_data);
72 if (is_slave) 74 if (is_slave)
73 pci_write_config_byte(dev, slave_port, slave_data); 75 pci_write_config_byte(dev, slave_port, slave_data);
74 spin_unlock_irqrestore(&ide_lock, flags); 76 spin_unlock_irqrestore(&slc90e66_lock, flags);
75} 77}
76 78
77static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed) 79static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
@@ -133,37 +135,28 @@ static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
133 u8 reg47 = 0; 135 u8 reg47 = 0;
134 u8 mask = hwif->channel ? 0x01 : 0x02; /* bit0:Primary */ 136 u8 mask = hwif->channel ? 0x01 : 0x02; /* bit0:Primary */
135 137
136 if (!hwif->irq)
137 hwif->irq = hwif->channel ? 15 : 14;
138
139 hwif->set_pio_mode = &slc90e66_set_pio_mode; 138 hwif->set_pio_mode = &slc90e66_set_pio_mode;
140 hwif->set_dma_mode = &slc90e66_set_dma_mode; 139 hwif->set_dma_mode = &slc90e66_set_dma_mode;
141 140
142 pci_read_config_byte(hwif->pci_dev, 0x47, &reg47); 141 pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
143 142
144 hwif->drives[0].autotune = 1;
145 hwif->drives[1].autotune = 1;
146
147 if (hwif->dma_base == 0) 143 if (hwif->dma_base == 0)
148 return; 144 return;
149 145
150 hwif->atapi_dma = 1;
151 hwif->ultra_mask = 0x1f;
152 hwif->mwdma_mask = 0x06;
153 hwif->swdma_mask = 0x04;
154
155 if (hwif->cbl != ATA_CBL_PATA40_SHORT) 146 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
156 /* bit[0(1)]: 0:80, 1:40 */ 147 /* bit[0(1)]: 0:80, 1:40 */
157 hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; 148 hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
158} 149}
159 150
160static ide_pci_device_t slc90e66_chipset __devinitdata = { 151static const struct ide_port_info slc90e66_chipset __devinitdata = {
161 .name = "SLC90E66", 152 .name = "SLC90E66",
162 .init_hwif = init_hwif_slc90e66, 153 .init_hwif = init_hwif_slc90e66,
163 .autodma = AUTODMA,
164 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, 154 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
165 .bootable = ON_BOARD, 155 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
166 .pio_mask = ATA_PIO4, 156 .pio_mask = ATA_PIO4,
157 .swdma_mask = ATA_SWDMA2_ONLY,
158 .mwdma_mask = ATA_MWDMA12_ONLY,
159 .udma_mask = ATA_UDMA4,
167}; 160};
168 161
169static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id) 162static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
diff --git a/drivers/ide/pci/tc86c001.c b/drivers/ide/pci/tc86c001.c
index de62db576adc..a66ebd14664e 100644
--- a/drivers/ide/pci/tc86c001.c
+++ b/drivers/ide/pci/tc86c001.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * drivers/ide/pci/tc86c001.c Version 1.00 Dec 12, 2006 2 * drivers/ide/pci/tc86c001.c Version 1.01 Sep 5, 2007
3 * 3 *
4 * Copyright (C) 2002 Toshiba Corporation 4 * Copyright (C) 2002 Toshiba Corporation
5 * Copyright (C) 2005-2006 MontaVista Software, Inc. <source@mvista.com> 5 * Copyright (C) 2005-2006 MontaVista Software, Inc. <source@mvista.com>
@@ -17,7 +17,7 @@ static void tc86c001_set_mode(ide_drive_t *drive, const u8 speed)
17{ 17{
18 ide_hwif_t *hwif = HWIF(drive); 18 ide_hwif_t *hwif = HWIF(drive);
19 unsigned long scr_port = hwif->config_data + (drive->dn ? 0x02 : 0x00); 19 unsigned long scr_port = hwif->config_data + (drive->dn ? 0x02 : 0x00);
20 u16 mode, scr = hwif->INW(scr_port); 20 u16 mode, scr = inw(scr_port);
21 21
22 switch (speed) { 22 switch (speed) {
23 case XFER_UDMA_4: mode = 0x00c0; break; 23 case XFER_UDMA_4: mode = 0x00c0; break;
@@ -65,7 +65,7 @@ static int tc86c001_timer_expiry(ide_drive_t *drive)
65 ide_hwif_t *hwif = HWIF(drive); 65 ide_hwif_t *hwif = HWIF(drive);
66 ide_expiry_t *expiry = ide_get_hwifdata(hwif); 66 ide_expiry_t *expiry = ide_get_hwifdata(hwif);
67 ide_hwgroup_t *hwgroup = HWGROUP(drive); 67 ide_hwgroup_t *hwgroup = HWGROUP(drive);
68 u8 dma_stat = hwif->INB(hwif->dma_status); 68 u8 dma_stat = inb(hwif->dma_status);
69 69
70 /* Restore a higher level driver's expiry handler first. */ 70 /* Restore a higher level driver's expiry handler first. */
71 hwgroup->expiry = expiry; 71 hwgroup->expiry = expiry;
@@ -73,7 +73,7 @@ static int tc86c001_timer_expiry(ide_drive_t *drive)
73 if ((dma_stat & 5) == 1) { /* DMA active and no interrupt */ 73 if ((dma_stat & 5) == 1) { /* DMA active and no interrupt */
74 unsigned long sc_base = hwif->config_data; 74 unsigned long sc_base = hwif->config_data;
75 unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04); 75 unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04);
76 u8 dma_cmd = hwif->INB(hwif->dma_command); 76 u8 dma_cmd = inb(hwif->dma_command);
77 77
78 printk(KERN_WARNING "%s: DMA interrupt possibly stuck, " 78 printk(KERN_WARNING "%s: DMA interrupt possibly stuck, "
79 "attempting recovery...\n", drive->name); 79 "attempting recovery...\n", drive->name);
@@ -135,7 +135,7 @@ static int tc86c001_busproc(ide_drive_t *drive, int state)
135 u16 scr1; 135 u16 scr1;
136 136
137 /* System Control 1 Register bit 11 (ATA Hard Reset) read */ 137 /* System Control 1 Register bit 11 (ATA Hard Reset) read */
138 scr1 = hwif->INW(sc_base + 0x00); 138 scr1 = inw(sc_base + 0x00);
139 139
140 switch (state) { 140 switch (state) {
141 case BUSSTATE_ON: 141 case BUSSTATE_ON:
@@ -165,7 +165,7 @@ static int tc86c001_busproc(ide_drive_t *drive, int state)
165static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif) 165static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
166{ 166{
167 unsigned long sc_base = pci_resource_start(hwif->pci_dev, 5); 167 unsigned long sc_base = pci_resource_start(hwif->pci_dev, 5);
168 u16 scr1 = hwif->INW(sc_base + 0x00);; 168 u16 scr1 = inw(sc_base + 0x00);
169 169
170 /* System Control 1 Register bit 15 (Soft Reset) set */ 170 /* System Control 1 Register bit 15 (Soft Reset) set */
171 outw(scr1 | 0x8000, sc_base + 0x00); 171 outw(scr1 | 0x8000, sc_base + 0x00);
@@ -184,8 +184,6 @@ static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
184 184
185 hwif->busproc = &tc86c001_busproc; 185 hwif->busproc = &tc86c001_busproc;
186 186
187 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
188
189 if (!hwif->dma_base) 187 if (!hwif->dma_base)
190 return; 188 return;
191 189
@@ -198,10 +196,6 @@ static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
198 /* Sector Count Register limit */ 196 /* Sector Count Register limit */
199 hwif->rqsize = 0xffff; 197 hwif->rqsize = 0xffff;
200 198
201 hwif->atapi_dma = 1;
202 hwif->ultra_mask = 0x1f;
203 hwif->mwdma_mask = 0x07;
204
205 hwif->dma_start = &tc86c001_dma_start; 199 hwif->dma_start = &tc86c001_dma_start;
206 200
207 if (hwif->cbl != ATA_CBL_PATA40_SHORT) { 201 if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
@@ -209,7 +203,7 @@ static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
209 * System Control 1 Register bit 13 (PDIAGN): 203 * System Control 1 Register bit 13 (PDIAGN):
210 * 0=80-pin cable, 1=40-pin cable 204 * 0=80-pin cable, 1=40-pin cable
211 */ 205 */
212 scr1 = hwif->INW(sc_base + 0x00); 206 scr1 = inw(sc_base + 0x00);
213 hwif->cbl = (scr1 & 0x2000) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; 207 hwif->cbl = (scr1 & 0x2000) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
214 } 208 }
215} 209}
@@ -224,14 +218,14 @@ static unsigned int __devinit init_chipset_tc86c001(struct pci_dev *dev,
224 return err; 218 return err;
225} 219}
226 220
227static ide_pci_device_t tc86c001_chipset __devinitdata = { 221static const struct ide_port_info tc86c001_chipset __devinitdata = {
228 .name = "TC86C001", 222 .name = "TC86C001",
229 .init_chipset = init_chipset_tc86c001, 223 .init_chipset = init_chipset_tc86c001,
230 .init_hwif = init_hwif_tc86c001, 224 .init_hwif = init_hwif_tc86c001,
231 .autodma = AUTODMA, 225 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD,
232 .bootable = OFF_BOARD,
233 .host_flags = IDE_HFLAG_SINGLE,
234 .pio_mask = ATA_PIO4, 226 .pio_mask = ATA_PIO4,
227 .mwdma_mask = ATA_MWDMA2,
228 .udma_mask = ATA_UDMA4,
235}; 229};
236 230
237static int __devinit tc86c001_init_one(struct pci_dev *dev, 231static int __devinit tc86c001_init_one(struct pci_dev *dev,
diff --git a/drivers/ide/pci/triflex.c b/drivers/ide/pci/triflex.c
index 4075c907f05c..a227c41d23a3 100644
--- a/drivers/ide/pci/triflex.c
+++ b/drivers/ide/pci/triflex.c
@@ -100,22 +100,16 @@ static void __devinit init_hwif_triflex(ide_hwif_t *hwif)
100{ 100{
101 hwif->set_pio_mode = &triflex_set_pio_mode; 101 hwif->set_pio_mode = &triflex_set_pio_mode;
102 hwif->set_dma_mode = &triflex_set_mode; 102 hwif->set_dma_mode = &triflex_set_mode;
103
104 if (hwif->dma_base == 0)
105 return;
106
107 hwif->atapi_dma = 1;
108 hwif->mwdma_mask = 0x07;
109 hwif->swdma_mask = 0x07;
110} 103}
111 104
112static ide_pci_device_t triflex_device __devinitdata = { 105static const struct ide_port_info triflex_device __devinitdata = {
113 .name = "TRIFLEX", 106 .name = "TRIFLEX",
114 .init_hwif = init_hwif_triflex, 107 .init_hwif = init_hwif_triflex,
115 .autodma = AUTODMA,
116 .enablebits = {{0x80, 0x01, 0x01}, {0x80, 0x02, 0x02}}, 108 .enablebits = {{0x80, 0x01, 0x01}, {0x80, 0x02, 0x02}},
117 .bootable = ON_BOARD, 109 .host_flags = IDE_HFLAG_BOOTABLE,
118 .pio_mask = ATA_PIO4, 110 .pio_mask = ATA_PIO4,
111 .swdma_mask = ATA_SWDMA2,
112 .mwdma_mask = ATA_MWDMA2,
119}; 113};
120 114
121static int __devinit triflex_init_one(struct pci_dev *dev, 115static int __devinit triflex_init_one(struct pci_dev *dev,
diff --git a/drivers/ide/pci/trm290.c b/drivers/ide/pci/trm290.c
index e3d943ada7b0..5011ba22e36c 100644
--- a/drivers/ide/pci/trm290.c
+++ b/drivers/ide/pci/trm290.c
@@ -250,8 +250,6 @@ static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
250 u8 reg = 0; 250 u8 reg = 0;
251 struct pci_dev *dev = hwif->pci_dev; 251 struct pci_dev *dev = hwif->pci_dev;
252 252
253 hwif->no_lba48 = 1;
254 hwif->chipset = ide_trm290;
255 cfgbase = pci_resource_start(dev, 4); 253 cfgbase = pci_resource_start(dev, 4);
256 if ((dev->class & 5) && cfgbase) { 254 if ((dev->class & 5) && cfgbase) {
257 hwif->config_data = cfgbase; 255 hwif->config_data = cfgbase;
@@ -321,14 +319,17 @@ static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
321#endif 319#endif
322} 320}
323 321
324static ide_pci_device_t trm290_chipset __devinitdata = { 322static const struct ide_port_info trm290_chipset __devinitdata = {
325 .name = "TRM290", 323 .name = "TRM290",
326 .init_hwif = init_hwif_trm290, 324 .init_hwif = init_hwif_trm290,
327 .autodma = NOAUTODMA, 325 .chipset = ide_trm290,
328 .bootable = ON_BOARD, 326 .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
329#if 0 /* play it safe for now */ 327#if 0 /* play it safe for now */
330 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, 328 IDE_HFLAG_TRUST_BIOS_FOR_DMA |
331#endif 329#endif
330 IDE_HFLAG_NO_AUTODMA |
331 IDE_HFLAG_BOOTABLE |
332 IDE_HFLAG_NO_LBA48,
332}; 333};
333 334
334static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id) 335static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
diff --git a/drivers/ide/pci/via82cxxx.c b/drivers/ide/pci/via82cxxx.c
index b25fb65b240e..a0d3c16b68ec 100644
--- a/drivers/ide/pci/via82cxxx.c
+++ b/drivers/ide/pci/via82cxxx.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * 2 *
3 * Version 3.49 3 * Version 3.50
4 * 4 *
5 * VIA IDE driver for Linux. Supported southbridges: 5 * VIA IDE driver for Linux. Supported southbridges:
6 * 6 *
@@ -422,67 +422,40 @@ static u8 __devinit via82cxxx_cable_detect(ide_hwif_t *hwif)
422 422
423static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif) 423static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
424{ 424{
425 struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
426 int i;
427
428 hwif->set_pio_mode = &via_set_pio_mode; 425 hwif->set_pio_mode = &via_set_pio_mode;
429 hwif->set_dma_mode = &via_set_drive; 426 hwif->set_dma_mode = &via_set_drive;
430 427
431#ifdef CONFIG_PPC_CHRP
432 if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) {
433 hwif->irq = hwif->channel ? 15 : 14;
434 }
435#endif
436
437 for (i = 0; i < 2; i++) {
438 hwif->drives[i].io_32bit = 1;
439 hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
440 hwif->drives[i].autotune = 1;
441 }
442
443 if (!hwif->dma_base) 428 if (!hwif->dma_base)
444 return; 429 return;
445 430
446 hwif->atapi_dma = 1;
447
448 hwif->ultra_mask = vdev->via_config->udma_mask;
449 hwif->mwdma_mask = 0x07;
450 hwif->swdma_mask = 0x07;
451
452 if (hwif->cbl != ATA_CBL_PATA40_SHORT) 431 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
453 hwif->cbl = via82cxxx_cable_detect(hwif); 432 hwif->cbl = via82cxxx_cable_detect(hwif);
454} 433}
455 434
456static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = { 435static const struct ide_port_info via82cxxx_chipset __devinitdata = {
457 { /* 0 */ 436 .name = "VP_IDE",
458 .name = "VP_IDE", 437 .init_chipset = init_chipset_via82cxxx,
459 .init_chipset = init_chipset_via82cxxx, 438 .init_hwif = init_hwif_via82cxxx,
460 .init_hwif = init_hwif_via82cxxx, 439 .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
461 .autodma = NOAUTODMA, 440 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST |
462 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, 441 IDE_HFLAG_PIO_NO_DOWNGRADE |
463 .bootable = ON_BOARD, 442 IDE_HFLAG_POST_SET_MODE |
464 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST 443 IDE_HFLAG_IO_32BIT |
465 | IDE_HFLAG_PIO_NO_DOWNGRADE 444 IDE_HFLAG_BOOTABLE,
466 | IDE_HFLAG_POST_SET_MODE, 445 .pio_mask = ATA_PIO5,
467 .pio_mask = ATA_PIO5, 446 .swdma_mask = ATA_SWDMA2,
468 },{ /* 1 */ 447 .mwdma_mask = ATA_MWDMA2,
469 .name = "VP_IDE",
470 .init_chipset = init_chipset_via82cxxx,
471 .init_hwif = init_hwif_via82cxxx,
472 .autodma = AUTODMA,
473 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
474 .bootable = ON_BOARD,
475 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST
476 | IDE_HFLAG_PIO_NO_DOWNGRADE
477 | IDE_HFLAG_POST_SET_MODE,
478 .pio_mask = ATA_PIO5,
479 }
480}; 448};
481 449
482static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id) 450static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
483{ 451{
484 struct pci_dev *isa = NULL; 452 struct pci_dev *isa = NULL;
485 struct via_isa_bridge *via_config; 453 struct via_isa_bridge *via_config;
454 u8 idx = id->driver_data;
455 struct ide_port_info d;
456
457 d = via82cxxx_chipset;
458
486 /* 459 /*
487 * Find the ISA bridge and check we know what it is. 460 * Find the ISA bridge and check we know what it is.
488 */ 461 */
@@ -492,7 +465,23 @@ static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_i
492 printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n"); 465 printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
493 return -ENODEV; 466 return -ENODEV;
494 } 467 }
495 return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]); 468
469 if (idx == 0)
470 d.host_flags |= IDE_HFLAG_NO_AUTODMA;
471 else
472 d.enablebits[1].reg = d.enablebits[0].reg = 0;
473
474 if ((via_config->flags & VIA_NO_UNMASK) == 0)
475 d.host_flags |= IDE_HFLAG_UNMASK_IRQS;
476
477#ifdef CONFIG_PPC_CHRP
478 if (machine_is(chrp) && _chrp_type == _CHRP_Pegasos)
479 d.host_flags |= IDE_HFLAG_FORCE_LEGACY_IRQS;
480#endif
481
482 d.udma_mask = via_config->udma_mask;
483
484 return ide_setup_pci_device(dev, &d);
496} 485}
497 486
498static const struct pci_device_id via_pci_tbl[] = { 487static const struct pci_device_id via_pci_tbl[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-21 21:52:14 -0500