diff options
Diffstat (limited to 'drivers/ide/pci')
-rw-r--r-- | drivers/ide/pci/aec62xx.c | 5 | ||||
-rw-r--r-- | drivers/ide/pci/alim15x3.c | 12 | ||||
-rw-r--r-- | drivers/ide/pci/amd74xx.c | 1 | ||||
-rw-r--r-- | drivers/ide/pci/cmd640.c | 29 | ||||
-rw-r--r-- | drivers/ide/pci/cmd64x.c | 12 | ||||
-rw-r--r-- | drivers/ide/pci/cs5520.c | 41 | ||||
-rw-r--r-- | drivers/ide/pci/cs5535.c | 3 | ||||
-rw-r--r-- | drivers/ide/pci/delkin_cb.c | 25 | ||||
-rw-r--r-- | drivers/ide/pci/hpt34x.c | 1 | ||||
-rw-r--r-- | drivers/ide/pci/hpt366.c | 23 | ||||
-rw-r--r-- | drivers/ide/pci/ns87415.c | 115 | ||||
-rw-r--r-- | drivers/ide/pci/pdc202xx_old.c | 3 | ||||
-rw-r--r-- | drivers/ide/pci/piix.c | 4 | ||||
-rw-r--r-- | drivers/ide/pci/scc_pata.c | 139 | ||||
-rw-r--r-- | drivers/ide/pci/serverworks.c | 4 | ||||
-rw-r--r-- | drivers/ide/pci/sgiioc4.c | 65 | ||||
-rw-r--r-- | drivers/ide/pci/siimage.c | 6 | ||||
-rw-r--r-- | drivers/ide/pci/sl82c105.c | 4 | ||||
-rw-r--r-- | drivers/ide/pci/tc86c001.c | 16 | ||||
-rw-r--r-- | drivers/ide/pci/via82cxxx.c | 1 |
20 files changed, 251 insertions, 258 deletions
diff --git a/drivers/ide/pci/aec62xx.c b/drivers/ide/pci/aec62xx.c index ae7a4329a581..fbc43e121e6b 100644 --- a/drivers/ide/pci/aec62xx.c +++ b/drivers/ide/pci/aec62xx.c | |||
@@ -195,7 +195,6 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = { | |||
195 | .host_flags = IDE_HFLAG_SERIALIZE | | 195 | .host_flags = IDE_HFLAG_SERIALIZE | |
196 | IDE_HFLAG_NO_ATAPI_DMA | | 196 | IDE_HFLAG_NO_ATAPI_DMA | |
197 | IDE_HFLAG_NO_DSC | | 197 | IDE_HFLAG_NO_DSC | |
198 | IDE_HFLAG_ABUSE_SET_DMA_MODE | | ||
199 | IDE_HFLAG_OFF_BOARD, | 198 | IDE_HFLAG_OFF_BOARD, |
200 | .pio_mask = ATA_PIO4, | 199 | .pio_mask = ATA_PIO4, |
201 | .mwdma_mask = ATA_MWDMA2, | 200 | .mwdma_mask = ATA_MWDMA2, |
@@ -205,7 +204,6 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = { | |||
205 | .init_chipset = init_chipset_aec62xx, | 204 | .init_chipset = init_chipset_aec62xx, |
206 | .port_ops = &atp86x_port_ops, | 205 | .port_ops = &atp86x_port_ops, |
207 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA | | 206 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA | |
208 | IDE_HFLAG_ABUSE_SET_DMA_MODE | | ||
209 | IDE_HFLAG_OFF_BOARD, | 207 | IDE_HFLAG_OFF_BOARD, |
210 | .pio_mask = ATA_PIO4, | 208 | .pio_mask = ATA_PIO4, |
211 | .mwdma_mask = ATA_MWDMA2, | 209 | .mwdma_mask = ATA_MWDMA2, |
@@ -216,7 +214,6 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = { | |||
216 | .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, | 214 | .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, |
217 | .port_ops = &atp86x_port_ops, | 215 | .port_ops = &atp86x_port_ops, |
218 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | | 216 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | |
219 | IDE_HFLAG_ABUSE_SET_DMA_MODE | | ||
220 | IDE_HFLAG_NON_BOOTABLE, | 217 | IDE_HFLAG_NON_BOOTABLE, |
221 | .pio_mask = ATA_PIO4, | 218 | .pio_mask = ATA_PIO4, |
222 | .mwdma_mask = ATA_MWDMA2, | 219 | .mwdma_mask = ATA_MWDMA2, |
@@ -226,7 +223,6 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = { | |||
226 | .init_chipset = init_chipset_aec62xx, | 223 | .init_chipset = init_chipset_aec62xx, |
227 | .port_ops = &atp86x_port_ops, | 224 | .port_ops = &atp86x_port_ops, |
228 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | | 225 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | |
229 | IDE_HFLAG_ABUSE_SET_DMA_MODE | | ||
230 | IDE_HFLAG_OFF_BOARD, | 226 | IDE_HFLAG_OFF_BOARD, |
231 | .pio_mask = ATA_PIO4, | 227 | .pio_mask = ATA_PIO4, |
232 | .mwdma_mask = ATA_MWDMA2, | 228 | .mwdma_mask = ATA_MWDMA2, |
@@ -237,7 +233,6 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = { | |||
237 | .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, | 233 | .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, |
238 | .port_ops = &atp86x_port_ops, | 234 | .port_ops = &atp86x_port_ops, |
239 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | | 235 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | |
240 | IDE_HFLAG_ABUSE_SET_DMA_MODE | | ||
241 | IDE_HFLAG_OFF_BOARD, | 236 | IDE_HFLAG_OFF_BOARD, |
242 | .pio_mask = ATA_PIO4, | 237 | .pio_mask = ATA_PIO4, |
243 | .mwdma_mask = ATA_MWDMA2, | 238 | .mwdma_mask = ATA_MWDMA2, |
diff --git a/drivers/ide/pci/alim15x3.c b/drivers/ide/pci/alim15x3.c index 80d19c0eb780..5ef7817ac64f 100644 --- a/drivers/ide/pci/alim15x3.c +++ b/drivers/ide/pci/alim15x3.c | |||
@@ -471,7 +471,15 @@ static int __devinit init_dma_ali15x3(ide_hwif_t *hwif, | |||
471 | struct pci_dev *dev = to_pci_dev(hwif->dev); | 471 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
472 | unsigned long base = ide_pci_dma_base(hwif, d); | 472 | unsigned long base = ide_pci_dma_base(hwif, d); |
473 | 473 | ||
474 | if (base == 0 || ide_pci_set_master(dev, d->name) < 0) | 474 | if (base == 0) |
475 | return -1; | ||
476 | |||
477 | hwif->dma_base = base; | ||
478 | |||
479 | if (ide_pci_check_simplex(hwif, d) < 0) | ||
480 | return -1; | ||
481 | |||
482 | if (ide_pci_set_master(dev, d->name) < 0) | ||
475 | return -1; | 483 | return -1; |
476 | 484 | ||
477 | if (!hwif->channel) | 485 | if (!hwif->channel) |
@@ -483,7 +491,7 @@ static int __devinit init_dma_ali15x3(ide_hwif_t *hwif, | |||
483 | if (ide_allocate_dma_engine(hwif)) | 491 | if (ide_allocate_dma_engine(hwif)) |
484 | return -1; | 492 | return -1; |
485 | 493 | ||
486 | ide_setup_dma(hwif, base); | 494 | hwif->dma_ops = &sff_dma_ops; |
487 | 495 | ||
488 | return 0; | 496 | return 0; |
489 | } | 497 | } |
diff --git a/drivers/ide/pci/amd74xx.c b/drivers/ide/pci/amd74xx.c index 0bfcdd0e77b3..ef7d971031ee 100644 --- a/drivers/ide/pci/amd74xx.c +++ b/drivers/ide/pci/amd74xx.c | |||
@@ -218,7 +218,6 @@ static const struct ide_port_ops amd_port_ops = { | |||
218 | 218 | ||
219 | #define IDE_HFLAGS_AMD \ | 219 | #define IDE_HFLAGS_AMD \ |
220 | (IDE_HFLAG_PIO_NO_BLACKLIST | \ | 220 | (IDE_HFLAG_PIO_NO_BLACKLIST | \ |
221 | IDE_HFLAG_ABUSE_SET_DMA_MODE | \ | ||
222 | IDE_HFLAG_POST_SET_MODE | \ | 221 | IDE_HFLAG_POST_SET_MODE | \ |
223 | IDE_HFLAG_IO_32BIT | \ | 222 | IDE_HFLAG_IO_32BIT | \ |
224 | IDE_HFLAG_UNMASK_IRQS) | 223 | IDE_HFLAG_UNMASK_IRQS) |
diff --git a/drivers/ide/pci/cmd640.c b/drivers/ide/pci/cmd640.c index 1ad1e23e3105..e6c62006ca1a 100644 --- a/drivers/ide/pci/cmd640.c +++ b/drivers/ide/pci/cmd640.c | |||
@@ -181,11 +181,6 @@ static u8 recovery_counts[4] = {16, 16, 16, 16}; /* Recovery count (encoded) */ | |||
181 | static DEFINE_SPINLOCK(cmd640_lock); | 181 | static DEFINE_SPINLOCK(cmd640_lock); |
182 | 182 | ||
183 | /* | 183 | /* |
184 | * These are initialized to point at the devices we control | ||
185 | */ | ||
186 | static ide_hwif_t *cmd_hwif0, *cmd_hwif1; | ||
187 | |||
188 | /* | ||
189 | * Interface to access cmd640x registers | 184 | * Interface to access cmd640x registers |
190 | */ | 185 | */ |
191 | static unsigned int cmd640_key; | 186 | static unsigned int cmd640_key; |
@@ -717,8 +712,7 @@ static int __init cmd640x_init(void) | |||
717 | int second_port_cmd640 = 0, rc; | 712 | int second_port_cmd640 = 0, rc; |
718 | const char *bus_type, *port2; | 713 | const char *bus_type, *port2; |
719 | u8 b, cfr; | 714 | u8 b, cfr; |
720 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; | 715 | hw_regs_t hw[2], *hws[] = { NULL, NULL, NULL, NULL }; |
721 | hw_regs_t hw[2]; | ||
722 | 716 | ||
723 | if (cmd640_vlb && probe_for_cmd640_vlb()) { | 717 | if (cmd640_vlb && probe_for_cmd640_vlb()) { |
724 | bus_type = "VLB"; | 718 | bus_type = "VLB"; |
@@ -781,15 +775,10 @@ static int __init cmd640x_init(void) | |||
781 | printk(KERN_INFO "cmd640: buggy cmd640%c interface on %s, config=0x%02x" | 775 | printk(KERN_INFO "cmd640: buggy cmd640%c interface on %s, config=0x%02x" |
782 | "\n", 'a' + cmd640_chip_version - 1, bus_type, cfr); | 776 | "\n", 'a' + cmd640_chip_version - 1, bus_type, cfr); |
783 | 777 | ||
784 | cmd_hwif0 = ide_find_port(); | ||
785 | |||
786 | /* | 778 | /* |
787 | * Initialize data for primary port | 779 | * Initialize data for primary port |
788 | */ | 780 | */ |
789 | if (cmd_hwif0) { | 781 | hws[0] = &hw[0]; |
790 | ide_init_port_hw(cmd_hwif0, &hw[0]); | ||
791 | idx[0] = cmd_hwif0->index; | ||
792 | } | ||
793 | 782 | ||
794 | /* | 783 | /* |
795 | * Ensure compatibility by always using the slowest timings | 784 | * Ensure compatibility by always using the slowest timings |
@@ -829,13 +818,9 @@ static int __init cmd640x_init(void) | |||
829 | /* | 818 | /* |
830 | * Initialize data for secondary cmd640 port, if enabled | 819 | * Initialize data for secondary cmd640 port, if enabled |
831 | */ | 820 | */ |
832 | if (second_port_cmd640) { | 821 | if (second_port_cmd640) |
833 | cmd_hwif1 = ide_find_port(); | 822 | hws[1] = &hw[1]; |
834 | if (cmd_hwif1) { | 823 | |
835 | ide_init_port_hw(cmd_hwif1, &hw[1]); | ||
836 | idx[1] = cmd_hwif1->index; | ||
837 | } | ||
838 | } | ||
839 | printk(KERN_INFO "cmd640: %sserialized, secondary interface %s\n", | 824 | printk(KERN_INFO "cmd640: %sserialized, secondary interface %s\n", |
840 | second_port_cmd640 ? "" : "not ", port2); | 825 | second_port_cmd640 ? "" : "not ", port2); |
841 | 826 | ||
@@ -843,9 +828,7 @@ static int __init cmd640x_init(void) | |||
843 | cmd640_dump_regs(); | 828 | cmd640_dump_regs(); |
844 | #endif | 829 | #endif |
845 | 830 | ||
846 | ide_device_add(idx, &cmd640_port_info); | 831 | return ide_host_add(&cmd640_port_info, hws, NULL); |
847 | |||
848 | return 1; | ||
849 | } | 832 | } |
850 | 833 | ||
851 | module_param_named(probe_vlb, cmd640_vlb, bool, 0); | 834 | module_param_named(probe_vlb, cmd640_vlb, bool, 0); |
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c index cfa784bacf48..ce58bfcdb3c6 100644 --- a/drivers/ide/pci/cmd64x.c +++ b/drivers/ide/pci/cmd64x.c | |||
@@ -262,7 +262,7 @@ static int cmd648_dma_test_irq(ide_drive_t *drive) | |||
262 | unsigned long base = hwif->dma_base - (hwif->channel * 8); | 262 | unsigned long base = hwif->dma_base - (hwif->channel * 8); |
263 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : | 263 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : |
264 | MRDMODE_INTR_CH0; | 264 | MRDMODE_INTR_CH0; |
265 | u8 dma_stat = inb(hwif->dma_status); | 265 | u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
266 | u8 mrdmode = inb(base + 1); | 266 | u8 mrdmode = inb(base + 1); |
267 | 267 | ||
268 | #ifdef DEBUG | 268 | #ifdef DEBUG |
@@ -286,7 +286,7 @@ static int cmd64x_dma_test_irq(ide_drive_t *drive) | |||
286 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; | 286 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
287 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : | 287 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : |
288 | CFR_INTR_CH0; | 288 | CFR_INTR_CH0; |
289 | u8 dma_stat = inb(hwif->dma_status); | 289 | u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
290 | u8 irq_stat = 0; | 290 | u8 irq_stat = 0; |
291 | 291 | ||
292 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); | 292 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); |
@@ -317,13 +317,13 @@ static int cmd646_1_dma_end(ide_drive_t *drive) | |||
317 | 317 | ||
318 | drive->waiting_for_dma = 0; | 318 | drive->waiting_for_dma = 0; |
319 | /* get DMA status */ | 319 | /* get DMA status */ |
320 | dma_stat = inb(hwif->dma_status); | 320 | dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
321 | /* read DMA command state */ | 321 | /* read DMA command state */ |
322 | dma_cmd = inb(hwif->dma_command); | 322 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
323 | /* stop DMA */ | 323 | /* stop DMA */ |
324 | outb(dma_cmd & ~1, hwif->dma_command); | 324 | outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); |
325 | /* clear the INTR & ERROR bits */ | 325 | /* clear the INTR & ERROR bits */ |
326 | outb(dma_stat | 6, hwif->dma_status); | 326 | outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS); |
327 | /* and free any DMA resources */ | 327 | /* and free any DMA resources */ |
328 | ide_destroy_dmatable(drive); | 328 | ide_destroy_dmatable(drive); |
329 | /* verify good DMA status */ | 329 | /* verify good DMA status */ |
diff --git a/drivers/ide/pci/cs5520.c b/drivers/ide/pci/cs5520.c index 992b1cf8db69..b03d8ae947e6 100644 --- a/drivers/ide/pci/cs5520.c +++ b/drivers/ide/pci/cs5520.c | |||
@@ -62,8 +62,6 @@ static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio) | |||
62 | struct pci_dev *pdev = to_pci_dev(hwif->dev); | 62 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
63 | int controller = drive->dn > 1 ? 1 : 0; | 63 | int controller = drive->dn > 1 ? 1 : 0; |
64 | 64 | ||
65 | /* FIXME: if DMA = 1 do we need to set the DMA bit here ? */ | ||
66 | |||
67 | /* 8bit CAT/CRT - 8bit command timing for channel */ | 65 | /* 8bit CAT/CRT - 8bit command timing for channel */ |
68 | pci_write_config_byte(pdev, 0x62 + controller, | 66 | pci_write_config_byte(pdev, 0x62 + controller, |
69 | (cs5520_pio_clocks[pio].recovery << 4) | | 67 | (cs5520_pio_clocks[pio].recovery << 4) | |
@@ -89,46 +87,17 @@ static void cs5520_set_dma_mode(ide_drive_t *drive, const u8 speed) | |||
89 | cs5520_set_pio_mode(drive, 0); | 87 | cs5520_set_pio_mode(drive, 0); |
90 | } | 88 | } |
91 | 89 | ||
92 | /* | ||
93 | * We wrap the DMA activate to set the vdma flag. This is needed | ||
94 | * so that the IDE DMA layer issues PIO not DMA commands over the | ||
95 | * DMA channel | ||
96 | * | ||
97 | * ATAPI is harder so disable it for now using IDE_HFLAG_NO_ATAPI_DMA | ||
98 | */ | ||
99 | |||
100 | static void cs5520_dma_host_set(ide_drive_t *drive, int on) | ||
101 | { | ||
102 | drive->vdma = on; | ||
103 | ide_dma_host_set(drive, on); | ||
104 | } | ||
105 | |||
106 | static const struct ide_port_ops cs5520_port_ops = { | 90 | static const struct ide_port_ops cs5520_port_ops = { |
107 | .set_pio_mode = cs5520_set_pio_mode, | 91 | .set_pio_mode = cs5520_set_pio_mode, |
108 | .set_dma_mode = cs5520_set_dma_mode, | 92 | .set_dma_mode = cs5520_set_dma_mode, |
109 | }; | 93 | }; |
110 | 94 | ||
111 | static const struct ide_dma_ops cs5520_dma_ops = { | ||
112 | .dma_host_set = cs5520_dma_host_set, | ||
113 | .dma_setup = ide_dma_setup, | ||
114 | .dma_exec_cmd = ide_dma_exec_cmd, | ||
115 | .dma_start = ide_dma_start, | ||
116 | .dma_end = __ide_dma_end, | ||
117 | .dma_test_irq = ide_dma_test_irq, | ||
118 | .dma_lost_irq = ide_dma_lost_irq, | ||
119 | .dma_timeout = ide_dma_timeout, | ||
120 | }; | ||
121 | |||
122 | /* FIXME: VDMA is disabled because it caused system hangs */ | ||
123 | #define DECLARE_CS_DEV(name_str) \ | 95 | #define DECLARE_CS_DEV(name_str) \ |
124 | { \ | 96 | { \ |
125 | .name = name_str, \ | 97 | .name = name_str, \ |
126 | .port_ops = &cs5520_port_ops, \ | 98 | .port_ops = &cs5520_port_ops, \ |
127 | .dma_ops = &cs5520_dma_ops, \ | ||
128 | .host_flags = IDE_HFLAG_ISA_PORTS | \ | 99 | .host_flags = IDE_HFLAG_ISA_PORTS | \ |
129 | IDE_HFLAG_CS5520 | \ | 100 | IDE_HFLAG_CS5520, \ |
130 | IDE_HFLAG_NO_ATAPI_DMA | \ | ||
131 | IDE_HFLAG_ABUSE_SET_DMA_MODE, \ | ||
132 | .pio_mask = ATA_PIO4, \ | 101 | .pio_mask = ATA_PIO4, \ |
133 | } | 102 | } |
134 | 103 | ||
@@ -146,7 +115,7 @@ static const struct ide_port_info cyrix_chipsets[] __devinitdata = { | |||
146 | static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id) | 115 | static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
147 | { | 116 | { |
148 | const struct ide_port_info *d = &cyrix_chipsets[id->driver_data]; | 117 | const struct ide_port_info *d = &cyrix_chipsets[id->driver_data]; |
149 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; | 118 | hw_regs_t hw[4], *hws[] = { NULL, NULL, NULL, NULL }; |
150 | 119 | ||
151 | ide_setup_pci_noise(dev, d); | 120 | ide_setup_pci_noise(dev, d); |
152 | 121 | ||
@@ -168,11 +137,9 @@ static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_devic | |||
168 | * do all the device setup for us | 137 | * do all the device setup for us |
169 | */ | 138 | */ |
170 | 139 | ||
171 | ide_pci_setup_ports(dev, d, 14, &idx[0]); | 140 | ide_pci_setup_ports(dev, d, 14, &hw[0], &hws[0]); |
172 | |||
173 | ide_device_add(idx, d); | ||
174 | 141 | ||
175 | return 0; | 142 | return ide_host_add(d, hws, NULL); |
176 | } | 143 | } |
177 | 144 | ||
178 | static const struct pci_device_id cs5520_pci_tbl[] = { | 145 | static const struct pci_device_id cs5520_pci_tbl[] = { |
diff --git a/drivers/ide/pci/cs5535.c b/drivers/ide/pci/cs5535.c index dc97c48623f3..5404fe4f701d 100644 --- a/drivers/ide/pci/cs5535.c +++ b/drivers/ide/pci/cs5535.c | |||
@@ -171,8 +171,7 @@ static const struct ide_port_ops cs5535_port_ops = { | |||
171 | static const struct ide_port_info cs5535_chipset __devinitdata = { | 171 | static const struct ide_port_info cs5535_chipset __devinitdata = { |
172 | .name = "CS5535", | 172 | .name = "CS5535", |
173 | .port_ops = &cs5535_port_ops, | 173 | .port_ops = &cs5535_port_ops, |
174 | .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE | | 174 | .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE, |
175 | IDE_HFLAG_ABUSE_SET_DMA_MODE, | ||
176 | .pio_mask = ATA_PIO4, | 175 | .pio_mask = ATA_PIO4, |
177 | .mwdma_mask = ATA_MWDMA2, | 176 | .mwdma_mask = ATA_MWDMA2, |
178 | .udma_mask = ATA_UDMA4, | 177 | .udma_mask = ATA_UDMA4, |
diff --git a/drivers/ide/pci/delkin_cb.c b/drivers/ide/pci/delkin_cb.c index 0106e2a2df77..f84bfb4f600f 100644 --- a/drivers/ide/pci/delkin_cb.c +++ b/drivers/ide/pci/delkin_cb.c | |||
@@ -56,11 +56,10 @@ static const struct ide_port_info delkin_cb_port_info = { | |||
56 | static int __devinit | 56 | static int __devinit |
57 | delkin_cb_probe (struct pci_dev *dev, const struct pci_device_id *id) | 57 | delkin_cb_probe (struct pci_dev *dev, const struct pci_device_id *id) |
58 | { | 58 | { |
59 | struct ide_host *host; | ||
59 | unsigned long base; | 60 | unsigned long base; |
60 | hw_regs_t hw; | ||
61 | ide_hwif_t *hwif = NULL; | ||
62 | int i, rc; | 61 | int i, rc; |
63 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; | 62 | hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL }; |
64 | 63 | ||
65 | rc = pci_enable_device(dev); | 64 | rc = pci_enable_device(dev); |
66 | if (rc) { | 65 | if (rc) { |
@@ -87,34 +86,26 @@ delkin_cb_probe (struct pci_dev *dev, const struct pci_device_id *id) | |||
87 | hw.dev = &dev->dev; | 86 | hw.dev = &dev->dev; |
88 | hw.chipset = ide_pci; /* this enables IRQ sharing */ | 87 | hw.chipset = ide_pci; /* this enables IRQ sharing */ |
89 | 88 | ||
90 | hwif = ide_find_port(); | 89 | rc = ide_host_add(&delkin_cb_port_info, hws, &host); |
91 | if (hwif == NULL) | 90 | if (rc) |
92 | goto out_disable; | 91 | goto out_disable; |
93 | 92 | ||
94 | i = hwif->index; | 93 | pci_set_drvdata(dev, host); |
95 | |||
96 | ide_init_port_hw(hwif, &hw); | ||
97 | |||
98 | idx[0] = i; | ||
99 | |||
100 | ide_device_add(idx, &delkin_cb_port_info); | ||
101 | |||
102 | pci_set_drvdata(dev, hwif); | ||
103 | 94 | ||
104 | return 0; | 95 | return 0; |
105 | 96 | ||
106 | out_disable: | 97 | out_disable: |
107 | pci_release_regions(dev); | 98 | pci_release_regions(dev); |
108 | pci_disable_device(dev); | 99 | pci_disable_device(dev); |
109 | return -ENODEV; | 100 | return rc; |
110 | } | 101 | } |
111 | 102 | ||
112 | static void | 103 | static void |
113 | delkin_cb_remove (struct pci_dev *dev) | 104 | delkin_cb_remove (struct pci_dev *dev) |
114 | { | 105 | { |
115 | ide_hwif_t *hwif = pci_get_drvdata(dev); | 106 | struct ide_host *host = pci_get_drvdata(dev); |
116 | 107 | ||
117 | ide_unregister(hwif); | 108 | ide_host_remove(host); |
118 | 109 | ||
119 | pci_release_regions(dev); | 110 | pci_release_regions(dev); |
120 | pci_disable_device(dev); | 111 | pci_disable_device(dev); |
diff --git a/drivers/ide/pci/hpt34x.c b/drivers/ide/pci/hpt34x.c index 84c36c117194..9e1d1c4741da 100644 --- a/drivers/ide/pci/hpt34x.c +++ b/drivers/ide/pci/hpt34x.c | |||
@@ -123,7 +123,6 @@ static const struct ide_port_ops hpt34x_port_ops = { | |||
123 | #define IDE_HFLAGS_HPT34X \ | 123 | #define IDE_HFLAGS_HPT34X \ |
124 | (IDE_HFLAG_NO_ATAPI_DMA | \ | 124 | (IDE_HFLAG_NO_ATAPI_DMA | \ |
125 | IDE_HFLAG_NO_DSC | \ | 125 | IDE_HFLAG_NO_DSC | \ |
126 | IDE_HFLAG_ABUSE_SET_DMA_MODE | \ | ||
127 | IDE_HFLAG_NO_AUTODMA) | 126 | IDE_HFLAG_NO_AUTODMA) |
128 | 127 | ||
129 | static const struct ide_port_info hpt34x_chipsets[] __devinitdata = { | 128 | static const struct ide_port_info hpt34x_chipsets[] __devinitdata = { |
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c index 397c6cbe953c..1f1135ce7cd6 100644 --- a/drivers/ide/pci/hpt366.c +++ b/drivers/ide/pci/hpt366.c | |||
@@ -801,9 +801,9 @@ static void hpt370_irq_timeout(ide_drive_t *drive) | |||
801 | printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff); | 801 | printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff); |
802 | 802 | ||
803 | /* get DMA command mode */ | 803 | /* get DMA command mode */ |
804 | dma_cmd = inb(hwif->dma_command); | 804 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
805 | /* stop DMA */ | 805 | /* stop DMA */ |
806 | outb(dma_cmd & ~0x1, hwif->dma_command); | 806 | outb(dma_cmd & ~0x1, hwif->dma_base + ATA_DMA_CMD); |
807 | hpt370_clear_engine(drive); | 807 | hpt370_clear_engine(drive); |
808 | } | 808 | } |
809 | 809 | ||
@@ -818,12 +818,12 @@ static void hpt370_dma_start(ide_drive_t *drive) | |||
818 | static int hpt370_dma_end(ide_drive_t *drive) | 818 | static int hpt370_dma_end(ide_drive_t *drive) |
819 | { | 819 | { |
820 | ide_hwif_t *hwif = HWIF(drive); | 820 | ide_hwif_t *hwif = HWIF(drive); |
821 | u8 dma_stat = inb(hwif->dma_status); | 821 | u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
822 | 822 | ||
823 | if (dma_stat & 0x01) { | 823 | if (dma_stat & 0x01) { |
824 | /* wait a little */ | 824 | /* wait a little */ |
825 | udelay(20); | 825 | udelay(20); |
826 | dma_stat = inb(hwif->dma_status); | 826 | dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
827 | if (dma_stat & 0x01) | 827 | if (dma_stat & 0x01) |
828 | hpt370_irq_timeout(drive); | 828 | hpt370_irq_timeout(drive); |
829 | } | 829 | } |
@@ -850,7 +850,7 @@ static int hpt374_dma_test_irq(ide_drive_t *drive) | |||
850 | return 0; | 850 | return 0; |
851 | } | 851 | } |
852 | 852 | ||
853 | dma_stat = inb(hwif->dma_status); | 853 | dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
854 | /* return 1 if INTR asserted */ | 854 | /* return 1 if INTR asserted */ |
855 | if (dma_stat & 4) | 855 | if (dma_stat & 4) |
856 | return 1; | 856 | return 1; |
@@ -1320,7 +1320,15 @@ static int __devinit init_dma_hpt366(ide_hwif_t *hwif, | |||
1320 | unsigned long flags, base = ide_pci_dma_base(hwif, d); | 1320 | unsigned long flags, base = ide_pci_dma_base(hwif, d); |
1321 | u8 dma_old, dma_new, masterdma = 0, slavedma = 0; | 1321 | u8 dma_old, dma_new, masterdma = 0, slavedma = 0; |
1322 | 1322 | ||
1323 | if (base == 0 || ide_pci_set_master(dev, d->name) < 0) | 1323 | if (base == 0) |
1324 | return -1; | ||
1325 | |||
1326 | hwif->dma_base = base; | ||
1327 | |||
1328 | if (ide_pci_check_simplex(hwif, d) < 0) | ||
1329 | return -1; | ||
1330 | |||
1331 | if (ide_pci_set_master(dev, d->name) < 0) | ||
1324 | return -1; | 1332 | return -1; |
1325 | 1333 | ||
1326 | dma_old = inb(base + 2); | 1334 | dma_old = inb(base + 2); |
@@ -1346,7 +1354,7 @@ static int __devinit init_dma_hpt366(ide_hwif_t *hwif, | |||
1346 | if (ide_allocate_dma_engine(hwif)) | 1354 | if (ide_allocate_dma_engine(hwif)) |
1347 | return -1; | 1355 | return -1; |
1348 | 1356 | ||
1349 | ide_setup_dma(hwif, base); | 1357 | hwif->dma_ops = &sff_dma_ops; |
1350 | 1358 | ||
1351 | return 0; | 1359 | return 0; |
1352 | } | 1360 | } |
@@ -1401,7 +1409,6 @@ static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2) | |||
1401 | 1409 | ||
1402 | #define IDE_HFLAGS_HPT3XX \ | 1410 | #define IDE_HFLAGS_HPT3XX \ |
1403 | (IDE_HFLAG_NO_ATAPI_DMA | \ | 1411 | (IDE_HFLAG_NO_ATAPI_DMA | \ |
1404 | IDE_HFLAG_ABUSE_SET_DMA_MODE | \ | ||
1405 | IDE_HFLAG_OFF_BOARD) | 1412 | IDE_HFLAG_OFF_BOARD) |
1406 | 1413 | ||
1407 | static const struct ide_port_ops hpt3xx_port_ops = { | 1414 | static const struct ide_port_ops hpt3xx_port_ops = { |
diff --git a/drivers/ide/pci/ns87415.c b/drivers/ide/pci/ns87415.c index 45ba71a7182f..5cd2b32ff0ef 100644 --- a/drivers/ide/pci/ns87415.c +++ b/drivers/ide/pci/ns87415.c | |||
@@ -28,10 +28,6 @@ | |||
28 | */ | 28 | */ |
29 | #include <asm/superio.h> | 29 | #include <asm/superio.h> |
30 | 30 | ||
31 | static unsigned long superio_ide_status[2]; | ||
32 | static unsigned long superio_ide_select[2]; | ||
33 | static unsigned long superio_ide_dma_status[2]; | ||
34 | |||
35 | #define SUPERIO_IDE_MAX_RETRIES 25 | 31 | #define SUPERIO_IDE_MAX_RETRIES 25 |
36 | 32 | ||
37 | /* Because of a defect in Super I/O, all reads of the PCI DMA status | 33 | /* Because of a defect in Super I/O, all reads of the PCI DMA status |
@@ -40,27 +36,28 @@ static unsigned long superio_ide_dma_status[2]; | |||
40 | */ | 36 | */ |
41 | static u8 superio_ide_inb (unsigned long port) | 37 | static u8 superio_ide_inb (unsigned long port) |
42 | { | 38 | { |
43 | if (port == superio_ide_status[0] || | 39 | u8 tmp; |
44 | port == superio_ide_status[1] || | 40 | int retries = SUPERIO_IDE_MAX_RETRIES; |
45 | port == superio_ide_select[0] || | ||
46 | port == superio_ide_select[1] || | ||
47 | port == superio_ide_dma_status[0] || | ||
48 | port == superio_ide_dma_status[1]) { | ||
49 | u8 tmp; | ||
50 | int retries = SUPERIO_IDE_MAX_RETRIES; | ||
51 | 41 | ||
52 | /* printk(" [ reading port 0x%x with retry ] ", port); */ | 42 | /* printk(" [ reading port 0x%x with retry ] ", port); */ |
53 | 43 | ||
54 | do { | 44 | do { |
55 | tmp = inb(port); | 45 | tmp = inb(port); |
56 | if (tmp == 0) | 46 | if (tmp == 0) |
57 | udelay(50); | 47 | udelay(50); |
58 | } while (tmp == 0 && retries-- > 0); | 48 | } while (tmp == 0 && retries-- > 0); |
59 | 49 | ||
60 | return tmp; | 50 | return tmp; |
61 | } | 51 | } |
62 | 52 | ||
63 | return inb(port); | 53 | static u8 superio_read_status(ide_hwif_t *hwif) |
54 | { | ||
55 | return superio_ide_inb(hwif->io_ports.status_addr); | ||
56 | } | ||
57 | |||
58 | static u8 superio_read_sff_dma_status(ide_hwif_t *hwif) | ||
59 | { | ||
60 | return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS); | ||
64 | } | 61 | } |
65 | 62 | ||
66 | static void superio_tf_read(ide_drive_t *drive, ide_task_t *task) | 63 | static void superio_tf_read(ide_drive_t *drive, ide_task_t *task) |
@@ -78,6 +75,8 @@ static void superio_tf_read(ide_drive_t *drive, ide_task_t *task) | |||
78 | /* be sure we're looking at the low order bits */ | 75 | /* be sure we're looking at the low order bits */ |
79 | outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr); | 76 | outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr); |
80 | 77 | ||
78 | if (task->tf_flags & IDE_TFLAG_IN_FEATURE) | ||
79 | tf->feature = inb(io_ports->feature_addr); | ||
81 | if (task->tf_flags & IDE_TFLAG_IN_NSECT) | 80 | if (task->tf_flags & IDE_TFLAG_IN_NSECT) |
82 | tf->nsect = inb(io_ports->nsect_addr); | 81 | tf->nsect = inb(io_ports->nsect_addr); |
83 | if (task->tf_flags & IDE_TFLAG_IN_LBAL) | 82 | if (task->tf_flags & IDE_TFLAG_IN_LBAL) |
@@ -105,36 +104,32 @@ static void superio_tf_read(ide_drive_t *drive, ide_task_t *task) | |||
105 | } | 104 | } |
106 | } | 105 | } |
107 | 106 | ||
108 | static void __devinit superio_ide_init_iops (struct hwif_s *hwif) | 107 | static const struct ide_tp_ops superio_tp_ops = { |
109 | { | 108 | .exec_command = ide_exec_command, |
110 | struct pci_dev *pdev = to_pci_dev(hwif->dev); | 109 | .read_status = superio_read_status, |
111 | u32 base, dmabase; | 110 | .read_altstatus = ide_read_altstatus, |
112 | u8 port = hwif->channel, tmp; | 111 | .read_sff_dma_status = superio_read_sff_dma_status, |
113 | 112 | ||
114 | base = pci_resource_start(pdev, port * 2) & ~3; | 113 | .set_irq = ide_set_irq, |
115 | dmabase = pci_resource_start(pdev, 4) & ~3; | ||
116 | |||
117 | superio_ide_status[port] = base + 7; | ||
118 | superio_ide_select[port] = base + 6; | ||
119 | superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa); | ||
120 | |||
121 | /* Clear error/interrupt, enable dma */ | ||
122 | tmp = superio_ide_inb(superio_ide_dma_status[port]); | ||
123 | outb(tmp | 0x66, superio_ide_dma_status[port]); | ||
124 | 114 | ||
125 | hwif->tf_read = superio_tf_read; | 115 | .tf_load = ide_tf_load, |
116 | .tf_read = superio_tf_read, | ||
126 | 117 | ||
127 | /* We need to override inb to workaround a SuperIO errata */ | 118 | .input_data = ide_input_data, |
128 | hwif->INB = superio_ide_inb; | 119 | .output_data = ide_output_data, |
129 | } | 120 | }; |
130 | 121 | ||
131 | static void __devinit init_iops_ns87415(ide_hwif_t *hwif) | 122 | static void __devinit superio_init_iops(struct hwif_s *hwif) |
132 | { | 123 | { |
133 | struct pci_dev *dev = to_pci_dev(hwif->dev); | 124 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
125 | u32 dma_stat; | ||
126 | u8 port = hwif->channel, tmp; | ||
134 | 127 | ||
135 | if (PCI_SLOT(dev->devfn) == 0xE) | 128 | dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa); |
136 | /* Built-in - assume it's under superio. */ | 129 | |
137 | superio_ide_init_iops(hwif); | 130 | /* Clear error/interrupt, enable dma */ |
131 | tmp = superio_ide_inb(dma_stat); | ||
132 | outb(tmp | 0x66, dma_stat); | ||
138 | } | 133 | } |
139 | #endif | 134 | #endif |
140 | 135 | ||
@@ -200,14 +195,14 @@ static int ns87415_dma_end(ide_drive_t *drive) | |||
200 | u8 dma_stat = 0, dma_cmd = 0; | 195 | u8 dma_stat = 0, dma_cmd = 0; |
201 | 196 | ||
202 | drive->waiting_for_dma = 0; | 197 | drive->waiting_for_dma = 0; |
203 | dma_stat = hwif->INB(hwif->dma_status); | 198 | dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); |
204 | /* get dma command mode */ | 199 | /* get DMA command mode */ |
205 | dma_cmd = hwif->INB(hwif->dma_command); | 200 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
206 | /* stop DMA */ | 201 | /* stop DMA */ |
207 | outb(dma_cmd & ~1, hwif->dma_command); | 202 | outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); |
208 | /* from ERRATA: clear the INTR & ERROR bits */ | 203 | /* from ERRATA: clear the INTR & ERROR bits */ |
209 | dma_cmd = hwif->INB(hwif->dma_command); | 204 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
210 | outb(dma_cmd | 6, hwif->dma_command); | 205 | outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD); |
211 | /* and free any DMA resources */ | 206 | /* and free any DMA resources */ |
212 | ide_destroy_dmatable(drive); | 207 | ide_destroy_dmatable(drive); |
213 | /* verify good DMA status */ | 208 | /* verify good DMA status */ |
@@ -276,7 +271,7 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif) | |||
276 | outb(8, hwif->io_ports.ctl_addr); | 271 | outb(8, hwif->io_ports.ctl_addr); |
277 | do { | 272 | do { |
278 | udelay(50); | 273 | udelay(50); |
279 | stat = hwif->INB(hwif->io_ports.status_addr); | 274 | stat = hwif->tp_ops->read_status(hwif); |
280 | if (stat == 0xff) | 275 | if (stat == 0xff) |
281 | break; | 276 | break; |
282 | } while ((stat & BUSY_STAT) && --timeout); | 277 | } while ((stat & BUSY_STAT) && --timeout); |
@@ -291,7 +286,7 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif) | |||
291 | if (!hwif->dma_base) | 286 | if (!hwif->dma_base) |
292 | return; | 287 | return; |
293 | 288 | ||
294 | outb(0x60, hwif->dma_status); | 289 | outb(0x60, hwif->dma_base + ATA_DMA_STATUS); |
295 | } | 290 | } |
296 | 291 | ||
297 | static const struct ide_port_ops ns87415_port_ops = { | 292 | static const struct ide_port_ops ns87415_port_ops = { |
@@ -311,9 +306,6 @@ static const struct ide_dma_ops ns87415_dma_ops = { | |||
311 | 306 | ||
312 | static const struct ide_port_info ns87415_chipset __devinitdata = { | 307 | static const struct ide_port_info ns87415_chipset __devinitdata = { |
313 | .name = "NS87415", | 308 | .name = "NS87415", |
314 | #ifdef CONFIG_SUPERIO | ||
315 | .init_iops = init_iops_ns87415, | ||
316 | #endif | ||
317 | .init_hwif = init_hwif_ns87415, | 309 | .init_hwif = init_hwif_ns87415, |
318 | .port_ops = &ns87415_port_ops, | 310 | .port_ops = &ns87415_port_ops, |
319 | .dma_ops = &ns87415_dma_ops, | 311 | .dma_ops = &ns87415_dma_ops, |
@@ -323,7 +315,16 @@ static const struct ide_port_info ns87415_chipset __devinitdata = { | |||
323 | 315 | ||
324 | static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id) | 316 | static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
325 | { | 317 | { |
326 | return ide_setup_pci_device(dev, &ns87415_chipset); | 318 | struct ide_port_info d = ns87415_chipset; |
319 | |||
320 | #ifdef CONFIG_SUPERIO | ||
321 | if (PCI_SLOT(dev->devfn) == 0xE) { | ||
322 | /* Built-in - assume it's under superio. */ | ||
323 | d.init_iops = superio_init_iops; | ||
324 | d.tp_ops = &superio_tp_ops; | ||
325 | } | ||
326 | #endif | ||
327 | return ide_setup_pci_device(dev, &d); | ||
327 | } | 328 | } |
328 | 329 | ||
329 | static const struct pci_device_id ns87415_pci_tbl[] = { | 330 | static const struct pci_device_id ns87415_pci_tbl[] = { |
diff --git a/drivers/ide/pci/pdc202xx_old.c b/drivers/ide/pci/pdc202xx_old.c index fca89eda5c02..e54dc653b8c4 100644 --- a/drivers/ide/pci/pdc202xx_old.c +++ b/drivers/ide/pci/pdc202xx_old.c | |||
@@ -206,7 +206,7 @@ static int pdc202xx_dma_test_irq(ide_drive_t *drive) | |||
206 | { | 206 | { |
207 | ide_hwif_t *hwif = HWIF(drive); | 207 | ide_hwif_t *hwif = HWIF(drive); |
208 | unsigned long high_16 = hwif->extra_base - 16; | 208 | unsigned long high_16 = hwif->extra_base - 16; |
209 | u8 dma_stat = inb(hwif->dma_status); | 209 | u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
210 | u8 sc1d = inb(high_16 + 0x001d); | 210 | u8 sc1d = inb(high_16 + 0x001d); |
211 | 211 | ||
212 | if (hwif->channel) { | 212 | if (hwif->channel) { |
@@ -312,7 +312,6 @@ static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev, | |||
312 | 312 | ||
313 | #define IDE_HFLAGS_PDC202XX \ | 313 | #define IDE_HFLAGS_PDC202XX \ |
314 | (IDE_HFLAG_ERROR_STOPS_FIFO | \ | 314 | (IDE_HFLAG_ERROR_STOPS_FIFO | \ |
315 | IDE_HFLAG_ABUSE_SET_DMA_MODE | \ | ||
316 | IDE_HFLAG_OFF_BOARD) | 315 | IDE_HFLAG_OFF_BOARD) |
317 | 316 | ||
318 | static const struct ide_port_ops pdc20246_port_ops = { | 317 | static const struct ide_port_ops pdc20246_port_ops = { |
diff --git a/drivers/ide/pci/piix.c b/drivers/ide/pci/piix.c index f04738d14a6f..0ce41b4dddaf 100644 --- a/drivers/ide/pci/piix.c +++ b/drivers/ide/pci/piix.c | |||
@@ -227,9 +227,9 @@ static void piix_dma_clear_irq(ide_drive_t *drive) | |||
227 | u8 dma_stat; | 227 | u8 dma_stat; |
228 | 228 | ||
229 | /* clear the INTR & ERROR bits */ | 229 | /* clear the INTR & ERROR bits */ |
230 | dma_stat = inb(hwif->dma_status); | 230 | dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
231 | /* Should we force the bit as well ? */ | 231 | /* Should we force the bit as well ? */ |
232 | outb(dma_stat, hwif->dma_status); | 232 | outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS); |
233 | } | 233 | } |
234 | 234 | ||
235 | struct ich_laptop { | 235 | struct ich_laptop { |
diff --git a/drivers/ide/pci/scc_pata.c b/drivers/ide/pci/scc_pata.c index 789c66dfbde5..94a7ab864236 100644 --- a/drivers/ide/pci/scc_pata.c +++ b/drivers/ide/pci/scc_pata.c | |||
@@ -65,7 +65,7 @@ | |||
65 | 65 | ||
66 | static struct scc_ports { | 66 | static struct scc_ports { |
67 | unsigned long ctl, dma; | 67 | unsigned long ctl, dma; |
68 | ide_hwif_t *hwif; /* for removing port from system */ | 68 | struct ide_host *host; /* for removing port from system */ |
69 | } scc_ports[MAX_HWIFS]; | 69 | } scc_ports[MAX_HWIFS]; |
70 | 70 | ||
71 | /* PIO transfer mode table */ | 71 | /* PIO transfer mode table */ |
@@ -126,6 +126,46 @@ static u8 scc_ide_inb(unsigned long port) | |||
126 | return (u8)data; | 126 | return (u8)data; |
127 | } | 127 | } |
128 | 128 | ||
129 | static void scc_exec_command(ide_hwif_t *hwif, u8 cmd) | ||
130 | { | ||
131 | out_be32((void *)hwif->io_ports.command_addr, cmd); | ||
132 | eieio(); | ||
133 | in_be32((void *)(hwif->dma_base + 0x01c)); | ||
134 | eieio(); | ||
135 | } | ||
136 | |||
137 | static u8 scc_read_status(ide_hwif_t *hwif) | ||
138 | { | ||
139 | return (u8)in_be32((void *)hwif->io_ports.status_addr); | ||
140 | } | ||
141 | |||
142 | static u8 scc_read_altstatus(ide_hwif_t *hwif) | ||
143 | { | ||
144 | return (u8)in_be32((void *)hwif->io_ports.ctl_addr); | ||
145 | } | ||
146 | |||
147 | static u8 scc_read_sff_dma_status(ide_hwif_t *hwif) | ||
148 | { | ||
149 | return (u8)in_be32((void *)(hwif->dma_base + 4)); | ||
150 | } | ||
151 | |||
152 | static void scc_set_irq(ide_hwif_t *hwif, int on) | ||
153 | { | ||
154 | u8 ctl = ATA_DEVCTL_OBS; | ||
155 | |||
156 | if (on == 4) { /* hack for SRST */ | ||
157 | ctl |= 4; | ||
158 | on &= ~4; | ||
159 | } | ||
160 | |||
161 | ctl |= on ? 0 : 2; | ||
162 | |||
163 | out_be32((void *)hwif->io_ports.ctl_addr, ctl); | ||
164 | eieio(); | ||
165 | in_be32((void *)(hwif->dma_base + 0x01c)); | ||
166 | eieio(); | ||
167 | } | ||
168 | |||
129 | static void scc_ide_insw(unsigned long port, void *addr, u32 count) | 169 | static void scc_ide_insw(unsigned long port, void *addr, u32 count) |
130 | { | 170 | { |
131 | u16 *ptr = (u16 *)addr; | 171 | u16 *ptr = (u16 *)addr; |
@@ -148,14 +188,6 @@ static void scc_ide_outb(u8 addr, unsigned long port) | |||
148 | out_be32((void*)port, addr); | 188 | out_be32((void*)port, addr); |
149 | } | 189 | } |
150 | 190 | ||
151 | static void scc_ide_outbsync(ide_hwif_t *hwif, u8 addr, unsigned long port) | ||
152 | { | ||
153 | out_be32((void*)port, addr); | ||
154 | eieio(); | ||
155 | in_be32((void*)(hwif->dma_base + 0x01c)); | ||
156 | eieio(); | ||
157 | } | ||
158 | |||
159 | static void | 191 | static void |
160 | scc_ide_outsw(unsigned long port, void *addr, u32 count) | 192 | scc_ide_outsw(unsigned long port, void *addr, u32 count) |
161 | { | 193 | { |
@@ -261,14 +293,14 @@ static void scc_dma_host_set(ide_drive_t *drive, int on) | |||
261 | { | 293 | { |
262 | ide_hwif_t *hwif = drive->hwif; | 294 | ide_hwif_t *hwif = drive->hwif; |
263 | u8 unit = (drive->select.b.unit & 0x01); | 295 | u8 unit = (drive->select.b.unit & 0x01); |
264 | u8 dma_stat = scc_ide_inb(hwif->dma_status); | 296 | u8 dma_stat = scc_ide_inb(hwif->dma_base + 4); |
265 | 297 | ||
266 | if (on) | 298 | if (on) |
267 | dma_stat |= (1 << (5 + unit)); | 299 | dma_stat |= (1 << (5 + unit)); |
268 | else | 300 | else |
269 | dma_stat &= ~(1 << (5 + unit)); | 301 | dma_stat &= ~(1 << (5 + unit)); |
270 | 302 | ||
271 | scc_ide_outb(dma_stat, hwif->dma_status); | 303 | scc_ide_outb(dma_stat, hwif->dma_base + 4); |
272 | } | 304 | } |
273 | 305 | ||
274 | /** | 306 | /** |
@@ -304,13 +336,13 @@ static int scc_dma_setup(ide_drive_t *drive) | |||
304 | out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma); | 336 | out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma); |
305 | 337 | ||
306 | /* specify r/w */ | 338 | /* specify r/w */ |
307 | out_be32((void __iomem *)hwif->dma_command, reading); | 339 | out_be32((void __iomem *)hwif->dma_base, reading); |
308 | 340 | ||
309 | /* read dma_status for INTR & ERROR flags */ | 341 | /* read DMA status for INTR & ERROR flags */ |
310 | dma_stat = in_be32((void __iomem *)hwif->dma_status); | 342 | dma_stat = in_be32((void __iomem *)(hwif->dma_base + 4)); |
311 | 343 | ||
312 | /* clear INTR & ERROR flags */ | 344 | /* clear INTR & ERROR flags */ |
313 | out_be32((void __iomem *)hwif->dma_status, dma_stat|6); | 345 | out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6); |
314 | drive->waiting_for_dma = 1; | 346 | drive->waiting_for_dma = 1; |
315 | return 0; | 347 | return 0; |
316 | } | 348 | } |
@@ -318,10 +350,10 @@ static int scc_dma_setup(ide_drive_t *drive) | |||
318 | static void scc_dma_start(ide_drive_t *drive) | 350 | static void scc_dma_start(ide_drive_t *drive) |
319 | { | 351 | { |
320 | ide_hwif_t *hwif = drive->hwif; | 352 | ide_hwif_t *hwif = drive->hwif; |
321 | u8 dma_cmd = scc_ide_inb(hwif->dma_command); | 353 | u8 dma_cmd = scc_ide_inb(hwif->dma_base); |
322 | 354 | ||
323 | /* start DMA */ | 355 | /* start DMA */ |
324 | scc_ide_outb(dma_cmd | 1, hwif->dma_command); | 356 | scc_ide_outb(dma_cmd | 1, hwif->dma_base); |
325 | hwif->dma = 1; | 357 | hwif->dma = 1; |
326 | wmb(); | 358 | wmb(); |
327 | } | 359 | } |
@@ -333,13 +365,13 @@ static int __scc_dma_end(ide_drive_t *drive) | |||
333 | 365 | ||
334 | drive->waiting_for_dma = 0; | 366 | drive->waiting_for_dma = 0; |
335 | /* get DMA command mode */ | 367 | /* get DMA command mode */ |
336 | dma_cmd = scc_ide_inb(hwif->dma_command); | 368 | dma_cmd = scc_ide_inb(hwif->dma_base); |
337 | /* stop DMA */ | 369 | /* stop DMA */ |
338 | scc_ide_outb(dma_cmd & ~1, hwif->dma_command); | 370 | scc_ide_outb(dma_cmd & ~1, hwif->dma_base); |
339 | /* get DMA status */ | 371 | /* get DMA status */ |
340 | dma_stat = scc_ide_inb(hwif->dma_status); | 372 | dma_stat = scc_ide_inb(hwif->dma_base + 4); |
341 | /* clear the INTR & ERROR bits */ | 373 | /* clear the INTR & ERROR bits */ |
342 | scc_ide_outb(dma_stat | 6, hwif->dma_status); | 374 | scc_ide_outb(dma_stat | 6, hwif->dma_base + 4); |
343 | /* purge DMA mappings */ | 375 | /* purge DMA mappings */ |
344 | ide_destroy_dmatable(drive); | 376 | ide_destroy_dmatable(drive); |
345 | /* verify good DMA status */ | 377 | /* verify good DMA status */ |
@@ -359,6 +391,7 @@ static int __scc_dma_end(ide_drive_t *drive) | |||
359 | static int scc_dma_end(ide_drive_t *drive) | 391 | static int scc_dma_end(ide_drive_t *drive) |
360 | { | 392 | { |
361 | ide_hwif_t *hwif = HWIF(drive); | 393 | ide_hwif_t *hwif = HWIF(drive); |
394 | void __iomem *dma_base = (void __iomem *)hwif->dma_base; | ||
362 | unsigned long intsts_port = hwif->dma_base + 0x014; | 395 | unsigned long intsts_port = hwif->dma_base + 0x014; |
363 | u32 reg; | 396 | u32 reg; |
364 | int dma_stat, data_loss = 0; | 397 | int dma_stat, data_loss = 0; |
@@ -397,7 +430,7 @@ static int scc_dma_end(ide_drive_t *drive) | |||
397 | printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME); | 430 | printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME); |
398 | out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT); | 431 | out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT); |
399 | 432 | ||
400 | out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); | 433 | out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
401 | continue; | 434 | continue; |
402 | } | 435 | } |
403 | 436 | ||
@@ -412,7 +445,7 @@ static int scc_dma_end(ide_drive_t *drive) | |||
412 | 445 | ||
413 | out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT); | 446 | out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT); |
414 | 447 | ||
415 | out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); | 448 | out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
416 | continue; | 449 | continue; |
417 | } | 450 | } |
418 | 451 | ||
@@ -420,12 +453,12 @@ static int scc_dma_end(ide_drive_t *drive) | |||
420 | printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME); | 453 | printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME); |
421 | out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT); | 454 | out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT); |
422 | 455 | ||
423 | out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); | 456 | out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
424 | continue; | 457 | continue; |
425 | } | 458 | } |
426 | 459 | ||
427 | if (reg & INTSTS_ICERR) { | 460 | if (reg & INTSTS_ICERR) { |
428 | out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); | 461 | out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
429 | 462 | ||
430 | printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME); | 463 | printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME); |
431 | out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT); | 464 | out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT); |
@@ -553,14 +586,9 @@ static int scc_ide_setup_pci_device(struct pci_dev *dev, | |||
553 | const struct ide_port_info *d) | 586 | const struct ide_port_info *d) |
554 | { | 587 | { |
555 | struct scc_ports *ports = pci_get_drvdata(dev); | 588 | struct scc_ports *ports = pci_get_drvdata(dev); |
556 | ide_hwif_t *hwif = NULL; | 589 | struct ide_host *host; |
557 | hw_regs_t hw; | 590 | hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL }; |
558 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; | 591 | int i, rc; |
559 | int i; | ||
560 | |||
561 | hwif = ide_find_port_slot(d); | ||
562 | if (hwif == NULL) | ||
563 | return -ENOMEM; | ||
564 | 592 | ||
565 | memset(&hw, 0, sizeof(hw)); | 593 | memset(&hw, 0, sizeof(hw)); |
566 | for (i = 0; i <= 8; i++) | 594 | for (i = 0; i <= 8; i++) |
@@ -568,11 +596,12 @@ static int scc_ide_setup_pci_device(struct pci_dev *dev, | |||
568 | hw.irq = dev->irq; | 596 | hw.irq = dev->irq; |
569 | hw.dev = &dev->dev; | 597 | hw.dev = &dev->dev; |
570 | hw.chipset = ide_pci; | 598 | hw.chipset = ide_pci; |
571 | ide_init_port_hw(hwif, &hw); | ||
572 | 599 | ||
573 | idx[0] = hwif->index; | 600 | rc = ide_host_add(d, hws, &host); |
601 | if (rc) | ||
602 | return rc; | ||
574 | 603 | ||
575 | ide_device_add(idx, d); | 604 | ports->host = host; |
576 | 605 | ||
577 | return 0; | 606 | return 0; |
578 | } | 607 | } |
@@ -701,6 +730,8 @@ static void scc_tf_read(ide_drive_t *drive, ide_task_t *task) | |||
701 | /* be sure we're looking at the low order bits */ | 730 | /* be sure we're looking at the low order bits */ |
702 | scc_ide_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr); | 731 | scc_ide_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr); |
703 | 732 | ||
733 | if (task->tf_flags & IDE_TFLAG_IN_FEATURE) | ||
734 | tf->feature = scc_ide_inb(io_ports->feature_addr); | ||
704 | if (task->tf_flags & IDE_TFLAG_IN_NSECT) | 735 | if (task->tf_flags & IDE_TFLAG_IN_NSECT) |
705 | tf->nsect = scc_ide_inb(io_ports->nsect_addr); | 736 | tf->nsect = scc_ide_inb(io_ports->nsect_addr); |
706 | if (task->tf_flags & IDE_TFLAG_IN_LBAL) | 737 | if (task->tf_flags & IDE_TFLAG_IN_LBAL) |
@@ -774,16 +805,6 @@ static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif) | |||
774 | 805 | ||
775 | ide_set_hwifdata(hwif, ports); | 806 | ide_set_hwifdata(hwif, ports); |
776 | 807 | ||
777 | hwif->tf_load = scc_tf_load; | ||
778 | hwif->tf_read = scc_tf_read; | ||
779 | |||
780 | hwif->input_data = scc_input_data; | ||
781 | hwif->output_data = scc_output_data; | ||
782 | |||
783 | hwif->INB = scc_ide_inb; | ||
784 | hwif->OUTB = scc_ide_outb; | ||
785 | hwif->OUTBSYNC = scc_ide_outbsync; | ||
786 | |||
787 | hwif->dma_base = dma_base; | 808 | hwif->dma_base = dma_base; |
788 | hwif->config_data = ports->ctl; | 809 | hwif->config_data = ports->ctl; |
789 | } | 810 | } |
@@ -824,11 +845,6 @@ static void __devinit init_hwif_scc(ide_hwif_t *hwif) | |||
824 | { | 845 | { |
825 | struct scc_ports *ports = ide_get_hwifdata(hwif); | 846 | struct scc_ports *ports = ide_get_hwifdata(hwif); |
826 | 847 | ||
827 | ports->hwif = hwif; | ||
828 | |||
829 | hwif->dma_command = hwif->dma_base; | ||
830 | hwif->dma_status = hwif->dma_base + 0x04; | ||
831 | |||
832 | /* PTERADD */ | 848 | /* PTERADD */ |
833 | out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma); | 849 | out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma); |
834 | 850 | ||
@@ -838,6 +854,21 @@ static void __devinit init_hwif_scc(ide_hwif_t *hwif) | |||
838 | hwif->ultra_mask = ATA_UDMA5; /* 100MHz */ | 854 | hwif->ultra_mask = ATA_UDMA5; /* 100MHz */ |
839 | } | 855 | } |
840 | 856 | ||
857 | static const struct ide_tp_ops scc_tp_ops = { | ||
858 | .exec_command = scc_exec_command, | ||
859 | .read_status = scc_read_status, | ||
860 | .read_altstatus = scc_read_altstatus, | ||
861 | .read_sff_dma_status = scc_read_sff_dma_status, | ||
862 | |||
863 | .set_irq = scc_set_irq, | ||
864 | |||
865 | .tf_load = scc_tf_load, | ||
866 | .tf_read = scc_tf_read, | ||
867 | |||
868 | .input_data = scc_input_data, | ||
869 | .output_data = scc_output_data, | ||
870 | }; | ||
871 | |||
841 | static const struct ide_port_ops scc_port_ops = { | 872 | static const struct ide_port_ops scc_port_ops = { |
842 | .set_pio_mode = scc_set_pio_mode, | 873 | .set_pio_mode = scc_set_pio_mode, |
843 | .set_dma_mode = scc_set_dma_mode, | 874 | .set_dma_mode = scc_set_dma_mode, |
@@ -861,6 +892,7 @@ static const struct ide_dma_ops scc_dma_ops = { | |||
861 | .name = name_str, \ | 892 | .name = name_str, \ |
862 | .init_iops = init_iops_scc, \ | 893 | .init_iops = init_iops_scc, \ |
863 | .init_hwif = init_hwif_scc, \ | 894 | .init_hwif = init_hwif_scc, \ |
895 | .tp_ops = &scc_tp_ops, \ | ||
864 | .port_ops = &scc_port_ops, \ | 896 | .port_ops = &scc_port_ops, \ |
865 | .dma_ops = &scc_dma_ops, \ | 897 | .dma_ops = &scc_dma_ops, \ |
866 | .host_flags = IDE_HFLAG_SINGLE, \ | 898 | .host_flags = IDE_HFLAG_SINGLE, \ |
@@ -895,7 +927,8 @@ static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_i | |||
895 | static void __devexit scc_remove(struct pci_dev *dev) | 927 | static void __devexit scc_remove(struct pci_dev *dev) |
896 | { | 928 | { |
897 | struct scc_ports *ports = pci_get_drvdata(dev); | 929 | struct scc_ports *ports = pci_get_drvdata(dev); |
898 | ide_hwif_t *hwif = ports->hwif; | 930 | struct ide_host *host = ports->host; |
931 | ide_hwif_t *hwif = host->ports[0]; | ||
899 | 932 | ||
900 | if (hwif->dmatable_cpu) { | 933 | if (hwif->dmatable_cpu) { |
901 | pci_free_consistent(dev, PRD_ENTRIES * PRD_BYTES, | 934 | pci_free_consistent(dev, PRD_ENTRIES * PRD_BYTES, |
@@ -903,7 +936,7 @@ static void __devexit scc_remove(struct pci_dev *dev) | |||
903 | hwif->dmatable_cpu = NULL; | 936 | hwif->dmatable_cpu = NULL; |
904 | } | 937 | } |
905 | 938 | ||
906 | ide_unregister(hwif); | 939 | ide_host_remove(host); |
907 | 940 | ||
908 | iounmap((void*)ports->dma); | 941 | iounmap((void*)ports->dma); |
909 | iounmap((void*)ports->ctl); | 942 | iounmap((void*)ports->ctl); |
diff --git a/drivers/ide/pci/serverworks.c b/drivers/ide/pci/serverworks.c index a1fb20826a5b..127ccb45e261 100644 --- a/drivers/ide/pci/serverworks.c +++ b/drivers/ide/pci/serverworks.c | |||
@@ -349,9 +349,7 @@ static const struct ide_port_ops svwks_port_ops = { | |||
349 | .cable_detect = svwks_cable_detect, | 349 | .cable_detect = svwks_cable_detect, |
350 | }; | 350 | }; |
351 | 351 | ||
352 | #define IDE_HFLAGS_SVWKS \ | 352 | #define IDE_HFLAGS_SVWKS IDE_HFLAG_LEGACY_IRQS |
353 | (IDE_HFLAG_LEGACY_IRQS | \ | ||
354 | IDE_HFLAG_ABUSE_SET_DMA_MODE) | ||
355 | 353 | ||
356 | static const struct ide_port_info serverworks_chipsets[] __devinitdata = { | 354 | static const struct ide_port_info serverworks_chipsets[] __devinitdata = { |
357 | { /* 0 */ | 355 | { /* 0 */ |
diff --git a/drivers/ide/pci/sgiioc4.c b/drivers/ide/pci/sgiioc4.c index c79ff5b41088..42eef19a18f1 100644 --- a/drivers/ide/pci/sgiioc4.c +++ b/drivers/ide/pci/sgiioc4.c | |||
@@ -127,7 +127,7 @@ sgiioc4_checkirq(ide_hwif_t * hwif) | |||
127 | return 0; | 127 | return 0; |
128 | } | 128 | } |
129 | 129 | ||
130 | static u8 sgiioc4_INB(unsigned long); | 130 | static u8 sgiioc4_read_status(ide_hwif_t *); |
131 | 131 | ||
132 | static int | 132 | static int |
133 | sgiioc4_clearirq(ide_drive_t * drive) | 133 | sgiioc4_clearirq(ide_drive_t * drive) |
@@ -141,18 +141,19 @@ sgiioc4_clearirq(ide_drive_t * drive) | |||
141 | intr_reg = readl((void __iomem *)other_ir); | 141 | intr_reg = readl((void __iomem *)other_ir); |
142 | if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */ | 142 | if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */ |
143 | /* | 143 | /* |
144 | * Using sgiioc4_INB to read the Status register has a side | 144 | * Using sgiioc4_read_status to read the Status register has a |
145 | * effect of clearing the interrupt. The first read should | 145 | * side effect of clearing the interrupt. The first read should |
146 | * clear it if it is set. The second read should return | 146 | * clear it if it is set. The second read should return |
147 | * a "clear" status if it got cleared. If not, then spin | 147 | * a "clear" status if it got cleared. If not, then spin |
148 | * for a bit trying to clear it. | 148 | * for a bit trying to clear it. |
149 | */ | 149 | */ |
150 | u8 stat = sgiioc4_INB(io_ports->status_addr); | 150 | u8 stat = sgiioc4_read_status(hwif); |
151 | int count = 0; | 151 | int count = 0; |
152 | stat = sgiioc4_INB(io_ports->status_addr); | 152 | |
153 | stat = sgiioc4_read_status(hwif); | ||
153 | while ((stat & 0x80) && (count++ < 100)) { | 154 | while ((stat & 0x80) && (count++ < 100)) { |
154 | udelay(1); | 155 | udelay(1); |
155 | stat = sgiioc4_INB(io_ports->status_addr); | 156 | stat = sgiioc4_read_status(hwif); |
156 | } | 157 | } |
157 | 158 | ||
158 | if (intr_reg & 0x02) { | 159 | if (intr_reg & 0x02) { |
@@ -304,9 +305,9 @@ sgiioc4_dma_lost_irq(ide_drive_t * drive) | |||
304 | ide_dma_lost_irq(drive); | 305 | ide_dma_lost_irq(drive); |
305 | } | 306 | } |
306 | 307 | ||
307 | static u8 | 308 | static u8 sgiioc4_read_status(ide_hwif_t *hwif) |
308 | sgiioc4_INB(unsigned long port) | ||
309 | { | 309 | { |
310 | unsigned long port = hwif->io_ports.status_addr; | ||
310 | u8 reg = (u8) readb((void __iomem *) port); | 311 | u8 reg = (u8) readb((void __iomem *) port); |
311 | 312 | ||
312 | if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */ | 313 | if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */ |
@@ -549,6 +550,21 @@ static int sgiioc4_dma_setup(ide_drive_t *drive) | |||
549 | return 0; | 550 | return 0; |
550 | } | 551 | } |
551 | 552 | ||
553 | static const struct ide_tp_ops sgiioc4_tp_ops = { | ||
554 | .exec_command = ide_exec_command, | ||
555 | .read_status = sgiioc4_read_status, | ||
556 | .read_altstatus = ide_read_altstatus, | ||
557 | .read_sff_dma_status = ide_read_sff_dma_status, | ||
558 | |||
559 | .set_irq = ide_set_irq, | ||
560 | |||
561 | .tf_load = ide_tf_load, | ||
562 | .tf_read = ide_tf_read, | ||
563 | |||
564 | .input_data = ide_input_data, | ||
565 | .output_data = ide_output_data, | ||
566 | }; | ||
567 | |||
552 | static const struct ide_port_ops sgiioc4_port_ops = { | 568 | static const struct ide_port_ops sgiioc4_port_ops = { |
553 | .set_dma_mode = sgiioc4_set_dma_mode, | 569 | .set_dma_mode = sgiioc4_set_dma_mode, |
554 | /* reset DMA engine, clear IRQs */ | 570 | /* reset DMA engine, clear IRQs */ |
@@ -571,6 +587,7 @@ static const struct ide_port_info sgiioc4_port_info __devinitdata = { | |||
571 | .name = DRV_NAME, | 587 | .name = DRV_NAME, |
572 | .chipset = ide_pci, | 588 | .chipset = ide_pci, |
573 | .init_dma = ide_dma_sgiioc4, | 589 | .init_dma = ide_dma_sgiioc4, |
590 | .tp_ops = &sgiioc4_tp_ops, | ||
574 | .port_ops = &sgiioc4_port_ops, | 591 | .port_ops = &sgiioc4_port_ops, |
575 | .dma_ops = &sgiioc4_dma_ops, | 592 | .dma_ops = &sgiioc4_dma_ops, |
576 | .host_flags = IDE_HFLAG_MMIO, | 593 | .host_flags = IDE_HFLAG_MMIO, |
@@ -583,10 +600,10 @@ sgiioc4_ide_setup_pci_device(struct pci_dev *dev) | |||
583 | unsigned long cmd_base, irqport; | 600 | unsigned long cmd_base, irqport; |
584 | unsigned long bar0, cmd_phys_base, ctl; | 601 | unsigned long bar0, cmd_phys_base, ctl; |
585 | void __iomem *virt_base; | 602 | void __iomem *virt_base; |
586 | ide_hwif_t *hwif; | 603 | struct ide_host *host; |
587 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; | 604 | hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL }; |
588 | hw_regs_t hw; | ||
589 | struct ide_port_info d = sgiioc4_port_info; | 605 | struct ide_port_info d = sgiioc4_port_info; |
606 | int rc; | ||
590 | 607 | ||
591 | /* Get the CmdBlk and CtrlBlk Base Registers */ | 608 | /* Get the CmdBlk and CtrlBlk Base Registers */ |
592 | bar0 = pci_resource_start(dev, 0); | 609 | bar0 = pci_resource_start(dev, 0); |
@@ -618,30 +635,26 @@ sgiioc4_ide_setup_pci_device(struct pci_dev *dev) | |||
618 | hw.chipset = ide_pci; | 635 | hw.chipset = ide_pci; |
619 | hw.dev = &dev->dev; | 636 | hw.dev = &dev->dev; |
620 | 637 | ||
621 | hwif = ide_find_port_slot(&d); | ||
622 | if (hwif == NULL) | ||
623 | goto err; | ||
624 | |||
625 | ide_init_port_hw(hwif, &hw); | ||
626 | |||
627 | /* The IOC4 uses MMIO rather than Port IO. */ | ||
628 | default_hwif_mmiops(hwif); | ||
629 | |||
630 | /* Initializing chipset IRQ Registers */ | 638 | /* Initializing chipset IRQ Registers */ |
631 | writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4)); | 639 | writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4)); |
632 | 640 | ||
633 | hwif->INB = &sgiioc4_INB; | 641 | host = ide_host_alloc(&d, hws); |
634 | 642 | if (host == NULL) { | |
635 | idx[0] = hwif->index; | 643 | rc = -ENOMEM; |
644 | goto err; | ||
645 | } | ||
636 | 646 | ||
637 | if (ide_device_add(idx, &d)) | 647 | rc = ide_host_register(host, &d, hws); |
638 | return -EIO; | 648 | if (rc) |
649 | goto err_free; | ||
639 | 650 | ||
640 | return 0; | 651 | return 0; |
652 | err_free: | ||
653 | ide_host_free(host); | ||
641 | err: | 654 | err: |
642 | release_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE); | 655 | release_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE); |
643 | iounmap(virt_base); | 656 | iounmap(virt_base); |
644 | return -ENOMEM; | 657 | return rc; |
645 | } | 658 | } |
646 | 659 | ||
647 | static unsigned int __devinit | 660 | static unsigned int __devinit |
diff --git a/drivers/ide/pci/siimage.c b/drivers/ide/pci/siimage.c index 6e9d7655d89c..5965a35d94ae 100644 --- a/drivers/ide/pci/siimage.c +++ b/drivers/ide/pci/siimage.c | |||
@@ -334,7 +334,7 @@ static int siimage_io_dma_test_irq(ide_drive_t *drive) | |||
334 | unsigned long addr = siimage_selreg(hwif, 1); | 334 | unsigned long addr = siimage_selreg(hwif, 1); |
335 | 335 | ||
336 | /* return 1 if INTR asserted */ | 336 | /* return 1 if INTR asserted */ |
337 | if (hwif->INB(hwif->dma_status) & 4) | 337 | if (inb(hwif->dma_base + ATA_DMA_STATUS) & 4) |
338 | return 1; | 338 | return 1; |
339 | 339 | ||
340 | /* return 1 if Device INTR asserted */ | 340 | /* return 1 if Device INTR asserted */ |
@@ -382,7 +382,7 @@ static int siimage_mmio_dma_test_irq(ide_drive_t *drive) | |||
382 | } | 382 | } |
383 | 383 | ||
384 | /* return 1 if INTR asserted */ | 384 | /* return 1 if INTR asserted */ |
385 | if (readb((void __iomem *)hwif->dma_status) & 0x04) | 385 | if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4) |
386 | return 1; | 386 | return 1; |
387 | 387 | ||
388 | /* return 1 if Device INTR asserted */ | 388 | /* return 1 if Device INTR asserted */ |
@@ -601,7 +601,7 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) | |||
601 | * Fill in the basic hwif bits | 601 | * Fill in the basic hwif bits |
602 | */ | 602 | */ |
603 | hwif->host_flags |= IDE_HFLAG_MMIO; | 603 | hwif->host_flags |= IDE_HFLAG_MMIO; |
604 | default_hwif_mmiops(hwif); | 604 | |
605 | hwif->hwif_data = addr; | 605 | hwif->hwif_data = addr; |
606 | 606 | ||
607 | /* | 607 | /* |
diff --git a/drivers/ide/pci/sl82c105.c b/drivers/ide/pci/sl82c105.c index 6efbde297174..f82a6502c1b7 100644 --- a/drivers/ide/pci/sl82c105.c +++ b/drivers/ide/pci/sl82c105.c | |||
@@ -157,9 +157,9 @@ static void sl82c105_dma_lost_irq(ide_drive_t *drive) | |||
157 | * Was DMA enabled? If so, disable it - we're resetting the | 157 | * Was DMA enabled? If so, disable it - we're resetting the |
158 | * host. The IDE layer will be handling the drive for us. | 158 | * host. The IDE layer will be handling the drive for us. |
159 | */ | 159 | */ |
160 | dma_cmd = inb(hwif->dma_command); | 160 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
161 | if (dma_cmd & 1) { | 161 | if (dma_cmd & 1) { |
162 | outb(dma_cmd & ~1, hwif->dma_command); | 162 | outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); |
163 | printk("sl82c105: DMA was enabled\n"); | 163 | printk("sl82c105: DMA was enabled\n"); |
164 | } | 164 | } |
165 | 165 | ||
diff --git a/drivers/ide/pci/tc86c001.c b/drivers/ide/pci/tc86c001.c index 9b4b27a4c711..477e19790102 100644 --- a/drivers/ide/pci/tc86c001.c +++ b/drivers/ide/pci/tc86c001.c | |||
@@ -63,7 +63,7 @@ static int tc86c001_timer_expiry(ide_drive_t *drive) | |||
63 | ide_hwif_t *hwif = HWIF(drive); | 63 | ide_hwif_t *hwif = HWIF(drive); |
64 | ide_expiry_t *expiry = ide_get_hwifdata(hwif); | 64 | ide_expiry_t *expiry = ide_get_hwifdata(hwif); |
65 | ide_hwgroup_t *hwgroup = HWGROUP(drive); | 65 | ide_hwgroup_t *hwgroup = HWGROUP(drive); |
66 | u8 dma_stat = inb(hwif->dma_status); | 66 | u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
67 | 67 | ||
68 | /* Restore a higher level driver's expiry handler first. */ | 68 | /* Restore a higher level driver's expiry handler first. */ |
69 | hwgroup->expiry = expiry; | 69 | hwgroup->expiry = expiry; |
@@ -71,21 +71,24 @@ static int tc86c001_timer_expiry(ide_drive_t *drive) | |||
71 | if ((dma_stat & 5) == 1) { /* DMA active and no interrupt */ | 71 | if ((dma_stat & 5) == 1) { /* DMA active and no interrupt */ |
72 | unsigned long sc_base = hwif->config_data; | 72 | unsigned long sc_base = hwif->config_data; |
73 | unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04); | 73 | unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04); |
74 | u8 dma_cmd = inb(hwif->dma_command); | 74 | u8 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
75 | 75 | ||
76 | printk(KERN_WARNING "%s: DMA interrupt possibly stuck, " | 76 | printk(KERN_WARNING "%s: DMA interrupt possibly stuck, " |
77 | "attempting recovery...\n", drive->name); | 77 | "attempting recovery...\n", drive->name); |
78 | 78 | ||
79 | /* Stop DMA */ | 79 | /* Stop DMA */ |
80 | outb(dma_cmd & ~0x01, hwif->dma_command); | 80 | outb(dma_cmd & ~0x01, hwif->dma_base + ATA_DMA_CMD); |
81 | 81 | ||
82 | /* Setup the dummy DMA transfer */ | 82 | /* Setup the dummy DMA transfer */ |
83 | outw(0, sc_base + 0x0a); /* Sector Count */ | 83 | outw(0, sc_base + 0x0a); /* Sector Count */ |
84 | outw(0, twcr_port); /* Transfer Word Count 1 or 2 */ | 84 | outw(0, twcr_port); /* Transfer Word Count 1 or 2 */ |
85 | 85 | ||
86 | /* Start the dummy DMA transfer */ | 86 | /* Start the dummy DMA transfer */ |
87 | outb(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */ | 87 | |
88 | outb(0x01, hwif->dma_command); /* set START_STOPBM */ | 88 | /* clear R_OR_WCTR for write */ |
89 | outb(0x00, hwif->dma_base + ATA_DMA_CMD); | ||
90 | /* set START_STOPBM */ | ||
91 | outb(0x01, hwif->dma_base + ATA_DMA_CMD); | ||
89 | 92 | ||
90 | /* | 93 | /* |
91 | * If an interrupt was pending, it should come thru shortly. | 94 | * If an interrupt was pending, it should come thru shortly. |
@@ -203,8 +206,7 @@ static const struct ide_port_info tc86c001_chipset __devinitdata = { | |||
203 | .init_hwif = init_hwif_tc86c001, | 206 | .init_hwif = init_hwif_tc86c001, |
204 | .port_ops = &tc86c001_port_ops, | 207 | .port_ops = &tc86c001_port_ops, |
205 | .dma_ops = &tc86c001_dma_ops, | 208 | .dma_ops = &tc86c001_dma_ops, |
206 | .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD | | 209 | .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD, |
207 | IDE_HFLAG_ABUSE_SET_DMA_MODE, | ||
208 | .pio_mask = ATA_PIO4, | 210 | .pio_mask = ATA_PIO4, |
209 | .mwdma_mask = ATA_MWDMA2, | 211 | .mwdma_mask = ATA_MWDMA2, |
210 | .udma_mask = ATA_UDMA4, | 212 | .udma_mask = ATA_UDMA4, |
diff --git a/drivers/ide/pci/via82cxxx.c b/drivers/ide/pci/via82cxxx.c index e47384c70c40..09dc4803ef9d 100644 --- a/drivers/ide/pci/via82cxxx.c +++ b/drivers/ide/pci/via82cxxx.c | |||
@@ -425,7 +425,6 @@ static const struct ide_port_info via82cxxx_chipset __devinitdata = { | |||
425 | .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } }, | 425 | .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } }, |
426 | .port_ops = &via_port_ops, | 426 | .port_ops = &via_port_ops, |
427 | .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST | | 427 | .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST | |
428 | IDE_HFLAG_ABUSE_SET_DMA_MODE | | ||
429 | IDE_HFLAG_POST_SET_MODE | | 428 | IDE_HFLAG_POST_SET_MODE | |
430 | IDE_HFLAG_IO_32BIT, | 429 | IDE_HFLAG_IO_32BIT, |
431 | .pio_mask = ATA_PIO5, | 430 | .pio_mask = ATA_PIO5, |