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-rw-r--r--drivers/ide/pci/Makefile1
-rw-r--r--drivers/ide/pci/generic.c73
-rw-r--r--drivers/ide/pci/hpt366.c470
-rw-r--r--drivers/ide/pci/it821x.c812
-rw-r--r--drivers/ide/pci/serverworks.c10
5 files changed, 1094 insertions, 272 deletions
diff --git a/drivers/ide/pci/Makefile b/drivers/ide/pci/Makefile
index 55e6e553e497..af46226c1796 100644
--- a/drivers/ide/pci/Makefile
+++ b/drivers/ide/pci/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_BLK_DEV_HPT34X) += hpt34x.o
12obj-$(CONFIG_BLK_DEV_HPT366) += hpt366.o 12obj-$(CONFIG_BLK_DEV_HPT366) += hpt366.o
13#obj-$(CONFIG_BLK_DEV_HPT37X) += hpt37x.o 13#obj-$(CONFIG_BLK_DEV_HPT37X) += hpt37x.o
14obj-$(CONFIG_BLK_DEV_IT8172) += it8172.o 14obj-$(CONFIG_BLK_DEV_IT8172) += it8172.o
15obj-$(CONFIG_BLK_DEV_IT821X) += it821x.o
15obj-$(CONFIG_BLK_DEV_NS87415) += ns87415.o 16obj-$(CONFIG_BLK_DEV_NS87415) += ns87415.o
16obj-$(CONFIG_BLK_DEV_OPTI621) += opti621.o 17obj-$(CONFIG_BLK_DEV_OPTI621) += opti621.o
17obj-$(CONFIG_BLK_DEV_PDC202XX_OLD) += pdc202xx_old.o 18obj-$(CONFIG_BLK_DEV_PDC202XX_OLD) += pdc202xx_old.o
diff --git a/drivers/ide/pci/generic.c b/drivers/ide/pci/generic.c
index 4565cc311ff3..da46577380f3 100644
--- a/drivers/ide/pci/generic.c
+++ b/drivers/ide/pci/generic.c
@@ -39,6 +39,17 @@
39 39
40#include <asm/io.h> 40#include <asm/io.h>
41 41
42static int ide_generic_all; /* Set to claim all devices */
43
44static int __init ide_generic_all_on(char *unused)
45{
46 ide_generic_all = 1;
47 printk(KERN_INFO "IDE generic will claim all unknown PCI IDE storage controllers.\n");
48 return 1;
49}
50
51__setup("all-generic-ide", ide_generic_all_on);
52
42static void __devinit init_hwif_generic (ide_hwif_t *hwif) 53static void __devinit init_hwif_generic (ide_hwif_t *hwif)
43{ 54{
44 switch(hwif->pci_dev->device) { 55 switch(hwif->pci_dev->device) {
@@ -78,79 +89,85 @@ static void __devinit init_hwif_generic (ide_hwif_t *hwif)
78 89
79static ide_pci_device_t generic_chipsets[] __devinitdata = { 90static ide_pci_device_t generic_chipsets[] __devinitdata = {
80 { /* 0 */ 91 { /* 0 */
92 .name = "Unknown",
93 .init_hwif = init_hwif_generic,
94 .channels = 2,
95 .autodma = AUTODMA,
96 .bootable = ON_BOARD,
97 },{ /* 1 */
81 .name = "NS87410", 98 .name = "NS87410",
82 .init_hwif = init_hwif_generic, 99 .init_hwif = init_hwif_generic,
83 .channels = 2, 100 .channels = 2,
84 .autodma = AUTODMA, 101 .autodma = AUTODMA,
85 .enablebits = {{0x43,0x08,0x08}, {0x47,0x08,0x08}}, 102 .enablebits = {{0x43,0x08,0x08}, {0x47,0x08,0x08}},
86 .bootable = ON_BOARD, 103 .bootable = ON_BOARD,
87 },{ /* 1 */ 104 },{ /* 2 */
88 .name = "SAMURAI", 105 .name = "SAMURAI",
89 .init_hwif = init_hwif_generic, 106 .init_hwif = init_hwif_generic,
90 .channels = 2, 107 .channels = 2,
91 .autodma = AUTODMA, 108 .autodma = AUTODMA,
92 .bootable = ON_BOARD, 109 .bootable = ON_BOARD,
93 },{ /* 2 */ 110 },{ /* 3 */
94 .name = "HT6565", 111 .name = "HT6565",
95 .init_hwif = init_hwif_generic, 112 .init_hwif = init_hwif_generic,
96 .channels = 2, 113 .channels = 2,
97 .autodma = AUTODMA, 114 .autodma = AUTODMA,
98 .bootable = ON_BOARD, 115 .bootable = ON_BOARD,
99 },{ /* 3 */ 116 },{ /* 4 */
100 .name = "UM8673F", 117 .name = "UM8673F",
101 .init_hwif = init_hwif_generic, 118 .init_hwif = init_hwif_generic,
102 .channels = 2, 119 .channels = 2,
103 .autodma = NODMA, 120 .autodma = NODMA,
104 .bootable = ON_BOARD, 121 .bootable = ON_BOARD,
105 },{ /* 4 */ 122 },{ /* 5 */
106 .name = "UM8886A", 123 .name = "UM8886A",
107 .init_hwif = init_hwif_generic, 124 .init_hwif = init_hwif_generic,
108 .channels = 2, 125 .channels = 2,
109 .autodma = NODMA, 126 .autodma = NODMA,
110 .bootable = ON_BOARD, 127 .bootable = ON_BOARD,
111 },{ /* 5 */ 128 },{ /* 6 */
112 .name = "UM8886BF", 129 .name = "UM8886BF",
113 .init_hwif = init_hwif_generic, 130 .init_hwif = init_hwif_generic,
114 .channels = 2, 131 .channels = 2,
115 .autodma = NODMA, 132 .autodma = NODMA,
116 .bootable = ON_BOARD, 133 .bootable = ON_BOARD,
117 },{ /* 6 */ 134 },{ /* 7 */
118 .name = "HINT_IDE", 135 .name = "HINT_IDE",
119 .init_hwif = init_hwif_generic, 136 .init_hwif = init_hwif_generic,
120 .channels = 2, 137 .channels = 2,
121 .autodma = AUTODMA, 138 .autodma = AUTODMA,
122 .bootable = ON_BOARD, 139 .bootable = ON_BOARD,
123 },{ /* 7 */ 140 },{ /* 8 */
124 .name = "VIA_IDE", 141 .name = "VIA_IDE",
125 .init_hwif = init_hwif_generic, 142 .init_hwif = init_hwif_generic,
126 .channels = 2, 143 .channels = 2,
127 .autodma = NOAUTODMA, 144 .autodma = NOAUTODMA,
128 .bootable = ON_BOARD, 145 .bootable = ON_BOARD,
129 },{ /* 8 */ 146 },{ /* 9 */
130 .name = "OPTI621V", 147 .name = "OPTI621V",
131 .init_hwif = init_hwif_generic, 148 .init_hwif = init_hwif_generic,
132 .channels = 2, 149 .channels = 2,
133 .autodma = NOAUTODMA, 150 .autodma = NOAUTODMA,
134 .bootable = ON_BOARD, 151 .bootable = ON_BOARD,
135 },{ /* 9 */ 152 },{ /* 10 */
136 .name = "VIA8237SATA", 153 .name = "VIA8237SATA",
137 .init_hwif = init_hwif_generic, 154 .init_hwif = init_hwif_generic,
138 .channels = 2, 155 .channels = 2,
139 .autodma = AUTODMA, 156 .autodma = AUTODMA,
140 .bootable = OFF_BOARD, 157 .bootable = OFF_BOARD,
141 },{ /* 10 */ 158 },{ /* 11 */
142 .name = "Piccolo0102", 159 .name = "Piccolo0102",
143 .init_hwif = init_hwif_generic, 160 .init_hwif = init_hwif_generic,
144 .channels = 2, 161 .channels = 2,
145 .autodma = NOAUTODMA, 162 .autodma = NOAUTODMA,
146 .bootable = ON_BOARD, 163 .bootable = ON_BOARD,
147 },{ /* 11 */ 164 },{ /* 12 */
148 .name = "Piccolo0103", 165 .name = "Piccolo0103",
149 .init_hwif = init_hwif_generic, 166 .init_hwif = init_hwif_generic,
150 .channels = 2, 167 .channels = 2,
151 .autodma = NOAUTODMA, 168 .autodma = NOAUTODMA,
152 .bootable = ON_BOARD, 169 .bootable = ON_BOARD,
153 },{ /* 12 */ 170 },{ /* 13 */
154 .name = "Piccolo0105", 171 .name = "Piccolo0105",
155 .init_hwif = init_hwif_generic, 172 .init_hwif = init_hwif_generic,
156 .channels = 2, 173 .channels = 2,
@@ -174,6 +191,10 @@ static int __devinit generic_init_one(struct pci_dev *dev, const struct pci_devi
174 u16 command; 191 u16 command;
175 int ret = -ENODEV; 192 int ret = -ENODEV;
176 193
194 /* Don't use the generic entry unless instructed to do so */
195 if (id->driver_data == 0 && ide_generic_all == 0)
196 goto out;
197
177 if (dev->vendor == PCI_VENDOR_ID_UMC && 198 if (dev->vendor == PCI_VENDOR_ID_UMC &&
178 dev->device == PCI_DEVICE_ID_UMC_UM8886A && 199 dev->device == PCI_DEVICE_ID_UMC_UM8886A &&
179 (!(PCI_FUNC(dev->devfn) & 1))) 200 (!(PCI_FUNC(dev->devfn) & 1)))
@@ -195,21 +216,23 @@ out:
195} 216}
196 217
197static struct pci_device_id generic_pci_tbl[] = { 218static struct pci_device_id generic_pci_tbl[] = {
198 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 219 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
199 { PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, 220 { PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
200 { PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, 221 { PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
201 { PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, 222 { PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
202 { PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, 223 { PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
203 { PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5}, 224 { PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
204 { PCI_VENDOR_ID_HINT, PCI_DEVICE_ID_HINT_VXPROII_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6}, 225 { PCI_VENDOR_ID_HINT, PCI_DEVICE_ID_HINT_VXPROII_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
205 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7}, 226 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
206 { PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8}, 227 { PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
207#ifdef CONFIG_BLK_DEV_IDE_SATA 228#ifdef CONFIG_BLK_DEV_IDE_SATA
208 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9}, 229 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
209#endif 230#endif
210 { PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10}, 231 { PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
211 { PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11}, 232 { PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
212 { PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12}, 233 { PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
234 /* Must come last. If you add entries adjust this table appropriately and the init_one code */
235 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL, 0},
213 { 0, }, 236 { 0, },
214}; 237};
215MODULE_DEVICE_TABLE(pci, generic_pci_tbl); 238MODULE_DEVICE_TABLE(pci, generic_pci_tbl);
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index c8ee0b8c0292..7b64db10d1b0 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -10,6 +10,11 @@
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated 10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support. 11 * development and support.
12 * 12 *
13 *
14 * Highpoint have their own driver (source except for the raid part)
15 * available from http://www.highpoint-tech.com/hpt3xx-opensource-v131.tgz
16 * This may be useful to anyone wanting to work on the mainstream hpt IDE.
17 *
13 * Note that final HPT370 support was done by force extraction of GPL. 18 * Note that final HPT370 support was done by force extraction of GPL.
14 * 19 *
15 * - add function for getting/setting power status of drive 20 * - add function for getting/setting power status of drive
@@ -446,44 +451,29 @@ static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
446#define F_LOW_PCI_50 0x2d 451#define F_LOW_PCI_50 0x2d
447#define F_LOW_PCI_66 0x42 452#define F_LOW_PCI_66 0x42
448 453
449/* FIXME: compare with driver's code before removing */ 454/*
450#if 0 455 * Hold all the highpoint quirks and revision information in one
451 if (hpt_minimum_revision(dev, 3)) { 456 * place.
452 u8 cbl; 457 */
453 cbl = inb(iobase + 0x7b);
454 outb(cbl | 1, iobase + 0x7b);
455 outb(cbl & ~1, iobase + 0x7b);
456 cbl = inb(iobase + 0x7a);
457 p += sprintf(p, "Cable: ATA-%d"
458 " ATA-%d\n",
459 (cbl & 0x02) ? 33 : 66,
460 (cbl & 0x01) ? 33 : 66);
461 p += sprintf(p, "\n");
462 }
463 {
464 u8 c2, c3;
465 /* older revs don't have these registers mapped
466 * into io space */
467 pci_read_config_byte(dev, 0x43, &c0);
468 pci_read_config_byte(dev, 0x47, &c1);
469 pci_read_config_byte(dev, 0x4b, &c2);
470 pci_read_config_byte(dev, 0x4f, &c3);
471
472 p += sprintf(p, "Mode: %s %s"
473 " %s %s\n",
474 (c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " :
475 (c0 & 0x80) ? "PIO " : "off ",
476 (c1 & 0x10) ? "UDMA" : (c1 & 0x20) ? "DMA " :
477 (c1 & 0x80) ? "PIO " : "off ",
478 (c2 & 0x10) ? "UDMA" : (c2 & 0x20) ? "DMA " :
479 (c2 & 0x80) ? "PIO " : "off ",
480 (c3 & 0x10) ? "UDMA" : (c3 & 0x20) ? "DMA " :
481 (c3 & 0x80) ? "PIO " : "off ");
482 }
483 }
484#endif
485 458
486static u32 hpt_revision (struct pci_dev *dev) 459struct hpt_info
460{
461 u8 max_mode; /* Speeds allowed */
462 int revision; /* Chipset revision */
463 int flags; /* Chipset properties */
464#define PLL_MODE 1
465#define IS_372N 2
466 /* Speed table */
467 struct chipset_bus_clock_list_entry *speed;
468};
469
470/*
471 * This wants fixing so that we do everything not by classrev
472 * (which breaks on the newest chips) but by creating an
473 * enumeration of chip variants and using that
474 */
475
476static __devinit u32 hpt_revision (struct pci_dev *dev)
487{ 477{
488 u32 class_rev; 478 u32 class_rev;
489 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 479 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
@@ -507,37 +497,33 @@ static u32 hpt_revision (struct pci_dev *dev)
507 return class_rev; 497 return class_rev;
508} 498}
509 499
510static u32 hpt_minimum_revision (struct pci_dev *dev, int revision)
511{
512 unsigned int class_rev = hpt_revision(dev);
513 revision--;
514 return ((int) (class_rev > revision) ? 1 : 0);
515}
516
517static int check_in_drive_lists(ide_drive_t *drive, const char **list); 500static int check_in_drive_lists(ide_drive_t *drive, const char **list);
518 501
519static u8 hpt3xx_ratemask (ide_drive_t *drive) 502static u8 hpt3xx_ratemask (ide_drive_t *drive)
520{ 503{
521 struct pci_dev *dev = HWIF(drive)->pci_dev; 504 ide_hwif_t *hwif = drive->hwif;
505 struct hpt_info *info = ide_get_hwifdata(hwif);
522 u8 mode = 0; 506 u8 mode = 0;
523 507
524 if (hpt_minimum_revision(dev, 8)) { /* HPT374 */ 508 /* FIXME: TODO - move this to set info->mode once at boot */
509
510 if (info->revision >= 8) { /* HPT374 */
525 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3; 511 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
526 } else if (hpt_minimum_revision(dev, 7)) { /* HPT371 */ 512 } else if (info->revision >= 7) { /* HPT371 */
527 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3; 513 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
528 } else if (hpt_minimum_revision(dev, 6)) { /* HPT302 */ 514 } else if (info->revision >= 6) { /* HPT302 */
529 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3; 515 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
530 } else if (hpt_minimum_revision(dev, 5)) { /* HPT372 */ 516 } else if (info->revision >= 5) { /* HPT372 */
531 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3; 517 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
532 } else if (hpt_minimum_revision(dev, 4)) { /* HPT370A */ 518 } else if (info->revision >= 4) { /* HPT370A */
533 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2; 519 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
534 } else if (hpt_minimum_revision(dev, 3)) { /* HPT370 */ 520 } else if (info->revision >= 3) { /* HPT370 */
535 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2; 521 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
536 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode; 522 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
537 } else { /* HPT366 and HPT368 */ 523 } else { /* HPT366 and HPT368 */
538 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2; 524 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
539 } 525 }
540 if (!eighty_ninty_three(drive) && (mode)) 526 if (!eighty_ninty_three(drive) && mode)
541 mode = min(mode, (u8)1); 527 mode = min(mode, (u8)1);
542 return mode; 528 return mode;
543} 529}
@@ -549,7 +535,8 @@ static u8 hpt3xx_ratemask (ide_drive_t *drive)
549 535
550static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed) 536static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
551{ 537{
552 struct pci_dev *dev = HWIF(drive)->pci_dev; 538 ide_hwif_t *hwif = drive->hwif;
539 struct hpt_info *info = ide_get_hwifdata(hwif);
553 u8 mode = hpt3xx_ratemask(drive); 540 u8 mode = hpt3xx_ratemask(drive);
554 541
555 if (drive->media != ide_disk) 542 if (drive->media != ide_disk)
@@ -561,7 +548,7 @@ static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
561 break; 548 break;
562 case 0x03: 549 case 0x03:
563 speed = min(speed, (u8)XFER_UDMA_5); 550 speed = min(speed, (u8)XFER_UDMA_5);
564 if (hpt_minimum_revision(dev, 5)) 551 if (info->revision >= 5)
565 break; 552 break;
566 if (check_in_drive_lists(drive, bad_ata100_5)) 553 if (check_in_drive_lists(drive, bad_ata100_5))
567 speed = min(speed, (u8)XFER_UDMA_4); 554 speed = min(speed, (u8)XFER_UDMA_4);
@@ -571,7 +558,7 @@ static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
571 /* 558 /*
572 * CHECK ME, Does this need to be set to 5 ?? 559 * CHECK ME, Does this need to be set to 5 ??
573 */ 560 */
574 if (hpt_minimum_revision(dev, 3)) 561 if (info->revision >= 3)
575 break; 562 break;
576 if ((check_in_drive_lists(drive, bad_ata66_4)) || 563 if ((check_in_drive_lists(drive, bad_ata66_4)) ||
577 (!(HPT366_ALLOW_ATA66_4))) 564 (!(HPT366_ALLOW_ATA66_4)))
@@ -585,7 +572,7 @@ static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
585 /* 572 /*
586 * CHECK ME, Does this need to be set to 5 ?? 573 * CHECK ME, Does this need to be set to 5 ??
587 */ 574 */
588 if (hpt_minimum_revision(dev, 3)) 575 if (info->revision >= 3)
589 break; 576 break;
590 if (check_in_drive_lists(drive, bad_ata33)) 577 if (check_in_drive_lists(drive, bad_ata33))
591 speed = min(speed, (u8)XFER_MW_DMA_2); 578 speed = min(speed, (u8)XFER_MW_DMA_2);
@@ -624,11 +611,12 @@ static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_
624 611
625static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed) 612static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
626{ 613{
627 struct pci_dev *dev = HWIF(drive)->pci_dev; 614 ide_hwif_t *hwif = drive->hwif;
615 struct pci_dev *dev = hwif->pci_dev;
616 struct hpt_info *info = ide_get_hwifdata(hwif);
628 u8 speed = hpt3xx_ratefilter(drive, xferspeed); 617 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
629// u8 speed = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
630 u8 regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40; 618 u8 regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
631 u8 regfast = (HWIF(drive)->channel) ? 0x55 : 0x51; 619 u8 regfast = (hwif->channel) ? 0x55 : 0x51;
632 u8 drive_fast = 0; 620 u8 drive_fast = 0;
633 u32 reg1 = 0, reg2 = 0; 621 u32 reg1 = 0, reg2 = 0;
634 622
@@ -636,16 +624,11 @@ static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
636 * Disable the "fast interrupt" prediction. 624 * Disable the "fast interrupt" prediction.
637 */ 625 */
638 pci_read_config_byte(dev, regfast, &drive_fast); 626 pci_read_config_byte(dev, regfast, &drive_fast);
639#if 0
640 if (drive_fast & 0x02)
641 pci_write_config_byte(dev, regfast, drive_fast & ~0x20);
642#else
643 if (drive_fast & 0x80) 627 if (drive_fast & 0x80)
644 pci_write_config_byte(dev, regfast, drive_fast & ~0x80); 628 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
645#endif
646 629
647 reg2 = pci_bus_clock_list(speed, 630 reg2 = pci_bus_clock_list(speed, info->speed);
648 (struct chipset_bus_clock_list_entry *) pci_get_drvdata(dev)); 631
649 /* 632 /*
650 * Disable on-chip PIO FIFO/buffer 633 * Disable on-chip PIO FIFO/buffer
651 * (to avoid problems handling I/O errors later) 634 * (to avoid problems handling I/O errors later)
@@ -665,10 +648,11 @@ static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
665 648
666static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed) 649static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
667{ 650{
668 struct pci_dev *dev = HWIF(drive)->pci_dev; 651 ide_hwif_t *hwif = drive->hwif;
652 struct pci_dev *dev = hwif->pci_dev;
653 struct hpt_info *info = ide_get_hwifdata(hwif);
669 u8 speed = hpt3xx_ratefilter(drive, xferspeed); 654 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
670// u8 speed = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed); 655 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51;
671 u8 regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
672 u8 drive_pci = 0x40 + (drive->dn * 4); 656 u8 drive_pci = 0x40 + (drive->dn * 4);
673 u8 new_fast = 0, drive_fast = 0; 657 u8 new_fast = 0, drive_fast = 0;
674 u32 list_conf = 0, drive_conf = 0; 658 u32 list_conf = 0, drive_conf = 0;
@@ -693,17 +677,13 @@ static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
693 if (new_fast != drive_fast) 677 if (new_fast != drive_fast)
694 pci_write_config_byte(dev, regfast, new_fast); 678 pci_write_config_byte(dev, regfast, new_fast);
695 679
696 list_conf = pci_bus_clock_list(speed, 680 list_conf = pci_bus_clock_list(speed, info->speed);
697 (struct chipset_bus_clock_list_entry *)
698 pci_get_drvdata(dev));
699 681
700 pci_read_config_dword(dev, drive_pci, &drive_conf); 682 pci_read_config_dword(dev, drive_pci, &drive_conf);
701 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask); 683 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
702 684
703 if (speed < XFER_MW_DMA_0) { 685 if (speed < XFER_MW_DMA_0)
704 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */ 686 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
705 }
706
707 pci_write_config_dword(dev, drive_pci, list_conf); 687 pci_write_config_dword(dev, drive_pci, list_conf);
708 688
709 return ide_config_drive_speed(drive, speed); 689 return ide_config_drive_speed(drive, speed);
@@ -711,10 +691,11 @@ static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
711 691
712static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed) 692static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
713{ 693{
714 struct pci_dev *dev = HWIF(drive)->pci_dev; 694 ide_hwif_t *hwif = drive->hwif;
695 struct pci_dev *dev = hwif->pci_dev;
696 struct hpt_info *info = ide_get_hwifdata(hwif);
715 u8 speed = hpt3xx_ratefilter(drive, xferspeed); 697 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
716// u8 speed = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed); 698 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51;
717 u8 regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
718 u8 drive_fast = 0, drive_pci = 0x40 + (drive->dn * 4); 699 u8 drive_fast = 0, drive_pci = 0x40 + (drive->dn * 4);
719 u32 list_conf = 0, drive_conf = 0; 700 u32 list_conf = 0, drive_conf = 0;
720 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000; 701 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
@@ -726,10 +707,8 @@ static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
726 pci_read_config_byte(dev, regfast, &drive_fast); 707 pci_read_config_byte(dev, regfast, &drive_fast);
727 drive_fast &= ~0x07; 708 drive_fast &= ~0x07;
728 pci_write_config_byte(dev, regfast, drive_fast); 709 pci_write_config_byte(dev, regfast, drive_fast);
729 710
730 list_conf = pci_bus_clock_list(speed, 711 list_conf = pci_bus_clock_list(speed, info->speed);
731 (struct chipset_bus_clock_list_entry *)
732 pci_get_drvdata(dev));
733 pci_read_config_dword(dev, drive_pci, &drive_conf); 712 pci_read_config_dword(dev, drive_pci, &drive_conf);
734 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask); 713 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
735 if (speed < XFER_MW_DMA_0) 714 if (speed < XFER_MW_DMA_0)
@@ -741,19 +720,14 @@ static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
741 720
742static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed) 721static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
743{ 722{
744 struct pci_dev *dev = HWIF(drive)->pci_dev; 723 ide_hwif_t *hwif = drive->hwif;
724 struct hpt_info *info = ide_get_hwifdata(hwif);
745 725
746 if (hpt_minimum_revision(dev, 8)) 726 if (info->revision >= 8)
747 return hpt372_tune_chipset(drive, speed); /* not a typo */ 727 return hpt372_tune_chipset(drive, speed); /* not a typo */
748#if 0 728 else if (info->revision >= 5)
749 else if (hpt_minimum_revision(dev, 7))
750 hpt371_tune_chipset(drive, speed);
751 else if (hpt_minimum_revision(dev, 6))
752 hpt302_tune_chipset(drive, speed);
753#endif
754 else if (hpt_minimum_revision(dev, 5))
755 return hpt372_tune_chipset(drive, speed); 729 return hpt372_tune_chipset(drive, speed);
756 else if (hpt_minimum_revision(dev, 3)) 730 else if (info->revision >= 3)
757 return hpt370_tune_chipset(drive, speed); 731 return hpt370_tune_chipset(drive, speed);
758 else /* hpt368: hpt_minimum_revision(dev, 2) */ 732 else /* hpt368: hpt_minimum_revision(dev, 2) */
759 return hpt36x_tune_chipset(drive, speed); 733 return hpt36x_tune_chipset(drive, speed);
@@ -779,8 +753,14 @@ static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
779static int config_chipset_for_dma (ide_drive_t *drive) 753static int config_chipset_for_dma (ide_drive_t *drive)
780{ 754{
781 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive)); 755 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
756 ide_hwif_t *hwif = drive->hwif;
757 struct hpt_info *info = ide_get_hwifdata(hwif);
782 758
783 if (!(speed)) 759 if (!speed)
760 return 0;
761
762 /* If we don't have any timings we can't do a lot */
763 if (info->speed == NULL)
784 return 0; 764 return 0;
785 765
786 (void) hpt3xx_tune_chipset(drive, speed); 766 (void) hpt3xx_tune_chipset(drive, speed);
@@ -794,7 +774,7 @@ static int hpt3xx_quirkproc (ide_drive_t *drive)
794 774
795static void hpt3xx_intrproc (ide_drive_t *drive) 775static void hpt3xx_intrproc (ide_drive_t *drive)
796{ 776{
797 ide_hwif_t *hwif = HWIF(drive); 777 ide_hwif_t *hwif = drive->hwif;
798 778
799 if (drive->quirk_list) 779 if (drive->quirk_list)
800 return; 780 return;
@@ -804,24 +784,26 @@ static void hpt3xx_intrproc (ide_drive_t *drive)
804 784
805static void hpt3xx_maskproc (ide_drive_t *drive, int mask) 785static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
806{ 786{
807 struct pci_dev *dev = HWIF(drive)->pci_dev; 787 ide_hwif_t *hwif = drive->hwif;
788 struct hpt_info *info = ide_get_hwifdata(hwif);
789 struct pci_dev *dev = hwif->pci_dev;
808 790
809 if (drive->quirk_list) { 791 if (drive->quirk_list) {
810 if (hpt_minimum_revision(dev,3)) { 792 if (info->revision >= 3) {
811 u8 reg5a = 0; 793 u8 reg5a = 0;
812 pci_read_config_byte(dev, 0x5a, &reg5a); 794 pci_read_config_byte(dev, 0x5a, &reg5a);
813 if (((reg5a & 0x10) >> 4) != mask) 795 if (((reg5a & 0x10) >> 4) != mask)
814 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10)); 796 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
815 } else { 797 } else {
816 if (mask) { 798 if (mask) {
817 disable_irq(HWIF(drive)->irq); 799 disable_irq(hwif->irq);
818 } else { 800 } else {
819 enable_irq(HWIF(drive)->irq); 801 enable_irq(hwif->irq);
820 } 802 }
821 } 803 }
822 } else { 804 } else {
823 if (IDE_CONTROL_REG) 805 if (IDE_CONTROL_REG)
824 HWIF(drive)->OUTB(mask ? (drive->ctl | 2) : 806 hwif->OUTB(mask ? (drive->ctl | 2) :
825 (drive->ctl & ~2), 807 (drive->ctl & ~2),
826 IDE_CONTROL_REG); 808 IDE_CONTROL_REG);
827 } 809 }
@@ -829,12 +811,12 @@ static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
829 811
830static int hpt366_config_drive_xfer_rate (ide_drive_t *drive) 812static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
831{ 813{
832 ide_hwif_t *hwif = HWIF(drive); 814 ide_hwif_t *hwif = drive->hwif;
833 struct hd_driveid *id = drive->id; 815 struct hd_driveid *id = drive->id;
834 816
835 drive->init_speed = 0; 817 drive->init_speed = 0;
836 818
837 if (id && (id->capability & 1) && drive->autodma) { 819 if ((id->capability & 1) && drive->autodma) {
838 820
839 if (ide_use_dma(drive)) { 821 if (ide_use_dma(drive)) {
840 if (config_chipset_for_dma(drive)) 822 if (config_chipset_for_dma(drive))
@@ -868,15 +850,6 @@ static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
868 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah); 850 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
869 if (reg5ah & 0x10) 851 if (reg5ah & 0x10)
870 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10); 852 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
871#if 0
872 /* how about we flush and reset, mmmkay? */
873 pci_write_config_byte(dev, 0x51, 0x1F);
874 /* fall through to a reset */
875 case dma_start:
876 case ide_dma_end:
877 /* reset the chips state over and over.. */
878 pci_write_config_byte(dev, 0x51, 0x13);
879#endif
880 return __ide_dma_lostirq(drive); 853 return __ide_dma_lostirq(drive);
881} 854}
882 855
@@ -919,7 +892,7 @@ static void hpt370_lostirq_timeout (ide_drive_t *drive)
919 u8 dma_stat = 0, dma_cmd = 0; 892 u8 dma_stat = 0, dma_cmd = 0;
920 893
921 pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo); 894 pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
922 printk("%s: %d bytes in FIFO\n", drive->name, bfifo); 895 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
923 hpt370_clear_engine(drive); 896 hpt370_clear_engine(drive);
924 /* get dma command mode */ 897 /* get dma command mode */
925 dma_cmd = hwif->INB(hwif->dma_command); 898 dma_cmd = hwif->INB(hwif->dma_command);
@@ -1047,15 +1020,6 @@ static void hpt372n_rw_disk(ide_drive_t *drive, struct request *rq)
1047 1020
1048static void hpt3xx_reset (ide_drive_t *drive) 1021static void hpt3xx_reset (ide_drive_t *drive)
1049{ 1022{
1050#if 0
1051 unsigned long high_16 = pci_resource_start(HWIF(drive)->pci_dev, 4);
1052 u8 reset = (HWIF(drive)->channel) ? 0x80 : 0x40;
1053 u8 reg59h = 0;
1054
1055 pci_read_config_byte(HWIF(drive)->pci_dev, 0x59, &reg59h);
1056 pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h|reset);
1057 pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h);
1058#endif
1059} 1023}
1060 1024
1061static int hpt3xx_tristate (ide_drive_t * drive, int state) 1025static int hpt3xx_tristate (ide_drive_t * drive, int state)
@@ -1065,8 +1029,6 @@ static int hpt3xx_tristate (ide_drive_t * drive, int state)
1065 u8 reg59h = 0, reset = (hwif->channel) ? 0x80 : 0x40; 1029 u8 reg59h = 0, reset = (hwif->channel) ? 0x80 : 0x40;
1066 u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53; 1030 u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
1067 1031
1068// hwif->bus_state = state;
1069
1070 pci_read_config_byte(dev, 0x59, &reg59h); 1032 pci_read_config_byte(dev, 0x59, &reg59h);
1071 pci_read_config_byte(dev, state_reg, &regXXh); 1033 pci_read_config_byte(dev, state_reg, &regXXh);
1072 1034
@@ -1093,7 +1055,7 @@ static int hpt3xx_tristate (ide_drive_t * drive, int state)
1093#define TRISTATE_BIT 0x8000 1055#define TRISTATE_BIT 0x8000
1094static int hpt370_busproc(ide_drive_t * drive, int state) 1056static int hpt370_busproc(ide_drive_t * drive, int state)
1095{ 1057{
1096 ide_hwif_t *hwif = HWIF(drive); 1058 ide_hwif_t *hwif = drive->hwif;
1097 struct pci_dev *dev = hwif->pci_dev; 1059 struct pci_dev *dev = hwif->pci_dev;
1098 u8 tristate = 0, resetmask = 0, bus_reg = 0; 1060 u8 tristate = 0, resetmask = 0, bus_reg = 0;
1099 u16 tri_reg; 1061 u16 tri_reg;
@@ -1148,33 +1110,44 @@ static int hpt370_busproc(ide_drive_t * drive, int state)
1148 return 0; 1110 return 0;
1149} 1111}
1150 1112
1151static int __devinit init_hpt37x(struct pci_dev *dev) 1113static void __devinit hpt366_clocking(ide_hwif_t *hwif)
1152{ 1114{
1115 u32 reg1 = 0;
1116 struct hpt_info *info = ide_get_hwifdata(hwif);
1117
1118 pci_read_config_dword(hwif->pci_dev, 0x40, &reg1);
1119
1120 /* detect bus speed by looking at control reg timing: */
1121 switch((reg1 >> 8) & 7) {
1122 case 5:
1123 info->speed = forty_base_hpt366;
1124 break;
1125 case 9:
1126 info->speed = twenty_five_base_hpt366;
1127 break;
1128 case 7:
1129 default:
1130 info->speed = thirty_three_base_hpt366;
1131 break;
1132 }
1133}
1134
1135static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1136{
1137 struct hpt_info *info = ide_get_hwifdata(hwif);
1138 struct pci_dev *dev = hwif->pci_dev;
1153 int adjust, i; 1139 int adjust, i;
1154 u16 freq; 1140 u16 freq;
1155 u32 pll; 1141 u32 pll;
1156 u8 reg5bh; 1142 u8 reg5bh;
1157 u8 reg5ah = 0;
1158 unsigned long dmabase = pci_resource_start(dev, 4);
1159 u8 did, rid;
1160 int is_372n = 0;
1161 1143
1162 pci_read_config_byte(dev, 0x5a, &reg5ah);
1163 /* interrupt force enable */
1164 pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1165
1166 if(dmabase)
1167 {
1168 did = inb(dmabase + 0x22);
1169 rid = inb(dmabase + 0x28);
1170
1171 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1172 is_372n = 1;
1173 }
1174
1175 /* 1144 /*
1176 * default to pci clock. make sure MA15/16 are set to output 1145 * default to pci clock. make sure MA15/16 are set to output
1177 * to prevent drives having problems with 40-pin cables. 1146 * to prevent drives having problems with 40-pin cables. Needed
1147 * for some drives such as IBM-DTLA which will not enter ready
1148 * state on reset when PDIAG is a input.
1149 *
1150 * ToDo: should we set 0x21 when using PLL mode ?
1178 */ 1151 */
1179 pci_write_config_byte(dev, 0x5b, 0x23); 1152 pci_write_config_byte(dev, 0x5b, 0x23);
1180 1153
@@ -1197,9 +1170,7 @@ static int __devinit init_hpt37x(struct pci_dev *dev)
1197 * Currently we always set up the PLL for the 372N 1170 * Currently we always set up the PLL for the 372N
1198 */ 1171 */
1199 1172
1200 pci_set_drvdata(dev, NULL); 1173 if(info->flags & IS_372N)
1201
1202 if(is_372n)
1203 { 1174 {
1204 printk(KERN_INFO "hpt: HPT372N detected, using 372N timing.\n"); 1175 printk(KERN_INFO "hpt: HPT372N detected, using 372N timing.\n");
1205 if(freq < 0x55) 1176 if(freq < 0x55)
@@ -1227,39 +1198,38 @@ static int __devinit init_hpt37x(struct pci_dev *dev)
1227 pll = F_LOW_PCI_66; 1198 pll = F_LOW_PCI_66;
1228 1199
1229 if (pll == F_LOW_PCI_33) { 1200 if (pll == F_LOW_PCI_33) {
1230 if (hpt_minimum_revision(dev,8)) 1201 if (info->revision >= 8)
1231 pci_set_drvdata(dev, (void *) thirty_three_base_hpt374); 1202 info->speed = thirty_three_base_hpt374;
1232 else if (hpt_minimum_revision(dev,5)) 1203 else if (info->revision >= 5)
1233 pci_set_drvdata(dev, (void *) thirty_three_base_hpt372); 1204 info->speed = thirty_three_base_hpt372;
1234 else if (hpt_minimum_revision(dev,4)) 1205 else if (info->revision >= 4)
1235 pci_set_drvdata(dev, (void *) thirty_three_base_hpt370a); 1206 info->speed = thirty_three_base_hpt370a;
1236 else 1207 else
1237 pci_set_drvdata(dev, (void *) thirty_three_base_hpt370); 1208 info->speed = thirty_three_base_hpt370;
1238 printk("HPT37X: using 33MHz PCI clock\n"); 1209 printk(KERN_DEBUG "HPT37X: using 33MHz PCI clock\n");
1239 } else if (pll == F_LOW_PCI_40) { 1210 } else if (pll == F_LOW_PCI_40) {
1240 /* Unsupported */ 1211 /* Unsupported */
1241 } else if (pll == F_LOW_PCI_50) { 1212 } else if (pll == F_LOW_PCI_50) {
1242 if (hpt_minimum_revision(dev,8)) 1213 if (info->revision >= 8)
1243 pci_set_drvdata(dev, (void *) fifty_base_hpt370a); 1214 info->speed = fifty_base_hpt370a;
1244 else if (hpt_minimum_revision(dev,5)) 1215 else if (info->revision >= 5)
1245 pci_set_drvdata(dev, (void *) fifty_base_hpt372); 1216 info->speed = fifty_base_hpt372;
1246 else if (hpt_minimum_revision(dev,4)) 1217 else if (info->revision >= 4)
1247 pci_set_drvdata(dev, (void *) fifty_base_hpt370a); 1218 info->speed = fifty_base_hpt370a;
1248 else 1219 else
1249 pci_set_drvdata(dev, (void *) fifty_base_hpt370a); 1220 info->speed = fifty_base_hpt370a;
1250 printk("HPT37X: using 50MHz PCI clock\n"); 1221 printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n");
1251 } else { 1222 } else {
1252 if (hpt_minimum_revision(dev,8)) 1223 if (info->revision >= 8) {
1253 {
1254 printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n"); 1224 printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
1255 } 1225 }
1256 else if (hpt_minimum_revision(dev,5)) 1226 else if (info->revision >= 5)
1257 pci_set_drvdata(dev, (void *) sixty_six_base_hpt372); 1227 info->speed = sixty_six_base_hpt372;
1258 else if (hpt_minimum_revision(dev,4)) 1228 else if (info->revision >= 4)
1259 pci_set_drvdata(dev, (void *) sixty_six_base_hpt370a); 1229 info->speed = sixty_six_base_hpt370a;
1260 else 1230 else
1261 pci_set_drvdata(dev, (void *) sixty_six_base_hpt370); 1231 info->speed = sixty_six_base_hpt370;
1262 printk("HPT37X: using 66MHz PCI clock\n"); 1232 printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1263 } 1233 }
1264 } 1234 }
1265 1235
@@ -1269,11 +1239,19 @@ static int __devinit init_hpt37x(struct pci_dev *dev)
1269 * result in slow reads when using a 33MHz PCI clock. we also 1239 * result in slow reads when using a 33MHz PCI clock. we also
1270 * don't like to use the PLL because it will cause glitches 1240 * don't like to use the PLL because it will cause glitches
1271 * on PRST/SRST when the HPT state engine gets reset. 1241 * on PRST/SRST when the HPT state engine gets reset.
1242 *
1243 * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1244 * 372 device so we can get ATA133 support
1272 */ 1245 */
1273 if (pci_get_drvdata(dev)) 1246 if (info->speed)
1274 goto init_hpt37X_done; 1247 goto init_hpt37X_done;
1248
1249 info->flags |= PLL_MODE;
1275 1250
1276 /* 1251 /*
1252 * FIXME: make this work correctly, esp with 372N as per
1253 * reference driver code.
1254 *
1277 * adjust PLL based upon PCI clock, enable it, and wait for 1255 * adjust PLL based upon PCI clock, enable it, and wait for
1278 * stabilization. 1256 * stabilization.
1279 */ 1257 */
@@ -1298,14 +1276,14 @@ static int __devinit init_hpt37x(struct pci_dev *dev)
1298 pci_write_config_dword(dev, 0x5c, 1276 pci_write_config_dword(dev, 0x5c,
1299 pll & ~0x100); 1277 pll & ~0x100);
1300 pci_write_config_byte(dev, 0x5b, 0x21); 1278 pci_write_config_byte(dev, 0x5b, 0x21);
1301 if (hpt_minimum_revision(dev,8)) 1279 if (info->revision >= 8)
1302 pci_set_drvdata(dev, (void *) fifty_base_hpt370a); 1280 info->speed = fifty_base_hpt370a;
1303 else if (hpt_minimum_revision(dev,5)) 1281 else if (info->revision >= 5)
1304 pci_set_drvdata(dev, (void *) fifty_base_hpt372); 1282 info->speed = fifty_base_hpt372;
1305 else if (hpt_minimum_revision(dev,4)) 1283 else if (info->revision >= 4)
1306 pci_set_drvdata(dev, (void *) fifty_base_hpt370a); 1284 info->speed = fifty_base_hpt370a;
1307 else 1285 else
1308 pci_set_drvdata(dev, (void *) fifty_base_hpt370a); 1286 info->speed = fifty_base_hpt370a;
1309 printk("HPT37X: using 50MHz internal PLL\n"); 1287 printk("HPT37X: using 50MHz internal PLL\n");
1310 goto init_hpt37X_done; 1288 goto init_hpt37X_done;
1311 } 1289 }
@@ -1318,10 +1296,22 @@ pll_recal:
1318 } 1296 }
1319 1297
1320init_hpt37X_done: 1298init_hpt37X_done:
1299 if (!info->speed)
1300 printk(KERN_ERR "HPT37X%s: unknown bus timing [%d %d].\n",
1301 (info->flags & IS_372N)?"N":"", pll, freq);
1321 /* reset state engine */ 1302 /* reset state engine */
1322 pci_write_config_byte(dev, 0x50, 0x37); 1303 pci_write_config_byte(dev, 0x50, 0x37);
1323 pci_write_config_byte(dev, 0x54, 0x37); 1304 pci_write_config_byte(dev, 0x54, 0x37);
1324 udelay(100); 1305 udelay(100);
1306}
1307
1308static int __devinit init_hpt37x(struct pci_dev *dev)
1309{
1310 u8 reg5ah;
1311
1312 pci_read_config_byte(dev, 0x5a, &reg5ah);
1313 /* interrupt force enable */
1314 pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1325 return 0; 1315 return 0;
1326} 1316}
1327 1317
@@ -1338,59 +1328,27 @@ static int __devinit init_hpt366(struct pci_dev *dev)
1338 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80); 1328 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1339 pci_read_config_dword(dev, 0x40, &reg1); 1329 pci_read_config_dword(dev, 0x40, &reg1);
1340 1330
1341 /* detect bus speed by looking at control reg timing: */
1342 switch((reg1 >> 8) & 7) {
1343 case 5:
1344 pci_set_drvdata(dev, (void *) forty_base_hpt366);
1345 break;
1346 case 9:
1347 pci_set_drvdata(dev, (void *) twenty_five_base_hpt366);
1348 break;
1349 case 7:
1350 default:
1351 pci_set_drvdata(dev, (void *) thirty_three_base_hpt366);
1352 break;
1353 }
1354
1355 if (!pci_get_drvdata(dev))
1356 {
1357 printk(KERN_ERR "hpt366: unknown bus timing.\n");
1358 pci_set_drvdata(dev, NULL);
1359 }
1360 return 0; 1331 return 0;
1361} 1332}
1362 1333
1363static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name) 1334static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1364{ 1335{
1365 int ret = 0; 1336 int ret = 0;
1366 u8 test = 0; 1337 /* FIXME: Not portable */
1367
1368 if (dev->resource[PCI_ROM_RESOURCE].start) 1338 if (dev->resource[PCI_ROM_RESOURCE].start)
1369 pci_write_config_byte(dev, PCI_ROM_ADDRESS, 1339 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
1370 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); 1340 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1371 1341
1372 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test); 1342 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1373 if (test != (L1_CACHE_BYTES / 4)) 1343 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1374 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 1344 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1375 (L1_CACHE_BYTES / 4)); 1345 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1376
1377 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
1378 if (test != 0x78)
1379 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1380 1346
1381 pci_read_config_byte(dev, PCI_MIN_GNT, &test); 1347 if (hpt_revision(dev) >= 3)
1382 if (test != 0x08)
1383 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1384
1385 pci_read_config_byte(dev, PCI_MAX_LAT, &test);
1386 if (test != 0x08)
1387 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1388
1389 if (hpt_minimum_revision(dev, 3)) {
1390 ret = init_hpt37x(dev); 1348 ret = init_hpt37x(dev);
1391 } else { 1349 else
1392 ret =init_hpt366(dev); 1350 ret = init_hpt366(dev);
1393 } 1351
1394 if (ret) 1352 if (ret)
1395 return ret; 1353 return ret;
1396 1354
@@ -1400,27 +1358,16 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
1400static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) 1358static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1401{ 1359{
1402 struct pci_dev *dev = hwif->pci_dev; 1360 struct pci_dev *dev = hwif->pci_dev;
1361 struct hpt_info *info = ide_get_hwifdata(hwif);
1403 u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02; 1362 u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02;
1404 u8 did, rid;
1405 unsigned long dmabase = hwif->dma_base;
1406 int is_372n = 0;
1407 1363
1408 if(dmabase)
1409 {
1410 did = inb(dmabase + 0x22);
1411 rid = inb(dmabase + 0x28);
1412
1413 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1414 is_372n = 1;
1415 }
1416
1417 hwif->tuneproc = &hpt3xx_tune_drive; 1364 hwif->tuneproc = &hpt3xx_tune_drive;
1418 hwif->speedproc = &hpt3xx_tune_chipset; 1365 hwif->speedproc = &hpt3xx_tune_chipset;
1419 hwif->quirkproc = &hpt3xx_quirkproc; 1366 hwif->quirkproc = &hpt3xx_quirkproc;
1420 hwif->intrproc = &hpt3xx_intrproc; 1367 hwif->intrproc = &hpt3xx_intrproc;
1421 hwif->maskproc = &hpt3xx_maskproc; 1368 hwif->maskproc = &hpt3xx_maskproc;
1422 1369
1423 if(is_372n) 1370 if(info->flags & IS_372N)
1424 hwif->rw_disk = &hpt372n_rw_disk; 1371 hwif->rw_disk = &hpt372n_rw_disk;
1425 1372
1426 /* 1373 /*
@@ -1428,7 +1375,7 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1428 * address lines to access an external eeprom. To read valid 1375 * address lines to access an external eeprom. To read valid
1429 * cable detect state the pins must be enabled as inputs. 1376 * cable detect state the pins must be enabled as inputs.
1430 */ 1377 */
1431 if (hpt_minimum_revision(dev, 8) && PCI_FUNC(dev->devfn) & 1) { 1378 if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1432 /* 1379 /*
1433 * HPT374 PCI function 1 1380 * HPT374 PCI function 1
1434 * - set bit 15 of reg 0x52 to enable TCBLID as input 1381 * - set bit 15 of reg 0x52 to enable TCBLID as input
@@ -1443,7 +1390,7 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1443 pci_read_config_byte(dev, 0x5a, &ata66); 1390 pci_read_config_byte(dev, 0x5a, &ata66);
1444 pci_write_config_word(dev, 0x52, mcr3); 1391 pci_write_config_word(dev, 0x52, mcr3);
1445 pci_write_config_word(dev, 0x56, mcr6); 1392 pci_write_config_word(dev, 0x56, mcr6);
1446 } else if (hpt_minimum_revision(dev, 3)) { 1393 } else if (info->revision >= 3) {
1447 /* 1394 /*
1448 * HPT370/372 and 374 pcifn 0 1395 * HPT370/372 and 374 pcifn 0
1449 * - clear bit 0 of 0x5b to enable P/SCBLID as inputs 1396 * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
@@ -1470,7 +1417,7 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1470 hwif->serialized = hwif->mate->serialized = 1; 1417 hwif->serialized = hwif->mate->serialized = 1;
1471#endif 1418#endif
1472 1419
1473 if (hpt_minimum_revision(dev,3)) { 1420 if (info->revision >= 3) {
1474 u8 reg5ah = 0; 1421 u8 reg5ah = 0;
1475 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10); 1422 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1476 /* 1423 /*
@@ -1480,8 +1427,7 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1480 */ 1427 */
1481 hwif->resetproc = &hpt3xx_reset; 1428 hwif->resetproc = &hpt3xx_reset;
1482 hwif->busproc = &hpt370_busproc; 1429 hwif->busproc = &hpt370_busproc;
1483// hwif->drives[0].autotune = hwif->drives[1].autotune = 1; 1430 } else if (info->revision >= 2) {
1484 } else if (hpt_minimum_revision(dev,2)) {
1485 hwif->resetproc = &hpt3xx_reset; 1431 hwif->resetproc = &hpt3xx_reset;
1486 hwif->busproc = &hpt3xx_tristate; 1432 hwif->busproc = &hpt3xx_tristate;
1487 } else { 1433 } else {
@@ -1502,18 +1448,18 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1502 hwif->udma_four = ((ata66 & regmask) ? 0 : 1); 1448 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1503 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate; 1449 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1504 1450
1505 if (hpt_minimum_revision(dev,8)) { 1451 if (info->revision >= 8) {
1506 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq; 1452 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1507 hwif->ide_dma_end = &hpt374_ide_dma_end; 1453 hwif->ide_dma_end = &hpt374_ide_dma_end;
1508 } else if (hpt_minimum_revision(dev,5)) { 1454 } else if (info->revision >= 5) {
1509 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq; 1455 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1510 hwif->ide_dma_end = &hpt374_ide_dma_end; 1456 hwif->ide_dma_end = &hpt374_ide_dma_end;
1511 } else if (hpt_minimum_revision(dev,3)) { 1457 } else if (info->revision >= 3) {
1512 hwif->dma_start = &hpt370_ide_dma_start; 1458 hwif->dma_start = &hpt370_ide_dma_start;
1513 hwif->ide_dma_end = &hpt370_ide_dma_end; 1459 hwif->ide_dma_end = &hpt370_ide_dma_end;
1514 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout; 1460 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1515 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq; 1461 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1516 } else if (hpt_minimum_revision(dev,2)) 1462 } else if (info->revision >= 2)
1517 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq; 1463 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1518 else 1464 else
1519 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq; 1465 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
@@ -1526,6 +1472,7 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1526 1472
1527static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase) 1473static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1528{ 1474{
1475 struct hpt_info *info = ide_get_hwifdata(hwif);
1529 u8 masterdma = 0, slavedma = 0; 1476 u8 masterdma = 0, slavedma = 0;
1530 u8 dma_new = 0, dma_old = 0; 1477 u8 dma_new = 0, dma_old = 0;
1531 u8 primary = hwif->channel ? 0x4b : 0x43; 1478 u8 primary = hwif->channel ? 0x4b : 0x43;
@@ -1535,8 +1482,7 @@ static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1535 if (!dmabase) 1482 if (!dmabase)
1536 return; 1483 return;
1537 1484
1538 if(pci_get_drvdata(hwif->pci_dev) == NULL) 1485 if(info->speed == NULL) {
1539 {
1540 printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n"); 1486 printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n");
1541 return; 1487 return;
1542 } 1488 }
@@ -1559,6 +1505,40 @@ static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1559 ide_setup_dma(hwif, dmabase, 8); 1505 ide_setup_dma(hwif, dmabase, 8);
1560} 1506}
1561 1507
1508/*
1509 * We "borrow" this hook in order to set the data structures
1510 * up early enough before dma or init_hwif calls are made.
1511 */
1512
1513static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1514{
1515 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
1516 unsigned long dmabase = pci_resource_start(hwif->pci_dev, 4);
1517 u8 did, rid;
1518
1519 if(info == NULL) {
1520 printk(KERN_WARNING "hpt366: out of memory.\n");
1521 return;
1522 }
1523 memset(info, 0, sizeof(struct hpt_info));
1524 ide_set_hwifdata(hwif, info);
1525
1526 if(dmabase) {
1527 did = inb(dmabase + 0x22);
1528 rid = inb(dmabase + 0x28);
1529
1530 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1531 info->flags |= IS_372N;
1532 }
1533
1534 info->revision = hpt_revision(hwif->pci_dev);
1535
1536 if (info->revision >= 3)
1537 hpt37x_clocking(hwif);
1538 else
1539 hpt366_clocking(hwif);
1540}
1541
1562static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d) 1542static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1563{ 1543{
1564 struct pci_dev *findev = NULL; 1544 struct pci_dev *findev = NULL;
@@ -1646,6 +1626,7 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1646 .name = "HPT366", 1626 .name = "HPT366",
1647 .init_setup = init_setup_hpt366, 1627 .init_setup = init_setup_hpt366,
1648 .init_chipset = init_chipset_hpt366, 1628 .init_chipset = init_chipset_hpt366,
1629 .init_iops = init_iops_hpt366,
1649 .init_hwif = init_hwif_hpt366, 1630 .init_hwif = init_hwif_hpt366,
1650 .init_dma = init_dma_hpt366, 1631 .init_dma = init_dma_hpt366,
1651 .channels = 2, 1632 .channels = 2,
@@ -1656,6 +1637,7 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1656 .name = "HPT372A", 1637 .name = "HPT372A",
1657 .init_setup = init_setup_hpt37x, 1638 .init_setup = init_setup_hpt37x,
1658 .init_chipset = init_chipset_hpt366, 1639 .init_chipset = init_chipset_hpt366,
1640 .init_iops = init_iops_hpt366,
1659 .init_hwif = init_hwif_hpt366, 1641 .init_hwif = init_hwif_hpt366,
1660 .init_dma = init_dma_hpt366, 1642 .init_dma = init_dma_hpt366,
1661 .channels = 2, 1643 .channels = 2,
@@ -1665,6 +1647,7 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1665 .name = "HPT302", 1647 .name = "HPT302",
1666 .init_setup = init_setup_hpt37x, 1648 .init_setup = init_setup_hpt37x,
1667 .init_chipset = init_chipset_hpt366, 1649 .init_chipset = init_chipset_hpt366,
1650 .init_iops = init_iops_hpt366,
1668 .init_hwif = init_hwif_hpt366, 1651 .init_hwif = init_hwif_hpt366,
1669 .init_dma = init_dma_hpt366, 1652 .init_dma = init_dma_hpt366,
1670 .channels = 2, 1653 .channels = 2,
@@ -1674,6 +1657,7 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1674 .name = "HPT371", 1657 .name = "HPT371",
1675 .init_setup = init_setup_hpt37x, 1658 .init_setup = init_setup_hpt37x,
1676 .init_chipset = init_chipset_hpt366, 1659 .init_chipset = init_chipset_hpt366,
1660 .init_iops = init_iops_hpt366,
1677 .init_hwif = init_hwif_hpt366, 1661 .init_hwif = init_hwif_hpt366,
1678 .init_dma = init_dma_hpt366, 1662 .init_dma = init_dma_hpt366,
1679 .channels = 2, 1663 .channels = 2,
@@ -1683,6 +1667,7 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1683 .name = "HPT374", 1667 .name = "HPT374",
1684 .init_setup = init_setup_hpt374, 1668 .init_setup = init_setup_hpt374,
1685 .init_chipset = init_chipset_hpt366, 1669 .init_chipset = init_chipset_hpt366,
1670 .init_iops = init_iops_hpt366,
1686 .init_hwif = init_hwif_hpt366, 1671 .init_hwif = init_hwif_hpt366,
1687 .init_dma = init_dma_hpt366, 1672 .init_dma = init_dma_hpt366,
1688 .channels = 2, /* 4 */ 1673 .channels = 2, /* 4 */
@@ -1692,6 +1677,7 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1692 .name = "HPT372N", 1677 .name = "HPT372N",
1693 .init_setup = init_setup_hpt37x, 1678 .init_setup = init_setup_hpt37x,
1694 .init_chipset = init_chipset_hpt366, 1679 .init_chipset = init_chipset_hpt366,
1680 .init_iops = init_iops_hpt366,
1695 .init_hwif = init_hwif_hpt366, 1681 .init_hwif = init_hwif_hpt366,
1696 .init_dma = init_dma_hpt366, 1682 .init_dma = init_dma_hpt366,
1697 .channels = 2, /* 4 */ 1683 .channels = 2, /* 4 */
diff --git a/drivers/ide/pci/it821x.c b/drivers/ide/pci/it821x.c
new file mode 100644
index 000000000000..e440036e651f
--- /dev/null
+++ b/drivers/ide/pci/it821x.c
@@ -0,0 +1,812 @@
1
2/*
3 * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004
4 *
5 * Copyright (C) 2004 Red Hat <alan@redhat.com>
6 *
7 * May be copied or modified under the terms of the GNU General Public License
8 * Based in part on the ITE vendor provided SCSI driver.
9 *
10 * Documentation available from
11 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
12 * Some other documents are NDA.
13 *
14 * The ITE8212 isn't exactly a standard IDE controller. It has two
15 * modes. In pass through mode then it is an IDE controller. In its smart
16 * mode its actually quite a capable hardware raid controller disguised
17 * as an IDE controller. Smart mode only understands DMA read/write and
18 * identify, none of the fancier commands apply. The IT8211 is identical
19 * in other respects but lacks the raid mode.
20 *
21 * Errata:
22 * o Rev 0x10 also requires master/slave hold the same DMA timings and
23 * cannot do ATAPI MWDMA.
24 * o The identify data for raid volumes lacks CHS info (technically ok)
25 * but also fails to set the LBA28 and other bits. We fix these in
26 * the IDE probe quirk code.
27 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
28 * raid then the controller firmware dies
29 * o Smart mode without RAID doesn't clear all the necessary identify
30 * bits to reduce the command set to the one used
31 *
32 * This has a few impacts on the driver
33 * - In pass through mode we do all the work you would expect
34 * - In smart mode the clocking set up is done by the controller generally
35 * but we must watch the other limits and filter.
36 * - There are a few extra vendor commands that actually talk to the
37 * controller but only work PIO with no IRQ.
38 *
39 * Vendor areas of the identify block in smart mode are used for the
40 * timing and policy set up. Each HDD in raid mode also has a serial
41 * block on the disk. The hardware extra commands are get/set chip status,
42 * rebuild, get rebuild status.
43 *
44 * In Linux the driver supports pass through mode as if the device was
45 * just another IDE controller. If the smart mode is running then
46 * volumes are managed by the controller firmware and each IDE "disk"
47 * is a raid volume. Even more cute - the controller can do automated
48 * hotplug and rebuild.
49 *
50 * The pass through controller itself is a little demented. It has a
51 * flaw that it has a single set of PIO/MWDMA timings per channel so
52 * non UDMA devices restrict each others performance. It also has a
53 * single clock source per channel so mixed UDMA100/133 performance
54 * isn't perfect and we have to pick a clock. Thankfully none of this
55 * matters in smart mode. ATAPI DMA is not currently supported.
56 *
57 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
58 *
59 * TODO
60 * - ATAPI UDMA is ok but not MWDMA it seems
61 * - RAID configuration ioctls
62 * - Move to libata once it grows up
63 */
64
65#include <linux/config.h>
66#include <linux/types.h>
67#include <linux/module.h>
68#include <linux/pci.h>
69#include <linux/delay.h>
70#include <linux/hdreg.h>
71#include <linux/ide.h>
72#include <linux/init.h>
73
74#include <asm/io.h>
75
76struct it821x_dev
77{
78 unsigned int smart:1, /* Are we in smart raid mode */
79 timing10:1; /* Rev 0x10 */
80 u8 clock_mode; /* 0, ATA_50 or ATA_66 */
81 u8 want[2][2]; /* Mode/Pri log for master slave */
82 /* We need these for switching the clock when DMA goes on/off
83 The high byte is the 66Mhz timing */
84 u16 pio[2]; /* Cached PIO values */
85 u16 mwdma[2]; /* Cached MWDMA values */
86 u16 udma[2]; /* Cached UDMA values (per drive) */
87};
88
89#define ATA_66 0
90#define ATA_50 1
91#define ATA_ANY 2
92
93#define UDMA_OFF 0
94#define MWDMA_OFF 0
95
96/*
97 * We allow users to force the card into non raid mode without
98 * flashing the alternative BIOS. This is also neccessary right now
99 * for embedded platforms that cannot run a PC BIOS but are using this
100 * device.
101 */
102
103static int it8212_noraid;
104
105/**
106 * it821x_program - program the PIO/MWDMA registers
107 * @drive: drive to tune
108 *
109 * Program the PIO/MWDMA timing for this channel according to the
110 * current clock.
111 */
112
113static void it821x_program(ide_drive_t *drive, u16 timing)
114{
115 ide_hwif_t *hwif = drive->hwif;
116 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
117 int channel = hwif->channel;
118 u8 conf;
119
120 /* Program PIO/MWDMA timing bits */
121 if(itdev->clock_mode == ATA_66)
122 conf = timing >> 8;
123 else
124 conf = timing & 0xFF;
125 pci_write_config_byte(hwif->pci_dev, 0x54 + 4 * channel, conf);
126}
127
128/**
129 * it821x_program_udma - program the UDMA registers
130 * @drive: drive to tune
131 *
132 * Program the UDMA timing for this drive according to the
133 * current clock.
134 */
135
136static void it821x_program_udma(ide_drive_t *drive, u16 timing)
137{
138 ide_hwif_t *hwif = drive->hwif;
139 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
140 int channel = hwif->channel;
141 int unit = drive->select.b.unit;
142 u8 conf;
143
144 /* Program UDMA timing bits */
145 if(itdev->clock_mode == ATA_66)
146 conf = timing >> 8;
147 else
148 conf = timing & 0xFF;
149 if(itdev->timing10 == 0)
150 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + unit, conf);
151 else {
152 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel, conf);
153 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + 1, conf);
154 }
155}
156
157
158/**
159 * it821x_clock_strategy
160 * @hwif: hardware interface
161 *
162 * Select between the 50 and 66Mhz base clocks to get the best
163 * results for this interface.
164 */
165
166static void it821x_clock_strategy(ide_drive_t *drive)
167{
168 ide_hwif_t *hwif = drive->hwif;
169 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
170
171 u8 unit = drive->select.b.unit;
172 ide_drive_t *pair = &hwif->drives[1-unit];
173
174 int clock, altclock;
175 u8 v;
176 int sel = 0;
177
178 if(itdev->want[0][0] > itdev->want[1][0]) {
179 clock = itdev->want[0][1];
180 altclock = itdev->want[1][1];
181 } else {
182 clock = itdev->want[1][1];
183 altclock = itdev->want[0][1];
184 }
185
186 /* Master doesn't care does the slave ? */
187 if(clock == ATA_ANY)
188 clock = altclock;
189
190 /* Nobody cares - keep the same clock */
191 if(clock == ATA_ANY)
192 return;
193 /* No change */
194 if(clock == itdev->clock_mode)
195 return;
196
197 /* Load this into the controller ? */
198 if(clock == ATA_66)
199 itdev->clock_mode = ATA_66;
200 else {
201 itdev->clock_mode = ATA_50;
202 sel = 1;
203 }
204 pci_read_config_byte(hwif->pci_dev, 0x50, &v);
205 v &= ~(1 << (1 + hwif->channel));
206 v |= sel << (1 + hwif->channel);
207 pci_write_config_byte(hwif->pci_dev, 0x50, v);
208
209 /*
210 * Reprogram the UDMA/PIO of the pair drive for the switch
211 * MWDMA will be dealt with by the dma switcher
212 */
213 if(pair && itdev->udma[1-unit] != UDMA_OFF) {
214 it821x_program_udma(pair, itdev->udma[1-unit]);
215 it821x_program(pair, itdev->pio[1-unit]);
216 }
217 /*
218 * Reprogram the UDMA/PIO of our drive for the switch.
219 * MWDMA will be dealt with by the dma switcher
220 */
221 if(itdev->udma[unit] != UDMA_OFF) {
222 it821x_program_udma(drive, itdev->udma[unit]);
223 it821x_program(drive, itdev->pio[unit]);
224 }
225}
226
227/**
228 * it821x_ratemask - Compute available modes
229 * @drive: IDE drive
230 *
231 * Compute the available speeds for the devices on the interface. This
232 * is all modes to ATA133 clipped by drive cable setup.
233 */
234
235static u8 it821x_ratemask (ide_drive_t *drive)
236{
237 u8 mode = 4;
238 if (!eighty_ninty_three(drive))
239 mode = min(mode, (u8)1);
240 return mode;
241}
242
243/**
244 * it821x_tuneproc - tune a drive
245 * @drive: drive to tune
246 * @mode_wanted: the target operating mode
247 *
248 * Load the timing settings for this device mode into the
249 * controller. By the time we are called the mode has been
250 * modified as neccessary to handle the absence of seperate
251 * master/slave timers for MWDMA/PIO.
252 *
253 * This code is only used in pass through mode.
254 */
255
256static void it821x_tuneproc (ide_drive_t *drive, byte mode_wanted)
257{
258 ide_hwif_t *hwif = drive->hwif;
259 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
260 int unit = drive->select.b.unit;
261
262 /* Spec says 89 ref driver uses 88 */
263 static u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
264 static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
265
266 if(itdev->smart)
267 return;
268
269 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
270 itdev->want[unit][1] = pio_want[mode_wanted];
271 itdev->want[unit][0] = 1; /* PIO is lowest priority */
272 itdev->pio[unit] = pio[mode_wanted];
273 it821x_clock_strategy(drive);
274 it821x_program(drive, itdev->pio[unit]);
275}
276
277/**
278 * it821x_tune_mwdma - tune a channel for MWDMA
279 * @drive: drive to set up
280 * @mode_wanted: the target operating mode
281 *
282 * Load the timing settings for this device mode into the
283 * controller when doing MWDMA in pass through mode. The caller
284 * must manage the whole lack of per device MWDMA/PIO timings and
285 * the shared MWDMA/PIO timing register.
286 */
287
288static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted)
289{
290 ide_hwif_t *hwif = drive->hwif;
291 struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif);
292 int unit = drive->select.b.unit;
293 int channel = hwif->channel;
294 u8 conf;
295
296 static u16 dma[] = { 0x8866, 0x3222, 0x3121 };
297 static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
298
299 itdev->want[unit][1] = mwdma_want[mode_wanted];
300 itdev->want[unit][0] = 2; /* MWDMA is low priority */
301 itdev->mwdma[unit] = dma[mode_wanted];
302 itdev->udma[unit] = UDMA_OFF;
303
304 /* UDMA bits off - Revision 0x10 do them in pairs */
305 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
306 if(itdev->timing10)
307 conf |= channel ? 0x60: 0x18;
308 else
309 conf |= 1 << (3 + 2 * channel + unit);
310 pci_write_config_byte(hwif->pci_dev, 0x50, conf);
311
312 it821x_clock_strategy(drive);
313 /* FIXME: do we need to program this ? */
314 /* it821x_program(drive, itdev->mwdma[unit]); */
315}
316
317/**
318 * it821x_tune_udma - tune a channel for UDMA
319 * @drive: drive to set up
320 * @mode_wanted: the target operating mode
321 *
322 * Load the timing settings for this device mode into the
323 * controller when doing UDMA modes in pass through.
324 */
325
326static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted)
327{
328 ide_hwif_t *hwif = drive->hwif;
329 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
330 int unit = drive->select.b.unit;
331 int channel = hwif->channel;
332 u8 conf;
333
334 static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
335 static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
336
337 itdev->want[unit][1] = udma_want[mode_wanted];
338 itdev->want[unit][0] = 3; /* UDMA is high priority */
339 itdev->mwdma[unit] = MWDMA_OFF;
340 itdev->udma[unit] = udma[mode_wanted];
341 if(mode_wanted >= 5)
342 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
343
344 /* UDMA on. Again revision 0x10 must do the pair */
345 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
346 if(itdev->timing10)
347 conf &= channel ? 0x9F: 0xE7;
348 else
349 conf &= ~ (1 << (3 + 2 * channel + unit));
350 pci_write_config_byte(hwif->pci_dev, 0x50, conf);
351
352 it821x_clock_strategy(drive);
353 it821x_program_udma(drive, itdev->udma[unit]);
354
355}
356
357/**
358 * config_it821x_chipset_for_pio - set drive timings
359 * @drive: drive to tune
360 * @speed we want
361 *
362 * Compute the best pio mode we can for a given device. We must
363 * pick a speed that does not cause problems with the other device
364 * on the cable.
365 */
366
367static void config_it821x_chipset_for_pio (ide_drive_t *drive, byte set_speed)
368{
369 u8 unit = drive->select.b.unit;
370 ide_hwif_t *hwif = drive->hwif;
371 ide_drive_t *pair = &hwif->drives[1-unit];
372 u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
373 u8 pair_pio;
374
375 /* We have to deal with this mess in pairs */
376 if(pair != NULL) {
377 pair_pio = ide_get_best_pio_mode(pair, 255, 5, NULL);
378 /* Trim PIO to the slowest of the master/slave */
379 if(pair_pio < set_pio)
380 set_pio = pair_pio;
381 }
382 it821x_tuneproc(drive, set_pio);
383 speed = XFER_PIO_0 + set_pio;
384 /* XXX - We trim to the lowest of the pair so the other drive
385 will always be fine at this point until we do hotplug passthru */
386
387 if (set_speed)
388 (void) ide_config_drive_speed(drive, speed);
389}
390
391/**
392 * it821x_dma_read - DMA hook
393 * @drive: drive for DMA
394 *
395 * The IT821x has a single timing register for MWDMA and for PIO
396 * operations. As we flip back and forth we have to reload the
397 * clock. In addition the rev 0x10 device only works if the same
398 * timing value is loaded into the master and slave UDMA clock
399 * so we must also reload that.
400 *
401 * FIXME: we could figure out in advance if we need to do reloads
402 */
403
404static void it821x_dma_start(ide_drive_t *drive)
405{
406 ide_hwif_t *hwif = drive->hwif;
407 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
408 int unit = drive->select.b.unit;
409 if(itdev->mwdma[unit] != MWDMA_OFF)
410 it821x_program(drive, itdev->mwdma[unit]);
411 else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
412 it821x_program_udma(drive, itdev->udma[unit]);
413 ide_dma_start(drive);
414}
415
416/**
417 * it821x_dma_write - DMA hook
418 * @drive: drive for DMA stop
419 *
420 * The IT821x has a single timing register for MWDMA and for PIO
421 * operations. As we flip back and forth we have to reload the
422 * clock.
423 */
424
425static int it821x_dma_end(ide_drive_t *drive)
426{
427 ide_hwif_t *hwif = drive->hwif;
428 int unit = drive->select.b.unit;
429 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
430 int ret = __ide_dma_end(drive);
431 if(itdev->mwdma[unit] != MWDMA_OFF)
432 it821x_program(drive, itdev->pio[unit]);
433 return ret;
434}
435
436
437/**
438 * it821x_tune_chipset - set controller timings
439 * @drive: Drive to set up
440 * @xferspeed: speed we want to achieve
441 *
442 * Tune the ITE chipset for the desired mode. If we can't achieve
443 * the desired mode then tune for a lower one, but ultimately
444 * make the thing work.
445 */
446
447static int it821x_tune_chipset (ide_drive_t *drive, byte xferspeed)
448{
449
450 ide_hwif_t *hwif = drive->hwif;
451 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
452 u8 speed = ide_rate_filter(it821x_ratemask(drive), xferspeed);
453
454 if(!itdev->smart) {
455 switch(speed) {
456 case XFER_PIO_4:
457 case XFER_PIO_3:
458 case XFER_PIO_2:
459 case XFER_PIO_1:
460 case XFER_PIO_0:
461 it821x_tuneproc(drive, (speed - XFER_PIO_0));
462 break;
463 /* MWDMA tuning is really hard because our MWDMA and PIO
464 timings are kept in the same place. We can switch in the
465 host dma on/off callbacks */
466 case XFER_MW_DMA_2:
467 case XFER_MW_DMA_1:
468 case XFER_MW_DMA_0:
469 it821x_tune_mwdma(drive, (speed - XFER_MW_DMA_0));
470 break;
471 case XFER_UDMA_6:
472 case XFER_UDMA_5:
473 case XFER_UDMA_4:
474 case XFER_UDMA_3:
475 case XFER_UDMA_2:
476 case XFER_UDMA_1:
477 case XFER_UDMA_0:
478 it821x_tune_udma(drive, (speed - XFER_UDMA_0));
479 break;
480 default:
481 return 1;
482 }
483 }
484 /*
485 * In smart mode the clocking is done by the host controller
486 * snooping the mode we picked. The rest of it is not our problem
487 */
488 return ide_config_drive_speed(drive, speed);
489}
490
491/**
492 * config_chipset_for_dma - configure for DMA
493 * @drive: drive to configure
494 *
495 * Called by the IDE layer when it wants the timings set up.
496 */
497
498static int config_chipset_for_dma (ide_drive_t *drive)
499{
500 u8 speed = ide_dma_speed(drive, it821x_ratemask(drive));
501
502 config_it821x_chipset_for_pio(drive, !speed);
503 it821x_tune_chipset(drive, speed);
504 return ide_dma_enable(drive);
505}
506
507/**
508 * it821x_configure_drive_for_dma - set up for DMA transfers
509 * @drive: drive we are going to set up
510 *
511 * Set up the drive for DMA, tune the controller and drive as
512 * required. If the drive isn't suitable for DMA or we hit
513 * other problems then we will drop down to PIO and set up
514 * PIO appropriately
515 */
516
517static int it821x_config_drive_for_dma (ide_drive_t *drive)
518{
519 ide_hwif_t *hwif = drive->hwif;
520
521 if (ide_use_dma(drive)) {
522 if (config_chipset_for_dma(drive))
523 return hwif->ide_dma_on(drive);
524 }
525 config_it821x_chipset_for_pio(drive, 1);
526 return hwif->ide_dma_off_quietly(drive);
527}
528
529/**
530 * ata66_it821x - check for 80 pin cable
531 * @hwif: interface to check
532 *
533 * Check for the presence of an ATA66 capable cable on the
534 * interface. Problematic as it seems some cards don't have
535 * the needed logic onboard.
536 */
537
538static unsigned int __devinit ata66_it821x(ide_hwif_t *hwif)
539{
540 /* The reference driver also only does disk side */
541 return 1;
542}
543
544/**
545 * it821x_fixup - post init callback
546 * @hwif: interface
547 *
548 * This callback is run after the drives have been probed but
549 * before anything gets attached. It allows drivers to do any
550 * final tuning that is needed, or fixups to work around bugs.
551 */
552
553static void __devinit it821x_fixups(ide_hwif_t *hwif)
554{
555 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
556 int i;
557
558 if(!itdev->smart) {
559 /*
560 * If we are in pass through mode then not much
561 * needs to be done, but we do bother to clear the
562 * IRQ mask as we may well be in PIO (eg rev 0x10)
563 * for now and we know unmasking is safe on this chipset.
564 */
565 for (i = 0; i < 2; i++) {
566 ide_drive_t *drive = &hwif->drives[i];
567 if(drive->present)
568 drive->unmask = 1;
569 }
570 return;
571 }
572 /*
573 * Perform fixups on smart mode. We need to "lose" some
574 * capabilities the firmware lacks but does not filter, and
575 * also patch up some capability bits that it forgets to set
576 * in RAID mode.
577 */
578
579 for(i = 0; i < 2; i++) {
580 ide_drive_t *drive = &hwif->drives[i];
581 struct hd_driveid *id;
582 u16 *idbits;
583
584 if(!drive->present)
585 continue;
586 id = drive->id;
587 idbits = (u16 *)drive->id;
588
589 /* Check for RAID v native */
590 if(strstr(id->model, "Integrated Technology Express")) {
591 /* In raid mode the ident block is slightly buggy
592 We need to set the bits so that the IDE layer knows
593 LBA28. LBA48 and DMA ar valid */
594 id->capability |= 3; /* LBA28, DMA */
595 id->command_set_2 |= 0x0400; /* LBA48 valid */
596 id->cfs_enable_2 |= 0x0400; /* LBA48 on */
597 /* Reporting logic */
598 printk(KERN_INFO "%s: IT8212 %sRAID %d volume",
599 drive->name,
600 idbits[147] ? "Bootable ":"",
601 idbits[129]);
602 if(idbits[129] != 1)
603 printk("(%dK stripe)", idbits[146]);
604 printk(".\n");
605 /* Now the core code will have wrongly decided no DMA
606 so we need to fix this */
607 hwif->ide_dma_off_quietly(drive);
608#ifdef CONFIG_IDEDMA_ONLYDISK
609 if (drive->media == ide_disk)
610#endif
611 hwif->ide_dma_check(drive);
612 } else {
613 /* Non RAID volume. Fixups to stop the core code
614 doing unsupported things */
615 id->field_valid &= 1;
616 id->queue_depth = 0;
617 id->command_set_1 = 0;
618 id->command_set_2 &= 0xC400;
619 id->cfsse &= 0xC000;
620 id->cfs_enable_1 = 0;
621 id->cfs_enable_2 &= 0xC400;
622 id->csf_default &= 0xC000;
623 id->word127 = 0;
624 id->dlf = 0;
625 id->csfo = 0;
626 id->cfa_power = 0;
627 printk(KERN_INFO "%s: Performing identify fixups.\n",
628 drive->name);
629 }
630 }
631
632}
633
634/**
635 * init_hwif_it821x - set up hwif structs
636 * @hwif: interface to set up
637 *
638 * We do the basic set up of the interface structure. The IT8212
639 * requires several custom handlers so we override the default
640 * ide DMA handlers appropriately
641 */
642
643static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
644{
645 struct it821x_dev *idev = kmalloc(sizeof(struct it821x_dev), GFP_KERNEL);
646 u8 conf;
647
648 if(idev == NULL) {
649 printk(KERN_ERR "it821x: out of memory, falling back to legacy behaviour.\n");
650 goto fallback;
651 }
652 memset(idev, 0, sizeof(struct it821x_dev));
653 ide_set_hwifdata(hwif, idev);
654
655 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
656 if(conf & 1) {
657 idev->smart = 1;
658 hwif->atapi_dma = 0;
659 /* Long I/O's although allowed in LBA48 space cause the
660 onboard firmware to enter the twighlight zone */
661 hwif->rqsize = 256;
662 }
663
664 /* Pull the current clocks from 0x50 also */
665 if (conf & (1 << (1 + hwif->channel)))
666 idev->clock_mode = ATA_50;
667 else
668 idev->clock_mode = ATA_66;
669
670 idev->want[0][1] = ATA_ANY;
671 idev->want[1][1] = ATA_ANY;
672
673 /*
674 * Not in the docs but according to the reference driver
675 * this is neccessary.
676 */
677
678 pci_read_config_byte(hwif->pci_dev, 0x08, &conf);
679 if(conf == 0x10) {
680 idev->timing10 = 1;
681 hwif->atapi_dma = 0;
682 if(!idev->smart)
683 printk(KERN_WARNING "it821x: Revision 0x10, workarounds activated.\n");
684 }
685
686 hwif->speedproc = &it821x_tune_chipset;
687 hwif->tuneproc = &it821x_tuneproc;
688
689 /* MWDMA/PIO clock switching for pass through mode */
690 if(!idev->smart) {
691 hwif->dma_start = &it821x_dma_start;
692 hwif->ide_dma_end = &it821x_dma_end;
693 }
694
695 hwif->drives[0].autotune = 1;
696 hwif->drives[1].autotune = 1;
697
698 if (!hwif->dma_base)
699 goto fallback;
700
701 hwif->ultra_mask = 0x7f;
702 hwif->mwdma_mask = 0x07;
703 hwif->swdma_mask = 0x07;
704
705 hwif->ide_dma_check = &it821x_config_drive_for_dma;
706 if (!(hwif->udma_four))
707 hwif->udma_four = ata66_it821x(hwif);
708
709 /*
710 * The BIOS often doesn't set up DMA on this controller
711 * so we always do it.
712 */
713
714 hwif->autodma = 1;
715 hwif->drives[0].autodma = hwif->autodma;
716 hwif->drives[1].autodma = hwif->autodma;
717 return;
718fallback:
719 hwif->autodma = 0;
720 return;
721}
722
723static void __devinit it8212_disable_raid(struct pci_dev *dev)
724{
725 /* Reset local CPU, and set BIOS not ready */
726 pci_write_config_byte(dev, 0x5E, 0x01);
727
728 /* Set to bypass mode, and reset PCI bus */
729 pci_write_config_byte(dev, 0x50, 0x00);
730 pci_write_config_word(dev, PCI_COMMAND,
731 PCI_COMMAND_PARITY | PCI_COMMAND_IO |
732 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
733 pci_write_config_word(dev, 0x40, 0xA0F3);
734
735 pci_write_config_dword(dev,0x4C, 0x02040204);
736 pci_write_config_byte(dev, 0x42, 0x36);
737 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0);
738}
739
740static unsigned int __devinit init_chipset_it821x(struct pci_dev *dev, const char *name)
741{
742 u8 conf;
743 static char *mode[2] = { "pass through", "smart" };
744
745 /* Force the card into bypass mode if so requested */
746 if (it8212_noraid) {
747 printk(KERN_INFO "it8212: forcing bypass mode.\n");
748 it8212_disable_raid(dev);
749 }
750 pci_read_config_byte(dev, 0x50, &conf);
751 printk(KERN_INFO "it821x: controller in %s mode.\n", mode[conf & 1]);
752 return 0;
753}
754
755
756#define DECLARE_ITE_DEV(name_str) \
757 { \
758 .name = name_str, \
759 .init_chipset = init_chipset_it821x, \
760 .init_hwif = init_hwif_it821x, \
761 .channels = 2, \
762 .autodma = AUTODMA, \
763 .bootable = ON_BOARD, \
764 .fixup = it821x_fixups \
765 }
766
767static ide_pci_device_t it821x_chipsets[] __devinitdata = {
768 /* 0 */ DECLARE_ITE_DEV("IT8212"),
769};
770
771/**
772 * it821x_init_one - pci layer discovery entry
773 * @dev: PCI device
774 * @id: ident table entry
775 *
776 * Called by the PCI code when it finds an ITE821x controller.
777 * We then use the IDE PCI generic helper to do most of the work.
778 */
779
780static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
781{
782 ide_setup_pci_device(dev, &it821x_chipsets[id->driver_data]);
783 return 0;
784}
785
786static struct pci_device_id it821x_pci_tbl[] = {
787 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
788 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
789 { 0, },
790};
791
792MODULE_DEVICE_TABLE(pci, it821x_pci_tbl);
793
794static struct pci_driver driver = {
795 .name = "ITE821x IDE",
796 .id_table = it821x_pci_tbl,
797 .probe = it821x_init_one,
798};
799
800static int __init it821x_ide_init(void)
801{
802 return ide_pci_register_driver(&driver);
803}
804
805module_init(it821x_ide_init);
806
807module_param_named(noraid, it8212_noraid, int, S_IRUGO);
808MODULE_PARM_DESC(it8212_noraid, "Force card into bypass mode");
809
810MODULE_AUTHOR("Alan Cox");
811MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
812MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/serverworks.c b/drivers/ide/pci/serverworks.c
index 82a1103b2413..c6f5fa4b4ca6 100644
--- a/drivers/ide/pci/serverworks.c
+++ b/drivers/ide/pci/serverworks.c
@@ -442,7 +442,7 @@ static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const cha
442 return (dev->irq) ? dev->irq : 0; 442 return (dev->irq) ? dev->irq : 0;
443} 443}
444 444
445static unsigned int __init ata66_svwks_svwks (ide_hwif_t *hwif) 445static unsigned int __devinit ata66_svwks_svwks (ide_hwif_t *hwif)
446{ 446{
447 return 1; 447 return 1;
448} 448}
@@ -454,7 +454,7 @@ static unsigned int __init ata66_svwks_svwks (ide_hwif_t *hwif)
454 * Bit 14 clear = primary IDE channel does not have 80-pin cable. 454 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
455 * Bit 14 set = primary IDE channel has 80-pin cable. 455 * Bit 14 set = primary IDE channel has 80-pin cable.
456 */ 456 */
457static unsigned int __init ata66_svwks_dell (ide_hwif_t *hwif) 457static unsigned int __devinit ata66_svwks_dell (ide_hwif_t *hwif)
458{ 458{
459 struct pci_dev *dev = hwif->pci_dev; 459 struct pci_dev *dev = hwif->pci_dev;
460 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL && 460 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
@@ -472,7 +472,7 @@ static unsigned int __init ata66_svwks_dell (ide_hwif_t *hwif)
472 * 472 *
473 * WARNING: this only works on Alpine hardware! 473 * WARNING: this only works on Alpine hardware!
474 */ 474 */
475static unsigned int __init ata66_svwks_cobalt (ide_hwif_t *hwif) 475static unsigned int __devinit ata66_svwks_cobalt (ide_hwif_t *hwif)
476{ 476{
477 struct pci_dev *dev = hwif->pci_dev; 477 struct pci_dev *dev = hwif->pci_dev;
478 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN && 478 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
@@ -483,7 +483,7 @@ static unsigned int __init ata66_svwks_cobalt (ide_hwif_t *hwif)
483 return 0; 483 return 0;
484} 484}
485 485
486static unsigned int __init ata66_svwks (ide_hwif_t *hwif) 486static unsigned int __devinit ata66_svwks (ide_hwif_t *hwif)
487{ 487{
488 struct pci_dev *dev = hwif->pci_dev; 488 struct pci_dev *dev = hwif->pci_dev;
489 489
@@ -573,7 +573,7 @@ static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
573 return ide_setup_pci_device(dev, d); 573 return ide_setup_pci_device(dev, d);
574} 574}
575 575
576static int __init init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d) 576static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
577{ 577{
578 if (!(PCI_FUNC(dev->devfn) & 1)) { 578 if (!(PCI_FUNC(dev->devfn) & 1)) {
579 d->bootable = NEVER_BOARD; 579 d->bootable = NEVER_BOARD;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 23:16:27 -0500