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path: root/drivers/ide/pci
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-rw-r--r--drivers/ide/pci/sl82c105.c34
1 files changed, 3 insertions, 31 deletions
diff --git a/drivers/ide/pci/sl82c105.c b/drivers/ide/pci/sl82c105.c
index a85413467f93..c7a125b66c29 100644
--- a/drivers/ide/pci/sl82c105.c
+++ b/drivers/ide/pci/sl82c105.c
@@ -219,35 +219,8 @@ static int sl82c105_dma_end(ide_drive_t *drive)
219} 219}
220 220
221/* 221/*
222 * Ok, that is nasty, but we must make sure the DMA timings
223 * won't be used for a PIO access. The solution here is
224 * to make sure the 16 bits mode is diabled on the channel
225 * when DMA is enabled, thus causing the chip to use PIO0
226 * timings for those operations.
227 */
228static void sl82c105_selectproc(ide_drive_t *drive)
229{
230 ide_hwif_t *hwif = HWIF(drive);
231 struct pci_dev *dev = hwif->pci_dev;
232 u32 val, old, mask;
233
234 //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
235
236 mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
237 old = val = (u32)pci_get_drvdata(dev);
238 if (drive->using_dma)
239 val &= ~mask;
240 else
241 val |= mask;
242 if (old != val) {
243 pci_write_config_dword(dev, 0x40, val);
244 pci_set_drvdata(dev, (void *)val);
245 }
246}
247
248/*
249 * ATA reset will clear the 16 bits mode in the control 222 * ATA reset will clear the 16 bits mode in the control
250 * register, we need to update our cache 223 * register, we need to reprogram it
251 */ 224 */
252static void sl82c105_resetproc(ide_drive_t *drive) 225static void sl82c105_resetproc(ide_drive_t *drive)
253{ 226{
@@ -257,7 +230,8 @@ static void sl82c105_resetproc(ide_drive_t *drive)
257 DBG(("sl82c105_resetproc(drive:%s)\n", drive->name)); 230 DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
258 231
259 pci_read_config_dword(dev, 0x40, &val); 232 pci_read_config_dword(dev, 0x40, &val);
260 pci_set_drvdata(dev, (void *)val); 233 val |= (CTRL_P1F16 | CTRL_P0F16);
234 pci_write_config_dword(dev, 0x40, val);
261} 235}
262 236
263/* 237/*
@@ -310,7 +284,6 @@ static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const c
310 pci_read_config_dword(dev, 0x40, &val); 284 pci_read_config_dword(dev, 0x40, &val);
311 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; 285 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
312 pci_write_config_dword(dev, 0x40, val); 286 pci_write_config_dword(dev, 0x40, val);
313 pci_set_drvdata(dev, (void *)val);
314 287
315 return dev->irq; 288 return dev->irq;
316} 289}
@@ -326,7 +299,6 @@ static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
326 299
327 hwif->set_pio_mode = &sl82c105_set_pio_mode; 300 hwif->set_pio_mode = &sl82c105_set_pio_mode;
328 hwif->set_dma_mode = &sl82c105_set_dma_mode; 301 hwif->set_dma_mode = &sl82c105_set_dma_mode;
329 hwif->selectproc = &sl82c105_selectproc;
330 hwif->resetproc = &sl82c105_resetproc; 302 hwif->resetproc = &sl82c105_resetproc;
331 303
332 if (!hwif->dma_base) 304 if (!hwif->dma_base)