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-rw-r--r--drivers/ide/pci/aec62xx.c22
-rw-r--r--drivers/ide/pci/alim15x3.c7
-rw-r--r--drivers/ide/pci/cmd64x.c537
-rw-r--r--drivers/ide/pci/hpt366.c7
-rw-r--r--drivers/ide/pci/it821x.c126
-rw-r--r--drivers/ide/pci/pdc202xx_new.c3
-rw-r--r--drivers/ide/pci/siimage.c12
-rw-r--r--drivers/ide/pci/sl82c105.c247
8 files changed, 454 insertions, 507 deletions
diff --git a/drivers/ide/pci/aec62xx.c b/drivers/ide/pci/aec62xx.c
index 990eafe5ea11..73bdf64dbbfc 100644
--- a/drivers/ide/pci/aec62xx.c
+++ b/drivers/ide/pci/aec62xx.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * linux/drivers/ide/pci/aec62xx.c Version 0.11 March 27, 2002 2 * linux/drivers/ide/pci/aec62xx.c Version 0.21 Apr 21, 2007
3 * 3 *
4 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
5 * 6 *
6 */ 7 */
7 8
@@ -193,18 +194,8 @@ static int config_chipset_for_dma (ide_drive_t *drive)
193 194
194static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio) 195static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
195{ 196{
196 u8 speed = 0; 197 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
197 u8 new_pio = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL); 198 (void) aec62xx_tune_chipset(drive, pio + XFER_PIO_0);
198
199 switch(pio) {
200 case 5: speed = new_pio; break;
201 case 4: speed = XFER_PIO_4; break;
202 case 3: speed = XFER_PIO_3; break;
203 case 2: speed = XFER_PIO_2; break;
204 case 1: speed = XFER_PIO_1; break;
205 default: speed = XFER_PIO_0; break;
206 }
207 (void) aec62xx_tune_chipset(drive, speed);
208} 199}
209 200
210static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive) 201static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
@@ -213,7 +204,7 @@ static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
213 return 0; 204 return 0;
214 205
215 if (ide_use_fast_pio(drive)) 206 if (ide_use_fast_pio(drive))
216 aec62xx_tune_drive(drive, 5); 207 aec62xx_tune_drive(drive, 255);
217 208
218 return -1; 209 return -1;
219} 210}
@@ -288,11 +279,10 @@ static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
288 279
289 hwif->ultra_mask = 0x7f; 280 hwif->ultra_mask = 0x7f;
290 hwif->mwdma_mask = 0x07; 281 hwif->mwdma_mask = 0x07;
291 hwif->swdma_mask = 0x07;
292 282
293 hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate; 283 hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate;
294 hwif->ide_dma_lostirq = &aec62xx_irq_timeout; 284 hwif->ide_dma_lostirq = &aec62xx_irq_timeout;
295 hwif->ide_dma_timeout = &aec62xx_irq_timeout; 285
296 if (!noautodma) 286 if (!noautodma)
297 hwif->autodma = 1; 287 hwif->autodma = 1;
298 hwif->drives[0].autodma = hwif->autodma; 288 hwif->drives[0].autodma = hwif->autodma;
diff --git a/drivers/ide/pci/alim15x3.c b/drivers/ide/pci/alim15x3.c
index 83e0aa65a431..946a12746cb5 100644
--- a/drivers/ide/pci/alim15x3.c
+++ b/drivers/ide/pci/alim15x3.c
@@ -534,7 +534,7 @@ static int ali15x3_config_drive_for_dma(ide_drive_t *drive)
534 struct hd_driveid *id = drive->id; 534 struct hd_driveid *id = drive->id;
535 535
536 if ((m5229_revision<=0x20) && (drive->media!=ide_disk)) 536 if ((m5229_revision<=0x20) && (drive->media!=ide_disk))
537 goto no_dma_set; 537 goto ata_pio;
538 538
539 drive->init_speed = 0; 539 drive->init_speed = 0;
540 540
@@ -555,20 +555,19 @@ try_dma_modes:
555 (id->dma_1word & hwif->swdma_mask)) { 555 (id->dma_1word & hwif->swdma_mask)) {
556 /* Force if Capable regular DMA modes */ 556 /* Force if Capable regular DMA modes */
557 if (!config_chipset_for_dma(drive)) 557 if (!config_chipset_for_dma(drive))
558 goto no_dma_set; 558 goto ata_pio;
559 } 559 }
560 } else if (__ide_dma_good_drive(drive) && 560 } else if (__ide_dma_good_drive(drive) &&
561 (id->eide_dma_time < 150)) { 561 (id->eide_dma_time < 150)) {
562 /* Consult the list of known "good" drives */ 562 /* Consult the list of known "good" drives */
563 if (!config_chipset_for_dma(drive)) 563 if (!config_chipset_for_dma(drive))
564 goto no_dma_set; 564 goto ata_pio;
565 } else { 565 } else {
566 goto ata_pio; 566 goto ata_pio;
567 } 567 }
568 } else { 568 } else {
569ata_pio: 569ata_pio:
570 hwif->tuneproc(drive, 255); 570 hwif->tuneproc(drive, 255);
571no_dma_set:
572 return -1; 571 return -1;
573 } 572 }
574 573
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c
index 561197f7b5bb..77f51ab6d439 100644
--- a/drivers/ide/pci/cmd64x.c
+++ b/drivers/ide/pci/cmd64x.c
@@ -1,10 +1,7 @@
1/* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16 1/*
2 * 2 * linux/drivers/ide/pci/cmd64x.c Version 1.47 Mar 19, 2007
3 * linux/drivers/ide/pci/cmd64x.c Version 1.42 Feb 8, 2007
4 * 3 *
5 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. 4 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
6 * Note, this driver is not used at all on other systems because
7 * there the "BIOS" has done all of the following already.
8 * Due to massive hardware bugs, UltraDMA is only supported 5 * Due to massive hardware bugs, UltraDMA is only supported
9 * on the 646U2 and not on the 646U. 6 * on the 646U2 and not on the 646U.
10 * 7 *
@@ -39,11 +36,12 @@
39 * CMD64x specific registers definition. 36 * CMD64x specific registers definition.
40 */ 37 */
41#define CFR 0x50 38#define CFR 0x50
42#define CFR_INTR_CH0 0x02 39#define CFR_INTR_CH0 0x04
43#define CNTRL 0x51 40#define CNTRL 0x51
44#define CNTRL_DIS_RA0 0x40 41#define CNTRL_ENA_1ST 0x04
45#define CNTRL_DIS_RA1 0x80 42#define CNTRL_ENA_2ND 0x08
46#define CNTRL_ENA_2ND 0x08 43#define CNTRL_DIS_RA0 0x40
44#define CNTRL_DIS_RA1 0x80
47 45
48#define CMDTIM 0x52 46#define CMDTIM 0x52
49#define ARTTIM0 0x53 47#define ARTTIM0 0x53
@@ -90,86 +88,67 @@ static int n_cmd_devs;
90static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index) 88static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
91{ 89{
92 char *p = buf; 90 char *p = buf;
93
94 u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0; /* primary */
95 u8 reg57 = 0, reg58 = 0, reg5b; /* secondary */
96 u8 reg72 = 0, reg73 = 0; /* primary */ 91 u8 reg72 = 0, reg73 = 0; /* primary */
97 u8 reg7a = 0, reg7b = 0; /* secondary */ 92 u8 reg7a = 0, reg7b = 0; /* secondary */
98 u8 reg50 = 0, reg71 = 0; /* extra */ 93 u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */
94 u8 rev = 0;
99 95
100 p += sprintf(p, "\nController: %d\n", index); 96 p += sprintf(p, "\nController: %d\n", index);
101 p += sprintf(p, "CMD%x Chipset.\n", dev->device); 97 p += sprintf(p, "PCI-%x Chipset.\n", dev->device);
98
102 (void) pci_read_config_byte(dev, CFR, &reg50); 99 (void) pci_read_config_byte(dev, CFR, &reg50);
103 (void) pci_read_config_byte(dev, ARTTIM0, &reg53); 100 (void) pci_read_config_byte(dev, CNTRL, &reg51);
104 (void) pci_read_config_byte(dev, DRWTIM0, &reg54); 101 (void) pci_read_config_byte(dev, ARTTIM23, &reg57);
105 (void) pci_read_config_byte(dev, ARTTIM1, &reg55);
106 (void) pci_read_config_byte(dev, DRWTIM1, &reg56);
107 (void) pci_read_config_byte(dev, ARTTIM2, &reg57);
108 (void) pci_read_config_byte(dev, DRWTIM2, &reg58);
109 (void) pci_read_config_byte(dev, DRWTIM3, &reg5b);
110 (void) pci_read_config_byte(dev, MRDMODE, &reg71); 102 (void) pci_read_config_byte(dev, MRDMODE, &reg71);
111 (void) pci_read_config_byte(dev, BMIDESR0, &reg72); 103 (void) pci_read_config_byte(dev, BMIDESR0, &reg72);
112 (void) pci_read_config_byte(dev, UDIDETCR0, &reg73); 104 (void) pci_read_config_byte(dev, UDIDETCR0, &reg73);
113 (void) pci_read_config_byte(dev, BMIDESR1, &reg7a); 105 (void) pci_read_config_byte(dev, BMIDESR1, &reg7a);
114 (void) pci_read_config_byte(dev, UDIDETCR1, &reg7b); 106 (void) pci_read_config_byte(dev, UDIDETCR1, &reg7b);
115 107
116 p += sprintf(p, "--------------- Primary Channel " 108 /* PCI0643/6 originally didn't have the primary channel enable bit */
117 "---------------- Secondary Channel " 109 (void) pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
118 "-------------\n"); 110 if ((dev->device == PCI_DEVICE_ID_CMD_643) ||
119 p += sprintf(p, " %sabled " 111 (dev->device == PCI_DEVICE_ID_CMD_646 && rev < 3))
120 " %sabled\n", 112 reg51 |= CNTRL_ENA_1ST;
121 (reg72&0x80)?"dis":" en", 113
122 (reg7a&0x80)?"dis":" en"); 114 p += sprintf(p, "---------------- Primary Channel "
123 p += sprintf(p, "--------------- drive0 " 115 "---------------- Secondary Channel ------------\n");
124 "--------- drive1 -------- drive0 " 116 p += sprintf(p, " %s %s\n",
125 "---------- drive1 ------\n"); 117 (reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled",
126 p += sprintf(p, "DMA enabled: %s %s" 118 (reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled");
127 " %s %s\n", 119 p += sprintf(p, "---------------- drive0 --------- drive1 "
128 (reg72&0x20)?"yes":"no ", (reg72&0x40)?"yes":"no ", 120 "-------- drive0 --------- drive1 ------\n");
129 (reg7a&0x20)?"yes":"no ", (reg7a&0x40)?"yes":"no "); 121 p += sprintf(p, "DMA enabled: %s %s"
130 122 " %s %s\n",
131 p += sprintf(p, "DMA Mode: %s(%s) %s(%s)", 123 (reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ",
132 (reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO", 124 (reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no ");
133 (reg72&0x20)?( 125 p += sprintf(p, "UltraDMA mode: %s (%c) %s (%c)",
134 ((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"): 126 ( reg73 & 0x01) ? " on" : "off",
135 ((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"): 127 ((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') :
136 ((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"): 128 ((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') :
137 ((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"): 129 ((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') :
138 "X"):"?", 130 ((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?',
139 (reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO", 131 ( reg73 & 0x02) ? " on" : "off",
140 (reg72&0x40)?( 132 ((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') :
141 ((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"): 133 ((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') :
142 ((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"): 134 ((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') :
143 ((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"): 135 ((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?');
144 ((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"): 136 p += sprintf(p, " %s (%c) %s (%c)\n",
145 "X"):"?"); 137 ( reg7b & 0x01) ? " on" : "off",
146 p += sprintf(p, " %s(%s) %s(%s)\n", 138 ((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') :
147 (reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO", 139 ((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') :
148 (reg7a&0x20)?( 140 ((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') :
149 ((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"): 141 ((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?',
150 ((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"): 142 ( reg7b & 0x02) ? " on" : "off",
151 ((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"): 143 ((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') :
152 ((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"): 144 ((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') :
153 "X"):"?", 145 ((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') :
154 (reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO", 146 ((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?');
155 (reg7a&0x40)?( 147 p += sprintf(p, "Interrupt: %s, %s %s, %s\n",
156 ((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"): 148 (reg71 & MRDMODE_BLK_CH0 ) ? "blocked" : "enabled",
157 ((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"): 149 (reg50 & CFR_INTR_CH0 ) ? "pending" : "clear ",
158 ((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"): 150 (reg71 & MRDMODE_BLK_CH1 ) ? "blocked" : "enabled",
159 ((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"): 151 (reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear ");
160 "X"):"?" );
161 p += sprintf(p, "PIO Mode: %s %s"
162 " %s %s\n",
163 "?", "?", "?", "?");
164 p += sprintf(p, " %s %s\n",
165 (reg50 & CFR_INTR_CH0) ? "interrupting" : "polling ",
166 (reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling");
167 p += sprintf(p, " %s %s\n",
168 (reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear ",
169 (reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear");
170 p += sprintf(p, " %s %s\n",
171 (reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled",
172 (reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled");
173 152
174 return (char *)p; 153 return (char *)p;
175} 154}
@@ -179,7 +158,6 @@ static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
179 char *p = buffer; 158 char *p = buffer;
180 int i; 159 int i;
181 160
182 p += sprintf(p, "\n");
183 for (i = 0; i < n_cmd_devs; i++) { 161 for (i = 0; i < n_cmd_devs; i++) {
184 struct pci_dev *dev = cmd_devs[i]; 162 struct pci_dev *dev = cmd_devs[i];
185 p = print_cmd64x_get_info(p, dev, i); 163 p = print_cmd64x_get_info(p, dev, i);
@@ -195,116 +173,103 @@ static u8 quantize_timing(int timing, int quant)
195} 173}
196 174
197/* 175/*
198 * This routine writes the prepared setup/active/recovery counts 176 * This routine calculates active/recovery counts and then writes them into
199 * for a drive into the cmd646 chipset registers to active them. 177 * the chipset registers.
200 */ 178 */
201static void program_drive_counts (ide_drive_t *drive, int setup_count, int active_count, int recovery_count) 179static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
202{ 180{
203 unsigned long flags; 181 struct pci_dev *dev = HWIF(drive)->pci_dev;
204 struct pci_dev *dev = HWIF(drive)->pci_dev; 182 int clock_time = 1000 / system_bus_clock();
205 ide_drive_t *drives = HWIF(drive)->drives; 183 u8 cycle_count, active_count, recovery_count, drwtim;
206 u8 temp_b; 184 static const u8 recovery_values[] =
207 static const u8 setup_counts[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
208 static const u8 recovery_counts[] =
209 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; 185 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
210 static const u8 arttim_regs[2][2] = { 186 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
211 { ARTTIM0, ARTTIM1 }, 187
212 { ARTTIM23, ARTTIM23 } 188 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
213 }; 189 cycle_time, active_time);
214 static const u8 drwtim_regs[2][2] = { 190
215 { DRWTIM0, DRWTIM1 }, 191 cycle_count = quantize_timing( cycle_time, clock_time);
216 { DRWTIM2, DRWTIM3 } 192 active_count = quantize_timing(active_time, clock_time);
217 }; 193 recovery_count = cycle_count - active_count;
218 int channel = (int) HWIF(drive)->channel; 194
219 int slave = (drives != drive); /* Is this really the best way to determine this?? */
220
221 cmdprintk("program_drive_count parameters = s(%d),a(%d),r(%d),p(%d)\n",
222 setup_count, active_count, recovery_count, drive->present);
223 /* 195 /*
224 * Set up address setup count registers. 196 * In case we've got too long recovery phase, try to lengthen
225 * Primary interface has individual count/timing registers for 197 * the active phase
226 * each drive. Secondary interface has one common set of registers,
227 * for address setup so we merge these timings, using the slowest
228 * value.
229 */ 198 */
230 if (channel) { 199 if (recovery_count > 16) {
231 drive->drive_data = setup_count; 200 active_count += recovery_count - 16;
232 setup_count = max(drives[0].drive_data, 201 recovery_count = 16;
233 drives[1].drive_data);
234 cmdprintk("Secondary interface, setup_count = %d\n",
235 setup_count);
236 } 202 }
203 if (active_count > 16) /* shouldn't actually happen... */
204 active_count = 16;
205
206 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
207 cycle_count, active_count, recovery_count);
237 208
238 /* 209 /*
239 * Convert values to internal chipset representation 210 * Convert values to internal chipset representation
240 */ 211 */
241 setup_count = (setup_count > 5) ? 0xc0 : (int) setup_counts[setup_count]; 212 recovery_count = recovery_values[recovery_count];
242 active_count &= 0xf; /* Remember, max value is 16 */ 213 active_count &= 0x0f;
243 recovery_count = (int) recovery_counts[recovery_count];
244 214
245 cmdprintk("Final values = %d,%d,%d\n", 215 /* Program the active/recovery counts into the DRWTIM register */
246 setup_count, active_count, recovery_count); 216 drwtim = (active_count << 4) | recovery_count;
247 217 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
248 /* 218 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
249 * Now that everything is ready, program the new timings
250 */
251 local_irq_save(flags);
252 /*
253 * Program the address_setup clocks into ARTTIM reg,
254 * and then the active/recovery counts into the DRWTIM reg
255 */
256 (void) pci_read_config_byte(dev, arttim_regs[channel][slave], &temp_b);
257 (void) pci_write_config_byte(dev, arttim_regs[channel][slave],
258 ((u8) setup_count) | (temp_b & 0x3f));
259 (void) pci_write_config_byte(dev, drwtim_regs[channel][slave],
260 (u8) ((active_count << 4) | recovery_count));
261 cmdprintk ("Write %x to %x\n",
262 ((u8) setup_count) | (temp_b & 0x3f),
263 arttim_regs[channel][slave]);
264 cmdprintk ("Write %x to %x\n",
265 (u8) ((active_count << 4) | recovery_count),
266 drwtim_regs[channel][slave]);
267 local_irq_restore(flags);
268} 219}
269 220
270/* 221/*
271 * This routine selects drive's best PIO mode, calculates setup/active/recovery 222 * This routine selects drive's best PIO mode and writes into the chipset
272 * counts, and then writes them into the chipset registers. 223 * registers setup/active/recovery timings.
273 */ 224 */
274static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted) 225static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted)
275{ 226{
276 int setup_time, active_time, cycle_time; 227 ide_hwif_t *hwif = HWIF(drive);
277 u8 cycle_count, setup_count, active_count, recovery_count; 228 struct pci_dev *dev = hwif->pci_dev;
278 u8 pio_mode;
279 int clock_time = 1000 / system_bus_clock();
280 ide_pio_data_t pio; 229 ide_pio_data_t pio;
281 230 u8 pio_mode, setup_count, arttim = 0;
231 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
232 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
282 pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio); 233 pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio);
283 cycle_time = pio.cycle_time;
284 234
285 setup_time = ide_pio_timings[pio_mode].setup_time; 235 cmdprintk("%s: PIO mode wanted %d, selected %d (%d ns)%s\n",
286 active_time = ide_pio_timings[pio_mode].active_time; 236 drive->name, mode_wanted, pio_mode, pio.cycle_time,
237 pio.overridden ? " (overriding vendor mode)" : "");
287 238
288 setup_count = quantize_timing( setup_time, clock_time); 239 program_cycle_times(drive, pio.cycle_time,
289 cycle_count = quantize_timing( cycle_time, clock_time); 240 ide_pio_timings[pio_mode].active_time);
290 active_count = quantize_timing(active_time, clock_time);
291 241
292 recovery_count = cycle_count - active_count; 242 setup_count = quantize_timing(ide_pio_timings[pio_mode].setup_time,
293 /* program_drive_counts() takes care of zero recovery cycles */ 243 1000 / system_bus_clock());
294 if (recovery_count > 16) { 244
295 active_count += recovery_count - 16; 245 /*
296 recovery_count = 16; 246 * The primary channel has individual address setup timing registers
247 * for each drive and the hardware selects the slowest timing itself.
248 * The secondary channel has one common register and we have to select
249 * the slowest address setup timing ourselves.
250 */
251 if (hwif->channel) {
252 ide_drive_t *drives = hwif->drives;
253
254 drive->drive_data = setup_count;
255 setup_count = max(drives[0].drive_data, drives[1].drive_data);
297 } 256 }
298 if (active_count > 16)
299 active_count = 16; /* maximum allowed by cmd64x */
300 257
301 program_drive_counts (drive, setup_count, active_count, recovery_count); 258 if (setup_count > 5) /* shouldn't actually happen... */
259 setup_count = 5;
260 cmdprintk("Final address setup count: %d\n", setup_count);
302 261
303 cmdprintk("%s: PIO mode wanted %d, selected %d (%dns)%s, " 262 /*
304 "clocks=%d/%d/%d\n", 263 * Program the address setup clocks into the ARTTIM registers.
305 drive->name, mode_wanted, pio_mode, cycle_time, 264 * Avoid clearing the secondary channel's interrupt bit.
306 pio.overridden ? " (overriding vendor mode)" : "", 265 */
307 setup_count, active_count, recovery_count); 266 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
267 if (hwif->channel)
268 arttim &= ~ARTTIM23_INTR_CH1;
269 arttim &= ~0xc0;
270 arttim |= setup_values[setup_count];
271 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
272 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
308 273
309 return pio_mode; 274 return pio_mode;
310} 275}
@@ -376,61 +341,64 @@ static u8 cmd64x_ratemask (ide_drive_t *drive)
376 return mode; 341 return mode;
377} 342}
378 343
379static int cmd64x_tune_chipset (ide_drive_t *drive, u8 xferspeed) 344static int cmd64x_tune_chipset (ide_drive_t *drive, u8 speed)
380{ 345{
381 ide_hwif_t *hwif = HWIF(drive); 346 ide_hwif_t *hwif = HWIF(drive);
382 struct pci_dev *dev = hwif->pci_dev; 347 struct pci_dev *dev = hwif->pci_dev;
348 u8 unit = drive->dn & 0x01;
349 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
383 350
384 u8 unit = (drive->select.b.unit & 0x01); 351 speed = ide_rate_filter(cmd64x_ratemask(drive), speed);
385 u8 regU = 0, pciU = (hwif->channel) ? UDIDETCR1 : UDIDETCR0;
386 u8 regD = 0, pciD = (hwif->channel) ? BMIDESR1 : BMIDESR0;
387
388 u8 speed = ide_rate_filter(cmd64x_ratemask(drive), xferspeed);
389 352
390 if (speed >= XFER_SW_DMA_0) { 353 if (speed >= XFER_SW_DMA_0) {
391 (void) pci_read_config_byte(dev, pciD, &regD);
392 (void) pci_read_config_byte(dev, pciU, &regU); 354 (void) pci_read_config_byte(dev, pciU, &regU);
393 regD &= ~(unit ? 0x40 : 0x20);
394 regU &= ~(unit ? 0xCA : 0x35); 355 regU &= ~(unit ? 0xCA : 0x35);
395 (void) pci_write_config_byte(dev, pciD, regD);
396 (void) pci_write_config_byte(dev, pciU, regU);
397 (void) pci_read_config_byte(dev, pciD, &regD);
398 (void) pci_read_config_byte(dev, pciU, &regU);
399 } 356 }
400 357
401 switch(speed) { 358 switch(speed) {
402 case XFER_UDMA_5: regU |= (unit ? 0x0A : 0x05); break; 359 case XFER_UDMA_5:
403 case XFER_UDMA_4: regU |= (unit ? 0x4A : 0x15); break; 360 regU |= unit ? 0x0A : 0x05;
404 case XFER_UDMA_3: regU |= (unit ? 0x8A : 0x25); break; 361 break;
405 case XFER_UDMA_2: regU |= (unit ? 0x42 : 0x11); break; 362 case XFER_UDMA_4:
406 case XFER_UDMA_1: regU |= (unit ? 0x82 : 0x21); break; 363 regU |= unit ? 0x4A : 0x15;
407 case XFER_UDMA_0: regU |= (unit ? 0xC2 : 0x31); break; 364 break;
408 case XFER_MW_DMA_2: regD |= (unit ? 0x40 : 0x10); break; 365 case XFER_UDMA_3:
409 case XFER_MW_DMA_1: regD |= (unit ? 0x80 : 0x20); break; 366 regU |= unit ? 0x8A : 0x25;
410 case XFER_MW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break; 367 break;
411 case XFER_SW_DMA_2: regD |= (unit ? 0x40 : 0x10); break; 368 case XFER_UDMA_2:
412 case XFER_SW_DMA_1: regD |= (unit ? 0x80 : 0x20); break; 369 regU |= unit ? 0x42 : 0x11;
413 case XFER_SW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break; 370 break;
414 case XFER_PIO_5: 371 case XFER_UDMA_1:
415 case XFER_PIO_4: 372 regU |= unit ? 0x82 : 0x21;
416 case XFER_PIO_3: 373 break;
417 case XFER_PIO_2: 374 case XFER_UDMA_0:
418 case XFER_PIO_1: 375 regU |= unit ? 0xC2 : 0x31;
419 case XFER_PIO_0: 376 break;
420 (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0); 377 case XFER_MW_DMA_2:
421 break; 378 program_cycle_times(drive, 120, 70);
422 379 break;
423 default: 380 case XFER_MW_DMA_1:
424 return 1; 381 program_cycle_times(drive, 150, 80);
382 break;
383 case XFER_MW_DMA_0:
384 program_cycle_times(drive, 480, 215);
385 break;
386 case XFER_PIO_5:
387 case XFER_PIO_4:
388 case XFER_PIO_3:
389 case XFER_PIO_2:
390 case XFER_PIO_1:
391 case XFER_PIO_0:
392 (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0);
393 break;
394 default:
395 return 1;
425 } 396 }
426 397
427 if (speed >= XFER_SW_DMA_0) { 398 if (speed >= XFER_SW_DMA_0)
428 (void) pci_write_config_byte(dev, pciU, regU); 399 (void) pci_write_config_byte(dev, pciU, regU);
429 regD |= (unit ? 0x40 : 0x20);
430 (void) pci_write_config_byte(dev, pciD, regD);
431 }
432 400
433 return (ide_config_drive_speed(drive, speed)); 401 return ide_config_drive_speed(drive, speed);
434} 402}
435 403
436static int config_chipset_for_dma (ide_drive_t *drive) 404static int config_chipset_for_dma (ide_drive_t *drive)
@@ -457,67 +425,80 @@ static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
457 return -1; 425 return -1;
458} 426}
459 427
460static int cmd64x_alt_dma_status (struct pci_dev *dev) 428static int cmd648_ide_dma_end (ide_drive_t *drive)
461{ 429{
462 switch(dev->device) { 430 ide_hwif_t *hwif = HWIF(drive);
463 case PCI_DEVICE_ID_CMD_648: 431 int err = __ide_dma_end(drive);
464 case PCI_DEVICE_ID_CMD_649: 432 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
465 return 1; 433 MRDMODE_INTR_CH0;
466 default: 434 u8 mrdmode = inb(hwif->dma_master + 0x01);
467 break; 435
468 } 436 /* clear the interrupt bit */
469 return 0; 437 outb(mrdmode | irq_mask, hwif->dma_master + 0x01);
438
439 return err;
470} 440}
471 441
472static int cmd64x_ide_dma_end (ide_drive_t *drive) 442static int cmd64x_ide_dma_end (ide_drive_t *drive)
473{ 443{
474 u8 dma_stat = 0, dma_cmd = 0;
475 ide_hwif_t *hwif = HWIF(drive); 444 ide_hwif_t *hwif = HWIF(drive);
476 struct pci_dev *dev = hwif->pci_dev; 445 struct pci_dev *dev = hwif->pci_dev;
446 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
447 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
448 CFR_INTR_CH0;
449 u8 irq_stat = 0;
450 int err = __ide_dma_end(drive);
477 451
478 drive->waiting_for_dma = 0; 452 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
479 /* read DMA command state */ 453 /* clear the interrupt bit */
480 dma_cmd = inb(hwif->dma_command); 454 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
481 /* stop DMA */ 455
482 outb(dma_cmd & ~1, hwif->dma_command); 456 return err;
483 /* get DMA status */ 457}
484 dma_stat = inb(hwif->dma_status); 458
485 /* clear the INTR & ERROR bits */ 459static int cmd648_ide_dma_test_irq (ide_drive_t *drive)
486 outb(dma_stat | 6, hwif->dma_status); 460{
487 if (cmd64x_alt_dma_status(dev)) { 461 ide_hwif_t *hwif = HWIF(drive);
488 u8 dma_intr = 0; 462 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
489 u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 : 463 MRDMODE_INTR_CH0;
490 CFR_INTR_CH0; 464 u8 dma_stat = inb(hwif->dma_status);
491 u8 dma_reg = (hwif->channel) ? ARTTIM2 : CFR; 465 u8 mrdmode = inb(hwif->dma_master + 0x01);
492 (void) pci_read_config_byte(dev, dma_reg, &dma_intr); 466
493 /* clear the INTR bit */ 467#ifdef DEBUG
494 (void) pci_write_config_byte(dev, dma_reg, dma_intr|dma_mask); 468 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
495 } 469 drive->name, dma_stat, mrdmode, irq_mask);
496 /* purge DMA mappings */ 470#endif
497 ide_destroy_dmatable(drive); 471 if (!(mrdmode & irq_mask))
498 /* verify good DMA status */ 472 return 0;
499 return (dma_stat & 7) != 4; 473
474 /* return 1 if INTR asserted */
475 if (dma_stat & 4)
476 return 1;
477
478 return 0;
500} 479}
501 480
502static int cmd64x_ide_dma_test_irq (ide_drive_t *drive) 481static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
503{ 482{
504 ide_hwif_t *hwif = HWIF(drive); 483 ide_hwif_t *hwif = HWIF(drive);
505 struct pci_dev *dev = hwif->pci_dev; 484 struct pci_dev *dev = hwif->pci_dev;
506 u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 : 485 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
507 MRDMODE_INTR_CH0; 486 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
508 u8 dma_stat = inb(hwif->dma_status); 487 CFR_INTR_CH0;
488 u8 dma_stat = inb(hwif->dma_status);
489 u8 irq_stat = 0;
490
491 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
509 492
510 (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat);
511#ifdef DEBUG 493#ifdef DEBUG
512 printk("%s: dma_stat: 0x%02x dma_alt_stat: " 494 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
513 "0x%02x mask: 0x%02x\n", drive->name, 495 drive->name, dma_stat, irq_stat, irq_mask);
514 dma_stat, dma_alt_stat, mask);
515#endif 496#endif
516 if (!(dma_alt_stat & mask)) 497 if (!(irq_stat & irq_mask))
517 return 0; 498 return 0;
518 499
519 /* return 1 if INTR asserted */ 500 /* return 1 if INTR asserted */
520 if ((dma_stat & 4) == 4) 501 if (dma_stat & 4)
521 return 1; 502 return 1;
522 503
523 return 0; 504 return 0;
@@ -665,7 +646,6 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
665 646
666 hwif->ultra_mask = 0x3f; 647 hwif->ultra_mask = 0x3f;
667 hwif->mwdma_mask = 0x07; 648 hwif->mwdma_mask = 0x07;
668 hwif->swdma_mask = 0x07;
669 649
670 if (dev->device == PCI_DEVICE_ID_CMD_643) 650 if (dev->device == PCI_DEVICE_ID_CMD_643)
671 hwif->ultra_mask = 0x80; 651 hwif->ultra_mask = 0x80;
@@ -678,17 +658,25 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
678 if (!(hwif->udma_four)) 658 if (!(hwif->udma_four))
679 hwif->udma_four = ata66_cmd64x(hwif); 659 hwif->udma_four = ata66_cmd64x(hwif);
680 660
681 if (dev->device == PCI_DEVICE_ID_CMD_646) { 661 switch(dev->device) {
662 case PCI_DEVICE_ID_CMD_648:
663 case PCI_DEVICE_ID_CMD_649:
664 alt_irq_bits:
665 hwif->ide_dma_end = &cmd648_ide_dma_end;
666 hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq;
667 break;
668 case PCI_DEVICE_ID_CMD_646:
682 hwif->chipset = ide_cmd646; 669 hwif->chipset = ide_cmd646;
683 if (class_rev == 0x01) { 670 if (class_rev == 0x01) {
684 hwif->ide_dma_end = &cmd646_1_ide_dma_end; 671 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
685 } else { 672 break;
686 hwif->ide_dma_end = &cmd64x_ide_dma_end; 673 } else if (class_rev >= 0x03)
687 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq; 674 goto alt_irq_bits;
688 } 675 /* fall thru */
689 } else { 676 default:
690 hwif->ide_dma_end = &cmd64x_ide_dma_end; 677 hwif->ide_dma_end = &cmd64x_ide_dma_end;
691 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq; 678 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
679 break;
692 } 680 }
693 681
694 682
@@ -698,42 +686,75 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
698 hwif->drives[1].autodma = hwif->autodma; 686 hwif->drives[1].autodma = hwif->autodma;
699} 687}
700 688
689static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d)
690{
691 return ide_setup_pci_device(dev, d);
692}
693
694static int __devinit init_setup_cmd646(struct pci_dev *dev, ide_pci_device_t *d)
695{
696 u8 rev = 0;
697
698 /*
699 * The original PCI0646 didn't have the primary channel enable bit,
700 * it appeared starting with PCI0646U (i.e. revision ID 3).
701 */
702 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
703 if (rev < 3)
704 d->enablebits[0].reg = 0;
705
706 return ide_setup_pci_device(dev, d);
707}
708
701static ide_pci_device_t cmd64x_chipsets[] __devinitdata = { 709static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
702 { /* 0 */ 710 { /* 0 */
703 .name = "CMD643", 711 .name = "CMD643",
712 .init_setup = init_setup_cmd64x,
704 .init_chipset = init_chipset_cmd64x, 713 .init_chipset = init_chipset_cmd64x,
705 .init_hwif = init_hwif_cmd64x, 714 .init_hwif = init_hwif_cmd64x,
706 .channels = 2, 715 .channels = 2,
707 .autodma = AUTODMA, 716 .autodma = AUTODMA,
717 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
708 .bootable = ON_BOARD, 718 .bootable = ON_BOARD,
709 },{ /* 1 */ 719 },{ /* 1 */
710 .name = "CMD646", 720 .name = "CMD646",
721 .init_setup = init_setup_cmd646,
711 .init_chipset = init_chipset_cmd64x, 722 .init_chipset = init_chipset_cmd64x,
712 .init_hwif = init_hwif_cmd64x, 723 .init_hwif = init_hwif_cmd64x,
713 .channels = 2, 724 .channels = 2,
714 .autodma = AUTODMA, 725 .autodma = AUTODMA,
715 .enablebits = {{0x00,0x00,0x00}, {0x51,0x80,0x80}}, 726 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
716 .bootable = ON_BOARD, 727 .bootable = ON_BOARD,
717 },{ /* 2 */ 728 },{ /* 2 */
718 .name = "CMD648", 729 .name = "CMD648",
730 .init_setup = init_setup_cmd64x,
719 .init_chipset = init_chipset_cmd64x, 731 .init_chipset = init_chipset_cmd64x,
720 .init_hwif = init_hwif_cmd64x, 732 .init_hwif = init_hwif_cmd64x,
721 .channels = 2, 733 .channels = 2,
722 .autodma = AUTODMA, 734 .autodma = AUTODMA,
735 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
723 .bootable = ON_BOARD, 736 .bootable = ON_BOARD,
724 },{ /* 3 */ 737 },{ /* 3 */
725 .name = "CMD649", 738 .name = "CMD649",
739 .init_setup = init_setup_cmd64x,
726 .init_chipset = init_chipset_cmd64x, 740 .init_chipset = init_chipset_cmd64x,
727 .init_hwif = init_hwif_cmd64x, 741 .init_hwif = init_hwif_cmd64x,
728 .channels = 2, 742 .channels = 2,
729 .autodma = AUTODMA, 743 .autodma = AUTODMA,
744 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
730 .bootable = ON_BOARD, 745 .bootable = ON_BOARD,
731 } 746 }
732}; 747};
733 748
749/*
750 * We may have to modify enablebits for PCI0646, so we'd better pass
751 * a local copy of the ide_pci_device_t structure down the call chain...
752 */
734static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id) 753static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
735{ 754{
736 return ide_setup_pci_device(dev, &cmd64x_chipsets[id->driver_data]); 755 ide_pci_device_t d = cmd64x_chipsets[id->driver_data];
756
757 return d.init_setup(dev, &d);
737} 758}
738 759
739static struct pci_device_id cmd64x_pci_tbl[] = { 760static struct pci_device_id cmd64x_pci_tbl[] = {
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index ab6fa271aeb3..cf9d344d19f8 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/hpt366.c Version 1.02 Apr 18, 2007 2 * linux/drivers/ide/pci/hpt366.c Version 1.03 May 4, 2007
3 * 3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
@@ -1527,7 +1527,12 @@ static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1527 if (rev > 2) 1527 if (rev > 2)
1528 goto init_single; 1528 goto init_single;
1529 1529
1530 /*
1531 * HPT36x chips are single channel and
1532 * do not seem to have the channel enable bit...
1533 */
1530 d->channels = 1; 1534 d->channels = 1;
1535 d->enablebits[0].reg = 0;
1531 1536
1532 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) { 1537 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1533 u8 pin1 = 0, pin2 = 0; 1538 u8 pin1 = 0, pin2 = 0;
diff --git a/drivers/ide/pci/it821x.c b/drivers/ide/pci/it821x.c
index a132767f7d90..4e1254813ee0 100644
--- a/drivers/ide/pci/it821x.c
+++ b/drivers/ide/pci/it821x.c
@@ -1,8 +1,9 @@
1 1
2/* 2/*
3 * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004 3 * linux/drivers/ide/pci/it821x.c Version 0.10 Mar 10 2007
4 * 4 *
5 * Copyright (C) 2004 Red Hat <alan@redhat.com> 5 * Copyright (C) 2004 Red Hat <alan@redhat.com>
6 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * 7 *
7 * May be copied or modified under the terms of the GNU General Public License 8 * May be copied or modified under the terms of the GNU General Public License
8 * Based in part on the ITE vendor provided SCSI driver. 9 * Based in part on the ITE vendor provided SCSI driver.
@@ -104,6 +105,7 @@ static int it8212_noraid;
104/** 105/**
105 * it821x_program - program the PIO/MWDMA registers 106 * it821x_program - program the PIO/MWDMA registers
106 * @drive: drive to tune 107 * @drive: drive to tune
108 * @timing: timing info
107 * 109 *
108 * Program the PIO/MWDMA timing for this channel according to the 110 * Program the PIO/MWDMA timing for this channel according to the
109 * current clock. 111 * current clock.
@@ -127,6 +129,7 @@ static void it821x_program(ide_drive_t *drive, u16 timing)
127/** 129/**
128 * it821x_program_udma - program the UDMA registers 130 * it821x_program_udma - program the UDMA registers
129 * @drive: drive to tune 131 * @drive: drive to tune
132 * @timing: timing info
130 * 133 *
131 * Program the UDMA timing for this drive according to the 134 * Program the UDMA timing for this drive according to the
132 * current clock. 135 * current clock.
@@ -153,10 +156,9 @@ static void it821x_program_udma(ide_drive_t *drive, u16 timing)
153 } 156 }
154} 157}
155 158
156
157/** 159/**
158 * it821x_clock_strategy 160 * it821x_clock_strategy
159 * @hwif: hardware interface 161 * @drive: drive to set up
160 * 162 *
161 * Select between the 50 and 66Mhz base clocks to get the best 163 * Select between the 50 and 66Mhz base clocks to get the best
162 * results for this interface. 164 * results for this interface.
@@ -182,8 +184,11 @@ static void it821x_clock_strategy(ide_drive_t *drive)
182 altclock = itdev->want[0][1]; 184 altclock = itdev->want[0][1];
183 } 185 }
184 186
185 /* Master doesn't care does the slave ? */ 187 /*
186 if(clock == ATA_ANY) 188 * if both clocks can be used for the mode with the higher priority
189 * use the clock needed by the mode with the lower priority
190 */
191 if (clock == ATA_ANY)
187 clock = altclock; 192 clock = altclock;
188 193
189 /* Nobody cares - keep the same clock */ 194 /* Nobody cares - keep the same clock */
@@ -240,37 +245,56 @@ static u8 it821x_ratemask (ide_drive_t *drive)
240} 245}
241 246
242/** 247/**
243 * it821x_tuneproc - tune a drive 248 * it821x_tunepio - tune a drive
244 * @drive: drive to tune 249 * @drive: drive to tune
245 * @mode_wanted: the target operating mode 250 * @pio: the desired PIO mode
246 *
247 * Load the timing settings for this device mode into the
248 * controller. By the time we are called the mode has been
249 * modified as neccessary to handle the absence of seperate
250 * master/slave timers for MWDMA/PIO.
251 * 251 *
252 * This code is only used in pass through mode. 252 * Try to tune the drive/host to the desired PIO mode taking into
253 * the consideration the maximum PIO mode supported by the other
254 * device on the cable.
253 */ 255 */
254 256
255static void it821x_tuneproc (ide_drive_t *drive, byte mode_wanted) 257static int it821x_tunepio(ide_drive_t *drive, u8 set_pio)
256{ 258{
257 ide_hwif_t *hwif = drive->hwif; 259 ide_hwif_t *hwif = drive->hwif;
258 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 260 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
259 int unit = drive->select.b.unit; 261 int unit = drive->select.b.unit;
262 ide_drive_t *pair = &hwif->drives[1 - unit];
260 263
261 /* Spec says 89 ref driver uses 88 */ 264 /* Spec says 89 ref driver uses 88 */
262 static u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 }; 265 static u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
263 static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY }; 266 static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
264 267
265 if(itdev->smart) 268 /*
266 return; 269 * Compute the best PIO mode we can for a given device. We must
270 * pick a speed that does not cause problems with the other device
271 * on the cable.
272 */
273 if (pair) {
274 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4, NULL);
275 /* trim PIO to the slowest of the master/slave */
276 if (pair_pio < set_pio)
277 set_pio = pair_pio;
278 }
279
280 if (itdev->smart)
281 goto set_drive_speed;
267 282
268 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */ 283 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
269 itdev->want[unit][1] = pio_want[mode_wanted]; 284 itdev->want[unit][1] = pio_want[set_pio];
270 itdev->want[unit][0] = 1; /* PIO is lowest priority */ 285 itdev->want[unit][0] = 1; /* PIO is lowest priority */
271 itdev->pio[unit] = pio[mode_wanted]; 286 itdev->pio[unit] = pio[set_pio];
272 it821x_clock_strategy(drive); 287 it821x_clock_strategy(drive);
273 it821x_program(drive, itdev->pio[unit]); 288 it821x_program(drive, itdev->pio[unit]);
289
290set_drive_speed:
291 return ide_config_drive_speed(drive, XFER_PIO_0 + set_pio);
292}
293
294static void it821x_tuneproc(ide_drive_t *drive, u8 pio)
295{
296 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
297 (void)it821x_tunepio(drive, pio);
274} 298}
275 299
276/** 300/**
@@ -354,40 +378,6 @@ static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted)
354} 378}
355 379
356/** 380/**
357 * config_it821x_chipset_for_pio - set drive timings
358 * @drive: drive to tune
359 * @speed we want
360 *
361 * Compute the best pio mode we can for a given device. We must
362 * pick a speed that does not cause problems with the other device
363 * on the cable.
364 */
365
366static void config_it821x_chipset_for_pio (ide_drive_t *drive, byte set_speed)
367{
368 u8 unit = drive->select.b.unit;
369 ide_hwif_t *hwif = drive->hwif;
370 ide_drive_t *pair = &hwif->drives[1-unit];
371 u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
372 u8 pair_pio;
373
374 /* We have to deal with this mess in pairs */
375 if(pair != NULL) {
376 pair_pio = ide_get_best_pio_mode(pair, 255, 5, NULL);
377 /* Trim PIO to the slowest of the master/slave */
378 if(pair_pio < set_pio)
379 set_pio = pair_pio;
380 }
381 it821x_tuneproc(drive, set_pio);
382 speed = XFER_PIO_0 + set_pio;
383 /* XXX - We trim to the lowest of the pair so the other drive
384 will always be fine at this point until we do hotplug passthru */
385
386 if (set_speed)
387 (void) ide_config_drive_speed(drive, speed);
388}
389
390/**
391 * it821x_dma_read - DMA hook 381 * it821x_dma_read - DMA hook
392 * @drive: drive for DMA 382 * @drive: drive for DMA
393 * 383 *
@@ -450,15 +440,17 @@ static int it821x_tune_chipset (ide_drive_t *drive, byte xferspeed)
450 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 440 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
451 u8 speed = ide_rate_filter(it821x_ratemask(drive), xferspeed); 441 u8 speed = ide_rate_filter(it821x_ratemask(drive), xferspeed);
452 442
453 if(!itdev->smart) { 443 switch (speed) {
454 switch(speed) { 444 case XFER_PIO_4:
455 case XFER_PIO_4: 445 case XFER_PIO_3:
456 case XFER_PIO_3: 446 case XFER_PIO_2:
457 case XFER_PIO_2: 447 case XFER_PIO_1:
458 case XFER_PIO_1: 448 case XFER_PIO_0:
459 case XFER_PIO_0: 449 return it821x_tunepio(drive, speed - XFER_PIO_0);
460 it821x_tuneproc(drive, (speed - XFER_PIO_0)); 450 }
461 break; 451
452 if (itdev->smart == 0) {
453 switch (speed) {
462 /* MWDMA tuning is really hard because our MWDMA and PIO 454 /* MWDMA tuning is really hard because our MWDMA and PIO
463 timings are kept in the same place. We can switch in the 455 timings are kept in the same place. We can switch in the
464 host dma on/off callbacks */ 456 host dma on/off callbacks */
@@ -498,14 +490,12 @@ static int config_chipset_for_dma (ide_drive_t *drive)
498{ 490{
499 u8 speed = ide_dma_speed(drive, it821x_ratemask(drive)); 491 u8 speed = ide_dma_speed(drive, it821x_ratemask(drive));
500 492
501 if (speed) { 493 if (speed == 0)
502 config_it821x_chipset_for_pio(drive, 0); 494 return 0;
503 it821x_tune_chipset(drive, speed);
504 495
505 return ide_dma_enable(drive); 496 it821x_tune_chipset(drive, speed);
506 }
507 497
508 return 0; 498 return ide_dma_enable(drive);
509} 499}
510 500
511/** 501/**
@@ -523,7 +513,7 @@ static int it821x_config_drive_for_dma (ide_drive_t *drive)
523 if (ide_use_dma(drive) && config_chipset_for_dma(drive)) 513 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
524 return 0; 514 return 0;
525 515
526 config_it821x_chipset_for_pio(drive, 1); 516 it821x_tuneproc(drive, 255);
527 517
528 return -1; 518 return -1;
529} 519}
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
index ae20fb3f6cbc..2cdd629c653d 100644
--- a/drivers/ide/pci/pdc202xx_new.c
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -255,9 +255,6 @@ static int config_chipset_for_dma(ide_drive_t *drive)
255 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name); 255 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
256 } 256 }
257 257
258 if (drive->media != ide_disk && drive->media != ide_cdrom)
259 return 0;
260
261 if (id->capability & 4) { 258 if (id->capability & 4) {
262 /* 259 /*
263 * Set IORDY_EN & PREFETCH_EN (this seems to have 260 * Set IORDY_EN & PREFETCH_EN (this seems to have
diff --git a/drivers/ide/pci/siimage.c b/drivers/ide/pci/siimage.c
index 71eccdf5f817..c0188de3cc66 100644
--- a/drivers/ide/pci/siimage.c
+++ b/drivers/ide/pci/siimage.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/siimage.c Version 1.11 Jan 27, 2007 2 * linux/drivers/ide/pci/siimage.c Version 1.12 Mar 10 2007
3 * 3 *
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com> 5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
@@ -287,11 +287,6 @@ static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
287 (void) ide_config_drive_speed(drive, speed); 287 (void) ide_config_drive_speed(drive, speed);
288} 288}
289 289
290static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
291{
292 config_siimage_chipset_for_pio(drive, set_speed);
293}
294
295/** 290/**
296 * siimage_tune_chipset - set controller timings 291 * siimage_tune_chipset - set controller timings
297 * @drive: Drive to set up 292 * @drive: Drive to set up
@@ -396,8 +391,6 @@ static int config_chipset_for_dma (ide_drive_t *drive)
396{ 391{
397 u8 speed = ide_dma_speed(drive, siimage_ratemask(drive)); 392 u8 speed = ide_dma_speed(drive, siimage_ratemask(drive));
398 393
399 config_chipset_for_pio(drive, !speed);
400
401 if (!speed) 394 if (!speed)
402 return 0; 395 return 0;
403 396
@@ -423,7 +416,7 @@ static int siimage_config_drive_for_dma (ide_drive_t *drive)
423 return 0; 416 return 0;
424 417
425 if (ide_use_fast_pio(drive)) 418 if (ide_use_fast_pio(drive))
426 config_chipset_for_pio(drive, 1); 419 config_siimage_chipset_for_pio(drive, 1);
427 420
428 return -1; 421 return -1;
429} 422}
@@ -1015,7 +1008,6 @@ static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
1015 1008
1016 hwif->ultra_mask = 0x7f; 1009 hwif->ultra_mask = 0x7f;
1017 hwif->mwdma_mask = 0x07; 1010 hwif->mwdma_mask = 0x07;
1018 hwif->swdma_mask = 0x07;
1019 1011
1020 if (!is_sata(hwif)) 1012 if (!is_sata(hwif))
1021 hwif->atapi_dma = 1; 1013 hwif->atapi_dma = 1;
diff --git a/drivers/ide/pci/sl82c105.c b/drivers/ide/pci/sl82c105.c
index 3a8a76fc78c7..fe3b4b91f854 100644
--- a/drivers/ide/pci/sl82c105.c
+++ b/drivers/ide/pci/sl82c105.c
@@ -11,6 +11,8 @@
11 * Merge in Russell's HW workarounds, fix various problems 11 * Merge in Russell's HW workarounds, fix various problems
12 * with the timing registers setup. 12 * with the timing registers setup.
13 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org 13 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
14 *
15 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
14 */ 16 */
15 17
16#include <linux/types.h> 18#include <linux/types.h>
@@ -47,25 +49,19 @@
47#define CTRL_P0EN (1 << 0) 49#define CTRL_P0EN (1 << 0)
48 50
49/* 51/*
50 * Convert a PIO mode and cycle time to the required on/off 52 * Convert a PIO mode and cycle time to the required on/off times
51 * times for the interface. This has protection against run-away 53 * for the interface. This has protection against runaway timings.
52 * timings.
53 */ 54 */
54static unsigned int get_timing_sl82c105(ide_pio_data_t *p) 55static unsigned int get_pio_timings(ide_pio_data_t *p)
55{ 56{
56 unsigned int cmd_on; 57 unsigned int cmd_on, cmd_off;
57 unsigned int cmd_off;
58 58
59 cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30; 59 cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
60 cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30; 60 cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30;
61 61
62 if (cmd_on > 32)
63 cmd_on = 32;
64 if (cmd_on == 0) 62 if (cmd_on == 0)
65 cmd_on = 1; 63 cmd_on = 1;
66 64
67 if (cmd_off > 32)
68 cmd_off = 32;
69 if (cmd_off == 0) 65 if (cmd_off == 0)
70 cmd_off = 1; 66 cmd_off = 1;
71 67
@@ -73,100 +69,59 @@ static unsigned int get_timing_sl82c105(ide_pio_data_t *p)
73} 69}
74 70
75/* 71/*
76 * Configure the drive and chipset for PIO 72 * Configure the chipset for PIO mode.
77 */ 73 */
78static void config_for_pio(ide_drive_t *drive, int pio, int report, int chipset_only) 74static u8 sl82c105_tune_pio(ide_drive_t *drive, u8 pio)
79{ 75{
80 ide_hwif_t *hwif = HWIF(drive); 76 struct pci_dev *dev = HWIF(drive)->pci_dev;
81 struct pci_dev *dev = hwif->pci_dev; 77 int reg = 0x44 + drive->dn * 4;
82 ide_pio_data_t p; 78 ide_pio_data_t p;
83 u16 drv_ctrl = 0x909; 79 u16 drv_ctrl;
84 unsigned int xfer_mode, reg;
85 80
86 DBG(("config_for_pio(drive:%s, pio:%d, report:%d, chipset_only:%d)\n", 81 DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive->name, pio));
87 drive->name, pio, report, chipset_only));
88
89 reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
90 82
91 pio = ide_get_best_pio_mode(drive, pio, 5, &p); 83 pio = ide_get_best_pio_mode(drive, pio, 5, &p);
92 84
93 xfer_mode = XFER_PIO_0 + pio; 85 drive->drive_data = drv_ctrl = get_pio_timings(&p);
94
95 if (chipset_only || ide_config_drive_speed(drive, xfer_mode) == 0) {
96 drv_ctrl = get_timing_sl82c105(&p);
97 drive->pio_speed = xfer_mode;
98 } else
99 drive->pio_speed = XFER_PIO_0;
100 86
101 if (drive->using_dma == 0) { 87 if (!drive->using_dma) {
102 /* 88 /*
103 * If we are actually using MW DMA, then we can not 89 * If we are actually using MW DMA, then we can not
104 * reprogram the interface drive control register. 90 * reprogram the interface drive control register.
105 */ 91 */
106 pci_write_config_word(dev, reg, drv_ctrl); 92 pci_write_config_word(dev, reg, drv_ctrl);
107 pci_read_config_word(dev, reg, &drv_ctrl); 93 pci_read_config_word (dev, reg, &drv_ctrl);
108
109 if (report) {
110 printk("%s: selected %s (%dns) (%04X)\n", drive->name,
111 ide_xfer_verbose(xfer_mode), p.cycle_time, drv_ctrl);
112 }
113 } 94 }
95
96 printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
97 ide_xfer_verbose(pio + XFER_PIO_0), p.cycle_time, drv_ctrl);
98
99 return pio;
114} 100}
115 101
116/* 102/*
117 * Configure the drive and the chipset for DMA 103 * Configure the drive for DMA.
104 * We'll program the chipset only when DMA is actually turned on.
118 */ 105 */
119static int config_for_dma (ide_drive_t *drive) 106static int config_for_dma(ide_drive_t *drive)
120{ 107{
121 ide_hwif_t *hwif = HWIF(drive);
122 struct pci_dev *dev = hwif->pci_dev;
123 unsigned int reg;
124
125 DBG(("config_for_dma(drive:%s)\n", drive->name)); 108 DBG(("config_for_dma(drive:%s)\n", drive->name));
126 109
127 reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
128
129 if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0) 110 if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0)
130 return 1; 111 return 0;
131 112
132 pci_write_config_word(dev, reg, 0x0240); 113 return ide_dma_enable(drive);
133
134 return 0;
135} 114}
136 115
137/* 116/*
138 * Check to see if the drive and 117 * Check to see if the drive and chipset are capable of DMA mode.
139 * chipset is capable of DMA mode
140 */ 118 */
141 119static int sl82c105_ide_dma_check(ide_drive_t *drive)
142static int sl82c105_check_drive (ide_drive_t *drive)
143{ 120{
144 ide_hwif_t *hwif = HWIF(drive); 121 DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive->name));
145
146 DBG(("sl82c105_check_drive(drive:%s)\n", drive->name));
147
148 do {
149 struct hd_driveid *id = drive->id;
150
151 if (!drive->autodma)
152 break;
153
154 if (!id || !(id->capability & 1))
155 break;
156 122
157 /* Consult the list of known "bad" drives */ 123 if (ide_use_dma(drive) && config_for_dma(drive))
158 if (__ide_dma_bad_drive(drive)) 124 return 0;
159 break;
160
161 if (id->field_valid & 2) {
162 if ((id->dma_mword & hwif->mwdma_mask) ||
163 (id->dma_1word & hwif->swdma_mask))
164 return 0;
165 }
166
167 if (__ide_dma_good_drive(drive) && id->eide_dma_time < 150)
168 return 0;
169 } while (0);
170 125
171 return -1; 126 return -1;
172} 127}
@@ -195,14 +150,14 @@ static inline void sl82c105_reset_host(struct pci_dev *dev)
195 * This function is called when the IDE timer expires, the drive 150 * This function is called when the IDE timer expires, the drive
196 * indicates that it is READY, and we were waiting for DMA to complete. 151 * indicates that it is READY, and we were waiting for DMA to complete.
197 */ 152 */
198static int sl82c105_ide_dma_lost_irq(ide_drive_t *drive) 153static int sl82c105_ide_dma_lostirq(ide_drive_t *drive)
199{ 154{
200 ide_hwif_t *hwif = HWIF(drive); 155 ide_hwif_t *hwif = HWIF(drive);
201 struct pci_dev *dev = hwif->pci_dev; 156 struct pci_dev *dev = hwif->pci_dev;
202 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; 157 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
203 unsigned long dma_base = hwif->dma_base; 158 u8 dma_cmd;
204 159
205 printk("sl82c105: lost IRQ: resetting host\n"); 160 printk("sl82c105: lost IRQ, resetting host\n");
206 161
207 /* 162 /*
208 * Check the raw interrupt from the drive. 163 * Check the raw interrupt from the drive.
@@ -215,15 +170,15 @@ static int sl82c105_ide_dma_lost_irq(ide_drive_t *drive)
215 * Was DMA enabled? If so, disable it - we're resetting the 170 * Was DMA enabled? If so, disable it - we're resetting the
216 * host. The IDE layer will be handling the drive for us. 171 * host. The IDE layer will be handling the drive for us.
217 */ 172 */
218 val = inb(dma_base); 173 dma_cmd = inb(hwif->dma_command);
219 if (val & 1) { 174 if (dma_cmd & 1) {
220 outb(val & ~1, dma_base); 175 outb(dma_cmd & ~1, hwif->dma_command);
221 printk("sl82c105: DMA was enabled\n"); 176 printk("sl82c105: DMA was enabled\n");
222 } 177 }
223 178
224 sl82c105_reset_host(dev); 179 sl82c105_reset_host(dev);
225 180
226 /* ide_dmaproc would return 1, so we do as well */ 181 /* __ide_dma_lostirq would return 1, so we do as well */
227 return 1; 182 return 1;
228} 183}
229 184
@@ -235,10 +190,10 @@ static int sl82c105_ide_dma_lost_irq(ide_drive_t *drive)
235 * The generic IDE core will have disabled the BMEN bit before this 190 * The generic IDE core will have disabled the BMEN bit before this
236 * function is called. 191 * function is called.
237 */ 192 */
238static void sl82c105_ide_dma_start(ide_drive_t *drive) 193static void sl82c105_dma_start(ide_drive_t *drive)
239{ 194{
240 ide_hwif_t *hwif = HWIF(drive); 195 ide_hwif_t *hwif = HWIF(drive);
241 struct pci_dev *dev = hwif->pci_dev; 196 struct pci_dev *dev = hwif->pci_dev;
242 197
243 sl82c105_reset_host(dev); 198 sl82c105_reset_host(dev);
244 ide_dma_start(drive); 199 ide_dma_start(drive);
@@ -246,8 +201,8 @@ static void sl82c105_ide_dma_start(ide_drive_t *drive)
246 201
247static int sl82c105_ide_dma_timeout(ide_drive_t *drive) 202static int sl82c105_ide_dma_timeout(ide_drive_t *drive)
248{ 203{
249 ide_hwif_t *hwif = HWIF(drive); 204 ide_hwif_t *hwif = HWIF(drive);
250 struct pci_dev *dev = hwif->pci_dev; 205 struct pci_dev *dev = hwif->pci_dev;
251 206
252 DBG(("sl82c105_ide_dma_timeout(drive:%s)\n", drive->name)); 207 DBG(("sl82c105_ide_dma_timeout(drive:%s)\n", drive->name));
253 208
@@ -255,26 +210,32 @@ static int sl82c105_ide_dma_timeout(ide_drive_t *drive)
255 return __ide_dma_timeout(drive); 210 return __ide_dma_timeout(drive);
256} 211}
257 212
258static int sl82c105_ide_dma_on (ide_drive_t *drive) 213static int sl82c105_ide_dma_on(ide_drive_t *drive)
259{ 214{
215 struct pci_dev *dev = HWIF(drive)->pci_dev;
216 int rc, reg = 0x44 + drive->dn * 4;
217
260 DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name)); 218 DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
261 219
262 if (config_for_dma(drive)) 220 rc = __ide_dma_on(drive);
263 return 1; 221 if (rc == 0) {
264 printk(KERN_INFO "%s: DMA enabled\n", drive->name); 222 pci_write_config_word(dev, reg, 0x0200);
265 return __ide_dma_on(drive); 223
224 printk(KERN_INFO "%s: DMA enabled\n", drive->name);
225 }
226 return rc;
266} 227}
267 228
268static void sl82c105_dma_off_quietly(ide_drive_t *drive) 229static void sl82c105_dma_off_quietly(ide_drive_t *drive)
269{ 230{
270 u8 speed = XFER_PIO_0; 231 struct pci_dev *dev = HWIF(drive)->pci_dev;
232 int reg = 0x44 + drive->dn * 4;
271 233
272 DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name)); 234 DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));
273 235
236 pci_write_config_word(dev, reg, drive->drive_data);
237
274 ide_dma_off_quietly(drive); 238 ide_dma_off_quietly(drive);
275 if (drive->pio_speed)
276 speed = drive->pio_speed - XFER_PIO_0;
277 config_for_pio(drive, speed, 0, 1);
278} 239}
279 240
280/* 241/*
@@ -286,8 +247,8 @@ static void sl82c105_dma_off_quietly(ide_drive_t *drive)
286 */ 247 */
287static void sl82c105_selectproc(ide_drive_t *drive) 248static void sl82c105_selectproc(ide_drive_t *drive)
288{ 249{
289 ide_hwif_t *hwif = HWIF(drive); 250 ide_hwif_t *hwif = HWIF(drive);
290 struct pci_dev *dev = hwif->pci_dev; 251 struct pci_dev *dev = hwif->pci_dev;
291 u32 val, old, mask; 252 u32 val, old, mask;
292 253
293 //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name)); 254 //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
@@ -323,18 +284,12 @@ static void sl82c105_resetproc(ide_drive_t *drive)
323 * We only deal with PIO mode here - DMA mode 'using_dma' is not 284 * We only deal with PIO mode here - DMA mode 'using_dma' is not
324 * initialised at the point that this function is called. 285 * initialised at the point that this function is called.
325 */ 286 */
326static void tune_sl82c105(ide_drive_t *drive, u8 pio) 287static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio)
327{ 288{
328 DBG(("tune_sl82c105(drive:%s)\n", drive->name)); 289 DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive->name, pio));
329
330 config_for_pio(drive, pio, 1, 0);
331 290
332 /* 291 pio = sl82c105_tune_pio(drive, pio);
333 * We support 32-bit I/O on this interface, and it 292 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
334 * doesn't have problems with interrupts.
335 */
336 drive->io_32bit = 1;
337 drive->unmask = 1;
338} 293}
339 294
340/* 295/*
@@ -393,7 +348,7 @@ static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const c
393} 348}
394 349
395/* 350/*
396 * Initialise the chip 351 * Initialise IDE channel
397 */ 352 */
398static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif) 353static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
399{ 354{
@@ -401,24 +356,22 @@ static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
401 356
402 DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index)); 357 DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
403 358
404 hwif->tuneproc = tune_sl82c105; 359 hwif->tuneproc = &sl82c105_tune_drive;
405 hwif->selectproc = sl82c105_selectproc; 360 hwif->selectproc = &sl82c105_selectproc;
406 hwif->resetproc = sl82c105_resetproc; 361 hwif->resetproc = &sl82c105_resetproc;
362
363 /*
364 * We support 32-bit I/O on this interface, and
365 * it doesn't have problems with interrupts.
366 */
367 hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1;
368 hwif->drives[0].unmask = hwif->drives[1].unmask = 1;
407 369
408 /* 370 /*
409 * Default to PIO 0 for fallback unless tuned otherwise.
410 * We always autotune PIO, this is done before DMA is checked, 371 * We always autotune PIO, this is done before DMA is checked,
411 * so there's no risk of accidentally disabling DMA 372 * so there's no risk of accidentally disabling DMA
412 */ 373 */
413 hwif->drives[0].pio_speed = XFER_PIO_0; 374 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
414 hwif->drives[0].autotune = 1;
415 hwif->drives[1].pio_speed = XFER_PIO_0;
416 hwif->drives[1].autotune = 1;
417
418 hwif->atapi_dma = 0;
419 hwif->mwdma_mask = 0;
420 hwif->swdma_mask = 0;
421 hwif->autodma = 0;
422 375
423 if (!hwif->dma_base) 376 if (!hwif->dma_base)
424 return; 377 return;
@@ -429,27 +382,27 @@ static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
429 * Never ever EVER under any circumstances enable 382 * Never ever EVER under any circumstances enable
430 * DMA when the bridge is this old. 383 * DMA when the bridge is this old.
431 */ 384 */
432 printk(" %s: Winbond 553 bridge revision %d, BM-DMA disabled\n", 385 printk(" %s: Winbond W83C553 bridge revision %d, "
433 hwif->name, rev); 386 "BM-DMA disabled\n", hwif->name, rev);
434 } else { 387 return;
435 hwif->atapi_dma = 1;
436 hwif->mwdma_mask = 0x04;
437
438 hwif->ide_dma_check = &sl82c105_check_drive;
439 hwif->ide_dma_on = &sl82c105_ide_dma_on;
440 hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
441 hwif->ide_dma_lostirq = &sl82c105_ide_dma_lost_irq;
442 hwif->dma_start = &sl82c105_ide_dma_start;
443 hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout;
444
445 if (!noautodma)
446 hwif->autodma = 1;
447 hwif->drives[0].autodma = hwif->autodma;
448 hwif->drives[1].autodma = hwif->autodma;
449
450 if (hwif->mate)
451 hwif->serialized = hwif->mate->serialized = 1;
452 } 388 }
389
390 hwif->atapi_dma = 1;
391 hwif->mwdma_mask = 0x04;
392
393 hwif->ide_dma_check = &sl82c105_ide_dma_check;
394 hwif->ide_dma_on = &sl82c105_ide_dma_on;
395 hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
396 hwif->ide_dma_lostirq = &sl82c105_ide_dma_lostirq;
397 hwif->dma_start = &sl82c105_dma_start;
398 hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout;
399
400 if (!noautodma)
401 hwif->autodma = 1;
402 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
403
404 if (hwif->mate)
405 hwif->serialized = hwif->mate->serialized = 1;
453} 406}
454 407
455static ide_pci_device_t sl82c105_chipset __devinitdata = { 408static ide_pci_device_t sl82c105_chipset __devinitdata = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 05:25:09 -0500