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path: root/drivers/ide/pci/sis5513.c
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Diffstat (limited to 'drivers/ide/pci/sis5513.c')
-rw-r--r--drivers/ide/pci/sis5513.c78
1 files changed, 45 insertions, 33 deletions
diff --git a/drivers/ide/pci/sis5513.c b/drivers/ide/pci/sis5513.c
index d90b42917775..3f35386d9cad 100644
--- a/drivers/ide/pci/sis5513.c
+++ b/drivers/ide/pci/sis5513.c
@@ -305,11 +305,52 @@ static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
305 sis_program_timings(drive, XFER_PIO_0 + pio); 305 sis_program_timings(drive, XFER_PIO_0 + pio);
306} 306}
307 307
308static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed) 308static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
309{ 309{
310 ide_hwif_t *hwif = HWIF(drive); 310 struct pci_dev *dev = drive->hwif->pci_dev;
311 struct pci_dev *dev = hwif->pci_dev; 311 u32 regdw = 0;
312 u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
313
314 pci_read_config_dword(dev, drive_pci, &regdw);
315
316 regdw |= 0x04;
317 regdw &= 0xfffff00f;
318 /* check if ATA133 enable */
319 clk = (regdw & 0x08) ? ATA_133 : ATA_100;
320 idx = mode - XFER_UDMA_0;
321 regdw |= cycle_time_value[clk][idx] << 4;
322 regdw |= cvs_time_value[clk][idx] << 8;
323
324 pci_write_config_dword(dev, drive_pci, regdw);
325}
326
327static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode)
328{
329 struct pci_dev *dev = drive->hwif->pci_dev;
330 u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family;
331
332 pci_read_config_byte(dev, drive_pci + 1, &reg);
312 333
334 /* force the UDMA bit on if we want to use UDMA */
335 reg |= 0x80;
336 /* clean reg cycle time bits */
337 reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]);
338 /* set reg cycle time bits */
339 reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i];
340
341 pci_write_config_byte(dev, drive_pci + 1, reg);
342}
343
344static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
345{
346 if (chipset_family >= ATA_133) /* ATA_133 */
347 sis_ata133_program_udma_timings(drive, mode);
348 else /* ATA_33/66/100a/100/133a */
349 sis_ata33_program_udma_timings(drive, mode);
350}
351
352static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
353{
313 /* Config chip for mode */ 354 /* Config chip for mode */
314 switch(speed) { 355 switch(speed) {
315 case XFER_UDMA_6: 356 case XFER_UDMA_6:
@@ -319,36 +360,7 @@ static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
319 case XFER_UDMA_2: 360 case XFER_UDMA_2:
320 case XFER_UDMA_1: 361 case XFER_UDMA_1:
321 case XFER_UDMA_0: 362 case XFER_UDMA_0:
322 if (chipset_family >= ATA_133) { 363 sis_program_udma_timings(drive, speed);
323 u32 regdw = 0;
324 u8 drive_pci = sis_ata133_get_base(drive);
325
326 pci_read_config_dword(dev, drive_pci, &regdw);
327 regdw |= 0x04;
328 regdw &= 0xfffff00f;
329 /* check if ATA133 enable */
330 if (regdw & 0x08) {
331 regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4;
332 regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8;
333 } else {
334 regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4;
335 regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8;
336 }
337 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
338 } else {
339 u8 drive_pci = 0x40 + drive->dn * 2, reg = 0;
340
341 pci_read_config_byte(dev, drive_pci+1, &reg);
342 /* Force the UDMA bit on if we want to use UDMA */
343 reg |= 0x80;
344 /* clean reg cycle time bits */
345 reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family]))
346 << cycle_time_offset[chipset_family]);
347 /* set reg cycle time bits */
348 reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0]
349 << cycle_time_offset[chipset_family];
350 pci_write_config_byte(dev, drive_pci+1, reg);
351 }
352 break; 364 break;
353 case XFER_MW_DMA_2: 365 case XFER_MW_DMA_2:
354 case XFER_MW_DMA_1: 366 case XFER_MW_DMA_1: