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path: root/drivers/ide/pci/sis5513.c
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Diffstat (limited to 'drivers/ide/pci/sis5513.c')
-rw-r--r--drivers/ide/pci/sis5513.c198
1 files changed, 98 insertions, 100 deletions
diff --git a/drivers/ide/pci/sis5513.c b/drivers/ide/pci/sis5513.c
index e29c90f045d5..65ee2ccabed6 100644
--- a/drivers/ide/pci/sis5513.c
+++ b/drivers/ide/pci/sis5513.c
@@ -59,10 +59,10 @@
59#define ATA_16 0x01 59#define ATA_16 0x01
60#define ATA_33 0x02 60#define ATA_33 0x02
61#define ATA_66 0x03 61#define ATA_66 0x03
62#define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout 62#define ATA_100a 0x04 /* SiS730/SiS550 is ATA100 with ATA66 layout */
63#define ATA_100 0x05 63#define ATA_100 0x05
64#define ATA_133a 0x06 // SiS961b with 133 support 64#define ATA_133a 0x06 /* SiS961b with 133 support */
65#define ATA_133 0x07 // SiS962/963 65#define ATA_133 0x07 /* SiS962/963 */
66 66
67static u8 chipset_family; 67static u8 chipset_family;
68 68
@@ -111,69 +111,70 @@ static const struct {
111 Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */ 111 Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
112 112
113/* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */ 113/* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
114static u8 cycle_time_offset[] = {0,0,5,4,4,0,0}; 114static u8 cycle_time_offset[] = { 0, 0, 5, 4, 4, 0, 0 };
115static u8 cycle_time_range[] = {0,0,2,3,3,4,4}; 115static u8 cycle_time_range[] = { 0, 0, 2, 3, 3, 4, 4 };
116static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = { 116static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
117 {0,0,0,0,0,0,0}, /* no udma */ 117 { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
118 {0,0,0,0,0,0,0}, /* no udma */ 118 { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
119 {3,2,1,0,0,0,0}, /* ATA_33 */ 119 { 3, 2, 1, 0, 0, 0, 0 }, /* ATA_33 */
120 {7,5,3,2,1,0,0}, /* ATA_66 */ 120 { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_66 */
121 {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */ 121 { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_100a (730 specific),
122 {11,7,5,4,2,1,0}, /* ATA_100 */ 122 different cycle_time range and offset */
123 {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */ 123 { 11, 7, 5, 4, 2, 1, 0 }, /* ATA_100 */
124 {15,10,7,5,3,2,1}, /* ATA_133 */ 124 { 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133a (earliest 691 southbridges) */
125 { 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133 */
125}; 126};
126/* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133 127/* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
127 See SiS962 data sheet for more detail */ 128 See SiS962 data sheet for more detail */
128static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = { 129static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
129 {0,0,0,0,0,0,0}, /* no udma */ 130 { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
130 {0,0,0,0,0,0,0}, /* no udma */ 131 { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
131 {2,1,1,0,0,0,0}, 132 { 2, 1, 1, 0, 0, 0, 0 },
132 {4,3,2,1,0,0,0}, 133 { 4, 3, 2, 1, 0, 0, 0 },
133 {4,3,2,1,0,0,0}, 134 { 4, 3, 2, 1, 0, 0, 0 },
134 {6,4,3,1,1,1,0}, 135 { 6, 4, 3, 1, 1, 1, 0 },
135 {9,6,4,2,2,2,2}, 136 { 9, 6, 4, 2, 2, 2, 2 },
136 {9,6,4,2,2,2,2}, 137 { 9, 6, 4, 2, 2, 2, 2 },
137}; 138};
138/* Initialize time, Active time, Recovery time vary across 139/* Initialize time, Active time, Recovery time vary across
139 IDE clock settings. These 3 arrays hold the register value 140 IDE clock settings. These 3 arrays hold the register value
140 for PIO0/1/2/3/4 and DMA0/1/2 mode in order */ 141 for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
141static u8 ini_time_value[][8] = { 142static u8 ini_time_value[][8] = {
142 {0,0,0,0,0,0,0,0}, 143 { 0, 0, 0, 0, 0, 0, 0, 0 },
143 {0,0,0,0,0,0,0,0}, 144 { 0, 0, 0, 0, 0, 0, 0, 0 },
144 {2,1,0,0,0,1,0,0}, 145 { 2, 1, 0, 0, 0, 1, 0, 0 },
145 {4,3,1,1,1,3,1,1}, 146 { 4, 3, 1, 1, 1, 3, 1, 1 },
146 {4,3,1,1,1,3,1,1}, 147 { 4, 3, 1, 1, 1, 3, 1, 1 },
147 {6,4,2,2,2,4,2,2}, 148 { 6, 4, 2, 2, 2, 4, 2, 2 },
148 {9,6,3,3,3,6,3,3}, 149 { 9, 6, 3, 3, 3, 6, 3, 3 },
149 {9,6,3,3,3,6,3,3}, 150 { 9, 6, 3, 3, 3, 6, 3, 3 },
150}; 151};
151static u8 act_time_value[][8] = { 152static u8 act_time_value[][8] = {
152 {0,0,0,0,0,0,0,0}, 153 { 0, 0, 0, 0, 0, 0, 0, 0 },
153 {0,0,0,0,0,0,0,0}, 154 { 0, 0, 0, 0, 0, 0, 0, 0 },
154 {9,9,9,2,2,7,2,2}, 155 { 9, 9, 9, 2, 2, 7, 2, 2 },
155 {19,19,19,5,4,14,5,4}, 156 { 19, 19, 19, 5, 4, 14, 5, 4 },
156 {19,19,19,5,4,14,5,4}, 157 { 19, 19, 19, 5, 4, 14, 5, 4 },
157 {28,28,28,7,6,21,7,6}, 158 { 28, 28, 28, 7, 6, 21, 7, 6 },
158 {38,38,38,10,9,28,10,9}, 159 { 38, 38, 38, 10, 9, 28, 10, 9 },
159 {38,38,38,10,9,28,10,9}, 160 { 38, 38, 38, 10, 9, 28, 10, 9 },
160}; 161};
161static u8 rco_time_value[][8] = { 162static u8 rco_time_value[][8] = {
162 {0,0,0,0,0,0,0,0}, 163 { 0, 0, 0, 0, 0, 0, 0, 0 },
163 {0,0,0,0,0,0,0,0}, 164 { 0, 0, 0, 0, 0, 0, 0, 0 },
164 {9,2,0,2,0,7,1,1}, 165 { 9, 2, 0, 2, 0, 7, 1, 1 },
165 {19,5,1,5,2,16,3,2}, 166 { 19, 5, 1, 5, 2, 16, 3, 2 },
166 {19,5,1,5,2,16,3,2}, 167 { 19, 5, 1, 5, 2, 16, 3, 2 },
167 {30,9,3,9,4,25,6,4}, 168 { 30, 9, 3, 9, 4, 25, 6, 4 },
168 {40,12,4,12,5,34,12,5}, 169 { 40, 12, 4, 12, 5, 34, 12, 5 },
169 {40,12,4,12,5,34,12,5}, 170 { 40, 12, 4, 12, 5, 34, 12, 5 },
170}; 171};
171 172
172/* 173/*
173 * Printing configuration 174 * Printing configuration
174 */ 175 */
175/* Used for chipset type printing at boot time */ 176/* Used for chipset type printing at boot time */
176static char* chipset_capability[] = { 177static char *chipset_capability[] = {
177 "ATA", "ATA 16", 178 "ATA", "ATA 16",
178 "ATA 33", "ATA 66", 179 "ATA 33", "ATA 66",
179 "ATA 100 (1st gen)", "ATA 100 (2nd gen)", 180 "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
@@ -272,7 +273,7 @@ static void sis_program_timings(ide_drive_t *drive, const u8 mode)
272 sis_ata133_program_timings(drive, mode); 273 sis_ata133_program_timings(drive, mode);
273} 274}
274 275
275static void config_drive_art_rwp (ide_drive_t *drive) 276static void config_drive_art_rwp(ide_drive_t *drive)
276{ 277{
277 ide_hwif_t *hwif = HWIF(drive); 278 ide_hwif_t *hwif = HWIF(drive);
278 struct pci_dev *dev = to_pci_dev(hwif->dev); 279 struct pci_dev *dev = to_pci_dev(hwif->dev);
@@ -359,7 +360,8 @@ static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)
359} 360}
360 361
361/* Chip detection and general config */ 362/* Chip detection and general config */
362static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name) 363static unsigned int __devinit init_chipset_sis5513(struct pci_dev *dev,
364 const char *name)
363{ 365{
364 struct pci_dev *host; 366 struct pci_dev *host;
365 int i = 0; 367 int i = 0;
@@ -381,7 +383,7 @@ static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const c
381 chipset_family = ATA_100a; 383 chipset_family = ATA_100a;
382 } 384 }
383 pci_dev_put(host); 385 pci_dev_put(host);
384 386
385 printk(KERN_INFO "SIS5513: %s %s controller\n", 387 printk(KERN_INFO "SIS5513: %s %s controller\n",
386 SiSHostChipInfo[i].name, chipset_capability[chipset_family]); 388 SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
387 } 389 }
@@ -448,55 +450,51 @@ static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const c
448 2/ tell old chips to allow per drive IDE timings */ 450 2/ tell old chips to allow per drive IDE timings */
449 451
450 { 452 {
451 u8 reg; 453 u8 reg;
452 u16 regw; 454 u16 regw;
453 455
454 switch(chipset_family) { 456 switch (chipset_family) {
455 case ATA_133: 457 case ATA_133:
456 /* SiS962 operation mode */ 458 /* SiS962 operation mode */
457 pci_read_config_word(dev, 0x50, &regw); 459 pci_read_config_word(dev, 0x50, &regw);
458 if (regw & 0x08) 460 if (regw & 0x08)
459 pci_write_config_word(dev, 0x50, regw&0xfff7); 461 pci_write_config_word(dev, 0x50, regw&0xfff7);
460 pci_read_config_word(dev, 0x52, &regw); 462 pci_read_config_word(dev, 0x52, &regw);
461 if (regw & 0x08) 463 if (regw & 0x08)
462 pci_write_config_word(dev, 0x52, regw&0xfff7); 464 pci_write_config_word(dev, 0x52, regw&0xfff7);
463 break; 465 break;
464 case ATA_133a: 466 case ATA_133a:
465 case ATA_100: 467 case ATA_100:
466 /* Fixup latency */ 468 /* Fixup latency */
467 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80); 469 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
468 /* Set compatibility bit */ 470 /* Set compatibility bit */
469 pci_read_config_byte(dev, 0x49, &reg); 471 pci_read_config_byte(dev, 0x49, &reg);
470 if (!(reg & 0x01)) { 472 if (!(reg & 0x01))
471 pci_write_config_byte(dev, 0x49, reg|0x01); 473 pci_write_config_byte(dev, 0x49, reg|0x01);
472 } 474 break;
473 break; 475 case ATA_100a:
474 case ATA_100a: 476 case ATA_66:
475 case ATA_66: 477 /* Fixup latency */
476 /* Fixup latency */ 478 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
477 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10); 479
478 480 /* On ATA_66 chips the bit was elsewhere */
479 /* On ATA_66 chips the bit was elsewhere */ 481 pci_read_config_byte(dev, 0x52, &reg);
480 pci_read_config_byte(dev, 0x52, &reg); 482 if (!(reg & 0x04))
481 if (!(reg & 0x04)) { 483 pci_write_config_byte(dev, 0x52, reg|0x04);
482 pci_write_config_byte(dev, 0x52, reg|0x04); 484 break;
483 } 485 case ATA_33:
484 break; 486 /* On ATA_33 we didn't have a single bit to set */
485 case ATA_33: 487 pci_read_config_byte(dev, 0x09, &reg);
486 /* On ATA_33 we didn't have a single bit to set */ 488 if ((reg & 0x0f) != 0x00)
487 pci_read_config_byte(dev, 0x09, &reg); 489 pci_write_config_byte(dev, 0x09, reg&0xf0);
488 if ((reg & 0x0f) != 0x00) { 490 case ATA_16:
489 pci_write_config_byte(dev, 0x09, reg&0xf0); 491 /* force per drive recovery and active timings
490 } 492 needed on ATA_33 and below chips */
491 case ATA_16: 493 pci_read_config_byte(dev, 0x52, &reg);
492 /* force per drive recovery and active timings 494 if (!(reg & 0x08))
493 needed on ATA_33 and below chips */ 495 pci_write_config_byte(dev, 0x52, reg|0x08);
494 pci_read_config_byte(dev, 0x52, &reg); 496 break;
495 if (!(reg & 0x08)) { 497 }
496 pci_write_config_byte(dev, 0x52, reg|0x08);
497 }
498 break;
499 }
500 } 498 }
501 499
502 return 0; 500 return 0;
@@ -546,7 +544,7 @@ static u8 __devinit ata66_sis5513(ide_hwif_t *hwif)
546 return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40; 544 return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
547} 545}
548 546
549static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif) 547static void __devinit init_hwif_sis5513(ide_hwif_t *hwif)
550{ 548{
551 u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f }; 549 u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
552 550
@@ -568,7 +566,7 @@ static const struct ide_port_info sis5513_chipset __devinitdata = {
568 .name = "SIS5513", 566 .name = "SIS5513",
569 .init_chipset = init_chipset_sis5513, 567 .init_chipset = init_chipset_sis5513,
570 .init_hwif = init_hwif_sis5513, 568 .init_hwif = init_hwif_sis5513,
571 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 569 .enablebits = { {0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04} },
572 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA, 570 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA,
573 .pio_mask = ATA_PIO4, 571 .pio_mask = ATA_PIO4,
574 .mwdma_mask = ATA_MWDMA2, 572 .mwdma_mask = ATA_MWDMA2,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 10:48:32 -0500