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path: root/drivers/ide/pci/sis5513.c
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Diffstat (limited to 'drivers/ide/pci/sis5513.c')
-rw-r--r--drivers/ide/pci/sis5513.c462
1 files changed, 92 insertions, 370 deletions
diff --git a/drivers/ide/pci/sis5513.c b/drivers/ide/pci/sis5513.c
index b375ee53d66d..5a54e2e20b3c 100644
--- a/drivers/ide/pci/sis5513.c
+++ b/drivers/ide/pci/sis5513.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/sis5513.c Version 0.27 Jul 14, 2007 2 * linux/drivers/ide/pci/sis5513.c Version 0.31 Aug 9, 2007
3 * 3 *
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer 5 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
@@ -65,8 +65,6 @@
65 65
66#include "ide-timing.h" 66#include "ide-timing.h"
67 67
68#define DISPLAY_SIS_TIMINGS
69
70/* registers layout and init values are chipset family dependant */ 68/* registers layout and init values are chipset family dependant */
71 69
72#define ATA_16 0x01 70#define ATA_16 0x01
@@ -193,362 +191,124 @@ static char* chipset_capability[] = {
193 "ATA 133 (1st gen)", "ATA 133 (2nd gen)" 191 "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
194}; 192};
195 193
196#if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS) 194/*
197#include <linux/stat.h> 195 * Configuration functions
198#include <linux/proc_fs.h> 196 */
199
200static u8 sis_proc = 0;
201
202static struct pci_dev *bmide_dev;
203
204static char* cable_type[] = {
205 "80 pins",
206 "40 pins"
207};
208 197
209static char* recovery_time[] ={ 198static u8 sis_ata133_get_base(ide_drive_t *drive)
210 "12 PCICLK", "1 PCICLK", 199{
211 "2 PCICLK", "3 PCICLK", 200 struct pci_dev *dev = drive->hwif->pci_dev;
212 "4 PCICLK", "5 PCICLCK", 201 u32 reg54 = 0;
213 "6 PCICLK", "7 PCICLCK",
214 "8 PCICLK", "9 PCICLCK",
215 "10 PCICLK", "11 PCICLK",
216 "13 PCICLK", "14 PCICLK",
217 "15 PCICLK", "15 PCICLK"
218};
219 202
220static char* active_time[] = { 203 pci_read_config_dword(dev, 0x54, &reg54);
221 "8 PCICLK", "1 PCICLCK",
222 "2 PCICLK", "3 PCICLK",
223 "4 PCICLK", "5 PCICLK",
224 "6 PCICLK", "12 PCICLK"
225};
226 204
227static char* cycle_time[] = { 205 return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
228 "Reserved", "2 CLK", 206}
229 "3 CLK", "4 CLK",
230 "5 CLK", "6 CLK",
231 "7 CLK", "8 CLK",
232 "9 CLK", "10 CLK",
233 "11 CLK", "12 CLK",
234 "13 CLK", "14 CLK",
235 "15 CLK", "16 CLK"
236};
237 207
238/* Generic add master or slave info function */ 208static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode)
239static char* get_drives_info (char *buffer, u8 pos)
240{ 209{
241 u8 reg00, reg01, reg10, reg11; /* timing registers */ 210 struct pci_dev *dev = drive->hwif->pci_dev;
242 u32 regdw0, regdw1; 211 u16 t1 = 0;
243 char* p = buffer; 212 u8 drive_pci = 0x40 + drive->dn * 2;
244
245/* Postwrite/Prefetch */
246 if (chipset_family < ATA_133) {
247 pci_read_config_byte(bmide_dev, 0x4b, &reg00);
248 p += sprintf(p, "Drive %d: Postwrite %s \t \t Postwrite %s\n",
249 pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled",
250 (reg00 & (0x40 << pos)) ? "Enabled" : "Disabled");
251 p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
252 (reg00 & (0x01 << pos)) ? "Enabled" : "Disabled",
253 (reg00 & (0x04 << pos)) ? "Enabled" : "Disabled");
254 pci_read_config_byte(bmide_dev, 0x40+2*pos, &reg00);
255 pci_read_config_byte(bmide_dev, 0x41+2*pos, &reg01);
256 pci_read_config_byte(bmide_dev, 0x44+2*pos, &reg10);
257 pci_read_config_byte(bmide_dev, 0x45+2*pos, &reg11);
258 } else {
259 u32 reg54h;
260 u8 drive_pci = 0x40;
261 pci_read_config_dword(bmide_dev, 0x54, &reg54h);
262 if (reg54h & 0x40000000) {
263 // Configuration space remapped to 0x70
264 drive_pci = 0x70;
265 }
266 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos, &regdw0);
267 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos+8, &regdw1);
268 213
269 p += sprintf(p, "Drive %d:\n", pos); 214 const u16 pio_timings[] = { 0x000, 0x607, 0x404, 0x303, 0x301 };
270 } 215 const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 };
271 216
217 pci_read_config_word(dev, drive_pci, &t1);
272 218
273/* UDMA */ 219 /* clear active/recovery timings */
274 if (chipset_family >= ATA_133) { 220 t1 &= ~0x070f;
275 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n", 221 if (mode >= XFER_MW_DMA_0) {
276 (regdw0 & 0x04) ? "Enabled" : "Disabled", 222 if (chipset_family > ATA_16)
277 (regdw1 & 0x04) ? "Enabled" : "Disabled"); 223 t1 &= ~0x8000; /* disable UDMA */
278 p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n", 224 t1 |= mwdma_timings[mode - XFER_MW_DMA_0];
279 cycle_time[(regdw0 & 0xF0) >> 4], 225 } else
280 cycle_time[(regdw1 & 0xF0) >> 4]); 226 t1 |= pio_timings[mode - XFER_PIO_0];
281 } else if (chipset_family >= ATA_33) {
282 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
283 (reg01 & 0x80) ? "Enabled" : "Disabled",
284 (reg11 & 0x80) ? "Enabled" : "Disabled");
285
286 p += sprintf(p, " UDMA Cycle Time ");
287 switch(chipset_family) {
288 case ATA_33: p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break;
289 case ATA_66:
290 case ATA_100a: p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break;
291 case ATA_100:
292 case ATA_133a: p += sprintf(p, cycle_time[reg01 & 0x0F]); break;
293 default: p += sprintf(p, "?"); break;
294 }
295 p += sprintf(p, " \t UDMA Cycle Time ");
296 switch(chipset_family) {
297 case ATA_33: p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break;
298 case ATA_66:
299 case ATA_100a: p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break;
300 case ATA_100:
301 case ATA_133a: p += sprintf(p, cycle_time[reg11 & 0x0F]); break;
302 default: p += sprintf(p, "?"); break;
303 }
304 p += sprintf(p, "\n");
305 }
306 227
228 pci_write_config_word(dev, drive_pci, t1);
229}
307 230
308 if (chipset_family < ATA_133) { /* else case TODO */ 231static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode)
232{
233 struct pci_dev *dev = drive->hwif->pci_dev;
234 u8 t1, drive_pci = 0x40 + drive->dn * 2;
309 235
310/* Data Active */ 236 /* timing bits: 7:4 active 3:0 recovery */
311 p += sprintf(p, " Data Active Time "); 237 const u8 pio_timings[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
312 switch(chipset_family) { 238 const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 };
313 case ATA_16: /* confirmed */
314 case ATA_33:
315 case ATA_66:
316 case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break;
317 case ATA_100:
318 case ATA_133a: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break;
319 default: p += sprintf(p, "?"); break;
320 }
321 p += sprintf(p, " \t Data Active Time ");
322 switch(chipset_family) {
323 case ATA_16:
324 case ATA_33:
325 case ATA_66:
326 case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break;
327 case ATA_100:
328 case ATA_133a: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break;
329 default: p += sprintf(p, "?"); break;
330 }
331 p += sprintf(p, "\n");
332 239
333/* Data Recovery */ 240 if (mode >= XFER_MW_DMA_0) {
334 /* warning: may need (reg&0x07) for pre ATA66 chips */ 241 u8 t2 = 0;
335 p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
336 recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]);
337 }
338 242
339 return p; 243 pci_read_config_byte(dev, drive_pci, &t2);
340} 244 t2 &= ~0x80; /* disable UDMA */
245 pci_write_config_byte(dev, drive_pci, t2);
341 246
342static char* get_masters_info(char* buffer) 247 t1 = mwdma_timings[mode - XFER_MW_DMA_0];
343{ 248 } else
344 return get_drives_info(buffer, 0); 249 t1 = pio_timings[mode - XFER_PIO_0];
345}
346 250
347static char* get_slaves_info(char* buffer) 251 pci_write_config_byte(dev, drive_pci + 1, t1);
348{
349 return get_drives_info(buffer, 1);
350} 252}
351 253
352/* Main get_info, called on /proc/ide/sis reads */ 254static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode)
353static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
354{ 255{
355 char *p = buffer; 256 struct pci_dev *dev = drive->hwif->pci_dev;
356 int len; 257 u32 t1 = 0;
357 u8 reg; 258 u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
358 u16 reg2, reg3;
359
360 p += sprintf(p, "\nSiS 5513 ");
361 switch(chipset_family) {
362 case ATA_16: p += sprintf(p, "DMA 16"); break;
363 case ATA_33: p += sprintf(p, "Ultra 33"); break;
364 case ATA_66: p += sprintf(p, "Ultra 66"); break;
365 case ATA_100a:
366 case ATA_100: p += sprintf(p, "Ultra 100"); break;
367 case ATA_133a:
368 case ATA_133: p += sprintf(p, "Ultra 133"); break;
369 default: p+= sprintf(p, "Unknown???"); break;
370 }
371 p += sprintf(p, " chipset\n");
372 p += sprintf(p, "--------------- Primary Channel "
373 "---------------- Secondary Channel "
374 "-------------\n");
375
376/* Status */
377 pci_read_config_byte(bmide_dev, 0x4a, &reg);
378 if (chipset_family == ATA_133) {
379 pci_read_config_word(bmide_dev, 0x50, &reg2);
380 pci_read_config_word(bmide_dev, 0x52, &reg3);
381 }
382 p += sprintf(p, "Channel Status: ");
383 if (chipset_family < ATA_66) {
384 p += sprintf(p, "%s \t \t \t \t %s\n",
385 (reg & 0x04) ? "On" : "Off",
386 (reg & 0x02) ? "On" : "Off");
387 } else if (chipset_family < ATA_133) {
388 p += sprintf(p, "%s \t \t \t \t %s \n",
389 (reg & 0x02) ? "On" : "Off",
390 (reg & 0x04) ? "On" : "Off");
391 } else { /* ATA_133 */
392 p += sprintf(p, "%s \t \t \t \t %s \n",
393 (reg2 & 0x02) ? "On" : "Off",
394 (reg3 & 0x02) ? "On" : "Off");
395 }
396
397/* Operation Mode */
398 pci_read_config_byte(bmide_dev, 0x09, &reg);
399 p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
400 (reg & 0x01) ? "Native" : "Compatible",
401 (reg & 0x04) ? "Native" : "Compatible");
402 259
403/* 80-pin cable ? */ 260 pci_read_config_dword(dev, drive_pci, &t1);
404 if (chipset_family >= ATA_133) {
405 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
406 (reg2 & 0x01) ? cable_type[1] : cable_type[0],
407 (reg3 & 0x01) ? cable_type[1] : cable_type[0]);
408 } else if (chipset_family > ATA_33) {
409 pci_read_config_byte(bmide_dev, 0x48, &reg);
410 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
411 (reg & 0x10) ? cable_type[1] : cable_type[0],
412 (reg & 0x20) ? cable_type[1] : cable_type[0]);
413 }
414 261
415/* Prefetch Count */ 262 t1 &= 0xc0c00fff;
416 if (chipset_family < ATA_133) { 263 clk = (t1 & 0x08) ? ATA_133 : ATA_100;
417 pci_read_config_word(bmide_dev, 0x4c, &reg2); 264 if (mode >= XFER_MW_DMA_0) {
418 pci_read_config_word(bmide_dev, 0x4e, &reg3); 265 t1 &= ~0x04; /* disable UDMA */
419 p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n", 266 idx = mode - XFER_MW_DMA_0 + 5;
420 reg2, reg3);
421 } 267 }
268 idx = mode - XFER_PIO_0;
269 t1 |= ini_time_value[clk][idx] << 12;
270 t1 |= act_time_value[clk][idx] << 16;
271 t1 |= rco_time_value[clk][idx] << 24;
422 272
423 p = get_masters_info(p); 273 pci_write_config_dword(dev, drive_pci, t1);
424 p = get_slaves_info(p); 274}
425
426 len = (p - buffer) - offset;
427 *addr = buffer + offset;
428 275
429 return len > count ? count : len; 276static void sis_program_timings(ide_drive_t *drive, const u8 mode)
277{
278 if (chipset_family < ATA_100) /* ATA_16/33/66/100a */
279 sis_ata16_program_timings(drive, mode);
280 else if (chipset_family < ATA_133) /* ATA_100/133a */
281 sis_ata100_program_timings(drive, mode);
282 else /* ATA_133 */
283 sis_ata133_program_timings(drive, mode);
430} 284}
431#endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
432 285
433/*
434 * Configuration functions
435 */
436/* Enables per-drive prefetch and postwrite */
437static void config_drive_art_rwp (ide_drive_t *drive) 286static void config_drive_art_rwp (ide_drive_t *drive)
438{ 287{
439 ide_hwif_t *hwif = HWIF(drive); 288 ide_hwif_t *hwif = HWIF(drive);
440 struct pci_dev *dev = hwif->pci_dev; 289 struct pci_dev *dev = hwif->pci_dev;
441
442 u8 reg4bh = 0; 290 u8 reg4bh = 0;
443 u8 rw_prefetch = (0x11 << drive->dn); 291 u8 rw_prefetch = 0;
444 292
445 if (drive->media != ide_disk)
446 return;
447 pci_read_config_byte(dev, 0x4b, &reg4bh); 293 pci_read_config_byte(dev, 0x4b, &reg4bh);
448 294
449 if ((reg4bh & rw_prefetch) != rw_prefetch) 295 if (drive->media == ide_disk)
296 rw_prefetch = 0x11 << drive->dn;
297
298 if ((reg4bh & (0x11 << drive->dn)) != rw_prefetch)
450 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch); 299 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
451} 300}
452 301
453/* Set per-drive active and recovery time */
454static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio) 302static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
455{ 303{
456 ide_hwif_t *hwif = HWIF(drive);
457 struct pci_dev *dev = hwif->pci_dev;
458
459 u8 drive_pci, test1, test2;
460
461 config_drive_art_rwp(drive); 304 config_drive_art_rwp(drive);
462 305 sis_program_timings(drive, XFER_PIO_0 + pio);
463 /* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */
464 drive_pci = 0x40;
465 /* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */
466 if (chipset_family >= ATA_133) {
467 u32 reg54h;
468 pci_read_config_dword(dev, 0x54, &reg54h);
469 if (reg54h & 0x40000000) drive_pci = 0x70;
470 drive_pci += ((drive->dn)*0x4);
471 } else {
472 drive_pci += ((drive->dn)*0x2);
473 }
474
475 /* register layout changed with newer ATA100 chips */
476 if (chipset_family < ATA_100) {
477 pci_read_config_byte(dev, drive_pci, &test1);
478 pci_read_config_byte(dev, drive_pci+1, &test2);
479
480 /* Clear active and recovery timings */
481 test1 &= ~0x0F;
482 test2 &= ~0x07;
483
484 switch(pio) {
485 case 4: test1 |= 0x01; test2 |= 0x03; break;
486 case 3: test1 |= 0x03; test2 |= 0x03; break;
487 case 2: test1 |= 0x04; test2 |= 0x04; break;
488 case 1: test1 |= 0x07; test2 |= 0x06; break;
489 case 0: /* PIO0: register setting == X000 */
490 default: break;
491 }
492 pci_write_config_byte(dev, drive_pci, test1);
493 pci_write_config_byte(dev, drive_pci+1, test2);
494 } else if (chipset_family < ATA_133) {
495 switch(pio) { /* active recovery
496 v v */
497 case 4: test1 = 0x30|0x01; break;
498 case 3: test1 = 0x30|0x03; break;
499 case 2: test1 = 0x40|0x04; break;
500 case 1: test1 = 0x60|0x07; break;
501 case 0: test1 = 0x00; break;
502 default: break;
503 }
504 pci_write_config_byte(dev, drive_pci, test1);
505 } else { /* ATA_133 */
506 u32 test3;
507 pci_read_config_dword(dev, drive_pci, &test3);
508 test3 &= 0xc0c00fff;
509 if (test3 & 0x08) {
510 test3 |= ini_time_value[ATA_133][pio] << 12;
511 test3 |= act_time_value[ATA_133][pio] << 16;
512 test3 |= rco_time_value[ATA_133][pio] << 24;
513 } else {
514 test3 |= ini_time_value[ATA_100][pio] << 12;
515 test3 |= act_time_value[ATA_100][pio] << 16;
516 test3 |= rco_time_value[ATA_100][pio] << 24;
517 }
518 pci_write_config_dword(dev, drive_pci, test3);
519 }
520} 306}
521 307
522static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed) 308static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
523{ 309{
524 ide_hwif_t *hwif = HWIF(drive); 310 ide_hwif_t *hwif = HWIF(drive);
525 struct pci_dev *dev = hwif->pci_dev; 311 struct pci_dev *dev = hwif->pci_dev;
526 u32 regdw;
527 u8 drive_pci, reg;
528
529 /* See sis_set_pio_mode() for drive PCI config registers */
530 drive_pci = 0x40;
531 if (chipset_family >= ATA_133) {
532 u32 reg54h;
533 pci_read_config_dword(dev, 0x54, &reg54h);
534 if (reg54h & 0x40000000) drive_pci = 0x70;
535 drive_pci += ((drive->dn)*0x4);
536 pci_read_config_dword(dev, (unsigned long)drive_pci, &regdw);
537 /* Disable UDMA bit for non UDMA modes on UDMA chips */
538 if (speed < XFER_UDMA_0) {
539 regdw &= 0xfffffffb;
540 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
541 }
542
543 } else {
544 drive_pci += ((drive->dn)*0x2);
545 pci_read_config_byte(dev, drive_pci+1, &reg);
546 /* Disable UDMA bit for non UDMA modes on UDMA chips */
547 if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) {
548 reg &= 0x7F;
549 pci_write_config_byte(dev, drive_pci+1, reg);
550 }
551 }
552 312
553 /* Config chip for mode */ 313 /* Config chip for mode */
554 switch(speed) { 314 switch(speed) {
@@ -560,6 +320,10 @@ static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
560 case XFER_UDMA_1: 320 case XFER_UDMA_1:
561 case XFER_UDMA_0: 321 case XFER_UDMA_0:
562 if (chipset_family >= ATA_133) { 322 if (chipset_family >= ATA_133) {
323 u32 regdw = 0;
324 u8 drive_pci = sis_ata133_get_base(drive);
325
326 pci_read_config_dword(dev, drive_pci, &regdw);
563 regdw |= 0x04; 327 regdw |= 0x04;
564 regdw &= 0xfffff00f; 328 regdw &= 0xfffff00f;
565 /* check if ATA133 enable */ 329 /* check if ATA133 enable */
@@ -572,6 +336,9 @@ static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
572 } 336 }
573 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw); 337 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
574 } else { 338 } else {
339 u8 drive_pci = 0x40 + drive->dn * 2, reg = 0;
340
341 pci_read_config_byte(dev, drive_pci+1, &reg);
575 /* Force the UDMA bit on if we want to use UDMA */ 342 /* Force the UDMA bit on if we want to use UDMA */
576 reg |= 0x80; 343 reg |= 0x80;
577 /* clean reg cycle time bits */ 344 /* clean reg cycle time bits */
@@ -586,9 +353,7 @@ static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
586 case XFER_MW_DMA_2: 353 case XFER_MW_DMA_2:
587 case XFER_MW_DMA_1: 354 case XFER_MW_DMA_1:
588 case XFER_MW_DMA_0: 355 case XFER_MW_DMA_0:
589 case XFER_SW_DMA_2: 356 sis_program_timings(drive, speed);
590 case XFER_SW_DMA_1:
591 case XFER_SW_DMA_0:
592 break; 357 break;
593 default: 358 default:
594 BUG(); 359 BUG();
@@ -596,32 +361,12 @@ static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
596 } 361 }
597} 362}
598 363
599static int sis5513_config_xfer_rate(ide_drive_t *drive)
600{
601 /*
602 * TODO: always set PIO mode and remove this
603 */
604 ide_set_max_pio(drive);
605
606 drive->init_speed = 0;
607
608 if (ide_tune_dma(drive))
609 return 0;
610
611 if (ide_use_fast_pio(drive))
612 ide_set_max_pio(drive);
613
614 return -1;
615}
616
617static u8 sis5513_ata133_udma_filter(ide_drive_t *drive) 364static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)
618{ 365{
619 struct pci_dev *dev = drive->hwif->pci_dev; 366 struct pci_dev *dev = drive->hwif->pci_dev;
620 int drive_pci; 367 u32 regdw = 0;
621 u32 reg54 = 0, regdw = 0; 368 u8 drive_pci = sis_ata133_get_base(drive);
622 369
623 pci_read_config_dword(dev, 0x54, &reg54);
624 drive_pci = ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
625 pci_read_config_dword(dev, drive_pci, &regdw); 370 pci_read_config_dword(dev, drive_pci, &regdw);
626 371
627 /* if ATA133 disable, we should not set speed above UDMA5 */ 372 /* if ATA133 disable, we should not set speed above UDMA5 */
@@ -767,14 +512,6 @@ static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const c
767 } 512 }
768 break; 513 break;
769 } 514 }
770
771#if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
772 if (!sis_proc) {
773 sis_proc = 1;
774 bmide_dev = dev;
775 ide_pci_create_host_proc("sis", sis_get_info);
776 }
777#endif
778 } 515 }
779 516
780 return 0; 517 return 0;
@@ -827,8 +564,6 @@ static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
827{ 564{
828 u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f }; 565 u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
829 566
830 hwif->autodma = 0;
831
832 if (!hwif->irq) 567 if (!hwif->irq)
833 hwif->irq = hwif->channel ? 15 : 14; 568 hwif->irq = hwif->channel ? 15 : 14;
834 569
@@ -838,32 +573,19 @@ static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
838 if (chipset_family >= ATA_133) 573 if (chipset_family >= ATA_133)
839 hwif->udma_filter = sis5513_ata133_udma_filter; 574 hwif->udma_filter = sis5513_ata133_udma_filter;
840 575
841 if (!(hwif->dma_base)) { 576 hwif->drives[0].autotune = 1;
842 hwif->drives[0].autotune = 1; 577 hwif->drives[1].autotune = 1;
843 hwif->drives[1].autotune = 1; 578
579 if (hwif->dma_base == 0)
844 return; 580 return;
845 }
846 581
847 hwif->atapi_dma = 1; 582 hwif->atapi_dma = 1;
848 583
849 hwif->ultra_mask = udma_rates[chipset_family]; 584 hwif->ultra_mask = udma_rates[chipset_family];
850 hwif->mwdma_mask = 0x07; 585 hwif->mwdma_mask = 0x07;
851 hwif->swdma_mask = 0x07;
852
853 if (!chipset_family)
854 return;
855 586
856 if (hwif->cbl != ATA_CBL_PATA40_SHORT) 587 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
857 hwif->cbl = ata66_sis5513(hwif); 588 hwif->cbl = ata66_sis5513(hwif);
858
859 if (chipset_family > ATA_16) {
860 hwif->ide_dma_check = &sis5513_config_xfer_rate;
861 if (!noautodma)
862 hwif->autodma = 1;
863 }
864 hwif->drives[0].autodma = hwif->autodma;
865 hwif->drives[1].autodma = hwif->autodma;
866 return;
867} 589}
868 590
869static ide_pci_device_t sis5513_chipset __devinitdata = { 591static ide_pci_device_t sis5513_chipset __devinitdata = {
@@ -881,10 +603,10 @@ static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_devi
881 return ide_setup_pci_device(dev, &sis5513_chipset); 603 return ide_setup_pci_device(dev, &sis5513_chipset);
882} 604}
883 605
884static struct pci_device_id sis5513_pci_tbl[] = { 606static const struct pci_device_id sis5513_pci_tbl[] = {
885 { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 607 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5513), 0 },
886 { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5518, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 608 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5518), 0 },
887 { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_1180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 609 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_1180), 0 },
888 { 0, }, 610 { 0, },
889}; 611};
890MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl); 612MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 20:43:31 -0500