1 files changed, 260 insertions, 304 deletions

diff --git a/drivers/ide/pci/siimage.c b/drivers/ide/pci/siimage.c
index 1fffea3211bd..4cf8fc54aa2a 100644
--- a/drivers/ide/pci/siimage.c
+++ b/drivers/ide/pci/siimage.c
@@ -1,8 +1,8 @@
 /*
  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
  * Copyright (C) 2003           Red Hat <alan@redhat.com>
- * Copyright (C) 2007           MontaVista Software, Inc.
- * Copyright (C) 2007           Bartlomiej Zolnierkiewicz
+ * Copyright (C) 2007-2008      MontaVista Software, Inc.
+ * Copyright (C) 2007-2008      Bartlomiej Zolnierkiewicz
  *
  *  May be copied or modified under the terms of the GNU General Public License
  *
@@ -17,10 +17,10 @@
  *
  *  FAQ Items:
  *      If you are using Marvell SATA-IDE adapters with Maxtor drives
- *      ensure the system is set up for ATA100/UDMA5 not UDMA6.
+ *      ensure the system is set up for ATA100/UDMA5, not UDMA6.
  *
  *      If you are using WD drives with SATA bridges you must set the
- *      drive to "Single". "Master" will hang
+ *      drive to "Single". "Master" will hang.
  *
  *      If you have strange problems with nVidia chipset systems please
  *      see the SI support documentation and update your system BIOS
@@ -42,25 +42,24 @@
 #include <linux/hdreg.h>
 #include <linux/ide.h>
 #include <linux/init.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
 
 /**
  *      pdev_is_sata            -       check if device is SATA
  *      @pdev:  PCI device to check
- *      
+ *
  *      Returns true if this is a SATA controller
  */
- 
+
 static int pdev_is_sata(struct pci_dev *pdev)
 {
 #ifdef CONFIG_BLK_DEV_IDE_SATA
-        switch(pdev->device) {
-                case PCI_DEVICE_ID_SII_3112:
-                case PCI_DEVICE_ID_SII_1210SA:
-                        return 1;
-                case PCI_DEVICE_ID_SII_680:
-                        return 0;
+        switch (pdev->device) {
+        case PCI_DEVICE_ID_SII_3112:
+        case PCI_DEVICE_ID_SII_1210SA:
+                return 1;
+        case PCI_DEVICE_ID_SII_680:
+                return 0;
         }
         BUG();
 #endif
@@ -70,10 +69,10 @@ static int pdev_is_sata(struct pci_dev *pdev)
 /**
  *      is_sata                 -       check if hwif is SATA
  *      @hwif:  interface to check
- *      
+ *
  *      Returns true if this is a SATA controller
  */
- 
+
 static inline int is_sata(ide_hwif_t *hwif)
 {
         return pdev_is_sata(to_pci_dev(hwif->dev));
@@ -86,21 +85,22 @@ static inline int is_sata(ide_hwif_t *hwif)
  *
  *      Turn a config register offset into the right address in either
  *      PCI space or MMIO space to access the control register in question
- *      Thankfully this is a configuration operation so isnt performance
- *      criticial. 
+ *      Thankfully this is a configuration operation, so isn't performance
+ *      critical.
  */
- 
+
 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
 {
         unsigned long base = (unsigned long)hwif->hwif_data;
+
         base += 0xA0 + r;
-        if(hwif->mmio)
-                base += (hwif->channel << 6);
+        if (hwif->mmio)
+                base += hwif->channel << 6;
         else
-                base += (hwif->channel << 4);
+                base += hwif->channel << 4;
         return base;
 }
-        
+
 /**
  *      siimage_seldev          -       return register base
  *      @hwif: interface
@@ -110,20 +110,69 @@ static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
  *      PCI space or MMIO space to access the control register in question
  *      including accounting for the unit shift.
  */
- 
+
 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
 {
         ide_hwif_t *hwif        = HWIF(drive);
-        unsigned long base = (unsigned long)hwif->hwif_data;
+        unsigned long base      = (unsigned long)hwif->hwif_data;
+
         base += 0xA0 + r;
-        if(hwif->mmio)
-                base += (hwif->channel << 6);
+        if (hwif->mmio)
+                base += hwif->channel << 6;
         else
-                base += (hwif->channel << 4);
+                base += hwif->channel << 4;
         base |= drive->select.b.unit << drive->select.b.unit;
         return base;
 }
 
+static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
+{
+        u8 tmp = 0;
+
+        if (pci_get_drvdata(dev))
+                tmp = readb((void __iomem *)addr);
+        else
+                pci_read_config_byte(dev, addr, &tmp);
+
+        return tmp;
+}
+
+static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
+{
+        u16 tmp = 0;
+
+        if (pci_get_drvdata(dev))
+                tmp = readw((void __iomem *)addr);
+        else
+                pci_read_config_word(dev, addr, &tmp);
+
+        return tmp;
+}
+
+static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
+{
+        if (pci_get_drvdata(dev))
+                writeb(val, (void __iomem *)addr);
+        else
+                pci_write_config_byte(dev, addr, val);
+}
+
+static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
+{
+        if (pci_get_drvdata(dev))
+                writew(val, (void __iomem *)addr);
+        else
+                pci_write_config_word(dev, addr, val);
+}
+
+static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
+{
+        if (pci_get_drvdata(dev))
+                writel(val, (void __iomem *)addr);
+        else
+                pci_write_config_dword(dev, addr, val);
+}
+
 /**
  *      sil_udma_filter         -       compute UDMA mask
  *      @drive: IDE device
@@ -136,24 +185,26 @@ static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
 
 static u8 sil_pata_udma_filter(ide_drive_t *drive)
 {
-        ide_hwif_t *hwif = drive->hwif;
-        struct pci_dev *dev = to_pci_dev(hwif->dev);
-        unsigned long base = (unsigned long) hwif->hwif_data;
-        u8 mask = 0, scsc = 0;
+        ide_hwif_t *hwif        = drive->hwif;
+        struct pci_dev *dev     = to_pci_dev(hwif->dev);
+        unsigned long base      = (unsigned long)hwif->hwif_data;
+        u8 scsc, mask           = 0;
 
-        if (hwif->mmio)
-                scsc = hwif->INB(base + 0x4A);
-        else
-                pci_read_config_byte(dev, 0x8A, &scsc);
+        scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A));
 
-        if ((scsc & 0x30) == 0x10)      /* 133 */
+        switch (scsc & 0x30) {
+        case 0x10:      /* 133 */
                 mask = ATA_UDMA6;
-        else if ((scsc & 0x30) == 0x20) /* 2xPCI */
+                break;
+        case 0x20:      /* 2xPCI */
                 mask = ATA_UDMA6;
-        else if ((scsc & 0x30) == 0x00) /* 100 */
+                break;
+        case 0x00:      /* 100 */
                 mask = ATA_UDMA5;
-        else    /* Disabled ? */
+                break;
+        default:        /* Disabled ? */
                 BUG();
+        }
 
         return mask;
 }
@@ -175,15 +226,16 @@ static u8 sil_sata_udma_filter(ide_drive_t *drive)
 
 static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
 {
-        const u16 tf_speed[]    = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
-        const u16 data_speed[]  = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
+        static const u16 tf_speed[]   = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
+        static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
 
         ide_hwif_t *hwif        = HWIF(drive);
+        struct pci_dev *dev     = to_pci_dev(hwif->dev);
         ide_drive_t *pair       = ide_get_paired_drive(drive);
         u32 speedt              = 0;
         u16 speedp              = 0;
         unsigned long addr      = siimage_seldev(drive, 0x04);
-        unsigned long tfaddr    = siimage_selreg(hwif, 0x02);
+        unsigned long tfaddr    = siimage_selreg(hwif,  0x02);
         unsigned long base      = (unsigned long)hwif->hwif_data;
         u8 tf_pio               = pio;
         u8 addr_mask            = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84)
@@ -203,36 +255,20 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
         speedp = data_speed[pio];
         speedt = tf_speed[tf_pio];
 
-        if (hwif->mmio) {
-                hwif->OUTW(speedp, addr);
-                hwif->OUTW(speedt, tfaddr);
-                /* Now set up IORDY */
-                if (pio > 2)
-                        hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
-                else
-                        hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
-
-                mode = hwif->INB(base + addr_mask);
-                mode &= ~(unit ? 0x30 : 0x03);
-                mode |= (unit ? 0x10 : 0x01);
-                hwif->OUTB(mode, base + addr_mask);
-        } else {
-                struct pci_dev *dev = to_pci_dev(hwif->dev);
-
-                pci_write_config_word(dev, addr, speedp);
-                pci_write_config_word(dev, tfaddr, speedt);
-                pci_read_config_word(dev, tfaddr - 2, &speedp);
-                speedp &= ~0x200;
-                /* Set IORDY for mode 3 or 4 */
-                if (pio > 2)
-                        speedp |= 0x200;
-                pci_write_config_word(dev, tfaddr - 2, speedp);
-
-                pci_read_config_byte(dev, addr_mask, &mode);
-                mode &= ~(unit ? 0x30 : 0x03);
-                mode |= (unit ? 0x10 : 0x01);
-                pci_write_config_byte(dev, addr_mask, mode);
-        }
+        sil_iowrite16(dev, speedp, addr);
+        sil_iowrite16(dev, speedt, tfaddr);
+
+        /* now set up IORDY */
+        speedp = sil_ioread16(dev, tfaddr - 2);
+        speedp &= ~0x200;
+        if (pio > 2)
+                speedp |= 0x200;
+        sil_iowrite16(dev, speedp, tfaddr - 2);
+
+        mode = sil_ioread8(dev, base + addr_mask);
+        mode &= ~(unit ? 0x30 : 0x03);
+        mode |= unit ? 0x10 : 0x01;
+        sil_iowrite8(dev, mode, base + addr_mask);
 }
 
 /**
@@ -245,59 +281,45 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
 
 static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
 {
-        u8 ultra6[]             = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
-        u8 ultra5[]             = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
-        u16 dma[]               = { 0x2208, 0x10C2, 0x10C1 };
+        static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
+        static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
+        static const u16 dma[]   = { 0x2208, 0x10C2, 0x10C1 };
 
         ide_hwif_t *hwif        = HWIF(drive);
         struct pci_dev *dev     = to_pci_dev(hwif->dev);
         u16 ultra = 0, multi    = 0;
         u8 mode = 0, unit       = drive->select.b.unit;
         unsigned long base      = (unsigned long)hwif->hwif_data;
-        u8 scsc = 0, addr_mask  = ((hwif->channel) ?
-                                    ((hwif->mmio) ? 0xF4 : 0x84) :
-                                    ((hwif->mmio) ? 0xB4 : 0x80));
-                                    
+        u8 scsc = 0, addr_mask  = hwif->channel ?
+                                        (hwif->mmio ? 0xF4 : 0x84) :
+                                        (hwif->mmio ? 0xB4 : 0x80);
         unsigned long ma        = siimage_seldev(drive, 0x08);
         unsigned long ua        = siimage_seldev(drive, 0x0C);
 
-        if (hwif->mmio) {
-                scsc = hwif->INB(base + 0x4A);
-                mode = hwif->INB(base + addr_mask);
-                multi = hwif->INW(ma);
-                ultra = hwif->INW(ua);
-        } else {
-                pci_read_config_byte(dev, 0x8A, &scsc);
-                pci_read_config_byte(dev, addr_mask, &mode);
-                pci_read_config_word(dev, ma, &multi);
-                pci_read_config_word(dev, ua, &ultra);
-        }
+        scsc  = sil_ioread8 (dev, base + (hwif->mmio ? 0x4A : 0x8A));
+        mode  = sil_ioread8 (dev, base + addr_mask);
+        multi = sil_ioread16(dev, ma);
+        ultra = sil_ioread16(dev, ua);
 
-        mode &= ~((unit) ? 0x30 : 0x03);
+        mode  &= ~(unit ? 0x30 : 0x03);
         ultra &= ~0x3F;
         scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
 
         scsc = is_sata(hwif) ? 1 : scsc;
 
         if (speed >= XFER_UDMA_0) {
-                multi = dma[2];
-                ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] :
-                                 ultra5[speed - XFER_UDMA_0]);
-                mode |= (unit ? 0x30 : 0x03);
+                multi  = dma[2];
+                ultra |= scsc ? ultra6[speed - XFER_UDMA_0] :
+                                ultra5[speed - XFER_UDMA_0];
+                mode  |= unit ? 0x30 : 0x03;
         } else {
                 multi = dma[speed - XFER_MW_DMA_0];
-                mode |= (unit ? 0x20 : 0x02);
+                mode |= unit ? 0x20 : 0x02;
         }
 
-        if (hwif->mmio) {
-                hwif->OUTB(mode, base + addr_mask);
-                hwif->OUTW(multi, ma);
-                hwif->OUTW(ultra, ua);
-        } else {
-                pci_write_config_byte(dev, addr_mask, mode);
-                pci_write_config_word(dev, ma, multi);
-                pci_write_config_word(dev, ua, ultra);
-        }
+        sil_iowrite8 (dev, mode, base + addr_mask);
+        sil_iowrite16(dev, multi, ma);
+        sil_iowrite16(dev, ultra, ua);
 }
 
 /* returns 1 if dma irq issued, 0 otherwise */
@@ -309,13 +331,14 @@ static int siimage_io_dma_test_irq(ide_drive_t *drive)
         unsigned long addr      = siimage_selreg(hwif, 1);
 
         /* return 1 if INTR asserted */
-        if ((hwif->INB(hwif->dma_status) & 4) == 4)
+        if (hwif->INB(hwif->dma_status) & 4)
                 return 1;
 
         /* return 1 if Device INTR asserted */
         pci_read_config_byte(dev, addr, &dma_altstat);
         if (dma_altstat & 8)
-                return 0;       //return 1;
+                return 0;       /* return 1; */
+
         return 0;
 }
 
@@ -335,9 +358,9 @@ static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
                 = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
 
         if (sata_error_addr) {
-                unsigned long base = (unsigned long)hwif->hwif_data;
-                u32 ext_stat = readl((void __iomem *)(base + 0x10));
-                u8 watchdog = 0;
+                unsigned long base      = (unsigned long)hwif->hwif_data;
+                u32 ext_stat            = readl((void __iomem *)(base + 0x10));
+                u8 watchdog             = 0;
 
                 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
                         u32 sata_error = readl(sata_error_addr);
@@ -346,25 +369,22 @@ static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
                         watchdog = (sata_error & 0x00680000) ? 1 : 0;
                         printk(KERN_WARNING "%s: sata_error = 0x%08x, "
                                 "watchdog = %d, %s\n",
-                                drive->name, sata_error, watchdog,
-                                __func__);
-
-                } else {
+                                drive->name, sata_error, watchdog, __func__);
+                } else
                         watchdog = (ext_stat & 0x8000) ? 1 : 0;
-                }
-                ext_stat >>= 16;
 
+                ext_stat >>= 16;
                 if (!(ext_stat & 0x0404) && !watchdog)
                         return 0;
         }
 
         /* return 1 if INTR asserted */
-        if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04)
+        if (readb((void __iomem *)hwif->dma_status) & 0x04)
                 return 1;
 
         /* return 1 if Device INTR asserted */
-        if ((readb((void __iomem *)addr) & 8) == 8)
-                return 0;       //return 1;
+        if (readb((void __iomem *)addr) & 8)
+                return 0;       /* return 1; */
 
         return 0;
 }
@@ -423,63 +443,33 @@ static void sil_sata_pre_reset(ide_drive_t *drive)
 }
 
 /**
- *      proc_reports_siimage            -       add siimage controller to proc
- *      @dev: PCI device
- *      @clocking: SCSC value
- *      @name: controller name
- *
- *      Report the clocking mode of the controller and add it to
- *      the /proc interface layer
- */
- 
-static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
-{
-        if (!pdev_is_sata(dev)) {
-                printk(KERN_INFO "%s: BASE CLOCK ", name);
-                clocking &= 0x03;
-                switch (clocking) {
-                        case 0x03: printk("DISABLED!\n"); break;
-                        case 0x02: printk("== 2X PCI\n"); break;
-                        case 0x01: printk("== 133\n"); break;
-                        case 0x00: printk("== 100\n"); break;
-                }
-        }
-}
-
-/**
- *      setup_mmio_siimage      -       switch an SI controller into MMIO
+ *      setup_mmio_siimage      -       switch controller into MMIO mode
  *      @dev: PCI device we are configuring
  *      @name: device name
  *
- *      Attempt to put the device into mmio mode. There are some slight
- *      complications here with certain systems where the mmio bar isnt
- *      mapped so we have to be sure we can fall back to I/O.
+ *      Attempt to put the device into MMIO mode. There are some slight
+ *      complications here with certain systems where the MMIO BAR isn't
+ *      mapped, so we have to be sure that we can fall back to I/O.
  */
- 
-static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
+
+static unsigned int setup_mmio_siimage(struct pci_dev *dev, const char *name)
 {
         resource_size_t bar5    = pci_resource_start(dev, 5);
         unsigned long barsize   = pci_resource_len(dev, 5);
-        u8 tmpbyte      = 0;
         void __iomem *ioaddr;
-        u32 tmp, irq_mask;
 
         /*
-         *      Drop back to PIO if we can't map the mmio. Some
-         *      systems seem to get terminally confused in the PCI
-         *      spaces.
+         *      Drop back to PIO if we can't map the MMIO. Some systems
+         *      seem to get terminally confused in the PCI spaces.
          */
-         
-        if(!request_mem_region(bar5, barsize, name))
-        {
-                printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
+        if (!request_mem_region(bar5, barsize, name)) {
+                printk(KERN_WARNING "siimage: IDE controller MMIO ports not "
+                                    "available.\n");
                 return 0;
         }
-                
-        ioaddr = ioremap(bar5, barsize);
 
-        if (ioaddr == NULL)
-        {
+        ioaddr = ioremap(bar5, barsize);
+        if (ioaddr == NULL) {
                 release_mem_region(bar5, barsize);
                 return 0;
         }
@@ -487,62 +477,6 @@ static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
         pci_set_master(dev);
         pci_set_drvdata(dev, (void *) ioaddr);
 
-        if (pdev_is_sata(dev)) {
-                /* make sure IDE0/1 interrupts are not masked */
-                irq_mask = (1 << 22) | (1 << 23);
-                tmp = readl(ioaddr + 0x48);
-                if (tmp & irq_mask) {
-                        tmp &= ~irq_mask;
-                        writel(tmp, ioaddr + 0x48);
-                        readl(ioaddr + 0x48); /* flush */
-                }
-                writel(0, ioaddr + 0x148);
-                writel(0, ioaddr + 0x1C8);
-        }
-
-        writeb(0, ioaddr + 0xB4);
-        writeb(0, ioaddr + 0xF4);
-        tmpbyte = readb(ioaddr + 0x4A);
-
-        switch(tmpbyte & 0x30) {
-                case 0x00:
-                        /* In 100 MHz clocking, try and switch to 133 */
-                        writeb(tmpbyte|0x10, ioaddr + 0x4A);
-                        break;
-                case 0x10:
-                        /* On 133Mhz clocking */
-                        break;
-                case 0x20:
-                        /* On PCIx2 clocking */
-                        break;
-                case 0x30:
-                        /* Clocking is disabled */
-                        /* 133 clock attempt to force it on */
-                        writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
-                        break;
-        }
-        
-        writeb(      0x72, ioaddr + 0xA1);
-        writew(    0x328A, ioaddr + 0xA2);
-        writel(0x62DD62DD, ioaddr + 0xA4);
-        writel(0x43924392, ioaddr + 0xA8);
-        writel(0x40094009, ioaddr + 0xAC);
-        writeb(      0x72, ioaddr + 0xE1);
-        writew(    0x328A, ioaddr + 0xE2);
-        writel(0x62DD62DD, ioaddr + 0xE4);
-        writel(0x43924392, ioaddr + 0xE8);
-        writel(0x40094009, ioaddr + 0xEC);
-
-        if (pdev_is_sata(dev)) {
-                writel(0xFFFF0000, ioaddr + 0x108);
-                writel(0xFFFF0000, ioaddr + 0x188);
-                writel(0x00680000, ioaddr + 0x148);
-                writel(0x00680000, ioaddr + 0x1C8);
-        }
-
-        tmpbyte = readb(ioaddr + 0x4A);
-
-        proc_reports_siimage(dev, (tmpbyte>>4), name);
         return 1;
 }
 
@@ -552,55 +486,92 @@ static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
  *      @name: device name
  *
  *      Perform the initial PCI set up for this device. Attempt to switch
- *      to 133MHz clocking if the system isn't already set up to do it.
+ *      to 133 MHz clocking if the system isn't already set up to do it.
  */
 
-static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
+static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev,
+                                                   const char *name)
 {
-        u8 rev = dev->revision, tmpbyte = 0, BA5_EN = 0;
+        unsigned long base, scsc_addr;
+        void __iomem *ioaddr = NULL;
+        u8 rev = dev->revision, tmp, BA5_EN;
 
         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
 
         pci_read_config_byte(dev, 0x8A, &BA5_EN);
-        if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
-                if (setup_mmio_siimage(dev, name)) {
-                        return 0;
+
+        if ((BA5_EN & 0x01) || pci_resource_start(dev, 5))
+                if (setup_mmio_siimage(dev, name))
+                        ioaddr = pci_get_drvdata(dev);
+
+        base = (unsigned long)ioaddr;
+
+        if (ioaddr && pdev_is_sata(dev)) {
+                u32 tmp32, irq_mask;
+
+                /* make sure IDE0/1 interrupts are not masked */
+                irq_mask = (1 << 22) | (1 << 23);
+                tmp32 = readl(ioaddr + 0x48);
+                if (tmp32 & irq_mask) {
+                        tmp32 &= ~irq_mask;
+                        writel(tmp32, ioaddr + 0x48);
+                        readl(ioaddr + 0x48); /* flush */
                 }
+                writel(0, ioaddr + 0x148);
+                writel(0, ioaddr + 0x1C8);
+        }
+
+        sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
+        sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
+
+        scsc_addr = base ? (base + 0x4A) : 0x8A;
+        tmp = sil_ioread8(dev, scsc_addr);
+
+        switch (tmp & 0x30) {
+        case 0x00:
+                /* On 100 MHz clocking, try and switch to 133 MHz */
+                sil_iowrite8(dev, tmp | 0x10, scsc_addr);
+                break;
+        case 0x30:
+                /* Clocking is disabled, attempt to force 133MHz clocking. */
+                sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
+        case 0x10:
+                /* On 133Mhz clocking. */
+                break;
+        case 0x20:
+                /* On PCIx2 clocking. */
+                break;
         }
 
-        pci_write_config_byte(dev, 0x80, 0x00);
-        pci_write_config_byte(dev, 0x84, 0x00);
-        pci_read_config_byte(dev, 0x8A, &tmpbyte);
-        switch(tmpbyte & 0x30) {
-                case 0x00:
-                        /* 133 clock attempt to force it on */
-                        pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
-                case 0x30:
-                        /* if clocking is disabled */
-                        /* 133 clock attempt to force it on */
-                        pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
-                case 0x10:
-                        /* 133 already */
-                        break;
-                case 0x20:
-                        /* BIOS set PCI x2 clocking */
-                        break;
+        tmp = sil_ioread8(dev, scsc_addr);
+
+        sil_iowrite8 (dev,       0x72, base + 0xA1);
+        sil_iowrite16(dev,     0x328A, base + 0xA2);
+        sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
+        sil_iowrite32(dev, 0x43924392, base + 0xA8);
+        sil_iowrite32(dev, 0x40094009, base + 0xAC);
+        sil_iowrite8 (dev,       0x72, base ? (base + 0xE1) : 0xB1);
+        sil_iowrite16(dev,     0x328A, base ? (base + 0xE2) : 0xB2);
+        sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
+        sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
+        sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
+
+        if (base && pdev_is_sata(dev)) {
+                writel(0xFFFF0000, ioaddr + 0x108);
+                writel(0xFFFF0000, ioaddr + 0x188);
+                writel(0x00680000, ioaddr + 0x148);
+                writel(0x00680000, ioaddr + 0x1C8);
         }
 
-        pci_read_config_byte(dev,   0x8A, &tmpbyte);
+        /* report the clocking mode of the controller */
+        if (!pdev_is_sata(dev)) {
+                static const char *clk_str[] =
+                        { "== 100", "== 133", "== 2X PCI", "DISABLED!" };
 
-        pci_write_config_byte(dev,  0xA1, 0x72);
-        pci_write_config_word(dev,  0xA2, 0x328A);
-        pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
-        pci_write_config_dword(dev, 0xA8, 0x43924392);
-        pci_write_config_dword(dev, 0xAC, 0x40094009);
-        pci_write_config_byte(dev,  0xB1, 0x72);
-        pci_write_config_word(dev,  0xB2, 0x328A);
-        pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
-        pci_write_config_dword(dev, 0xB8, 0x43924392);
-        pci_write_config_dword(dev, 0xBC, 0x40094009);
+                tmp >>= 4;
+                printk(KERN_INFO "%s: BASE CLOCK %s\n", name, clk_str[tmp & 3]);
+        }
 
-        proc_reports_siimage(dev, (tmpbyte>>4), name);
         return 0;
 }
 
@@ -610,8 +581,7 @@ static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const ch
  *
  *      The basic setup here is fairly simple, we can use standard MMIO
  *      operations. However we do have to set the taskfile register offsets
- *      by hand as there isnt a standard defined layout for them this
- *      time.
+ *      by hand as there isn't a standard defined layout for them this time.
  *
  *      The hardware supports buffered taskfiles and also some rather nice
  *      extended PRD tables. For better SI3112 support use the libata driver
@@ -622,23 +592,21 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
         struct pci_dev *dev     = to_pci_dev(hwif->dev);
         void *addr              = pci_get_drvdata(dev);
         u8 ch                   = hwif->channel;
-        hw_regs_t               hw;
-        unsigned long           base;
+        struct ide_io_ports *io_ports = &hwif->io_ports;
+        unsigned long base;
 
         /*
-         *      Fill in the basic HWIF bits
+         *      Fill in the basic hwif bits
          */
-
+        hwif->host_flags |= IDE_HFLAG_MMIO;
         default_hwif_mmiops(hwif);
-        hwif->hwif_data                 = addr;
+        hwif->hwif_data = addr;
 
         /*
-         *      Now set up the hw. We have to do this ourselves as
-         *      the MMIO layout isnt the same as the standard port
-         *      based I/O
+         *      Now set up the hw. We have to do this ourselves as the
+         *      MMIO layout isn't the same as the standard port based I/O.
          */
-
-        memset(&hw, 0, sizeof(hw_regs_t));
+        memset(io_ports, 0, sizeof(*io_ports));
 
         base = (unsigned long)addr;
         if (ch)
@@ -647,21 +615,18 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
                 base += 0x80;
 
         /*
-         *      The buffered task file doesn't have status/control
-         *      so we can't currently use it sanely since we want to
-         *      use LBA48 mode.
-         */     
-        hw.io_ports[IDE_DATA_OFFSET]    = base;
-        hw.io_ports[IDE_ERROR_OFFSET]   = base + 1;
-        hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
-        hw.io_ports[IDE_SECTOR_OFFSET]  = base + 3;
-        hw.io_ports[IDE_LCYL_OFFSET]    = base + 4;
-        hw.io_ports[IDE_HCYL_OFFSET]    = base + 5;
-        hw.io_ports[IDE_SELECT_OFFSET]  = base + 6;
-        hw.io_ports[IDE_STATUS_OFFSET]  = base + 7;
-        hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
-
-        hw.io_ports[IDE_IRQ_OFFSET]     = 0;
+         *      The buffered task file doesn't have status/control, so we
+         *      can't currently use it sanely since we want to use LBA48 mode.
+         */
+        io_ports->data_addr     = base;
+        io_ports->error_addr    = base + 1;
+        io_ports->nsect_addr    = base + 2;
+        io_ports->lbal_addr     = base + 3;
+        io_ports->lbam_addr     = base + 4;
+        io_ports->lbah_addr     = base + 5;
+        io_ports->device_addr   = base + 6;
+        io_ports->status_addr   = base + 7;
+        io_ports->ctl_addr      = base + 10;
 
         if (pdev_is_sata(dev)) {
                 base = (unsigned long)addr;
@@ -672,8 +637,6 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
                 hwif->sata_scr[SATA_CONTROL_OFFSET]     = base + 0x100;
         }
 
-        memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports));
-
         hwif->irq = dev->irq;
 
         hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
@@ -683,19 +646,17 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
 
 static int is_dev_seagate_sata(ide_drive_t *drive)
 {
-        const char *s = &drive->id->model[0];
-        unsigned len;
-
-        len = strnlen(s, sizeof(drive->id->model));
+        const char *s   = &drive->id->model[0];
+        unsigned len    = strnlen(s, sizeof(drive->id->model));
 
-        if ((len > 4) && (!memcmp(s, "ST", 2))) {
+        if ((len > 4) && (!memcmp(s, "ST", 2)))
                 if ((!memcmp(s + len - 2, "AS", 2)) ||
                     (!memcmp(s + len - 3, "ASL", 3))) {
                         printk(KERN_INFO "%s: applying pessimistic Seagate "
                                          "errata fix\n", drive->name);
                         return 1;
                 }
-        }
+
         return 0;
 }
 
@@ -712,7 +673,7 @@ static void __devinit sil_quirkproc(ide_drive_t *drive)
 {
         ide_hwif_t *hwif = drive->hwif;
 
-        /* Try and raise the rqsize */
+        /* Try and rise the rqsize */
         if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
                 hwif->rqsize = 128;
 }
@@ -746,20 +707,14 @@ static void __devinit init_iops_siimage(ide_hwif_t *hwif)
  *      sil_cable_detect        -       cable detection
  *      @hwif: interface to check
  *
- *      Check for the presence of an ATA66 capable cable on the
- *      interface.
+ *      Check for the presence of an ATA66 capable cable on the interface.
  */
 
 static u8 __devinit sil_cable_detect(ide_hwif_t *hwif)
 {
-        struct pci_dev *dev = to_pci_dev(hwif->dev);
-        unsigned long addr = siimage_selreg(hwif, 0);
-        u8 ata66 = 0;
-
-        if (pci_get_drvdata(dev) == NULL)
-                pci_read_config_byte(dev, addr, &ata66);
-        else
-                ata66 = hwif->INB(addr);
+        struct pci_dev *dev     = to_pci_dev(hwif->dev);
+        unsigned long addr      = siimage_selreg(hwif, 0);
+        u8 ata66                = sil_ioread8(dev, addr);
 
         return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 }
@@ -805,15 +760,16 @@ static const struct ide_port_info siimage_chipsets[] __devinitdata = {
 };
 
 /**
- *      siimage_init_one        -       pci layer discovery entry
+ *      siimage_init_one        -       PCI layer discovery entry
  *      @dev: PCI device
  *      @id: ident table entry
  *
- *      Called by the PCI code when it finds an SI680 or SI3112 controller.
+ *      Called by the PCI code when it finds an SiI680 or SiI3112 controller.
  *      We then use the IDE PCI generic helper to do most of the work.
  */
- 
-static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
+
+static int __devinit siimage_init_one(struct pci_dev *dev,
+                                      const struct pci_device_id *id)
 {
         struct ide_port_info d;
         u8 idx = id->driver_data;