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path: root/drivers/ide/pci/siimage.c
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Diffstat (limited to 'drivers/ide/pci/siimage.c')
-rw-r--r--drivers/ide/pci/siimage.c1133
1 files changed, 1133 insertions, 0 deletions
diff --git a/drivers/ide/pci/siimage.c b/drivers/ide/pci/siimage.c
new file mode 100644
index 000000000000..2b9961b88135
--- /dev/null
+++ b/drivers/ide/pci/siimage.c
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1/*
2 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
3 *
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
6 *
7 * May be copied or modified under the terms of the GNU General Public License
8 *
9 * Documentation available under NDA only
10 *
11 *
12 * FAQ Items:
13 * If you are using Marvell SATA-IDE adapters with Maxtor drives
14 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
15 *
16 * If you are using WD drives with SATA bridges you must set the
17 * drive to "Single". "Master" will hang
18 *
19 * If you have strange problems with nVidia chipset systems please
20 * see the SI support documentation and update your system BIOS
21 * if neccessary
22 */
23
24#include <linux/config.h>
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/delay.h>
29#include <linux/hdreg.h>
30#include <linux/ide.h>
31#include <linux/init.h>
32
33#include <asm/io.h>
34
35#undef SIIMAGE_VIRTUAL_DMAPIO
36#undef SIIMAGE_LARGE_DMA
37
38/**
39 * pdev_is_sata - check if device is SATA
40 * @pdev: PCI device to check
41 *
42 * Returns true if this is a SATA controller
43 */
44
45static int pdev_is_sata(struct pci_dev *pdev)
46{
47 switch(pdev->device)
48 {
49 case PCI_DEVICE_ID_SII_3112:
50 case PCI_DEVICE_ID_SII_1210SA:
51 return 1;
52 case PCI_DEVICE_ID_SII_680:
53 return 0;
54 }
55 BUG();
56 return 0;
57}
58
59/**
60 * is_sata - check if hwif is SATA
61 * @hwif: interface to check
62 *
63 * Returns true if this is a SATA controller
64 */
65
66static inline int is_sata(ide_hwif_t *hwif)
67{
68 return pdev_is_sata(hwif->pci_dev);
69}
70
71/**
72 * siimage_selreg - return register base
73 * @hwif: interface
74 * @r: config offset
75 *
76 * Turn a config register offset into the right address in either
77 * PCI space or MMIO space to access the control register in question
78 * Thankfully this is a configuration operation so isnt performance
79 * criticial.
80 */
81
82static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
83{
84 unsigned long base = (unsigned long)hwif->hwif_data;
85 base += 0xA0 + r;
86 if(hwif->mmio)
87 base += (hwif->channel << 6);
88 else
89 base += (hwif->channel << 4);
90 return base;
91}
92
93/**
94 * siimage_seldev - return register base
95 * @hwif: interface
96 * @r: config offset
97 *
98 * Turn a config register offset into the right address in either
99 * PCI space or MMIO space to access the control register in question
100 * including accounting for the unit shift.
101 */
102
103static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
104{
105 ide_hwif_t *hwif = HWIF(drive);
106 unsigned long base = (unsigned long)hwif->hwif_data;
107 base += 0xA0 + r;
108 if(hwif->mmio)
109 base += (hwif->channel << 6);
110 else
111 base += (hwif->channel << 4);
112 base |= drive->select.b.unit << drive->select.b.unit;
113 return base;
114}
115
116/**
117 * siimage_ratemask - Compute available modes
118 * @drive: IDE drive
119 *
120 * Compute the available speeds for the devices on the interface.
121 * For the CMD680 this depends on the clocking mode (scsc), for the
122 * SI3312 SATA controller life is a bit simpler. Enforce UDMA33
123 * as a limit if there is no 80pin cable present.
124 */
125
126static byte siimage_ratemask (ide_drive_t *drive)
127{
128 ide_hwif_t *hwif = HWIF(drive);
129 u8 mode = 0, scsc = 0;
130 unsigned long base = (unsigned long) hwif->hwif_data;
131
132 if (hwif->mmio)
133 scsc = hwif->INB(base + 0x4A);
134 else
135 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
136
137 if(is_sata(hwif))
138 {
139 if(strstr(drive->id->model, "Maxtor"))
140 return 3;
141 return 4;
142 }
143
144 if ((scsc & 0x30) == 0x10) /* 133 */
145 mode = 4;
146 else if ((scsc & 0x30) == 0x20) /* 2xPCI */
147 mode = 4;
148 else if ((scsc & 0x30) == 0x00) /* 100 */
149 mode = 3;
150 else /* Disabled ? */
151 BUG();
152
153 if (!eighty_ninty_three(drive))
154 mode = min(mode, (u8)1);
155 return mode;
156}
157
158/**
159 * siimage_taskfile_timing - turn timing data to a mode
160 * @hwif: interface to query
161 *
162 * Read the timing data for the interface and return the
163 * mode that is being used.
164 */
165
166static byte siimage_taskfile_timing (ide_hwif_t *hwif)
167{
168 u16 timing = 0x328a;
169 unsigned long addr = siimage_selreg(hwif, 2);
170
171 if (hwif->mmio)
172 timing = hwif->INW(addr);
173 else
174 pci_read_config_word(hwif->pci_dev, addr, &timing);
175
176 switch (timing) {
177 case 0x10c1: return 4;
178 case 0x10c3: return 3;
179 case 0x1104:
180 case 0x1281: return 2;
181 case 0x2283: return 1;
182 case 0x328a:
183 default: return 0;
184 }
185}
186
187/**
188 * simmage_tuneproc - tune a drive
189 * @drive: drive to tune
190 * @mode_wanted: the target operating mode
191 *
192 * Load the timing settings for this device mode into the
193 * controller. If we are in PIO mode 3 or 4 turn on IORDY
194 * monitoring (bit 9). The TF timing is bits 31:16
195 */
196
197static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted)
198{
199 ide_hwif_t *hwif = HWIF(drive);
200 u32 speedt = 0;
201 u16 speedp = 0;
202 unsigned long addr = siimage_seldev(drive, 0x04);
203 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
204
205 /* cheat for now and use the docs */
206 switch(mode_wanted) {
207 case 4:
208 speedp = 0x10c1;
209 speedt = 0x10c1;
210 break;
211 case 3:
212 speedp = 0x10C3;
213 speedt = 0x10C3;
214 break;
215 case 2:
216 speedp = 0x1104;
217 speedt = 0x1281;
218 break;
219 case 1:
220 speedp = 0x2283;
221 speedt = 0x1281;
222 break;
223 case 0:
224 default:
225 speedp = 0x328A;
226 speedt = 0x328A;
227 break;
228 }
229 if (hwif->mmio)
230 {
231 hwif->OUTW(speedt, addr);
232 hwif->OUTW(speedp, tfaddr);
233 /* Now set up IORDY */
234 if(mode_wanted == 3 || mode_wanted == 4)
235 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
236 else
237 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
238 }
239 else
240 {
241 pci_write_config_word(hwif->pci_dev, addr, speedp);
242 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
243 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
244 speedp &= ~0x200;
245 /* Set IORDY for mode 3 or 4 */
246 if(mode_wanted == 3 || mode_wanted == 4)
247 speedp |= 0x200;
248 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
249 }
250}
251
252/**
253 * config_siimage_chipset_for_pio - set drive timings
254 * @drive: drive to tune
255 * @speed we want
256 *
257 * Compute the best pio mode we can for a given device. Also honour
258 * the timings for the driver when dealing with mixed devices. Some
259 * of this is ugly but its all wrapped up here
260 *
261 * The SI680 can also do VDMA - we need to start using that
262 *
263 * FIXME: we use the BIOS channel timings to avoid driving the task
264 * files too fast at the disk. We need to compute the master/slave
265 * drive PIO mode properly so that we can up the speed on a hotplug
266 * system.
267 */
268
269static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
270{
271 u8 channel_timings = siimage_taskfile_timing(HWIF(drive));
272 u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
273
274 /* WARNING PIO timing mess is going to happen b/w devices, argh */
275 if ((channel_timings != set_pio) && (set_pio > channel_timings))
276 set_pio = channel_timings;
277
278 siimage_tuneproc(drive, set_pio);
279 speed = XFER_PIO_0 + set_pio;
280 if (set_speed)
281 (void) ide_config_drive_speed(drive, speed);
282}
283
284static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
285{
286 config_siimage_chipset_for_pio(drive, set_speed);
287}
288
289/**
290 * siimage_tune_chipset - set controller timings
291 * @drive: Drive to set up
292 * @xferspeed: speed we want to achieve
293 *
294 * Tune the SII chipset for the desired mode. If we can't achieve
295 * the desired mode then tune for a lower one, but ultimately
296 * make the thing work.
297 */
298
299static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed)
300{
301 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
302 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
303 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
304
305 ide_hwif_t *hwif = HWIF(drive);
306 u16 ultra = 0, multi = 0;
307 u8 mode = 0, unit = drive->select.b.unit;
308 u8 speed = ide_rate_filter(siimage_ratemask(drive), xferspeed);
309 unsigned long base = (unsigned long)hwif->hwif_data;
310 u8 scsc = 0, addr_mask = ((hwif->channel) ?
311 ((hwif->mmio) ? 0xF4 : 0x84) :
312 ((hwif->mmio) ? 0xB4 : 0x80));
313
314 unsigned long ma = siimage_seldev(drive, 0x08);
315 unsigned long ua = siimage_seldev(drive, 0x0C);
316
317 if (hwif->mmio) {
318 scsc = hwif->INB(base + 0x4A);
319 mode = hwif->INB(base + addr_mask);
320 multi = hwif->INW(ma);
321 ultra = hwif->INW(ua);
322 } else {
323 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
324 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
325 pci_read_config_word(hwif->pci_dev, ma, &multi);
326 pci_read_config_word(hwif->pci_dev, ua, &ultra);
327 }
328
329 mode &= ~((unit) ? 0x30 : 0x03);
330 ultra &= ~0x3F;
331 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
332
333 scsc = is_sata(hwif) ? 1 : scsc;
334
335 switch(speed) {
336 case XFER_PIO_4:
337 case XFER_PIO_3:
338 case XFER_PIO_2:
339 case XFER_PIO_1:
340 case XFER_PIO_0:
341 siimage_tuneproc(drive, (speed - XFER_PIO_0));
342 mode |= ((unit) ? 0x10 : 0x01);
343 break;
344 case XFER_MW_DMA_2:
345 case XFER_MW_DMA_1:
346 case XFER_MW_DMA_0:
347 multi = dma[speed - XFER_MW_DMA_0];
348 mode |= ((unit) ? 0x20 : 0x02);
349 config_siimage_chipset_for_pio(drive, 0);
350 break;
351 case XFER_UDMA_6:
352 case XFER_UDMA_5:
353 case XFER_UDMA_4:
354 case XFER_UDMA_3:
355 case XFER_UDMA_2:
356 case XFER_UDMA_1:
357 case XFER_UDMA_0:
358 multi = dma[2];
359 ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
360 (ultra5[speed - XFER_UDMA_0]));
361 mode |= ((unit) ? 0x30 : 0x03);
362 config_siimage_chipset_for_pio(drive, 0);
363 break;
364 default:
365 return 1;
366 }
367
368 if (hwif->mmio) {
369 hwif->OUTB(mode, base + addr_mask);
370 hwif->OUTW(multi, ma);
371 hwif->OUTW(ultra, ua);
372 } else {
373 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
374 pci_write_config_word(hwif->pci_dev, ma, multi);
375 pci_write_config_word(hwif->pci_dev, ua, ultra);
376 }
377 return (ide_config_drive_speed(drive, speed));
378}
379
380/**
381 * config_chipset_for_dma - configure for DMA
382 * @drive: drive to configure
383 *
384 * Called by the IDE layer when it wants the timings set up.
385 * For the CMD680 we also need to set up the PIO timings and
386 * enable DMA.
387 */
388
389static int config_chipset_for_dma (ide_drive_t *drive)
390{
391 u8 speed = ide_dma_speed(drive, siimage_ratemask(drive));
392
393 config_chipset_for_pio(drive, !speed);
394
395 if (!speed)
396 return 0;
397
398 if (ide_set_xfer_rate(drive, speed))
399 return 0;
400
401 if (!drive->init_speed)
402 drive->init_speed = speed;
403
404 return ide_dma_enable(drive);
405}
406
407/**
408 * siimage_configure_drive_for_dma - set up for DMA transfers
409 * @drive: drive we are going to set up
410 *
411 * Set up the drive for DMA, tune the controller and drive as
412 * required. If the drive isn't suitable for DMA or we hit
413 * other problems then we will drop down to PIO and set up
414 * PIO appropriately
415 */
416
417static int siimage_config_drive_for_dma (ide_drive_t *drive)
418{
419 ide_hwif_t *hwif = HWIF(drive);
420 struct hd_driveid *id = drive->id;
421
422 if ((id->capability & 1) != 0 && drive->autodma) {
423
424 if (ide_use_dma(drive)) {
425 if (config_chipset_for_dma(drive))
426 return hwif->ide_dma_on(drive);
427 }
428
429 goto fast_ata_pio;
430
431 } else if ((id->capability & 8) || (id->field_valid & 2)) {
432fast_ata_pio:
433 config_chipset_for_pio(drive, 1);
434 return hwif->ide_dma_off_quietly(drive);
435 }
436 /* IORDY not supported */
437 return 0;
438}
439
440/* returns 1 if dma irq issued, 0 otherwise */
441static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
442{
443 ide_hwif_t *hwif = HWIF(drive);
444 u8 dma_altstat = 0;
445 unsigned long addr = siimage_selreg(hwif, 1);
446
447 /* return 1 if INTR asserted */
448 if ((hwif->INB(hwif->dma_status) & 4) == 4)
449 return 1;
450
451 /* return 1 if Device INTR asserted */
452 pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
453 if (dma_altstat & 8)
454 return 0; //return 1;
455 return 0;
456}
457
458#if 0
459/**
460 * siimage_mmio_ide_dma_count - DMA bytes done
461 * @drive
462 *
463 * If we are doing VDMA the CMD680 requires a little bit
464 * of more careful handling and we have to read the counts
465 * off ourselves. For non VDMA life is normal.
466 */
467
468static int siimage_mmio_ide_dma_count (ide_drive_t *drive)
469{
470#ifdef SIIMAGE_VIRTUAL_DMAPIO
471 struct request *rq = HWGROUP(drive)->rq;
472 ide_hwif_t *hwif = HWIF(drive);
473 u32 count = (rq->nr_sectors * SECTOR_SIZE);
474 u32 rcount = 0;
475 unsigned long addr = siimage_selreg(hwif, 0x1C);
476
477 hwif->OUTL(count, addr);
478 rcount = hwif->INL(addr);
479
480 printk("\n%s: count = %d, rcount = %d, nr_sectors = %lu\n",
481 drive->name, count, rcount, rq->nr_sectors);
482
483#endif /* SIIMAGE_VIRTUAL_DMAPIO */
484 return __ide_dma_count(drive);
485}
486#endif
487
488/**
489 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
490 * @drive: drive we are testing
491 *
492 * Check if we caused an IDE DMA interrupt. We may also have caused
493 * SATA status interrupts, if so we clean them up and continue.
494 */
495
496static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
497{
498 ide_hwif_t *hwif = HWIF(drive);
499 unsigned long base = (unsigned long)hwif->hwif_data;
500 unsigned long addr = siimage_selreg(hwif, 0x1);
501
502 if (SATA_ERROR_REG) {
503 u32 ext_stat = hwif->INL(base + 0x10);
504 u8 watchdog = 0;
505 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
506 u32 sata_error = hwif->INL(SATA_ERROR_REG);
507 hwif->OUTL(sata_error, SATA_ERROR_REG);
508 watchdog = (sata_error & 0x00680000) ? 1 : 0;
509#if 1
510 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
511 "watchdog = %d, %s\n",
512 drive->name, sata_error, watchdog,
513 __FUNCTION__);
514#endif
515
516 } else {
517 watchdog = (ext_stat & 0x8000) ? 1 : 0;
518 }
519 ext_stat >>= 16;
520
521 if (!(ext_stat & 0x0404) && !watchdog)
522 return 0;
523 }
524
525 /* return 1 if INTR asserted */
526 if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04)
527 return 1;
528
529 /* return 1 if Device INTR asserted */
530 if ((hwif->INB(addr) & 8) == 8)
531 return 0; //return 1;
532
533 return 0;
534}
535
536/**
537 * siimage_busproc - bus isolation ioctl
538 * @drive: drive to isolate/restore
539 * @state: bus state to set
540 *
541 * Used by the SII3112 to handle bus isolation. As this is a
542 * SATA controller the work required is quite limited, we
543 * just have to clean up the statistics
544 */
545
546static int siimage_busproc (ide_drive_t * drive, int state)
547{
548 ide_hwif_t *hwif = HWIF(drive);
549 u32 stat_config = 0;
550 unsigned long addr = siimage_selreg(hwif, 0);
551
552 if (hwif->mmio) {
553 stat_config = hwif->INL(addr);
554 } else
555 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
556
557 switch (state) {
558 case BUSSTATE_ON:
559 hwif->drives[0].failures = 0;
560 hwif->drives[1].failures = 0;
561 break;
562 case BUSSTATE_OFF:
563 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
564 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
565 break;
566 case BUSSTATE_TRISTATE:
567 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
568 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
569 break;
570 default:
571 return -EINVAL;
572 }
573 hwif->bus_state = state;
574 return 0;
575}
576
577/**
578 * siimage_reset_poll - wait for sata reset
579 * @drive: drive we are resetting
580 *
581 * Poll the SATA phy and see whether it has come back from the dead
582 * yet.
583 */
584
585static int siimage_reset_poll (ide_drive_t *drive)
586{
587 if (SATA_STATUS_REG) {
588 ide_hwif_t *hwif = HWIF(drive);
589
590 if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) {
591 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
592 hwif->name, hwif->INL(SATA_STATUS_REG));
593 HWGROUP(drive)->polling = 0;
594 return ide_started;
595 }
596 return 0;
597 } else {
598 return 0;
599 }
600}
601
602/**
603 * siimage_pre_reset - reset hook
604 * @drive: IDE device being reset
605 *
606 * For the SATA devices we need to handle recalibration/geometry
607 * differently
608 */
609
610static void siimage_pre_reset (ide_drive_t *drive)
611{
612 if (drive->media != ide_disk)
613 return;
614
615 if (is_sata(HWIF(drive)))
616 {
617 drive->special.b.set_geometry = 0;
618 drive->special.b.recalibrate = 0;
619 }
620}
621
622/**
623 * siimage_reset - reset a device on an siimage controller
624 * @drive: drive to reset
625 *
626 * Perform a controller level reset fo the device. For
627 * SATA we must also check the PHY.
628 */
629
630static void siimage_reset (ide_drive_t *drive)
631{
632 ide_hwif_t *hwif = HWIF(drive);
633 u8 reset = 0;
634 unsigned long addr = siimage_selreg(hwif, 0);
635
636 if (hwif->mmio) {
637 reset = hwif->INB(addr);
638 hwif->OUTB((reset|0x03), addr);
639 /* FIXME:posting */
640 udelay(25);
641 hwif->OUTB(reset, addr);
642 (void) hwif->INB(addr);
643 } else {
644 pci_read_config_byte(hwif->pci_dev, addr, &reset);
645 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
646 udelay(25);
647 pci_write_config_byte(hwif->pci_dev, addr, reset);
648 pci_read_config_byte(hwif->pci_dev, addr, &reset);
649 }
650
651 if (SATA_STATUS_REG) {
652 u32 sata_stat = hwif->INL(SATA_STATUS_REG);
653 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
654 hwif->name, sata_stat, __FUNCTION__);
655 if (!(sata_stat)) {
656 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
657 hwif->name, sata_stat);
658 drive->failures++;
659 }
660 }
661
662}
663
664/**
665 * proc_reports_siimage - add siimage controller to proc
666 * @dev: PCI device
667 * @clocking: SCSC value
668 * @name: controller name
669 *
670 * Report the clocking mode of the controller and add it to
671 * the /proc interface layer
672 */
673
674static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
675{
676 if (!pdev_is_sata(dev)) {
677 printk(KERN_INFO "%s: BASE CLOCK ", name);
678 clocking &= 0x03;
679 switch (clocking) {
680 case 0x03: printk("DISABLED!\n"); break;
681 case 0x02: printk("== 2X PCI\n"); break;
682 case 0x01: printk("== 133\n"); break;
683 case 0x00: printk("== 100\n"); break;
684 }
685 }
686}
687
688/**
689 * setup_mmio_siimage - switch an SI controller into MMIO
690 * @dev: PCI device we are configuring
691 * @name: device name
692 *
693 * Attempt to put the device into mmio mode. There are some slight
694 * complications here with certain systems where the mmio bar isnt
695 * mapped so we have to be sure we can fall back to I/O.
696 */
697
698static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
699{
700 unsigned long bar5 = pci_resource_start(dev, 5);
701 unsigned long barsize = pci_resource_len(dev, 5);
702 u8 tmpbyte = 0;
703 void __iomem *ioaddr;
704
705 /*
706 * Drop back to PIO if we can't map the mmio. Some
707 * systems seem to get terminally confused in the PCI
708 * spaces.
709 */
710
711 if(!request_mem_region(bar5, barsize, name))
712 {
713 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
714 return 0;
715 }
716
717 ioaddr = ioremap(bar5, barsize);
718
719 if (ioaddr == NULL)
720 {
721 release_mem_region(bar5, barsize);
722 return 0;
723 }
724
725 pci_set_master(dev);
726 pci_set_drvdata(dev, (void *) ioaddr);
727
728 if (pdev_is_sata(dev)) {
729 writel(0, ioaddr + 0x148);
730 writel(0, ioaddr + 0x1C8);
731 }
732
733 writeb(0, ioaddr + 0xB4);
734 writeb(0, ioaddr + 0xF4);
735 tmpbyte = readb(ioaddr + 0x4A);
736
737 switch(tmpbyte & 0x30) {
738 case 0x00:
739 /* In 100 MHz clocking, try and switch to 133 */
740 writeb(tmpbyte|0x10, ioaddr + 0x4A);
741 break;
742 case 0x10:
743 /* On 133Mhz clocking */
744 break;
745 case 0x20:
746 /* On PCIx2 clocking */
747 break;
748 case 0x30:
749 /* Clocking is disabled */
750 /* 133 clock attempt to force it on */
751 writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
752 break;
753 }
754
755 writeb( 0x72, ioaddr + 0xA1);
756 writew( 0x328A, ioaddr + 0xA2);
757 writel(0x62DD62DD, ioaddr + 0xA4);
758 writel(0x43924392, ioaddr + 0xA8);
759 writel(0x40094009, ioaddr + 0xAC);
760 writeb( 0x72, ioaddr + 0xE1);
761 writew( 0x328A, ioaddr + 0xE2);
762 writel(0x62DD62DD, ioaddr + 0xE4);
763 writel(0x43924392, ioaddr + 0xE8);
764 writel(0x40094009, ioaddr + 0xEC);
765
766 if (pdev_is_sata(dev)) {
767 writel(0xFFFF0000, ioaddr + 0x108);
768 writel(0xFFFF0000, ioaddr + 0x188);
769 writel(0x00680000, ioaddr + 0x148);
770 writel(0x00680000, ioaddr + 0x1C8);
771 }
772
773 tmpbyte = readb(ioaddr + 0x4A);
774
775 proc_reports_siimage(dev, (tmpbyte>>4), name);
776 return 1;
777}
778
779/**
780 * init_chipset_siimage - set up an SI device
781 * @dev: PCI device
782 * @name: device name
783 *
784 * Perform the initial PCI set up for this device. Attempt to switch
785 * to 133MHz clocking if the system isn't already set up to do it.
786 */
787
788static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
789{
790 u32 class_rev = 0;
791 u8 tmpbyte = 0;
792 u8 BA5_EN = 0;
793
794 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
795 class_rev &= 0xff;
796 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
797
798 pci_read_config_byte(dev, 0x8A, &BA5_EN);
799 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
800 if (setup_mmio_siimage(dev, name)) {
801 return 0;
802 }
803 }
804
805 pci_write_config_byte(dev, 0x80, 0x00);
806 pci_write_config_byte(dev, 0x84, 0x00);
807 pci_read_config_byte(dev, 0x8A, &tmpbyte);
808 switch(tmpbyte & 0x30) {
809 case 0x00:
810 /* 133 clock attempt to force it on */
811 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
812 case 0x30:
813 /* if clocking is disabled */
814 /* 133 clock attempt to force it on */
815 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
816 case 0x10:
817 /* 133 already */
818 break;
819 case 0x20:
820 /* BIOS set PCI x2 clocking */
821 break;
822 }
823
824 pci_read_config_byte(dev, 0x8A, &tmpbyte);
825
826 pci_write_config_byte(dev, 0xA1, 0x72);
827 pci_write_config_word(dev, 0xA2, 0x328A);
828 pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
829 pci_write_config_dword(dev, 0xA8, 0x43924392);
830 pci_write_config_dword(dev, 0xAC, 0x40094009);
831 pci_write_config_byte(dev, 0xB1, 0x72);
832 pci_write_config_word(dev, 0xB2, 0x328A);
833 pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
834 pci_write_config_dword(dev, 0xB8, 0x43924392);
835 pci_write_config_dword(dev, 0xBC, 0x40094009);
836
837 proc_reports_siimage(dev, (tmpbyte>>4), name);
838 return 0;
839}
840
841/**
842 * init_mmio_iops_siimage - set up the iops for MMIO
843 * @hwif: interface to set up
844 *
845 * The basic setup here is fairly simple, we can use standard MMIO
846 * operations. However we do have to set the taskfile register offsets
847 * by hand as there isnt a standard defined layout for them this
848 * time.
849 *
850 * The hardware supports buffered taskfiles and also some rather nice
851 * extended PRD tables. Unfortunately right now we don't.
852 */
853
854static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
855{
856 struct pci_dev *dev = hwif->pci_dev;
857 void *addr = pci_get_drvdata(dev);
858 u8 ch = hwif->channel;
859 hw_regs_t hw;
860 unsigned long base;
861
862 /*
863 * Fill in the basic HWIF bits
864 */
865
866 default_hwif_mmiops(hwif);
867 hwif->hwif_data = addr;
868
869 /*
870 * Now set up the hw. We have to do this ourselves as
871 * the MMIO layout isnt the same as the the standard port
872 * based I/O
873 */
874
875 memset(&hw, 0, sizeof(hw_regs_t));
876
877 base = (unsigned long)addr;
878 if (ch)
879 base += 0xC0;
880 else
881 base += 0x80;
882
883 /*
884 * The buffered task file doesn't have status/control
885 * so we can't currently use it sanely since we want to
886 * use LBA48 mode.
887 */
888// base += 0x10;
889// hwif->no_lba48 = 1;
890
891 hw.io_ports[IDE_DATA_OFFSET] = base;
892 hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
893 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
894 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
895 hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
896 hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
897 hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
898 hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
899 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
900
901 hw.io_ports[IDE_IRQ_OFFSET] = 0;
902
903 if (pdev_is_sata(dev)) {
904 base = (unsigned long)addr;
905 if (ch)
906 base += 0x80;
907 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
908 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
909 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
910 hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140;
911 hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144;
912 hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148;
913 }
914
915 hw.irq = hwif->pci_dev->irq;
916
917 memcpy(&hwif->hw, &hw, sizeof(hw));
918 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
919
920 hwif->irq = hw.irq;
921
922 base = (unsigned long) addr;
923
924#ifdef SIIMAGE_LARGE_DMA
925/* Watch the brackets - even Ken and Dennis get some language design wrong */
926 hwif->dma_base = base + (ch ? 0x18 : 0x10);
927 hwif->dma_base2 = base + (ch ? 0x08 : 0x00);
928 hwif->dma_prdtable = hwif->dma_base2 + 4;
929#else /* ! SIIMAGE_LARGE_DMA */
930 hwif->dma_base = base + (ch ? 0x08 : 0x00);
931 hwif->dma_base2 = base + (ch ? 0x18 : 0x10);
932#endif /* SIIMAGE_LARGE_DMA */
933 hwif->mmio = 2;
934}
935
936static int is_dev_seagate_sata(ide_drive_t *drive)
937{
938 const char *s = &drive->id->model[0];
939 unsigned len;
940
941 if (!drive->present)
942 return 0;
943
944 len = strnlen(s, sizeof(drive->id->model));
945
946 if ((len > 4) && (!memcmp(s, "ST", 2))) {
947 if ((!memcmp(s + len - 2, "AS", 2)) ||
948 (!memcmp(s + len - 3, "ASL", 3))) {
949 printk(KERN_INFO "%s: applying pessimistic Seagate "
950 "errata fix\n", drive->name);
951 return 1;
952 }
953 }
954 return 0;
955}
956
957/**
958 * siimage_fixup - post probe fixups
959 * @hwif: interface to fix up
960 *
961 * Called after drive probe we use this to decide whether the
962 * Seagate fixup must be applied. This used to be in init_iops but
963 * that can occur before we know what drives are present.
964 */
965
966static void __devinit siimage_fixup(ide_hwif_t *hwif)
967{
968 /* Try and raise the rqsize */
969 if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0]))
970 hwif->rqsize = 128;
971}
972
973/**
974 * init_iops_siimage - set up iops
975 * @hwif: interface to set up
976 *
977 * Do the basic setup for the SIIMAGE hardware interface
978 * and then do the MMIO setup if we can. This is the first
979 * look in we get for setting up the hwif so that we
980 * can get the iops right before using them.
981 */
982
983static void __devinit init_iops_siimage(ide_hwif_t *hwif)
984{
985 struct pci_dev *dev = hwif->pci_dev;
986 u32 class_rev = 0;
987
988 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
989 class_rev &= 0xff;
990
991 hwif->hwif_data = NULL;
992
993 /* Pessimal until we finish probing */
994 hwif->rqsize = 15;
995
996 if (pci_get_drvdata(dev) == NULL)
997 return;
998 init_mmio_iops_siimage(hwif);
999}
1000
1001/**
1002 * ata66_siimage - check for 80 pin cable
1003 * @hwif: interface to check
1004 *
1005 * Check for the presence of an ATA66 capable cable on the
1006 * interface.
1007 */
1008
1009static unsigned int __devinit ata66_siimage(ide_hwif_t *hwif)
1010{
1011 unsigned long addr = siimage_selreg(hwif, 0);
1012 if (pci_get_drvdata(hwif->pci_dev) == NULL) {
1013 u8 ata66 = 0;
1014 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
1015 return (ata66 & 0x01) ? 1 : 0;
1016 }
1017
1018 return (hwif->INB(addr) & 0x01) ? 1 : 0;
1019}
1020
1021/**
1022 * init_hwif_siimage - set up hwif structs
1023 * @hwif: interface to set up
1024 *
1025 * We do the basic set up of the interface structure. The SIIMAGE
1026 * requires several custom handlers so we override the default
1027 * ide DMA handlers appropriately
1028 */
1029
1030static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
1031{
1032 hwif->autodma = 0;
1033
1034 hwif->resetproc = &siimage_reset;
1035 hwif->speedproc = &siimage_tune_chipset;
1036 hwif->tuneproc = &siimage_tuneproc;
1037 hwif->reset_poll = &siimage_reset_poll;
1038 hwif->pre_reset = &siimage_pre_reset;
1039
1040 if(is_sata(hwif))
1041 hwif->busproc = &siimage_busproc;
1042
1043 if (!hwif->dma_base) {
1044 hwif->drives[0].autotune = 1;
1045 hwif->drives[1].autotune = 1;
1046 return;
1047 }
1048
1049 hwif->ultra_mask = 0x7f;
1050 hwif->mwdma_mask = 0x07;
1051 hwif->swdma_mask = 0x07;
1052
1053 if (!is_sata(hwif))
1054 hwif->atapi_dma = 1;
1055
1056 hwif->ide_dma_check = &siimage_config_drive_for_dma;
1057 if (!(hwif->udma_four))
1058 hwif->udma_four = ata66_siimage(hwif);
1059
1060 if (hwif->mmio) {
1061 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
1062 } else {
1063 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
1064 }
1065
1066 /*
1067 * The BIOS often doesn't set up DMA on this controller
1068 * so we always do it.
1069 */
1070
1071 hwif->autodma = 1;
1072 hwif->drives[0].autodma = hwif->autodma;
1073 hwif->drives[1].autodma = hwif->autodma;
1074}
1075
1076#define DECLARE_SII_DEV(name_str) \
1077 { \
1078 .name = name_str, \
1079 .init_chipset = init_chipset_siimage, \
1080 .init_iops = init_iops_siimage, \
1081 .init_hwif = init_hwif_siimage, \
1082 .fixup = siimage_fixup, \
1083 .channels = 2, \
1084 .autodma = AUTODMA, \
1085 .bootable = ON_BOARD, \
1086 }
1087
1088static ide_pci_device_t siimage_chipsets[] __devinitdata = {
1089 /* 0 */ DECLARE_SII_DEV("SiI680"),
1090 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
1091 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
1092};
1093
1094/**
1095 * siimage_init_one - pci layer discovery entry
1096 * @dev: PCI device
1097 * @id: ident table entry
1098 *
1099 * Called by the PCI code when it finds an SI680 or SI3112 controller.
1100 * We then use the IDE PCI generic helper to do most of the work.
1101 */
1102
1103static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1104{
1105 return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
1106}
1107
1108static struct pci_device_id siimage_pci_tbl[] = {
1109 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1110#ifdef CONFIG_BLK_DEV_IDE_SATA
1111 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1112 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1113#endif
1114 { 0, },
1115};
1116MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
1117
1118static struct pci_driver driver = {
1119 .name = "SiI_IDE",
1120 .id_table = siimage_pci_tbl,
1121 .probe = siimage_init_one,
1122};
1123
1124static int siimage_ide_init(void)
1125{
1126 return ide_pci_register_driver(&driver);
1127}
1128
1129module_init(siimage_ide_init);
1130
1131MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1132MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1133MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 14:18:11 -0500