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path: root/drivers/ide/pci/pdc202xx_new.c
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Diffstat (limited to 'drivers/ide/pci/pdc202xx_new.c')
-rw-r--r--drivers/ide/pci/pdc202xx_new.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
index 7c5544d10b9a..3787194a2249 100644
--- a/drivers/ide/pci/pdc202xx_new.c
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -146,14 +146,12 @@ static struct udma_timing {
146 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ 146 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
147}; 147};
148 148
149static int pdcnew_tune_chipset(ide_drive_t *drive, u8 speed) 149static int pdcnew_tune_chipset(ide_drive_t *drive, const u8 speed)
150{ 150{
151 ide_hwif_t *hwif = HWIF(drive); 151 ide_hwif_t *hwif = HWIF(drive);
152 u8 adj = (drive->dn & 1) ? 0x08 : 0x00; 152 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
153 int err; 153 int err;
154 154
155 speed = ide_rate_filter(drive, speed);
156
157 /* 155 /*
158 * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will 156 * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
159 * automatically set the timing registers based on 100 MHz PLL output. 157 * automatically set the timing registers based on 100 MHz PLL output.