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-rw-r--r--drivers/ide/pci/it821x.c812
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diff --git a/drivers/ide/pci/it821x.c b/drivers/ide/pci/it821x.c
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1
2/*
3 * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004
4 *
5 * Copyright (C) 2004 Red Hat <alan@redhat.com>
6 *
7 * May be copied or modified under the terms of the GNU General Public License
8 * Based in part on the ITE vendor provided SCSI driver.
9 *
10 * Documentation available from
11 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
12 * Some other documents are NDA.
13 *
14 * The ITE8212 isn't exactly a standard IDE controller. It has two
15 * modes. In pass through mode then it is an IDE controller. In its smart
16 * mode its actually quite a capable hardware raid controller disguised
17 * as an IDE controller. Smart mode only understands DMA read/write and
18 * identify, none of the fancier commands apply. The IT8211 is identical
19 * in other respects but lacks the raid mode.
20 *
21 * Errata:
22 * o Rev 0x10 also requires master/slave hold the same DMA timings and
23 * cannot do ATAPI MWDMA.
24 * o The identify data for raid volumes lacks CHS info (technically ok)
25 * but also fails to set the LBA28 and other bits. We fix these in
26 * the IDE probe quirk code.
27 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
28 * raid then the controller firmware dies
29 * o Smart mode without RAID doesn't clear all the necessary identify
30 * bits to reduce the command set to the one used
31 *
32 * This has a few impacts on the driver
33 * - In pass through mode we do all the work you would expect
34 * - In smart mode the clocking set up is done by the controller generally
35 * but we must watch the other limits and filter.
36 * - There are a few extra vendor commands that actually talk to the
37 * controller but only work PIO with no IRQ.
38 *
39 * Vendor areas of the identify block in smart mode are used for the
40 * timing and policy set up. Each HDD in raid mode also has a serial
41 * block on the disk. The hardware extra commands are get/set chip status,
42 * rebuild, get rebuild status.
43 *
44 * In Linux the driver supports pass through mode as if the device was
45 * just another IDE controller. If the smart mode is running then
46 * volumes are managed by the controller firmware and each IDE "disk"
47 * is a raid volume. Even more cute - the controller can do automated
48 * hotplug and rebuild.
49 *
50 * The pass through controller itself is a little demented. It has a
51 * flaw that it has a single set of PIO/MWDMA timings per channel so
52 * non UDMA devices restrict each others performance. It also has a
53 * single clock source per channel so mixed UDMA100/133 performance
54 * isn't perfect and we have to pick a clock. Thankfully none of this
55 * matters in smart mode. ATAPI DMA is not currently supported.
56 *
57 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
58 *
59 * TODO
60 * - ATAPI UDMA is ok but not MWDMA it seems
61 * - RAID configuration ioctls
62 * - Move to libata once it grows up
63 */
64
65#include <linux/config.h>
66#include <linux/types.h>
67#include <linux/module.h>
68#include <linux/pci.h>
69#include <linux/delay.h>
70#include <linux/hdreg.h>
71#include <linux/ide.h>
72#include <linux/init.h>
73
74#include <asm/io.h>
75
76struct it821x_dev
77{
78 unsigned int smart:1, /* Are we in smart raid mode */
79 timing10:1; /* Rev 0x10 */
80 u8 clock_mode; /* 0, ATA_50 or ATA_66 */
81 u8 want[2][2]; /* Mode/Pri log for master slave */
82 /* We need these for switching the clock when DMA goes on/off
83 The high byte is the 66Mhz timing */
84 u16 pio[2]; /* Cached PIO values */
85 u16 mwdma[2]; /* Cached MWDMA values */
86 u16 udma[2]; /* Cached UDMA values (per drive) */
87};
88
89#define ATA_66 0
90#define ATA_50 1
91#define ATA_ANY 2
92
93#define UDMA_OFF 0
94#define MWDMA_OFF 0
95
96/*
97 * We allow users to force the card into non raid mode without
98 * flashing the alternative BIOS. This is also neccessary right now
99 * for embedded platforms that cannot run a PC BIOS but are using this
100 * device.
101 */
102
103static int it8212_noraid;
104
105/**
106 * it821x_program - program the PIO/MWDMA registers
107 * @drive: drive to tune
108 *
109 * Program the PIO/MWDMA timing for this channel according to the
110 * current clock.
111 */
112
113static void it821x_program(ide_drive_t *drive, u16 timing)
114{
115 ide_hwif_t *hwif = drive->hwif;
116 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
117 int channel = hwif->channel;
118 u8 conf;
119
120 /* Program PIO/MWDMA timing bits */
121 if(itdev->clock_mode == ATA_66)
122 conf = timing >> 8;
123 else
124 conf = timing & 0xFF;
125 pci_write_config_byte(hwif->pci_dev, 0x54 + 4 * channel, conf);
126}
127
128/**
129 * it821x_program_udma - program the UDMA registers
130 * @drive: drive to tune
131 *
132 * Program the UDMA timing for this drive according to the
133 * current clock.
134 */
135
136static void it821x_program_udma(ide_drive_t *drive, u16 timing)
137{
138 ide_hwif_t *hwif = drive->hwif;
139 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
140 int channel = hwif->channel;
141 int unit = drive->select.b.unit;
142 u8 conf;
143
144 /* Program UDMA timing bits */
145 if(itdev->clock_mode == ATA_66)
146 conf = timing >> 8;
147 else
148 conf = timing & 0xFF;
149 if(itdev->timing10 == 0)
150 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + unit, conf);
151 else {
152 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel, conf);
153 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + 1, conf);
154 }
155}
156
157
158/**
159 * it821x_clock_strategy
160 * @hwif: hardware interface
161 *
162 * Select between the 50 and 66Mhz base clocks to get the best
163 * results for this interface.
164 */
165
166static void it821x_clock_strategy(ide_drive_t *drive)
167{
168 ide_hwif_t *hwif = drive->hwif;
169 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
170
171 u8 unit = drive->select.b.unit;
172 ide_drive_t *pair = &hwif->drives[1-unit];
173
174 int clock, altclock;
175 u8 v;
176 int sel = 0;
177
178 if(itdev->want[0][0] > itdev->want[1][0]) {
179 clock = itdev->want[0][1];
180 altclock = itdev->want[1][1];
181 } else {
182 clock = itdev->want[1][1];
183 altclock = itdev->want[0][1];
184 }
185
186 /* Master doesn't care does the slave ? */
187 if(clock == ATA_ANY)
188 clock = altclock;
189
190 /* Nobody cares - keep the same clock */
191 if(clock == ATA_ANY)
192 return;
193 /* No change */
194 if(clock == itdev->clock_mode)
195 return;
196
197 /* Load this into the controller ? */
198 if(clock == ATA_66)
199 itdev->clock_mode = ATA_66;
200 else {
201 itdev->clock_mode = ATA_50;
202 sel = 1;
203 }
204 pci_read_config_byte(hwif->pci_dev, 0x50, &v);
205 v &= ~(1 << (1 + hwif->channel));
206 v |= sel << (1 + hwif->channel);
207 pci_write_config_byte(hwif->pci_dev, 0x50, v);
208
209 /*
210 * Reprogram the UDMA/PIO of the pair drive for the switch
211 * MWDMA will be dealt with by the dma switcher
212 */
213 if(pair && itdev->udma[1-unit] != UDMA_OFF) {
214 it821x_program_udma(pair, itdev->udma[1-unit]);
215 it821x_program(pair, itdev->pio[1-unit]);
216 }
217 /*
218 * Reprogram the UDMA/PIO of our drive for the switch.
219 * MWDMA will be dealt with by the dma switcher
220 */
221 if(itdev->udma[unit] != UDMA_OFF) {
222 it821x_program_udma(drive, itdev->udma[unit]);
223 it821x_program(drive, itdev->pio[unit]);
224 }
225}
226
227/**
228 * it821x_ratemask - Compute available modes
229 * @drive: IDE drive
230 *
231 * Compute the available speeds for the devices on the interface. This
232 * is all modes to ATA133 clipped by drive cable setup.
233 */
234
235static u8 it821x_ratemask (ide_drive_t *drive)
236{
237 u8 mode = 4;
238 if (!eighty_ninty_three(drive))
239 mode = min(mode, (u8)1);
240 return mode;
241}
242
243/**
244 * it821x_tuneproc - tune a drive
245 * @drive: drive to tune
246 * @mode_wanted: the target operating mode
247 *
248 * Load the timing settings for this device mode into the
249 * controller. By the time we are called the mode has been
250 * modified as neccessary to handle the absence of seperate
251 * master/slave timers for MWDMA/PIO.
252 *
253 * This code is only used in pass through mode.
254 */
255
256static void it821x_tuneproc (ide_drive_t *drive, byte mode_wanted)
257{
258 ide_hwif_t *hwif = drive->hwif;
259 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
260 int unit = drive->select.b.unit;
261
262 /* Spec says 89 ref driver uses 88 */
263 static u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
264 static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
265
266 if(itdev->smart)
267 return;
268
269 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
270 itdev->want[unit][1] = pio_want[mode_wanted];
271 itdev->want[unit][0] = 1; /* PIO is lowest priority */
272 itdev->pio[unit] = pio[mode_wanted];
273 it821x_clock_strategy(drive);
274 it821x_program(drive, itdev->pio[unit]);
275}
276
277/**
278 * it821x_tune_mwdma - tune a channel for MWDMA
279 * @drive: drive to set up
280 * @mode_wanted: the target operating mode
281 *
282 * Load the timing settings for this device mode into the
283 * controller when doing MWDMA in pass through mode. The caller
284 * must manage the whole lack of per device MWDMA/PIO timings and
285 * the shared MWDMA/PIO timing register.
286 */
287
288static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted)
289{
290 ide_hwif_t *hwif = drive->hwif;
291 struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif);
292 int unit = drive->select.b.unit;
293 int channel = hwif->channel;
294 u8 conf;
295
296 static u16 dma[] = { 0x8866, 0x3222, 0x3121 };
297 static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
298
299 itdev->want[unit][1] = mwdma_want[mode_wanted];
300 itdev->want[unit][0] = 2; /* MWDMA is low priority */
301 itdev->mwdma[unit] = dma[mode_wanted];
302 itdev->udma[unit] = UDMA_OFF;
303
304 /* UDMA bits off - Revision 0x10 do them in pairs */
305 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
306 if(itdev->timing10)
307 conf |= channel ? 0x60: 0x18;
308 else
309 conf |= 1 << (3 + 2 * channel + unit);
310 pci_write_config_byte(hwif->pci_dev, 0x50, conf);
311
312 it821x_clock_strategy(drive);
313 /* FIXME: do we need to program this ? */
314 /* it821x_program(drive, itdev->mwdma[unit]); */
315}
316
317/**
318 * it821x_tune_udma - tune a channel for UDMA
319 * @drive: drive to set up
320 * @mode_wanted: the target operating mode
321 *
322 * Load the timing settings for this device mode into the
323 * controller when doing UDMA modes in pass through.
324 */
325
326static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted)
327{
328 ide_hwif_t *hwif = drive->hwif;
329 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
330 int unit = drive->select.b.unit;
331 int channel = hwif->channel;
332 u8 conf;
333
334 static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
335 static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
336
337 itdev->want[unit][1] = udma_want[mode_wanted];
338 itdev->want[unit][0] = 3; /* UDMA is high priority */
339 itdev->mwdma[unit] = MWDMA_OFF;
340 itdev->udma[unit] = udma[mode_wanted];
341 if(mode_wanted >= 5)
342 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
343
344 /* UDMA on. Again revision 0x10 must do the pair */
345 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
346 if(itdev->timing10)
347 conf &= channel ? 0x9F: 0xE7;
348 else
349 conf &= ~ (1 << (3 + 2 * channel + unit));
350 pci_write_config_byte(hwif->pci_dev, 0x50, conf);
351
352 it821x_clock_strategy(drive);
353 it821x_program_udma(drive, itdev->udma[unit]);
354
355}
356
357/**
358 * config_it821x_chipset_for_pio - set drive timings
359 * @drive: drive to tune
360 * @speed we want
361 *
362 * Compute the best pio mode we can for a given device. We must
363 * pick a speed that does not cause problems with the other device
364 * on the cable.
365 */
366
367static void config_it821x_chipset_for_pio (ide_drive_t *drive, byte set_speed)
368{
369 u8 unit = drive->select.b.unit;
370 ide_hwif_t *hwif = drive->hwif;
371 ide_drive_t *pair = &hwif->drives[1-unit];
372 u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
373 u8 pair_pio;
374
375 /* We have to deal with this mess in pairs */
376 if(pair != NULL) {
377 pair_pio = ide_get_best_pio_mode(pair, 255, 5, NULL);
378 /* Trim PIO to the slowest of the master/slave */
379 if(pair_pio < set_pio)
380 set_pio = pair_pio;
381 }
382 it821x_tuneproc(drive, set_pio);
383 speed = XFER_PIO_0 + set_pio;
384 /* XXX - We trim to the lowest of the pair so the other drive
385 will always be fine at this point until we do hotplug passthru */
386
387 if (set_speed)
388 (void) ide_config_drive_speed(drive, speed);
389}
390
391/**
392 * it821x_dma_read - DMA hook
393 * @drive: drive for DMA
394 *
395 * The IT821x has a single timing register for MWDMA and for PIO
396 * operations. As we flip back and forth we have to reload the
397 * clock. In addition the rev 0x10 device only works if the same
398 * timing value is loaded into the master and slave UDMA clock
399 * so we must also reload that.
400 *
401 * FIXME: we could figure out in advance if we need to do reloads
402 */
403
404static void it821x_dma_start(ide_drive_t *drive)
405{
406 ide_hwif_t *hwif = drive->hwif;
407 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
408 int unit = drive->select.b.unit;
409 if(itdev->mwdma[unit] != MWDMA_OFF)
410 it821x_program(drive, itdev->mwdma[unit]);
411 else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
412 it821x_program_udma(drive, itdev->udma[unit]);
413 ide_dma_start(drive);
414}
415
416/**
417 * it821x_dma_write - DMA hook
418 * @drive: drive for DMA stop
419 *
420 * The IT821x has a single timing register for MWDMA and for PIO
421 * operations. As we flip back and forth we have to reload the
422 * clock.
423 */
424
425static int it821x_dma_end(ide_drive_t *drive)
426{
427 ide_hwif_t *hwif = drive->hwif;
428 int unit = drive->select.b.unit;
429 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
430 int ret = __ide_dma_end(drive);
431 if(itdev->mwdma[unit] != MWDMA_OFF)
432 it821x_program(drive, itdev->pio[unit]);
433 return ret;
434}
435
436
437/**
438 * it821x_tune_chipset - set controller timings
439 * @drive: Drive to set up
440 * @xferspeed: speed we want to achieve
441 *
442 * Tune the ITE chipset for the desired mode. If we can't achieve
443 * the desired mode then tune for a lower one, but ultimately
444 * make the thing work.
445 */
446
447static int it821x_tune_chipset (ide_drive_t *drive, byte xferspeed)
448{
449
450 ide_hwif_t *hwif = drive->hwif;
451 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
452 u8 speed = ide_rate_filter(it821x_ratemask(drive), xferspeed);
453
454 if(!itdev->smart) {
455 switch(speed) {
456 case XFER_PIO_4:
457 case XFER_PIO_3:
458 case XFER_PIO_2:
459 case XFER_PIO_1:
460 case XFER_PIO_0:
461 it821x_tuneproc(drive, (speed - XFER_PIO_0));
462 break;
463 /* MWDMA tuning is really hard because our MWDMA and PIO
464 timings are kept in the same place. We can switch in the
465 host dma on/off callbacks */
466 case XFER_MW_DMA_2:
467 case XFER_MW_DMA_1:
468 case XFER_MW_DMA_0:
469 it821x_tune_mwdma(drive, (speed - XFER_MW_DMA_0));
470 break;
471 case XFER_UDMA_6:
472 case XFER_UDMA_5:
473 case XFER_UDMA_4:
474 case XFER_UDMA_3:
475 case XFER_UDMA_2:
476 case XFER_UDMA_1:
477 case XFER_UDMA_0:
478 it821x_tune_udma(drive, (speed - XFER_UDMA_0));
479 break;
480 default:
481 return 1;
482 }
483 }
484 /*
485 * In smart mode the clocking is done by the host controller
486 * snooping the mode we picked. The rest of it is not our problem
487 */
488 return ide_config_drive_speed(drive, speed);
489}
490
491/**
492 * config_chipset_for_dma - configure for DMA
493 * @drive: drive to configure
494 *
495 * Called by the IDE layer when it wants the timings set up.
496 */
497
498static int config_chipset_for_dma (ide_drive_t *drive)
499{
500 u8 speed = ide_dma_speed(drive, it821x_ratemask(drive));
501
502 config_it821x_chipset_for_pio(drive, !speed);
503 it821x_tune_chipset(drive, speed);
504 return ide_dma_enable(drive);
505}
506
507/**
508 * it821x_configure_drive_for_dma - set up for DMA transfers
509 * @drive: drive we are going to set up
510 *
511 * Set up the drive for DMA, tune the controller and drive as
512 * required. If the drive isn't suitable for DMA or we hit
513 * other problems then we will drop down to PIO and set up
514 * PIO appropriately
515 */
516
517static int it821x_config_drive_for_dma (ide_drive_t *drive)
518{
519 ide_hwif_t *hwif = drive->hwif;
520
521 if (ide_use_dma(drive)) {
522 if (config_chipset_for_dma(drive))
523 return hwif->ide_dma_on(drive);
524 }
525 config_it821x_chipset_for_pio(drive, 1);
526 return hwif->ide_dma_off_quietly(drive);
527}
528
529/**
530 * ata66_it821x - check for 80 pin cable
531 * @hwif: interface to check
532 *
533 * Check for the presence of an ATA66 capable cable on the
534 * interface. Problematic as it seems some cards don't have
535 * the needed logic onboard.
536 */
537
538static unsigned int __devinit ata66_it821x(ide_hwif_t *hwif)
539{
540 /* The reference driver also only does disk side */
541 return 1;
542}
543
544/**
545 * it821x_fixup - post init callback
546 * @hwif: interface
547 *
548 * This callback is run after the drives have been probed but
549 * before anything gets attached. It allows drivers to do any
550 * final tuning that is needed, or fixups to work around bugs.
551 */
552
553static void __devinit it821x_fixups(ide_hwif_t *hwif)
554{
555 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
556 int i;
557
558 if(!itdev->smart) {
559 /*
560 * If we are in pass through mode then not much
561 * needs to be done, but we do bother to clear the
562 * IRQ mask as we may well be in PIO (eg rev 0x10)
563 * for now and we know unmasking is safe on this chipset.
564 */
565 for (i = 0; i < 2; i++) {
566 ide_drive_t *drive = &hwif->drives[i];
567 if(drive->present)
568 drive->unmask = 1;
569 }
570 return;
571 }
572 /*
573 * Perform fixups on smart mode. We need to "lose" some
574 * capabilities the firmware lacks but does not filter, and
575 * also patch up some capability bits that it forgets to set
576 * in RAID mode.
577 */
578
579 for(i = 0; i < 2; i++) {
580 ide_drive_t *drive = &hwif->drives[i];
581 struct hd_driveid *id;
582 u16 *idbits;
583
584 if(!drive->present)
585 continue;
586 id = drive->id;
587 idbits = (u16 *)drive->id;
588
589 /* Check for RAID v native */
590 if(strstr(id->model, "Integrated Technology Express")) {
591 /* In raid mode the ident block is slightly buggy
592 We need to set the bits so that the IDE layer knows
593 LBA28. LBA48 and DMA ar valid */
594 id->capability |= 3; /* LBA28, DMA */
595 id->command_set_2 |= 0x0400; /* LBA48 valid */
596 id->cfs_enable_2 |= 0x0400; /* LBA48 on */
597 /* Reporting logic */
598 printk(KERN_INFO "%s: IT8212 %sRAID %d volume",
599 drive->name,
600 idbits[147] ? "Bootable ":"",
601 idbits[129]);
602 if(idbits[129] != 1)
603 printk("(%dK stripe)", idbits[146]);
604 printk(".\n");
605 /* Now the core code will have wrongly decided no DMA
606 so we need to fix this */
607 hwif->ide_dma_off_quietly(drive);
608#ifdef CONFIG_IDEDMA_ONLYDISK
609 if (drive->media == ide_disk)
610#endif
611 hwif->ide_dma_check(drive);
612 } else {
613 /* Non RAID volume. Fixups to stop the core code
614 doing unsupported things */
615 id->field_valid &= 1;
616 id->queue_depth = 0;
617 id->command_set_1 = 0;
618 id->command_set_2 &= 0xC400;
619 id->cfsse &= 0xC000;
620 id->cfs_enable_1 = 0;
621 id->cfs_enable_2 &= 0xC400;
622 id->csf_default &= 0xC000;
623 id->word127 = 0;
624 id->dlf = 0;
625 id->csfo = 0;
626 id->cfa_power = 0;
627 printk(KERN_INFO "%s: Performing identify fixups.\n",
628 drive->name);
629 }
630 }
631
632}
633
634/**
635 * init_hwif_it821x - set up hwif structs
636 * @hwif: interface to set up
637 *
638 * We do the basic set up of the interface structure. The IT8212
639 * requires several custom handlers so we override the default
640 * ide DMA handlers appropriately
641 */
642
643static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
644{
645 struct it821x_dev *idev = kmalloc(sizeof(struct it821x_dev), GFP_KERNEL);
646 u8 conf;
647
648 if(idev == NULL) {
649 printk(KERN_ERR "it821x: out of memory, falling back to legacy behaviour.\n");
650 goto fallback;
651 }
652 memset(idev, 0, sizeof(struct it821x_dev));
653 ide_set_hwifdata(hwif, idev);
654
655 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
656 if(conf & 1) {
657 idev->smart = 1;
658 hwif->atapi_dma = 0;
659 /* Long I/O's although allowed in LBA48 space cause the
660 onboard firmware to enter the twighlight zone */
661 hwif->rqsize = 256;
662 }
663
664 /* Pull the current clocks from 0x50 also */
665 if (conf & (1 << (1 + hwif->channel)))
666 idev->clock_mode = ATA_50;
667 else
668 idev->clock_mode = ATA_66;
669
670 idev->want[0][1] = ATA_ANY;
671 idev->want[1][1] = ATA_ANY;
672
673 /*
674 * Not in the docs but according to the reference driver
675 * this is neccessary.
676 */
677
678 pci_read_config_byte(hwif->pci_dev, 0x08, &conf);
679 if(conf == 0x10) {
680 idev->timing10 = 1;
681 hwif->atapi_dma = 0;
682 if(!idev->smart)
683 printk(KERN_WARNING "it821x: Revision 0x10, workarounds activated.\n");
684 }
685
686 hwif->speedproc = &it821x_tune_chipset;
687 hwif->tuneproc = &it821x_tuneproc;
688
689 /* MWDMA/PIO clock switching for pass through mode */
690 if(!idev->smart) {
691 hwif->dma_start = &it821x_dma_start;
692 hwif->ide_dma_end = &it821x_dma_end;
693 }
694
695 hwif->drives[0].autotune = 1;
696 hwif->drives[1].autotune = 1;
697
698 if (!hwif->dma_base)
699 goto fallback;
700
701 hwif->ultra_mask = 0x7f;
702 hwif->mwdma_mask = 0x07;
703 hwif->swdma_mask = 0x07;
704
705 hwif->ide_dma_check = &it821x_config_drive_for_dma;
706 if (!(hwif->udma_four))
707 hwif->udma_four = ata66_it821x(hwif);
708
709 /*
710 * The BIOS often doesn't set up DMA on this controller
711 * so we always do it.
712 */
713
714 hwif->autodma = 1;
715 hwif->drives[0].autodma = hwif->autodma;
716 hwif->drives[1].autodma = hwif->autodma;
717 return;
718fallback:
719 hwif->autodma = 0;
720 return;
721}
722
723static void __devinit it8212_disable_raid(struct pci_dev *dev)
724{
725 /* Reset local CPU, and set BIOS not ready */
726 pci_write_config_byte(dev, 0x5E, 0x01);
727
728 /* Set to bypass mode, and reset PCI bus */
729 pci_write_config_byte(dev, 0x50, 0x00);
730 pci_write_config_word(dev, PCI_COMMAND,
731 PCI_COMMAND_PARITY | PCI_COMMAND_IO |
732 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
733 pci_write_config_word(dev, 0x40, 0xA0F3);
734
735 pci_write_config_dword(dev,0x4C, 0x02040204);
736 pci_write_config_byte(dev, 0x42, 0x36);
737 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0);
738}
739
740static unsigned int __devinit init_chipset_it821x(struct pci_dev *dev, const char *name)
741{
742 u8 conf;
743 static char *mode[2] = { "pass through", "smart" };
744
745 /* Force the card into bypass mode if so requested */
746 if (it8212_noraid) {
747 printk(KERN_INFO "it8212: forcing bypass mode.\n");
748 it8212_disable_raid(dev);
749 }
750 pci_read_config_byte(dev, 0x50, &conf);
751 printk(KERN_INFO "it821x: controller in %s mode.\n", mode[conf & 1]);
752 return 0;
753}
754
755
756#define DECLARE_ITE_DEV(name_str) \
757 { \
758 .name = name_str, \
759 .init_chipset = init_chipset_it821x, \
760 .init_hwif = init_hwif_it821x, \
761 .channels = 2, \
762 .autodma = AUTODMA, \
763 .bootable = ON_BOARD, \
764 .fixup = it821x_fixups \
765 }
766
767static ide_pci_device_t it821x_chipsets[] __devinitdata = {
768 /* 0 */ DECLARE_ITE_DEV("IT8212"),
769};
770
771/**
772 * it821x_init_one - pci layer discovery entry
773 * @dev: PCI device
774 * @id: ident table entry
775 *
776 * Called by the PCI code when it finds an ITE821x controller.
777 * We then use the IDE PCI generic helper to do most of the work.
778 */
779
780static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
781{
782 ide_setup_pci_device(dev, &it821x_chipsets[id->driver_data]);
783 return 0;
784}
785
786static struct pci_device_id it821x_pci_tbl[] = {
787 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
788 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
789 { 0, },
790};
791
792MODULE_DEVICE_TABLE(pci, it821x_pci_tbl);
793
794static struct pci_driver driver = {
795 .name = "ITE821x IDE",
796 .id_table = it821x_pci_tbl,
797 .probe = it821x_init_one,
798};
799
800static int __init it821x_ide_init(void)
801{
802 return ide_pci_register_driver(&driver);
803}
804
805module_init(it821x_ide_init);
806
807module_param_named(noraid, it8212_noraid, int, S_IRUGO);
808MODULE_PARM_DESC(it8212_noraid, "Force card into bypass mode");
809
810MODULE_AUTHOR("Alan Cox");
811MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
812MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 02:54:34 -0500