diff options
Diffstat (limited to 'drivers/ide/pci/hpt366.c')
-rw-r--r-- | drivers/ide/pci/hpt366.c | 154 |
1 files changed, 82 insertions, 72 deletions
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c index 65018814ed73..ce363c923613 100644 --- a/drivers/ide/pci/hpt366.c +++ b/drivers/ide/pci/hpt366.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * linux/drivers/ide/pci/hpt366.c Version 1.06 Jun 27, 2007 | 2 | * linux/drivers/ide/pci/hpt366.c Version 1.10 Jun 29, 2007 |
3 | * | 3 | * |
4 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | 4 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> |
5 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | 5 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. |
@@ -77,7 +77,7 @@ | |||
77 | * since they may tamper with its fields | 77 | * since they may tamper with its fields |
78 | * - prefix the driver startup messages with the real chip name | 78 | * - prefix the driver startup messages with the real chip name |
79 | * - claim the extra 240 bytes of I/O space for all chips | 79 | * - claim the extra 240 bytes of I/O space for all chips |
80 | * - optimize the rate masking/filtering and the drive list lookup code | 80 | * - optimize the UltraDMA filtering and the drive list lookup code |
81 | * - use pci_get_slot() to get to the function 1 of HPT36x/374 | 81 | * - use pci_get_slot() to get to the function 1 of HPT36x/374 |
82 | * - cache offset of the channel's misc. control registers (MCRs) being used | 82 | * - cache offset of the channel's misc. control registers (MCRs) being used |
83 | * throughout the driver | 83 | * throughout the driver |
@@ -99,9 +99,9 @@ | |||
99 | * stop duplicating it for each channel by storing the pointer in the pci_dev | 99 | * stop duplicating it for each channel by storing the pointer in the pci_dev |
100 | * structure: first, at the init_setup stage, point it to a static "template" | 100 | * structure: first, at the init_setup stage, point it to a static "template" |
101 | * with only the chip type and its specific base DPLL frequency, the highest | 101 | * with only the chip type and its specific base DPLL frequency, the highest |
102 | * supported DMA mode, and the chip settings table pointer filled, then, at | 102 | * UltraDMA mode, and the chip settings table pointer filled, then, at the |
103 | * the init_chipset stage, allocate per-chip instance and fill it with the | 103 | * init_chipset stage, allocate per-chip instance and fill it with the rest |
104 | * rest of the necessary information | 104 | * of the necessary information |
105 | * - get rid of the constant thresholds in the HPT37x PCI clock detection code, | 105 | * - get rid of the constant thresholds in the HPT37x PCI clock detection code, |
106 | * switch to calculating PCI clock frequency based on the chip's base DPLL | 106 | * switch to calculating PCI clock frequency based on the chip's base DPLL |
107 | * frequency | 107 | * frequency |
@@ -112,6 +112,7 @@ | |||
112 | * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips; | 112 | * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips; |
113 | * unify HPT36x/37x timing setup code and the speedproc handlers by joining | 113 | * unify HPT36x/37x timing setup code and the speedproc handlers by joining |
114 | * the register setting lists into the table indexed by the clock selected | 114 | * the register setting lists into the table indexed by the clock selected |
115 | * - set the correct hwif->ultra_mask for each individual chip | ||
115 | * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com> | 116 | * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com> |
116 | */ | 117 | */ |
117 | 118 | ||
@@ -391,7 +392,7 @@ enum ata_clock { | |||
391 | 392 | ||
392 | struct hpt_info { | 393 | struct hpt_info { |
393 | u8 chip_type; /* Chip type */ | 394 | u8 chip_type; /* Chip type */ |
394 | u8 max_mode; /* Speeds allowed */ | 395 | u8 max_ultra; /* Max. UltraDMA mode allowed */ |
395 | u8 dpll_clk; /* DPLL clock in MHz */ | 396 | u8 dpll_clk; /* DPLL clock in MHz */ |
396 | u8 pci_clk; /* PCI clock in MHz */ | 397 | u8 pci_clk; /* PCI clock in MHz */ |
397 | u32 **settings; /* Chipset settings table */ | 398 | u32 **settings; /* Chipset settings table */ |
@@ -430,77 +431,77 @@ static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = { | |||
430 | 431 | ||
431 | static struct hpt_info hpt36x __devinitdata = { | 432 | static struct hpt_info hpt36x __devinitdata = { |
432 | .chip_type = HPT36x, | 433 | .chip_type = HPT36x, |
433 | .max_mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1, | 434 | .max_ultra = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? 4 : 3) : 2, |
434 | .dpll_clk = 0, /* no DPLL */ | 435 | .dpll_clk = 0, /* no DPLL */ |
435 | .settings = hpt36x_settings | 436 | .settings = hpt36x_settings |
436 | }; | 437 | }; |
437 | 438 | ||
438 | static struct hpt_info hpt370 __devinitdata = { | 439 | static struct hpt_info hpt370 __devinitdata = { |
439 | .chip_type = HPT370, | 440 | .chip_type = HPT370, |
440 | .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2, | 441 | .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4, |
441 | .dpll_clk = 48, | 442 | .dpll_clk = 48, |
442 | .settings = hpt37x_settings | 443 | .settings = hpt37x_settings |
443 | }; | 444 | }; |
444 | 445 | ||
445 | static struct hpt_info hpt370a __devinitdata = { | 446 | static struct hpt_info hpt370a __devinitdata = { |
446 | .chip_type = HPT370A, | 447 | .chip_type = HPT370A, |
447 | .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2, | 448 | .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4, |
448 | .dpll_clk = 48, | 449 | .dpll_clk = 48, |
449 | .settings = hpt37x_settings | 450 | .settings = hpt37x_settings |
450 | }; | 451 | }; |
451 | 452 | ||
452 | static struct hpt_info hpt374 __devinitdata = { | 453 | static struct hpt_info hpt374 __devinitdata = { |
453 | .chip_type = HPT374, | 454 | .chip_type = HPT374, |
454 | .max_mode = 3, | 455 | .max_ultra = 5, |
455 | .dpll_clk = 48, | 456 | .dpll_clk = 48, |
456 | .settings = hpt37x_settings | 457 | .settings = hpt37x_settings |
457 | }; | 458 | }; |
458 | 459 | ||
459 | static struct hpt_info hpt372 __devinitdata = { | 460 | static struct hpt_info hpt372 __devinitdata = { |
460 | .chip_type = HPT372, | 461 | .chip_type = HPT372, |
461 | .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3, | 462 | .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5, |
462 | .dpll_clk = 55, | 463 | .dpll_clk = 55, |
463 | .settings = hpt37x_settings | 464 | .settings = hpt37x_settings |
464 | }; | 465 | }; |
465 | 466 | ||
466 | static struct hpt_info hpt372a __devinitdata = { | 467 | static struct hpt_info hpt372a __devinitdata = { |
467 | .chip_type = HPT372A, | 468 | .chip_type = HPT372A, |
468 | .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3, | 469 | .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5, |
469 | .dpll_clk = 66, | 470 | .dpll_clk = 66, |
470 | .settings = hpt37x_settings | 471 | .settings = hpt37x_settings |
471 | }; | 472 | }; |
472 | 473 | ||
473 | static struct hpt_info hpt302 __devinitdata = { | 474 | static struct hpt_info hpt302 __devinitdata = { |
474 | .chip_type = HPT302, | 475 | .chip_type = HPT302, |
475 | .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3, | 476 | .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5, |
476 | .dpll_clk = 66, | 477 | .dpll_clk = 66, |
477 | .settings = hpt37x_settings | 478 | .settings = hpt37x_settings |
478 | }; | 479 | }; |
479 | 480 | ||
480 | static struct hpt_info hpt371 __devinitdata = { | 481 | static struct hpt_info hpt371 __devinitdata = { |
481 | .chip_type = HPT371, | 482 | .chip_type = HPT371, |
482 | .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3, | 483 | .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5, |
483 | .dpll_clk = 66, | 484 | .dpll_clk = 66, |
484 | .settings = hpt37x_settings | 485 | .settings = hpt37x_settings |
485 | }; | 486 | }; |
486 | 487 | ||
487 | static struct hpt_info hpt372n __devinitdata = { | 488 | static struct hpt_info hpt372n __devinitdata = { |
488 | .chip_type = HPT372N, | 489 | .chip_type = HPT372N, |
489 | .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3, | 490 | .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5, |
490 | .dpll_clk = 77, | 491 | .dpll_clk = 77, |
491 | .settings = hpt37x_settings | 492 | .settings = hpt37x_settings |
492 | }; | 493 | }; |
493 | 494 | ||
494 | static struct hpt_info hpt302n __devinitdata = { | 495 | static struct hpt_info hpt302n __devinitdata = { |
495 | .chip_type = HPT302N, | 496 | .chip_type = HPT302N, |
496 | .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3, | 497 | .max_ultra = HPT302_ALLOW_ATA133_6 ? 6 : 5, |
497 | .dpll_clk = 77, | 498 | .dpll_clk = 77, |
498 | .settings = hpt37x_settings | 499 | .settings = hpt37x_settings |
499 | }; | 500 | }; |
500 | 501 | ||
501 | static struct hpt_info hpt371n __devinitdata = { | 502 | static struct hpt_info hpt371n __devinitdata = { |
502 | .chip_type = HPT371N, | 503 | .chip_type = HPT371N, |
503 | .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3, | 504 | .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5, |
504 | .dpll_clk = 77, | 505 | .dpll_clk = 77, |
505 | .settings = hpt37x_settings | 506 | .settings = hpt37x_settings |
506 | }; | 507 | }; |
@@ -523,53 +524,38 @@ static int check_in_drive_list(ide_drive_t *drive, const char **list) | |||
523 | static u8 hpt3xx_udma_filter(ide_drive_t *drive) | 524 | static u8 hpt3xx_udma_filter(ide_drive_t *drive) |
524 | { | 525 | { |
525 | struct hpt_info *info = pci_get_drvdata(HWIF(drive)->pci_dev); | 526 | struct hpt_info *info = pci_get_drvdata(HWIF(drive)->pci_dev); |
526 | u8 chip_type = info->chip_type; | ||
527 | u8 mode = info->max_mode; | ||
528 | u8 mask; | 527 | u8 mask; |
529 | 528 | ||
530 | switch (mode) { | 529 | switch (info->chip_type) { |
531 | case 0x04: | 530 | case HPT370A: |
532 | mask = 0x7f; | 531 | if (!HPT370_ALLOW_ATA100_5 || |
533 | break; | 532 | check_in_drive_list(drive, bad_ata100_5)) |
534 | case 0x03: | 533 | return 0x1f; |
534 | else | ||
535 | return 0x3f; | ||
536 | case HPT370: | ||
537 | if (!HPT370_ALLOW_ATA100_5 || | ||
538 | check_in_drive_list(drive, bad_ata100_5)) | ||
539 | mask = 0x1f; | ||
540 | else | ||
535 | mask = 0x3f; | 541 | mask = 0x3f; |
536 | if (chip_type >= HPT374) | 542 | break; |
537 | break; | 543 | case HPT36x: |
538 | if (!check_in_drive_list(drive, bad_ata100_5)) | 544 | if (!HPT366_ALLOW_ATA66_4 || |
539 | goto check_bad_ata33; | 545 | check_in_drive_list(drive, bad_ata66_4)) |
540 | /* fall thru */ | 546 | mask = 0x0f; |
541 | case 0x02: | 547 | else |
542 | mask = 0x1f; | 548 | mask = 0x1f; |
543 | 549 | ||
544 | /* | 550 | if (!HPT366_ALLOW_ATA66_3 || |
545 | * CHECK ME, Does this need to be changed to HPT374 ?? | 551 | check_in_drive_list(drive, bad_ata66_3)) |
546 | */ | ||
547 | if (chip_type >= HPT370) | ||
548 | goto check_bad_ata33; | ||
549 | if (HPT366_ALLOW_ATA66_4 && | ||
550 | !check_in_drive_list(drive, bad_ata66_4)) | ||
551 | goto check_bad_ata33; | ||
552 | |||
553 | mask = 0x0f; | ||
554 | if (HPT366_ALLOW_ATA66_3 && | ||
555 | !check_in_drive_list(drive, bad_ata66_3)) | ||
556 | goto check_bad_ata33; | ||
557 | /* fall thru */ | ||
558 | case 0x01: | ||
559 | mask = 0x07; | 552 | mask = 0x07; |
560 | 553 | break; | |
561 | check_bad_ata33: | 554 | default: |
562 | if (chip_type >= HPT370A) | 555 | return 0x7f; |
563 | break; | ||
564 | if (!check_in_drive_list(drive, bad_ata33)) | ||
565 | break; | ||
566 | /* fall thru */ | ||
567 | case 0x00: | ||
568 | default: | ||
569 | mask = 0x00; | ||
570 | break; | ||
571 | } | 556 | } |
572 | return mask; | 557 | |
558 | return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask; | ||
573 | } | 559 | } |
574 | 560 | ||
575 | static u32 get_speed_setting(u8 speed, struct hpt_info *info) | 561 | static u32 get_speed_setting(u8 speed, struct hpt_info *info) |
@@ -1150,7 +1136,7 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha | |||
1150 | * Select 66 MHz DPLL clock only if UltraATA/133 mode is | 1136 | * Select 66 MHz DPLL clock only if UltraATA/133 mode is |
1151 | * supported/enabled, use 50 MHz DPLL clock otherwise... | 1137 | * supported/enabled, use 50 MHz DPLL clock otherwise... |
1152 | */ | 1138 | */ |
1153 | if (info->max_mode == 0x04) { | 1139 | if (info->max_ultra == 6) { |
1154 | dpll_clk = 66; | 1140 | dpll_clk = 66; |
1155 | clock = ATA_CLOCK_66MHZ; | 1141 | clock = ATA_CLOCK_66MHZ; |
1156 | } else if (dpll_clk) { /* HPT36x chips don't have DPLL */ | 1142 | } else if (dpll_clk) { /* HPT36x chips don't have DPLL */ |
@@ -1243,7 +1229,7 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) | |||
1243 | struct pci_dev *dev = hwif->pci_dev; | 1229 | struct pci_dev *dev = hwif->pci_dev; |
1244 | struct hpt_info *info = pci_get_drvdata(dev); | 1230 | struct hpt_info *info = pci_get_drvdata(dev); |
1245 | int serialize = HPT_SERIALIZE_IO; | 1231 | int serialize = HPT_SERIALIZE_IO; |
1246 | u8 scr1 = 0, ata66 = (hwif->channel) ? 0x01 : 0x02; | 1232 | u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02; |
1247 | u8 chip_type = info->chip_type; | 1233 | u8 chip_type = info->chip_type; |
1248 | u8 new_mcr, old_mcr = 0; | 1234 | u8 new_mcr, old_mcr = 0; |
1249 | 1235 | ||
@@ -1256,7 +1242,9 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) | |||
1256 | hwif->intrproc = &hpt3xx_intrproc; | 1242 | hwif->intrproc = &hpt3xx_intrproc; |
1257 | hwif->maskproc = &hpt3xx_maskproc; | 1243 | hwif->maskproc = &hpt3xx_maskproc; |
1258 | hwif->busproc = &hpt3xx_busproc; | 1244 | hwif->busproc = &hpt3xx_busproc; |
1259 | hwif->udma_filter = &hpt3xx_udma_filter; | 1245 | |
1246 | if (chip_type <= HPT370A) | ||
1247 | hwif->udma_filter = &hpt3xx_udma_filter; | ||
1260 | 1248 | ||
1261 | /* | 1249 | /* |
1262 | * HPT3xxN chips have some complications: | 1250 | * HPT3xxN chips have some complications: |
@@ -1305,7 +1293,7 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) | |||
1305 | return; | 1293 | return; |
1306 | } | 1294 | } |
1307 | 1295 | ||
1308 | hwif->ultra_mask = 0x7f; | 1296 | hwif->ultra_mask = hwif->cds->udma_mask; |
1309 | hwif->mwdma_mask = 0x07; | 1297 | hwif->mwdma_mask = 0x07; |
1310 | 1298 | ||
1311 | /* | 1299 | /* |
@@ -1503,9 +1491,35 @@ static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d) | |||
1503 | 1491 | ||
1504 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); | 1492 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); |
1505 | 1493 | ||
1506 | if (rev > 6) | 1494 | switch (rev) { |
1495 | case 0: | ||
1496 | case 1: | ||
1497 | case 2: | ||
1498 | /* | ||
1499 | * HPT36x chips have one channel per function and have | ||
1500 | * both channel enable bits located differently and visible | ||
1501 | * to both functions -- really stupid design decision... :-( | ||
1502 | * Bit 4 is for the primary channel, bit 5 for the secondary. | ||
1503 | */ | ||
1504 | d->channels = 1; | ||
1505 | d->enablebits[0].mask = d->enablebits[0].val = 0x10; | ||
1506 | |||
1507 | d->udma_mask = HPT366_ALLOW_ATA66_3 ? | ||
1508 | (HPT366_ALLOW_ATA66_4 ? 0x1f : 0x0f) : 0x07; | ||
1509 | break; | ||
1510 | case 3: | ||
1511 | case 4: | ||
1512 | d->udma_mask = HPT370_ALLOW_ATA100_5 ? 0x3f : 0x1f; | ||
1513 | break; | ||
1514 | default: | ||
1507 | rev = 6; | 1515 | rev = 6; |
1508 | 1516 | /* fall thru */ | |
1517 | case 5: | ||
1518 | case 6: | ||
1519 | d->udma_mask = HPT372_ALLOW_ATA133_6 ? 0x7f : 0x3f; | ||
1520 | break; | ||
1521 | } | ||
1522 | |||
1509 | d->name = chipset_names[rev]; | 1523 | d->name = chipset_names[rev]; |
1510 | 1524 | ||
1511 | pci_set_drvdata(dev, info[rev]); | 1525 | pci_set_drvdata(dev, info[rev]); |
@@ -1513,15 +1527,6 @@ static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d) | |||
1513 | if (rev > 2) | 1527 | if (rev > 2) |
1514 | goto init_single; | 1528 | goto init_single; |
1515 | 1529 | ||
1516 | /* | ||
1517 | * HPT36x chips have one channel per function and have | ||
1518 | * both channel enable bits located differently and visible | ||
1519 | * to both functions -- really stupid design decision... :-( | ||
1520 | * Bit 4 is for the primary channel, bit 5 for the secondary. | ||
1521 | */ | ||
1522 | d->channels = 1; | ||
1523 | d->enablebits[0].mask = d->enablebits[0].val = 0x10; | ||
1524 | |||
1525 | if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) { | 1530 | if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) { |
1526 | u8 mcr1 = 0, pin1 = 0, pin2 = 0; | 1531 | u8 mcr1 = 0, pin1 = 0, pin2 = 0; |
1527 | int ret; | 1532 | int ret; |
@@ -1573,6 +1578,7 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = { | |||
1573 | .channels = 2, | 1578 | .channels = 2, |
1574 | .autodma = AUTODMA, | 1579 | .autodma = AUTODMA, |
1575 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, | 1580 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
1581 | .udma_mask = HPT372_ALLOW_ATA133_6 ? 0x7f : 0x3f, | ||
1576 | .bootable = OFF_BOARD, | 1582 | .bootable = OFF_BOARD, |
1577 | .extra = 240 | 1583 | .extra = 240 |
1578 | },{ /* 2 */ | 1584 | },{ /* 2 */ |
@@ -1584,6 +1590,7 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = { | |||
1584 | .channels = 2, | 1590 | .channels = 2, |
1585 | .autodma = AUTODMA, | 1591 | .autodma = AUTODMA, |
1586 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, | 1592 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
1593 | .udma_mask = HPT302_ALLOW_ATA133_6 ? 0x7f : 0x3f, | ||
1587 | .bootable = OFF_BOARD, | 1594 | .bootable = OFF_BOARD, |
1588 | .extra = 240 | 1595 | .extra = 240 |
1589 | },{ /* 3 */ | 1596 | },{ /* 3 */ |
@@ -1595,6 +1602,7 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = { | |||
1595 | .channels = 2, | 1602 | .channels = 2, |
1596 | .autodma = AUTODMA, | 1603 | .autodma = AUTODMA, |
1597 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, | 1604 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
1605 | .udma_mask = HPT371_ALLOW_ATA133_6 ? 0x7f : 0x3f, | ||
1598 | .bootable = OFF_BOARD, | 1606 | .bootable = OFF_BOARD, |
1599 | .extra = 240 | 1607 | .extra = 240 |
1600 | },{ /* 4 */ | 1608 | },{ /* 4 */ |
@@ -1606,6 +1614,7 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = { | |||
1606 | .channels = 2, /* 4 */ | 1614 | .channels = 2, /* 4 */ |
1607 | .autodma = AUTODMA, | 1615 | .autodma = AUTODMA, |
1608 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, | 1616 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
1617 | .udma_mask = 0x3f, | ||
1609 | .bootable = OFF_BOARD, | 1618 | .bootable = OFF_BOARD, |
1610 | .extra = 240 | 1619 | .extra = 240 |
1611 | },{ /* 5 */ | 1620 | },{ /* 5 */ |
@@ -1617,6 +1626,7 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = { | |||
1617 | .channels = 2, /* 4 */ | 1626 | .channels = 2, /* 4 */ |
1618 | .autodma = AUTODMA, | 1627 | .autodma = AUTODMA, |
1619 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, | 1628 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
1629 | .udma_mask = HPT372_ALLOW_ATA133_6 ? 0x7f : 0x3f, | ||
1620 | .bootable = OFF_BOARD, | 1630 | .bootable = OFF_BOARD, |
1621 | .extra = 240 | 1631 | .extra = 240 |
1622 | } | 1632 | } |