diff options
Diffstat (limited to 'drivers/ide/pci/cy82c693.c')
-rw-r--r-- | drivers/ide/pci/cy82c693.c | 124 |
1 files changed, 6 insertions, 118 deletions
diff --git a/drivers/ide/pci/cy82c693.c b/drivers/ide/pci/cy82c693.c index 69820e9224d1..5297f07d2933 100644 --- a/drivers/ide/pci/cy82c693.c +++ b/drivers/ide/pci/cy82c693.c | |||
@@ -50,18 +50,11 @@ | |||
50 | 50 | ||
51 | #define DRV_NAME "cy82c693" | 51 | #define DRV_NAME "cy82c693" |
52 | 52 | ||
53 | /* the current version */ | ||
54 | #define CY82_VERSION "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)" | ||
55 | |||
56 | /* | 53 | /* |
57 | * The following are used to debug the driver. | 54 | * The following are used to debug the driver. |
58 | */ | 55 | */ |
59 | #define CY82C693_DEBUG_LOGS 0 | ||
60 | #define CY82C693_DEBUG_INFO 0 | 56 | #define CY82C693_DEBUG_INFO 0 |
61 | 57 | ||
62 | /* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */ | ||
63 | #undef CY82C693_SETDMA_CLOCK | ||
64 | |||
65 | /* | 58 | /* |
66 | * NOTE: the value for busmaster timeout is tricky and I got it by | 59 | * NOTE: the value for busmaster timeout is tricky and I got it by |
67 | * trial and error! By using a to low value will cause DMA timeouts | 60 | * trial and error! By using a to low value will cause DMA timeouts |
@@ -89,7 +82,6 @@ | |||
89 | #define CY82_INDEX_PORT 0x22 | 82 | #define CY82_INDEX_PORT 0x22 |
90 | #define CY82_DATA_PORT 0x23 | 83 | #define CY82_DATA_PORT 0x23 |
91 | 84 | ||
92 | #define CY82_INDEX_CTRLREG1 0x01 | ||
93 | #define CY82_INDEX_CHANNEL0 0x30 | 85 | #define CY82_INDEX_CHANNEL0 0x30 |
94 | #define CY82_INDEX_CHANNEL1 0x31 | 86 | #define CY82_INDEX_CHANNEL1 0x31 |
95 | #define CY82_INDEX_TIMEOUT 0x32 | 87 | #define CY82_INDEX_TIMEOUT 0x32 |
@@ -179,17 +171,6 @@ static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode) | |||
179 | 171 | ||
180 | index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0; | 172 | index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0; |
181 | 173 | ||
182 | #if CY82C693_DEBUG_LOGS | ||
183 | /* for debug let's show the previous values */ | ||
184 | |||
185 | outb(index, CY82_INDEX_PORT); | ||
186 | data = inb(CY82_DATA_PORT); | ||
187 | |||
188 | printk(KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n", | ||
189 | drive->name, HWIF(drive)->channel, drive->select.b.unit, | ||
190 | (data&0x3), ((data>>2)&1)); | ||
191 | #endif /* CY82C693_DEBUG_LOGS */ | ||
192 | |||
193 | data = (mode & 3) | (single << 2); | 174 | data = (mode & 3) | (single << 2); |
194 | 175 | ||
195 | outb(index, CY82_INDEX_PORT); | 176 | outb(index, CY82_INDEX_PORT); |
@@ -197,8 +178,7 @@ static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode) | |||
197 | 178 | ||
198 | #if CY82C693_DEBUG_INFO | 179 | #if CY82C693_DEBUG_INFO |
199 | printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n", | 180 | printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n", |
200 | drive->name, HWIF(drive)->channel, drive->select.b.unit, | 181 | drive->name, hwif->channel, drive->dn & 1, mode & 3, single); |
201 | mode & 3, single); | ||
202 | #endif /* CY82C693_DEBUG_INFO */ | 182 | #endif /* CY82C693_DEBUG_INFO */ |
203 | 183 | ||
204 | /* | 184 | /* |
@@ -239,50 +219,11 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) | |||
239 | } | 219 | } |
240 | } | 220 | } |
241 | 221 | ||
242 | #if CY82C693_DEBUG_LOGS | ||
243 | /* for debug let's show the register values */ | ||
244 | |||
245 | if (drive->select.b.unit == 0) { | ||
246 | /* | ||
247 | * get master drive registers | ||
248 | * address setup control register | ||
249 | * is 32 bit !!! | ||
250 | */ | ||
251 | pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); | ||
252 | addrCtrl &= 0x0F; | ||
253 | |||
254 | /* now let's get the remaining registers */ | ||
255 | pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r); | ||
256 | pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w); | ||
257 | pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8); | ||
258 | } else { | ||
259 | /* | ||
260 | * set slave drive registers | ||
261 | * address setup control register | ||
262 | * is 32 bit !!! | ||
263 | */ | ||
264 | pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); | ||
265 | |||
266 | addrCtrl &= 0xF0; | ||
267 | addrCtrl >>= 4; | ||
268 | |||
269 | /* now let's get the remaining registers */ | ||
270 | pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r); | ||
271 | pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w); | ||
272 | pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8); | ||
273 | } | ||
274 | |||
275 | printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is " | ||
276 | "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n", | ||
277 | drive->name, hwif->channel, drive->select.b.unit, | ||
278 | addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8); | ||
279 | #endif /* CY82C693_DEBUG_LOGS */ | ||
280 | |||
281 | /* let's calc the values for this PIO mode */ | 222 | /* let's calc the values for this PIO mode */ |
282 | compute_clocks(pio, &pclk); | 223 | compute_clocks(pio, &pclk); |
283 | 224 | ||
284 | /* now let's write the clocks registers */ | 225 | /* now let's write the clocks registers */ |
285 | if (drive->select.b.unit == 0) { | 226 | if ((drive->dn & 1) == 0) { |
286 | /* | 227 | /* |
287 | * set master drive | 228 | * set master drive |
288 | * address setup control register | 229 | * address setup control register |
@@ -324,63 +265,11 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) | |||
324 | #if CY82C693_DEBUG_INFO | 265 | #if CY82C693_DEBUG_INFO |
325 | printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to " | 266 | printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to " |
326 | "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n", | 267 | "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n", |
327 | drive->name, hwif->channel, drive->select.b.unit, | 268 | drive->name, hwif->channel, drive->dn & 1, |
328 | addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8); | 269 | addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8); |
329 | #endif /* CY82C693_DEBUG_INFO */ | 270 | #endif /* CY82C693_DEBUG_INFO */ |
330 | } | 271 | } |
331 | 272 | ||
332 | /* | ||
333 | * this function is called during init and is used to setup the cy82c693 chip | ||
334 | */ | ||
335 | static unsigned int init_chipset_cy82c693(struct pci_dev *dev) | ||
336 | { | ||
337 | if (PCI_FUNC(dev->devfn) != 1) | ||
338 | return 0; | ||
339 | |||
340 | #ifdef CY82C693_SETDMA_CLOCK | ||
341 | u8 data = 0; | ||
342 | #endif /* CY82C693_SETDMA_CLOCK */ | ||
343 | |||
344 | /* write info about this verion of the driver */ | ||
345 | printk(KERN_INFO CY82_VERSION "\n"); | ||
346 | |||
347 | #ifdef CY82C693_SETDMA_CLOCK | ||
348 | /* okay let's set the DMA clock speed */ | ||
349 | |||
350 | outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT); | ||
351 | data = inb(CY82_DATA_PORT); | ||
352 | |||
353 | #if CY82C693_DEBUG_INFO | ||
354 | printk(KERN_INFO DRV_NAME ": Peripheral Configuration Register: 0x%X\n", | ||
355 | data); | ||
356 | #endif /* CY82C693_DEBUG_INFO */ | ||
357 | |||
358 | /* | ||
359 | * for some reason sometimes the DMA controller | ||
360 | * speed is set to ATCLK/2 ???? - we fix this here | ||
361 | * | ||
362 | * note: i don't know what causes this strange behaviour, | ||
363 | * but even changing the dma speed doesn't solve it :-( | ||
364 | * the ide performance is still only half the normal speed | ||
365 | * | ||
366 | * if anybody knows what goes wrong with my machine, please | ||
367 | * let me know - ASK | ||
368 | */ | ||
369 | |||
370 | data |= 0x03; | ||
371 | |||
372 | outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT); | ||
373 | outb(data, CY82_DATA_PORT); | ||
374 | |||
375 | #if CY82C693_DEBUG_INFO | ||
376 | printk(KERN_INFO ": New Peripheral Configuration Register: 0x%X\n", | ||
377 | data); | ||
378 | #endif /* CY82C693_DEBUG_INFO */ | ||
379 | |||
380 | #endif /* CY82C693_SETDMA_CLOCK */ | ||
381 | return 0; | ||
382 | } | ||
383 | |||
384 | static void __devinit init_iops_cy82c693(ide_hwif_t *hwif) | 273 | static void __devinit init_iops_cy82c693(ide_hwif_t *hwif) |
385 | { | 274 | { |
386 | static ide_hwif_t *primary; | 275 | static ide_hwif_t *primary; |
@@ -401,7 +290,6 @@ static const struct ide_port_ops cy82c693_port_ops = { | |||
401 | 290 | ||
402 | static const struct ide_port_info cy82c693_chipset __devinitdata = { | 291 | static const struct ide_port_info cy82c693_chipset __devinitdata = { |
403 | .name = DRV_NAME, | 292 | .name = DRV_NAME, |
404 | .init_chipset = init_chipset_cy82c693, | ||
405 | .init_iops = init_iops_cy82c693, | 293 | .init_iops = init_iops_cy82c693, |
406 | .port_ops = &cy82c693_port_ops, | 294 | .port_ops = &cy82c693_port_ops, |
407 | .chipset = ide_cy82c693, | 295 | .chipset = ide_cy82c693, |
@@ -443,7 +331,7 @@ static const struct pci_device_id cy82c693_pci_tbl[] = { | |||
443 | }; | 331 | }; |
444 | MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl); | 332 | MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl); |
445 | 333 | ||
446 | static struct pci_driver driver = { | 334 | static struct pci_driver cy82c693_pci_driver = { |
447 | .name = "Cypress_IDE", | 335 | .name = "Cypress_IDE", |
448 | .id_table = cy82c693_pci_tbl, | 336 | .id_table = cy82c693_pci_tbl, |
449 | .probe = cy82c693_init_one, | 337 | .probe = cy82c693_init_one, |
@@ -454,12 +342,12 @@ static struct pci_driver driver = { | |||
454 | 342 | ||
455 | static int __init cy82c693_ide_init(void) | 343 | static int __init cy82c693_ide_init(void) |
456 | { | 344 | { |
457 | return ide_pci_register_driver(&driver); | 345 | return ide_pci_register_driver(&cy82c693_pci_driver); |
458 | } | 346 | } |
459 | 347 | ||
460 | static void __exit cy82c693_ide_exit(void) | 348 | static void __exit cy82c693_ide_exit(void) |
461 | { | 349 | { |
462 | pci_unregister_driver(&driver); | 350 | pci_unregister_driver(&cy82c693_pci_driver); |
463 | } | 351 | } |
464 | 352 | ||
465 | module_init(cy82c693_ide_init); | 353 | module_init(cy82c693_ide_init); |