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Diffstat (limited to 'drivers/ide/pci/cs5530.c')
-rw-r--r--drivers/ide/pci/cs5530.c294
1 files changed, 0 insertions, 294 deletions
diff --git a/drivers/ide/pci/cs5530.c b/drivers/ide/pci/cs5530.c
deleted file mode 100644
index 53f079cc00af..000000000000
--- a/drivers/ide/pci/cs5530.c
+++ /dev/null
@@ -1,294 +0,0 @@
1/*
2 * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2000 Mark Lord <mlord@pobox.com>
4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5 *
6 * May be copied or modified under the terms of the GNU General Public License
7 *
8 * Development of this chipset driver was funded
9 * by the nice folks at National Semiconductor.
10 *
11 * Documentation:
12 * CS5530 documentation available from National Semiconductor.
13 */
14
15#include <linux/module.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/ide.h>
21
22#include <asm/io.h>
23
24#define DRV_NAME "cs5530"
25
26/*
27 * Here are the standard PIO mode 0-4 timings for each "format".
28 * Format-0 uses fast data reg timings, with slower command reg timings.
29 * Format-1 uses fast timings for all registers, but won't work with all drives.
30 */
31static unsigned int cs5530_pio_timings[2][5] = {
32 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
33 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
34};
35
36/*
37 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
38 */
39#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
40#define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
41
42/**
43 * cs5530_set_pio_mode - set host controller for PIO mode
44 * @drive: drive
45 * @pio: PIO mode number
46 *
47 * Handles setting of PIO mode for the chipset.
48 *
49 * The init_hwif_cs5530() routine guarantees that all drives
50 * will have valid default PIO timings set up before we get here.
51 */
52
53static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio)
54{
55 unsigned long basereg = CS5530_BASEREG(drive->hwif);
56 unsigned int format = (inl(basereg + 4) >> 31) & 1;
57
58 outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
59}
60
61/**
62 * cs5530_udma_filter - UDMA filter
63 * @drive: drive
64 *
65 * cs5530_udma_filter() does UDMA mask filtering for the given drive
66 * taking into the consideration capabilities of the mate device.
67 *
68 * The CS5530 specifies that two drives sharing a cable cannot mix
69 * UDMA/MDMA. It has to be one or the other, for the pair, though
70 * different timings can still be chosen for each drive. We could
71 * set the appropriate timing bits on the fly, but that might be
72 * a bit confusing. So, for now we statically handle this requirement
73 * by looking at our mate drive to see what it is capable of, before
74 * choosing a mode for our own drive.
75 *
76 * Note: This relies on the fact we never fail from UDMA to MWDMA2
77 * but instead drop to PIO.
78 */
79
80static u8 cs5530_udma_filter(ide_drive_t *drive)
81{
82 ide_hwif_t *hwif = drive->hwif;
83 ide_drive_t *mate = ide_get_pair_dev(drive);
84 u16 *mateid = mate->id;
85 u8 mask = hwif->ultra_mask;
86
87 if (mate == NULL)
88 goto out;
89
90 if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
91 if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
92 (mateid[ATA_ID_UDMA_MODES] & 7))
93 goto out;
94 if ((mateid[ATA_ID_FIELD_VALID] & 2) &&
95 (mateid[ATA_ID_MWDMA_MODES] & 7))
96 mask = 0;
97 }
98out:
99 return mask;
100}
101
102static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
103{
104 unsigned long basereg;
105 unsigned int reg, timings = 0;
106
107 switch (mode) {
108 case XFER_UDMA_0: timings = 0x00921250; break;
109 case XFER_UDMA_1: timings = 0x00911140; break;
110 case XFER_UDMA_2: timings = 0x00911030; break;
111 case XFER_MW_DMA_0: timings = 0x00077771; break;
112 case XFER_MW_DMA_1: timings = 0x00012121; break;
113 case XFER_MW_DMA_2: timings = 0x00002020; break;
114 }
115 basereg = CS5530_BASEREG(drive->hwif);
116 reg = inl(basereg + 4); /* get drive0 config register */
117 timings |= reg & 0x80000000; /* preserve PIO format bit */
118 if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */
119 outl(timings, basereg + 4); /* write drive0 config register */
120 } else {
121 if (timings & 0x00100000)
122 reg |= 0x00100000; /* enable UDMA timings for both drives */
123 else
124 reg &= ~0x00100000; /* disable UDMA timings for both drives */
125 outl(reg, basereg + 4); /* write drive0 config register */
126 outl(timings, basereg + 12); /* write drive1 config register */
127 }
128}
129
130/**
131 * init_chipset_5530 - set up 5530 bridge
132 * @dev: PCI device
133 *
134 * Initialize the cs5530 bridge for reliable IDE DMA operation.
135 */
136
137static unsigned int init_chipset_cs5530(struct pci_dev *dev)
138{
139 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
140
141 if (pci_resource_start(dev, 4) == 0)
142 return -EFAULT;
143
144 dev = NULL;
145 while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
146 switch (dev->device) {
147 case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
148 master_0 = pci_dev_get(dev);
149 break;
150 case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
151 cs5530_0 = pci_dev_get(dev);
152 break;
153 }
154 }
155 if (!master_0) {
156 printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
157 goto out;
158 }
159 if (!cs5530_0) {
160 printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
161 goto out;
162 }
163
164 /*
165 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
166 * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
167 */
168
169 pci_set_master(cs5530_0);
170 pci_try_set_mwi(cs5530_0);
171
172 /*
173 * Set PCI CacheLineSize to 16-bytes:
174 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
175 */
176
177 pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
178
179 /*
180 * Disable trapping of UDMA register accesses (Win98 hack):
181 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
182 */
183
184 pci_write_config_word(cs5530_0, 0xd0, 0x5006);
185
186 /*
187 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
188 * The other settings are what is necessary to get the register
189 * into a sane state for IDE DMA operation.
190 */
191
192 pci_write_config_byte(master_0, 0x40, 0x1e);
193
194 /*
195 * Set max PCI burst size (16-bytes seems to work best):
196 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
197 * all others: clear bit-1 at 0x41, and do:
198 * 128bytes: OR 0x00 at 0x41
199 * 256bytes: OR 0x04 at 0x41
200 * 512bytes: OR 0x08 at 0x41
201 * 1024bytes: OR 0x0c at 0x41
202 */
203
204 pci_write_config_byte(master_0, 0x41, 0x14);
205
206 /*
207 * These settings are necessary to get the chip
208 * into a sane state for IDE DMA operation.
209 */
210
211 pci_write_config_byte(master_0, 0x42, 0x00);
212 pci_write_config_byte(master_0, 0x43, 0xc1);
213
214out:
215 pci_dev_put(master_0);
216 pci_dev_put(cs5530_0);
217 return 0;
218}
219
220/**
221 * init_hwif_cs5530 - initialise an IDE channel
222 * @hwif: IDE to initialize
223 *
224 * This gets invoked by the IDE driver once for each channel. It
225 * performs channel-specific pre-initialization before drive probing.
226 */
227
228static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
229{
230 unsigned long basereg;
231 u32 d0_timings;
232
233 basereg = CS5530_BASEREG(hwif);
234 d0_timings = inl(basereg + 0);
235 if (CS5530_BAD_PIO(d0_timings))
236 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
237 if (CS5530_BAD_PIO(inl(basereg + 8)))
238 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
239}
240
241static const struct ide_port_ops cs5530_port_ops = {
242 .set_pio_mode = cs5530_set_pio_mode,
243 .set_dma_mode = cs5530_set_dma_mode,
244 .udma_filter = cs5530_udma_filter,
245};
246
247static const struct ide_port_info cs5530_chipset __devinitdata = {
248 .name = DRV_NAME,
249 .init_chipset = init_chipset_cs5530,
250 .init_hwif = init_hwif_cs5530,
251 .port_ops = &cs5530_port_ops,
252 .host_flags = IDE_HFLAG_SERIALIZE |
253 IDE_HFLAG_POST_SET_MODE,
254 .pio_mask = ATA_PIO4,
255 .mwdma_mask = ATA_MWDMA2,
256 .udma_mask = ATA_UDMA2,
257};
258
259static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
260{
261 return ide_pci_init_one(dev, &cs5530_chipset, NULL);
262}
263
264static const struct pci_device_id cs5530_pci_tbl[] = {
265 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), 0 },
266 { 0, },
267};
268MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
269
270static struct pci_driver cs5530_pci_driver = {
271 .name = "CS5530 IDE",
272 .id_table = cs5530_pci_tbl,
273 .probe = cs5530_init_one,
274 .remove = ide_pci_remove,
275 .suspend = ide_pci_suspend,
276 .resume = ide_pci_resume,
277};
278
279static int __init cs5530_ide_init(void)
280{
281 return ide_pci_register_driver(&cs5530_pci_driver);
282}
283
284static void __exit cs5530_ide_exit(void)
285{
286 pci_unregister_driver(&cs5530_pci_driver);
287}
288
289module_init(cs5530_ide_init);
290module_exit(cs5530_ide_exit);
291
292MODULE_AUTHOR("Mark Lord");
293MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
294MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 09:02:36 -0500