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path: root/drivers/ide/pci/cmd64x.c
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Diffstat (limited to 'drivers/ide/pci/cmd64x.c')
-rw-r--r--drivers/ide/pci/cmd64x.c821
1 files changed, 821 insertions, 0 deletions
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c
new file mode 100644
index 000000000000..3de9ab897e42
--- /dev/null
+++ b/drivers/ide/pci/cmd64x.c
@@ -0,0 +1,821 @@
1/* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16
2 *
3 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
4 *
5 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
6 * Note, this driver is not used at all on other systems because
7 * there the "BIOS" has done all of the following already.
8 * Due to massive hardware bugs, UltraDMA is only supported
9 * on the 646U2 and not on the 646U.
10 *
11 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
12 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
13 *
14 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
15 */
16
17#include <linux/config.h>
18#include <linux/module.h>
19#include <linux/types.h>
20#include <linux/pci.h>
21#include <linux/delay.h>
22#include <linux/hdreg.h>
23#include <linux/ide.h>
24#include <linux/init.h>
25
26#include <asm/io.h>
27
28#define DISPLAY_CMD64X_TIMINGS
29
30#define CMD_DEBUG 0
31
32#if CMD_DEBUG
33#define cmdprintk(x...) printk(x)
34#else
35#define cmdprintk(x...)
36#endif
37
38/*
39 * CMD64x specific registers definition.
40 */
41#define CFR 0x50
42#define CFR_INTR_CH0 0x02
43#define CNTRL 0x51
44#define CNTRL_DIS_RA0 0x40
45#define CNTRL_DIS_RA1 0x80
46#define CNTRL_ENA_2ND 0x08
47
48#define CMDTIM 0x52
49#define ARTTIM0 0x53
50#define DRWTIM0 0x54
51#define ARTTIM1 0x55
52#define DRWTIM1 0x56
53#define ARTTIM23 0x57
54#define ARTTIM23_DIS_RA2 0x04
55#define ARTTIM23_DIS_RA3 0x08
56#define ARTTIM23_INTR_CH1 0x10
57#define ARTTIM2 0x57
58#define ARTTIM3 0x57
59#define DRWTIM23 0x58
60#define DRWTIM2 0x58
61#define BRST 0x59
62#define DRWTIM3 0x5b
63
64#define BMIDECR0 0x70
65#define MRDMODE 0x71
66#define MRDMODE_INTR_CH0 0x04
67#define MRDMODE_INTR_CH1 0x08
68#define MRDMODE_BLK_CH0 0x10
69#define MRDMODE_BLK_CH1 0x20
70#define BMIDESR0 0x72
71#define UDIDETCR0 0x73
72#define DTPR0 0x74
73#define BMIDECR1 0x78
74#define BMIDECSR 0x79
75#define BMIDESR1 0x7A
76#define UDIDETCR1 0x7B
77#define DTPR1 0x7C
78
79#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
80#include <linux/stat.h>
81#include <linux/proc_fs.h>
82
83static u8 cmd64x_proc = 0;
84
85#define CMD_MAX_DEVS 5
86
87static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
88static int n_cmd_devs;
89
90static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
91{
92 char *p = buf;
93
94 u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0; /* primary */
95 u8 reg57 = 0, reg58 = 0, reg5b; /* secondary */
96 u8 reg72 = 0, reg73 = 0; /* primary */
97 u8 reg7a = 0, reg7b = 0; /* secondary */
98 u8 reg50 = 0, reg71 = 0; /* extra */
99
100 p += sprintf(p, "\nController: %d\n", index);
101 p += sprintf(p, "CMD%x Chipset.\n", dev->device);
102 (void) pci_read_config_byte(dev, CFR, &reg50);
103 (void) pci_read_config_byte(dev, ARTTIM0, &reg53);
104 (void) pci_read_config_byte(dev, DRWTIM0, &reg54);
105 (void) pci_read_config_byte(dev, ARTTIM1, &reg55);
106 (void) pci_read_config_byte(dev, DRWTIM1, &reg56);
107 (void) pci_read_config_byte(dev, ARTTIM2, &reg57);
108 (void) pci_read_config_byte(dev, DRWTIM2, &reg58);
109 (void) pci_read_config_byte(dev, DRWTIM3, &reg5b);
110 (void) pci_read_config_byte(dev, MRDMODE, &reg71);
111 (void) pci_read_config_byte(dev, BMIDESR0, &reg72);
112 (void) pci_read_config_byte(dev, UDIDETCR0, &reg73);
113 (void) pci_read_config_byte(dev, BMIDESR1, &reg7a);
114 (void) pci_read_config_byte(dev, UDIDETCR1, &reg7b);
115
116 p += sprintf(p, "--------------- Primary Channel "
117 "---------------- Secondary Channel "
118 "-------------\n");
119 p += sprintf(p, " %sabled "
120 " %sabled\n",
121 (reg72&0x80)?"dis":" en",
122 (reg7a&0x80)?"dis":" en");
123 p += sprintf(p, "--------------- drive0 "
124 "--------- drive1 -------- drive0 "
125 "---------- drive1 ------\n");
126 p += sprintf(p, "DMA enabled: %s %s"
127 " %s %s\n",
128 (reg72&0x20)?"yes":"no ", (reg72&0x40)?"yes":"no ",
129 (reg7a&0x20)?"yes":"no ", (reg7a&0x40)?"yes":"no ");
130
131 p += sprintf(p, "DMA Mode: %s(%s) %s(%s)",
132 (reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO",
133 (reg72&0x20)?(
134 ((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"):
135 ((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"):
136 ((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"):
137 ((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"):
138 "X"):"?",
139 (reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO",
140 (reg72&0x40)?(
141 ((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"):
142 ((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"):
143 ((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"):
144 ((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"):
145 "X"):"?");
146 p += sprintf(p, " %s(%s) %s(%s)\n",
147 (reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO",
148 (reg7a&0x20)?(
149 ((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"):
150 ((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"):
151 ((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"):
152 ((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"):
153 "X"):"?",
154 (reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO",
155 (reg7a&0x40)?(
156 ((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"):
157 ((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"):
158 ((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"):
159 ((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"):
160 "X"):"?" );
161 p += sprintf(p, "PIO Mode: %s %s"
162 " %s %s\n",
163 "?", "?", "?", "?");
164 p += sprintf(p, " %s %s\n",
165 (reg50 & CFR_INTR_CH0) ? "interrupting" : "polling ",
166 (reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling");
167 p += sprintf(p, " %s %s\n",
168 (reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear ",
169 (reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear");
170 p += sprintf(p, " %s %s\n",
171 (reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled",
172 (reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled");
173
174 return (char *)p;
175}
176
177static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
178{
179 char *p = buffer;
180 int i;
181
182 p += sprintf(p, "\n");
183 for (i = 0; i < n_cmd_devs; i++) {
184 struct pci_dev *dev = cmd_devs[i];
185 p = print_cmd64x_get_info(p, dev, i);
186 }
187 return p-buffer; /* => must be less than 4k! */
188}
189
190#endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */
191
192/*
193 * Registers and masks for easy access by drive index:
194 */
195#if 0
196static u8 prefetch_regs[4] = {CNTRL, CNTRL, ARTTIM23, ARTTIM23};
197static u8 prefetch_masks[4] = {CNTRL_DIS_RA0, CNTRL_DIS_RA1, ARTTIM23_DIS_RA2, ARTTIM23_DIS_RA3};
198#endif
199
200/*
201 * This routine writes the prepared setup/active/recovery counts
202 * for a drive into the cmd646 chipset registers to active them.
203 */
204static void program_drive_counts (ide_drive_t *drive, int setup_count, int active_count, int recovery_count)
205{
206 unsigned long flags;
207 struct pci_dev *dev = HWIF(drive)->pci_dev;
208 ide_drive_t *drives = HWIF(drive)->drives;
209 u8 temp_b;
210 static const u8 setup_counts[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
211 static const u8 recovery_counts[] =
212 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
213 static const u8 arttim_regs[2][2] = {
214 { ARTTIM0, ARTTIM1 },
215 { ARTTIM23, ARTTIM23 }
216 };
217 static const u8 drwtim_regs[2][2] = {
218 { DRWTIM0, DRWTIM1 },
219 { DRWTIM2, DRWTIM3 }
220 };
221 int channel = (int) HWIF(drive)->channel;
222 int slave = (drives != drive); /* Is this really the best way to determine this?? */
223
224 cmdprintk("program_drive_count parameters = s(%d),a(%d),r(%d),p(%d)\n",
225 setup_count, active_count, recovery_count, drive->present);
226 /*
227 * Set up address setup count registers.
228 * Primary interface has individual count/timing registers for
229 * each drive. Secondary interface has one common set of registers,
230 * for address setup so we merge these timings, using the slowest
231 * value.
232 */
233 if (channel) {
234 drive->drive_data = setup_count;
235 setup_count = max(drives[0].drive_data,
236 drives[1].drive_data);
237 cmdprintk("Secondary interface, setup_count = %d\n",
238 setup_count);
239 }
240
241 /*
242 * Convert values to internal chipset representation
243 */
244 setup_count = (setup_count > 5) ? 0xc0 : (int) setup_counts[setup_count];
245 active_count &= 0xf; /* Remember, max value is 16 */
246 recovery_count = (int) recovery_counts[recovery_count];
247
248 cmdprintk("Final values = %d,%d,%d\n",
249 setup_count, active_count, recovery_count);
250
251 /*
252 * Now that everything is ready, program the new timings
253 */
254 local_irq_save(flags);
255 /*
256 * Program the address_setup clocks into ARTTIM reg,
257 * and then the active/recovery counts into the DRWTIM reg
258 */
259 (void) pci_read_config_byte(dev, arttim_regs[channel][slave], &temp_b);
260 (void) pci_write_config_byte(dev, arttim_regs[channel][slave],
261 ((u8) setup_count) | (temp_b & 0x3f));
262 (void) pci_write_config_byte(dev, drwtim_regs[channel][slave],
263 (u8) ((active_count << 4) | recovery_count));
264 cmdprintk ("Write %x to %x\n",
265 ((u8) setup_count) | (temp_b & 0x3f),
266 arttim_regs[channel][slave]);
267 cmdprintk ("Write %x to %x\n",
268 (u8) ((active_count << 4) | recovery_count),
269 drwtim_regs[channel][slave]);
270 local_irq_restore(flags);
271}
272
273/*
274 * Attempts to set the interface PIO mode.
275 * The preferred method of selecting PIO modes (e.g. mode 4) is
276 * "echo 'piomode:4' > /proc/ide/hdx/settings". Special cases are
277 * 8: prefetch off, 9: prefetch on, 255: auto-select best mode.
278 * Called with 255 at boot time.
279 */
280
281static void cmd64x_tuneproc (ide_drive_t *drive, u8 mode_wanted)
282{
283 int setup_time, active_time, recovery_time;
284 int clock_time, pio_mode, cycle_time;
285 u8 recovery_count2, cycle_count;
286 int setup_count, active_count, recovery_count;
287 int bus_speed = system_bus_clock();
288 /*byte b;*/
289 ide_pio_data_t d;
290
291 switch (mode_wanted) {
292 case 8: /* set prefetch off */
293 case 9: /* set prefetch on */
294 mode_wanted &= 1;
295 /*set_prefetch_mode(index, mode_wanted);*/
296 cmdprintk("%s: %sabled cmd640 prefetch\n",
297 drive->name, mode_wanted ? "en" : "dis");
298 return;
299 }
300
301 mode_wanted = ide_get_best_pio_mode (drive, mode_wanted, 5, &d);
302 pio_mode = d.pio_mode;
303 cycle_time = d.cycle_time;
304
305 /*
306 * I copied all this complicated stuff from cmd640.c and made a few
307 * minor changes. For now I am just going to pray that it is correct.
308 */
309 if (pio_mode > 5)
310 pio_mode = 5;
311 setup_time = ide_pio_timings[pio_mode].setup_time;
312 active_time = ide_pio_timings[pio_mode].active_time;
313 recovery_time = cycle_time - (setup_time + active_time);
314 clock_time = 1000 / bus_speed;
315 cycle_count = (cycle_time + clock_time - 1) / clock_time;
316
317 setup_count = (setup_time + clock_time - 1) / clock_time;
318
319 active_count = (active_time + clock_time - 1) / clock_time;
320
321 recovery_count = (recovery_time + clock_time - 1) / clock_time;
322 recovery_count2 = cycle_count - (setup_count + active_count);
323 if (recovery_count2 > recovery_count)
324 recovery_count = recovery_count2;
325 if (recovery_count > 16) {
326 active_count += recovery_count - 16;
327 recovery_count = 16;
328 }
329 if (active_count > 16)
330 active_count = 16; /* maximum allowed by cmd646 */
331
332 /*
333 * In a perfect world, we might set the drive pio mode here
334 * (using WIN_SETFEATURE) before continuing.
335 *
336 * But we do not, because:
337 * 1) this is the wrong place to do it
338 * (proper is do_special() in ide.c)
339 * 2) in practice this is rarely, if ever, necessary
340 */
341 program_drive_counts (drive, setup_count, active_count, recovery_count);
342
343 cmdprintk("%s: selected cmd646 PIO mode%d : %d (%dns)%s, "
344 "clocks=%d/%d/%d\n",
345 drive->name, pio_mode, mode_wanted, cycle_time,
346 d.overridden ? " (overriding vendor mode)" : "",
347 setup_count, active_count, recovery_count);
348}
349
350static u8 cmd64x_ratemask (ide_drive_t *drive)
351{
352 struct pci_dev *dev = HWIF(drive)->pci_dev;
353 u8 mode = 0;
354
355 switch(dev->device) {
356 case PCI_DEVICE_ID_CMD_649:
357 mode = 3;
358 break;
359 case PCI_DEVICE_ID_CMD_648:
360 mode = 2;
361 break;
362 case PCI_DEVICE_ID_CMD_643:
363 return 0;
364
365 case PCI_DEVICE_ID_CMD_646:
366 {
367 unsigned int class_rev = 0;
368 pci_read_config_dword(dev,
369 PCI_CLASS_REVISION, &class_rev);
370 class_rev &= 0xff;
371 /*
372 * UltraDMA only supported on PCI646U and PCI646U2, which
373 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
374 * Actually, although the CMD tech support people won't
375 * tell me the details, the 0x03 revision cannot support
376 * UDMA correctly without hardware modifications, and even
377 * then it only works with Quantum disks due to some
378 * hold time assumptions in the 646U part which are fixed
379 * in the 646U2.
380 *
381 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
382 */
383 switch(class_rev) {
384 case 0x07:
385 case 0x05:
386 return 1;
387 case 0x03:
388 case 0x01:
389 default:
390 return 0;
391 }
392 }
393 }
394 if (!eighty_ninty_three(drive))
395 mode = min(mode, (u8)1);
396 return mode;
397}
398
399static void config_cmd64x_chipset_for_pio (ide_drive_t *drive, u8 set_speed)
400{
401 u8 speed = 0x00;
402 u8 set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
403
404 cmd64x_tuneproc(drive, set_pio);
405 speed = XFER_PIO_0 + set_pio;
406 if (set_speed)
407 (void) ide_config_drive_speed(drive, speed);
408}
409
410static void config_chipset_for_pio (ide_drive_t *drive, u8 set_speed)
411{
412 config_cmd64x_chipset_for_pio(drive, set_speed);
413}
414
415static int cmd64x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
416{
417 ide_hwif_t *hwif = HWIF(drive);
418 struct pci_dev *dev = hwif->pci_dev;
419
420 u8 unit = (drive->select.b.unit & 0x01);
421 u8 regU = 0, pciU = (hwif->channel) ? UDIDETCR1 : UDIDETCR0;
422 u8 regD = 0, pciD = (hwif->channel) ? BMIDESR1 : BMIDESR0;
423
424 u8 speed = ide_rate_filter(cmd64x_ratemask(drive), xferspeed);
425
426 if (speed > XFER_PIO_4) {
427 (void) pci_read_config_byte(dev, pciD, &regD);
428 (void) pci_read_config_byte(dev, pciU, &regU);
429 regD &= ~(unit ? 0x40 : 0x20);
430 regU &= ~(unit ? 0xCA : 0x35);
431 (void) pci_write_config_byte(dev, pciD, regD);
432 (void) pci_write_config_byte(dev, pciU, regU);
433 (void) pci_read_config_byte(dev, pciD, &regD);
434 (void) pci_read_config_byte(dev, pciU, &regU);
435 }
436
437 switch(speed) {
438 case XFER_UDMA_5: regU |= (unit ? 0x0A : 0x05); break;
439 case XFER_UDMA_4: regU |= (unit ? 0x4A : 0x15); break;
440 case XFER_UDMA_3: regU |= (unit ? 0x8A : 0x25); break;
441 case XFER_UDMA_2: regU |= (unit ? 0x42 : 0x11); break;
442 case XFER_UDMA_1: regU |= (unit ? 0x82 : 0x21); break;
443 case XFER_UDMA_0: regU |= (unit ? 0xC2 : 0x31); break;
444 case XFER_MW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
445 case XFER_MW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
446 case XFER_MW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
447 case XFER_SW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
448 case XFER_SW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
449 case XFER_SW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
450 case XFER_PIO_4: cmd64x_tuneproc(drive, 4); break;
451 case XFER_PIO_3: cmd64x_tuneproc(drive, 3); break;
452 case XFER_PIO_2: cmd64x_tuneproc(drive, 2); break;
453 case XFER_PIO_1: cmd64x_tuneproc(drive, 1); break;
454 case XFER_PIO_0: cmd64x_tuneproc(drive, 0); break;
455
456 default:
457 return 1;
458 }
459
460 if (speed > XFER_PIO_4) {
461 (void) pci_write_config_byte(dev, pciU, regU);
462 regD |= (unit ? 0x40 : 0x20);
463 (void) pci_write_config_byte(dev, pciD, regD);
464 }
465
466 return (ide_config_drive_speed(drive, speed));
467}
468
469static int config_chipset_for_dma (ide_drive_t *drive)
470{
471 u8 speed = ide_dma_speed(drive, cmd64x_ratemask(drive));
472
473 config_chipset_for_pio(drive, !speed);
474
475 if (!speed)
476 return 0;
477
478 if(ide_set_xfer_rate(drive, speed))
479 return 0;
480
481 if (!drive->init_speed)
482 drive->init_speed = speed;
483
484 return ide_dma_enable(drive);
485}
486
487static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
488{
489 ide_hwif_t *hwif = HWIF(drive);
490 struct hd_driveid *id = drive->id;
491
492 if ((id != NULL) && ((id->capability & 1) != 0) && drive->autodma) {
493
494 if (ide_use_dma(drive)) {
495 if (config_chipset_for_dma(drive))
496 return hwif->ide_dma_on(drive);
497 }
498
499 goto fast_ata_pio;
500
501 } else if ((id->capability & 8) || (id->field_valid & 2)) {
502fast_ata_pio:
503 config_chipset_for_pio(drive, 1);
504 return hwif->ide_dma_off_quietly(drive);
505 }
506 /* IORDY not supported */
507 return 0;
508}
509
510static int cmd64x_alt_dma_status (struct pci_dev *dev)
511{
512 switch(dev->device) {
513 case PCI_DEVICE_ID_CMD_648:
514 case PCI_DEVICE_ID_CMD_649:
515 return 1;
516 default:
517 break;
518 }
519 return 0;
520}
521
522static int cmd64x_ide_dma_end (ide_drive_t *drive)
523{
524 u8 dma_stat = 0, dma_cmd = 0;
525 ide_hwif_t *hwif = HWIF(drive);
526 struct pci_dev *dev = hwif->pci_dev;
527
528 drive->waiting_for_dma = 0;
529 /* read DMA command state */
530 dma_cmd = hwif->INB(hwif->dma_command);
531 /* stop DMA */
532 hwif->OUTB((dma_cmd & ~1), hwif->dma_command);
533 /* get DMA status */
534 dma_stat = hwif->INB(hwif->dma_status);
535 /* clear the INTR & ERROR bits */
536 hwif->OUTB(dma_stat|6, hwif->dma_status);
537 if (cmd64x_alt_dma_status(dev)) {
538 u8 dma_intr = 0;
539 u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 :
540 CFR_INTR_CH0;
541 u8 dma_reg = (hwif->channel) ? ARTTIM2 : CFR;
542 (void) pci_read_config_byte(dev, dma_reg, &dma_intr);
543 /* clear the INTR bit */
544 (void) pci_write_config_byte(dev, dma_reg, dma_intr|dma_mask);
545 }
546 /* purge DMA mappings */
547 ide_destroy_dmatable(drive);
548 /* verify good DMA status */
549 return (dma_stat & 7) != 4;
550}
551
552static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
553{
554 ide_hwif_t *hwif = HWIF(drive);
555 struct pci_dev *dev = hwif->pci_dev;
556 u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 :
557 MRDMODE_INTR_CH0;
558 u8 dma_stat = hwif->INB(hwif->dma_status);
559
560 (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat);
561#ifdef DEBUG
562 printk("%s: dma_stat: 0x%02x dma_alt_stat: "
563 "0x%02x mask: 0x%02x\n", drive->name,
564 dma_stat, dma_alt_stat, mask);
565#endif
566 if (!(dma_alt_stat & mask))
567 return 0;
568
569 /* return 1 if INTR asserted */
570 if ((dma_stat & 4) == 4)
571 return 1;
572
573 return 0;
574}
575
576/*
577 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
578 * event order for DMA transfers.
579 */
580
581static int cmd646_1_ide_dma_end (ide_drive_t *drive)
582{
583 ide_hwif_t *hwif = HWIF(drive);
584 u8 dma_stat = 0, dma_cmd = 0;
585
586 drive->waiting_for_dma = 0;
587 /* get DMA status */
588 dma_stat = hwif->INB(hwif->dma_status);
589 /* read DMA command state */
590 dma_cmd = hwif->INB(hwif->dma_command);
591 /* stop DMA */
592 hwif->OUTB((dma_cmd & ~1), hwif->dma_command);
593 /* clear the INTR & ERROR bits */
594 hwif->OUTB(dma_stat|6, hwif->dma_status);
595 /* and free any DMA resources */
596 ide_destroy_dmatable(drive);
597 /* verify good DMA status */
598 return (dma_stat & 7) != 4;
599}
600
601static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
602{
603 u32 class_rev = 0;
604 u8 mrdmode = 0;
605
606 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
607 class_rev &= 0xff;
608
609#ifdef __i386__
610 if (dev->resource[PCI_ROM_RESOURCE].start) {
611 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
612 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
613 }
614#endif
615
616 switch(dev->device) {
617 case PCI_DEVICE_ID_CMD_643:
618 break;
619 case PCI_DEVICE_ID_CMD_646:
620 printk(KERN_INFO "%s: chipset revision 0x%02X, ", name, class_rev);
621 switch(class_rev) {
622 case 0x07:
623 case 0x05:
624 printk("UltraDMA Capable");
625 break;
626 case 0x03:
627 printk("MultiWord DMA Force Limited");
628 break;
629 case 0x01:
630 default:
631 printk("MultiWord DMA Limited, IRQ workaround enabled");
632 break;
633 }
634 printk("\n");
635 break;
636 case PCI_DEVICE_ID_CMD_648:
637 case PCI_DEVICE_ID_CMD_649:
638 break;
639 default:
640 break;
641 }
642
643 /* Set a good latency timer and cache line size value. */
644 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
645 /* FIXME: pci_set_master() to ensure a good latency timer value */
646
647 /* Setup interrupts. */
648 (void) pci_read_config_byte(dev, MRDMODE, &mrdmode);
649 mrdmode &= ~(0x30);
650 (void) pci_write_config_byte(dev, MRDMODE, mrdmode);
651
652 /* Use MEMORY READ LINE for reads.
653 * NOTE: Although not mentioned in the PCI0646U specs,
654 * these bits are write only and won't be read
655 * back as set or not. The PCI0646U2 specs clarify
656 * this point.
657 */
658 (void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02);
659
660 /* Set reasonable active/recovery/address-setup values. */
661 (void) pci_write_config_byte(dev, ARTTIM0, 0x40);
662 (void) pci_write_config_byte(dev, DRWTIM0, 0x3f);
663 (void) pci_write_config_byte(dev, ARTTIM1, 0x40);
664 (void) pci_write_config_byte(dev, DRWTIM1, 0x3f);
665#ifdef __i386__
666 (void) pci_write_config_byte(dev, ARTTIM23, 0x1c);
667#else
668 (void) pci_write_config_byte(dev, ARTTIM23, 0x5c);
669#endif
670 (void) pci_write_config_byte(dev, DRWTIM23, 0x3f);
671 (void) pci_write_config_byte(dev, DRWTIM3, 0x3f);
672#ifdef CONFIG_PPC
673 (void) pci_write_config_byte(dev, UDIDETCR0, 0xf0);
674#endif /* CONFIG_PPC */
675
676#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
677
678 cmd_devs[n_cmd_devs++] = dev;
679
680 if (!cmd64x_proc) {
681 cmd64x_proc = 1;
682 ide_pci_create_host_proc("cmd64x", cmd64x_get_info);
683 }
684#endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */
685
686 return 0;
687}
688
689static unsigned int __devinit ata66_cmd64x(ide_hwif_t *hwif)
690{
691 u8 ata66 = 0, mask = (hwif->channel) ? 0x02 : 0x01;
692
693 switch(hwif->pci_dev->device) {
694 case PCI_DEVICE_ID_CMD_643:
695 case PCI_DEVICE_ID_CMD_646:
696 return ata66;
697 default:
698 break;
699 }
700 pci_read_config_byte(hwif->pci_dev, BMIDECSR, &ata66);
701 return (ata66 & mask) ? 1 : 0;
702}
703
704static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
705{
706 struct pci_dev *dev = hwif->pci_dev;
707 unsigned int class_rev;
708
709 hwif->autodma = 0;
710 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
711 class_rev &= 0xff;
712
713 hwif->tuneproc = &cmd64x_tuneproc;
714 hwif->speedproc = &cmd64x_tune_chipset;
715
716 if (!hwif->dma_base) {
717 hwif->drives[0].autotune = 1;
718 hwif->drives[1].autotune = 1;
719 return;
720 }
721
722 hwif->atapi_dma = 1;
723
724 hwif->ultra_mask = 0x3f;
725 hwif->mwdma_mask = 0x07;
726 hwif->swdma_mask = 0x07;
727
728 if (dev->device == PCI_DEVICE_ID_CMD_643)
729 hwif->ultra_mask = 0x80;
730 if (dev->device == PCI_DEVICE_ID_CMD_646)
731 hwif->ultra_mask = (class_rev > 0x04) ? 0x07 : 0x80;
732 if (dev->device == PCI_DEVICE_ID_CMD_648)
733 hwif->ultra_mask = 0x1f;
734
735 hwif->ide_dma_check = &cmd64x_config_drive_for_dma;
736 if (!(hwif->udma_four))
737 hwif->udma_four = ata66_cmd64x(hwif);
738
739 if (dev->device == PCI_DEVICE_ID_CMD_646) {
740 hwif->chipset = ide_cmd646;
741 if (class_rev == 0x01) {
742 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
743 } else {
744 hwif->ide_dma_end = &cmd64x_ide_dma_end;
745 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
746 }
747 } else {
748 hwif->ide_dma_end = &cmd64x_ide_dma_end;
749 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
750 }
751
752
753 if (!noautodma)
754 hwif->autodma = 1;
755 hwif->drives[0].autodma = hwif->autodma;
756 hwif->drives[1].autodma = hwif->autodma;
757}
758
759static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
760 { /* 0 */
761 .name = "CMD643",
762 .init_chipset = init_chipset_cmd64x,
763 .init_hwif = init_hwif_cmd64x,
764 .channels = 2,
765 .autodma = AUTODMA,
766 .bootable = ON_BOARD,
767 },{ /* 1 */
768 .name = "CMD646",
769 .init_chipset = init_chipset_cmd64x,
770 .init_hwif = init_hwif_cmd64x,
771 .channels = 2,
772 .autodma = AUTODMA,
773 .enablebits = {{0x00,0x00,0x00}, {0x51,0x80,0x80}},
774 .bootable = ON_BOARD,
775 },{ /* 2 */
776 .name = "CMD648",
777 .init_chipset = init_chipset_cmd64x,
778 .init_hwif = init_hwif_cmd64x,
779 .channels = 2,
780 .autodma = AUTODMA,
781 .bootable = ON_BOARD,
782 },{ /* 3 */
783 .name = "CMD649",
784 .init_chipset = init_chipset_cmd64x,
785 .init_hwif = init_hwif_cmd64x,
786 .channels = 2,
787 .autodma = AUTODMA,
788 .bootable = ON_BOARD,
789 }
790};
791
792static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
793{
794 return ide_setup_pci_device(dev, &cmd64x_chipsets[id->driver_data]);
795}
796
797static struct pci_device_id cmd64x_pci_tbl[] = {
798 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
799 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
800 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
801 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
802 { 0, },
803};
804MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
805
806static struct pci_driver driver = {
807 .name = "CMD64x_IDE",
808 .id_table = cmd64x_pci_tbl,
809 .probe = cmd64x_init_one,
810};
811
812static int cmd64x_ide_init(void)
813{
814 return ide_pci_register_driver(&driver);
815}
816
817module_init(cmd64x_ide_init);
818
819MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
820MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
821MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 17:01:38 -0500