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path: root/drivers/ide/pci/cmd64x.c
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Diffstat (limited to 'drivers/ide/pci/cmd64x.c')
-rw-r--r--drivers/ide/pci/cmd64x.c50
1 files changed, 22 insertions, 28 deletions
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c
index ce58bfcdb3c6..1360b4fa9fd3 100644
--- a/drivers/ide/pci/cmd64x.c
+++ b/drivers/ide/pci/cmd64x.c
@@ -19,6 +19,8 @@
19 19
20#include <asm/io.h> 20#include <asm/io.h>
21 21
22#define DRV_NAME "cmd64x"
23
22#define CMD_DEBUG 0 24#define CMD_DEBUG 0
23 25
24#if CMD_DEBUG 26#if CMD_DEBUG
@@ -330,28 +332,10 @@ static int cmd646_1_dma_end(ide_drive_t *drive)
330 return (dma_stat & 7) != 4; 332 return (dma_stat & 7) != 4;
331} 333}
332 334
333static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name) 335static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev)
334{ 336{
335 u8 mrdmode = 0; 337 u8 mrdmode = 0;
336 338
337 if (dev->device == PCI_DEVICE_ID_CMD_646) {
338
339 switch (dev->revision) {
340 case 0x07:
341 case 0x05:
342 printk("%s: UltraDMA capable\n", name);
343 break;
344 case 0x03:
345 default:
346 printk("%s: MultiWord DMA force limited\n", name);
347 break;
348 case 0x01:
349 printk("%s: MultiWord DMA limited, "
350 "IRQ workaround enabled\n", name);
351 break;
352 }
353 }
354
355 /* Set a good latency timer and cache line size value. */ 339 /* Set a good latency timer and cache line size value. */
356 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); 340 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
357 /* FIXME: pci_set_master() to ensure a good latency timer value */ 341 /* FIXME: pci_set_master() to ensure a good latency timer value */
@@ -425,8 +409,8 @@ static const struct ide_dma_ops cmd648_dma_ops = {
425}; 409};
426 410
427static const struct ide_port_info cmd64x_chipsets[] __devinitdata = { 411static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
428 { /* 0 */ 412 { /* 0: CMD643 */
429 .name = "CMD643", 413 .name = DRV_NAME,
430 .init_chipset = init_chipset_cmd64x, 414 .init_chipset = init_chipset_cmd64x,
431 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}}, 415 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
432 .port_ops = &cmd64x_port_ops, 416 .port_ops = &cmd64x_port_ops,
@@ -436,8 +420,9 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
436 .pio_mask = ATA_PIO5, 420 .pio_mask = ATA_PIO5,
437 .mwdma_mask = ATA_MWDMA2, 421 .mwdma_mask = ATA_MWDMA2,
438 .udma_mask = 0x00, /* no udma */ 422 .udma_mask = 0x00, /* no udma */
439 },{ /* 1 */ 423 },
440 .name = "CMD646", 424 { /* 1: CMD646 */
425 .name = DRV_NAME,
441 .init_chipset = init_chipset_cmd64x, 426 .init_chipset = init_chipset_cmd64x,
442 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, 427 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
443 .chipset = ide_cmd646, 428 .chipset = ide_cmd646,
@@ -447,8 +432,9 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
447 .pio_mask = ATA_PIO5, 432 .pio_mask = ATA_PIO5,
448 .mwdma_mask = ATA_MWDMA2, 433 .mwdma_mask = ATA_MWDMA2,
449 .udma_mask = ATA_UDMA2, 434 .udma_mask = ATA_UDMA2,
450 },{ /* 2 */ 435 },
451 .name = "CMD648", 436 { /* 2: CMD648 */
437 .name = DRV_NAME,
452 .init_chipset = init_chipset_cmd64x, 438 .init_chipset = init_chipset_cmd64x,
453 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, 439 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
454 .port_ops = &cmd64x_port_ops, 440 .port_ops = &cmd64x_port_ops,
@@ -457,8 +443,9 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
457 .pio_mask = ATA_PIO5, 443 .pio_mask = ATA_PIO5,
458 .mwdma_mask = ATA_MWDMA2, 444 .mwdma_mask = ATA_MWDMA2,
459 .udma_mask = ATA_UDMA4, 445 .udma_mask = ATA_UDMA4,
460 },{ /* 3 */ 446 },
461 .name = "CMD649", 447 { /* 3: CMD649 */
448 .name = DRV_NAME,
462 .init_chipset = init_chipset_cmd64x, 449 .init_chipset = init_chipset_cmd64x,
463 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, 450 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
464 .port_ops = &cmd64x_port_ops, 451 .port_ops = &cmd64x_port_ops,
@@ -507,7 +494,7 @@ static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_devic
507 } 494 }
508 } 495 }
509 496
510 return ide_setup_pci_device(dev, &d); 497 return ide_pci_init_one(dev, &d, NULL);
511} 498}
512 499
513static const struct pci_device_id cmd64x_pci_tbl[] = { 500static const struct pci_device_id cmd64x_pci_tbl[] = {
@@ -523,6 +510,7 @@ static struct pci_driver driver = {
523 .name = "CMD64x_IDE", 510 .name = "CMD64x_IDE",
524 .id_table = cmd64x_pci_tbl, 511 .id_table = cmd64x_pci_tbl,
525 .probe = cmd64x_init_one, 512 .probe = cmd64x_init_one,
513 .remove = ide_pci_remove,
526}; 514};
527 515
528static int __init cmd64x_ide_init(void) 516static int __init cmd64x_ide_init(void)
@@ -530,7 +518,13 @@ static int __init cmd64x_ide_init(void)
530 return ide_pci_register_driver(&driver); 518 return ide_pci_register_driver(&driver);
531} 519}
532 520
521static void __exit cmd64x_ide_exit(void)
522{
523 pci_unregister_driver(&driver);
524}
525
533module_init(cmd64x_ide_init); 526module_init(cmd64x_ide_init);
527module_exit(cmd64x_ide_exit);
534 528
535MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick"); 529MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
536MODULE_DESCRIPTION("PCI driver module for CMD64x IDE"); 530MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");