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path: root/drivers/ide/pci/cmd64x.c
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Diffstat (limited to 'drivers/ide/pci/cmd64x.c')
-rw-r--r--drivers/ide/pci/cmd64x.c537
1 files changed, 279 insertions, 258 deletions
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c
index 561197f7b5bb..77f51ab6d439 100644
--- a/drivers/ide/pci/cmd64x.c
+++ b/drivers/ide/pci/cmd64x.c
@@ -1,10 +1,7 @@
1/* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16 1/*
2 * 2 * linux/drivers/ide/pci/cmd64x.c Version 1.47 Mar 19, 2007
3 * linux/drivers/ide/pci/cmd64x.c Version 1.42 Feb 8, 2007
4 * 3 *
5 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. 4 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
6 * Note, this driver is not used at all on other systems because
7 * there the "BIOS" has done all of the following already.
8 * Due to massive hardware bugs, UltraDMA is only supported 5 * Due to massive hardware bugs, UltraDMA is only supported
9 * on the 646U2 and not on the 646U. 6 * on the 646U2 and not on the 646U.
10 * 7 *
@@ -39,11 +36,12 @@
39 * CMD64x specific registers definition. 36 * CMD64x specific registers definition.
40 */ 37 */
41#define CFR 0x50 38#define CFR 0x50
42#define CFR_INTR_CH0 0x02 39#define CFR_INTR_CH0 0x04
43#define CNTRL 0x51 40#define CNTRL 0x51
44#define CNTRL_DIS_RA0 0x40 41#define CNTRL_ENA_1ST 0x04
45#define CNTRL_DIS_RA1 0x80 42#define CNTRL_ENA_2ND 0x08
46#define CNTRL_ENA_2ND 0x08 43#define CNTRL_DIS_RA0 0x40
44#define CNTRL_DIS_RA1 0x80
47 45
48#define CMDTIM 0x52 46#define CMDTIM 0x52
49#define ARTTIM0 0x53 47#define ARTTIM0 0x53
@@ -90,86 +88,67 @@ static int n_cmd_devs;
90static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index) 88static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
91{ 89{
92 char *p = buf; 90 char *p = buf;
93
94 u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0; /* primary */
95 u8 reg57 = 0, reg58 = 0, reg5b; /* secondary */
96 u8 reg72 = 0, reg73 = 0; /* primary */ 91 u8 reg72 = 0, reg73 = 0; /* primary */
97 u8 reg7a = 0, reg7b = 0; /* secondary */ 92 u8 reg7a = 0, reg7b = 0; /* secondary */
98 u8 reg50 = 0, reg71 = 0; /* extra */ 93 u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */
94 u8 rev = 0;
99 95
100 p += sprintf(p, "\nController: %d\n", index); 96 p += sprintf(p, "\nController: %d\n", index);
101 p += sprintf(p, "CMD%x Chipset.\n", dev->device); 97 p += sprintf(p, "PCI-%x Chipset.\n", dev->device);
98
102 (void) pci_read_config_byte(dev, CFR, &reg50); 99 (void) pci_read_config_byte(dev, CFR, &reg50);
103 (void) pci_read_config_byte(dev, ARTTIM0, &reg53); 100 (void) pci_read_config_byte(dev, CNTRL, &reg51);
104 (void) pci_read_config_byte(dev, DRWTIM0, &reg54); 101 (void) pci_read_config_byte(dev, ARTTIM23, &reg57);
105 (void) pci_read_config_byte(dev, ARTTIM1, &reg55);
106 (void) pci_read_config_byte(dev, DRWTIM1, &reg56);
107 (void) pci_read_config_byte(dev, ARTTIM2, &reg57);
108 (void) pci_read_config_byte(dev, DRWTIM2, &reg58);
109 (void) pci_read_config_byte(dev, DRWTIM3, &reg5b);
110 (void) pci_read_config_byte(dev, MRDMODE, &reg71); 102 (void) pci_read_config_byte(dev, MRDMODE, &reg71);
111 (void) pci_read_config_byte(dev, BMIDESR0, &reg72); 103 (void) pci_read_config_byte(dev, BMIDESR0, &reg72);
112 (void) pci_read_config_byte(dev, UDIDETCR0, &reg73); 104 (void) pci_read_config_byte(dev, UDIDETCR0, &reg73);
113 (void) pci_read_config_byte(dev, BMIDESR1, &reg7a); 105 (void) pci_read_config_byte(dev, BMIDESR1, &reg7a);
114 (void) pci_read_config_byte(dev, UDIDETCR1, &reg7b); 106 (void) pci_read_config_byte(dev, UDIDETCR1, &reg7b);
115 107
116 p += sprintf(p, "--------------- Primary Channel " 108 /* PCI0643/6 originally didn't have the primary channel enable bit */
117 "---------------- Secondary Channel " 109 (void) pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
118 "-------------\n"); 110 if ((dev->device == PCI_DEVICE_ID_CMD_643) ||
119 p += sprintf(p, " %sabled " 111 (dev->device == PCI_DEVICE_ID_CMD_646 && rev < 3))
120 " %sabled\n", 112 reg51 |= CNTRL_ENA_1ST;
121 (reg72&0x80)?"dis":" en", 113
122 (reg7a&0x80)?"dis":" en"); 114 p += sprintf(p, "---------------- Primary Channel "
123 p += sprintf(p, "--------------- drive0 " 115 "---------------- Secondary Channel ------------\n");
124 "--------- drive1 -------- drive0 " 116 p += sprintf(p, " %s %s\n",
125 "---------- drive1 ------\n"); 117 (reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled",
126 p += sprintf(p, "DMA enabled: %s %s" 118 (reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled");
127 " %s %s\n", 119 p += sprintf(p, "---------------- drive0 --------- drive1 "
128 (reg72&0x20)?"yes":"no ", (reg72&0x40)?"yes":"no ", 120 "-------- drive0 --------- drive1 ------\n");
129 (reg7a&0x20)?"yes":"no ", (reg7a&0x40)?"yes":"no "); 121 p += sprintf(p, "DMA enabled: %s %s"
130 122 " %s %s\n",
131 p += sprintf(p, "DMA Mode: %s(%s) %s(%s)", 123 (reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ",
132 (reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO", 124 (reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no ");
133 (reg72&0x20)?( 125 p += sprintf(p, "UltraDMA mode: %s (%c) %s (%c)",
134 ((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"): 126 ( reg73 & 0x01) ? " on" : "off",
135 ((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"): 127 ((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') :
136 ((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"): 128 ((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') :
137 ((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"): 129 ((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') :
138 "X"):"?", 130 ((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?',
139 (reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO", 131 ( reg73 & 0x02) ? " on" : "off",
140 (reg72&0x40)?( 132 ((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') :
141 ((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"): 133 ((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') :
142 ((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"): 134 ((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') :
143 ((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"): 135 ((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?');
144 ((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"): 136 p += sprintf(p, " %s (%c) %s (%c)\n",
145 "X"):"?"); 137 ( reg7b & 0x01) ? " on" : "off",
146 p += sprintf(p, " %s(%s) %s(%s)\n", 138 ((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') :
147 (reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO", 139 ((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') :
148 (reg7a&0x20)?( 140 ((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') :
149 ((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"): 141 ((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?',
150 ((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"): 142 ( reg7b & 0x02) ? " on" : "off",
151 ((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"): 143 ((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') :
152 ((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"): 144 ((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') :
153 "X"):"?", 145 ((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') :
154 (reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO", 146 ((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?');
155 (reg7a&0x40)?( 147 p += sprintf(p, "Interrupt: %s, %s %s, %s\n",
156 ((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"): 148 (reg71 & MRDMODE_BLK_CH0 ) ? "blocked" : "enabled",
157 ((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"): 149 (reg50 & CFR_INTR_CH0 ) ? "pending" : "clear ",
158 ((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"): 150 (reg71 & MRDMODE_BLK_CH1 ) ? "blocked" : "enabled",
159 ((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"): 151 (reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear ");
160 "X"):"?" );
161 p += sprintf(p, "PIO Mode: %s %s"
162 " %s %s\n",
163 "?", "?", "?", "?");
164 p += sprintf(p, " %s %s\n",
165 (reg50 & CFR_INTR_CH0) ? "interrupting" : "polling ",
166 (reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling");
167 p += sprintf(p, " %s %s\n",
168 (reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear ",
169 (reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear");
170 p += sprintf(p, " %s %s\n",
171 (reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled",
172 (reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled");
173 152
174 return (char *)p; 153 return (char *)p;
175} 154}
@@ -179,7 +158,6 @@ static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
179 char *p = buffer; 158 char *p = buffer;
180 int i; 159 int i;
181 160
182 p += sprintf(p, "\n");
183 for (i = 0; i < n_cmd_devs; i++) { 161 for (i = 0; i < n_cmd_devs; i++) {
184 struct pci_dev *dev = cmd_devs[i]; 162 struct pci_dev *dev = cmd_devs[i];
185 p = print_cmd64x_get_info(p, dev, i); 163 p = print_cmd64x_get_info(p, dev, i);
@@ -195,116 +173,103 @@ static u8 quantize_timing(int timing, int quant)
195} 173}
196 174
197/* 175/*
198 * This routine writes the prepared setup/active/recovery counts 176 * This routine calculates active/recovery counts and then writes them into
199 * for a drive into the cmd646 chipset registers to active them. 177 * the chipset registers.
200 */ 178 */
201static void program_drive_counts (ide_drive_t *drive, int setup_count, int active_count, int recovery_count) 179static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
202{ 180{
203 unsigned long flags; 181 struct pci_dev *dev = HWIF(drive)->pci_dev;
204 struct pci_dev *dev = HWIF(drive)->pci_dev; 182 int clock_time = 1000 / system_bus_clock();
205 ide_drive_t *drives = HWIF(drive)->drives; 183 u8 cycle_count, active_count, recovery_count, drwtim;
206 u8 temp_b; 184 static const u8 recovery_values[] =
207 static const u8 setup_counts[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
208 static const u8 recovery_counts[] =
209 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; 185 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
210 static const u8 arttim_regs[2][2] = { 186 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
211 { ARTTIM0, ARTTIM1 }, 187
212 { ARTTIM23, ARTTIM23 } 188 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
213 }; 189 cycle_time, active_time);
214 static const u8 drwtim_regs[2][2] = { 190
215 { DRWTIM0, DRWTIM1 }, 191 cycle_count = quantize_timing( cycle_time, clock_time);
216 { DRWTIM2, DRWTIM3 } 192 active_count = quantize_timing(active_time, clock_time);
217 }; 193 recovery_count = cycle_count - active_count;
218 int channel = (int) HWIF(drive)->channel; 194
219 int slave = (drives != drive); /* Is this really the best way to determine this?? */
220
221 cmdprintk("program_drive_count parameters = s(%d),a(%d),r(%d),p(%d)\n",
222 setup_count, active_count, recovery_count, drive->present);
223 /* 195 /*
224 * Set up address setup count registers. 196 * In case we've got too long recovery phase, try to lengthen
225 * Primary interface has individual count/timing registers for 197 * the active phase
226 * each drive. Secondary interface has one common set of registers,
227 * for address setup so we merge these timings, using the slowest
228 * value.
229 */ 198 */
230 if (channel) { 199 if (recovery_count > 16) {
231 drive->drive_data = setup_count; 200 active_count += recovery_count - 16;
232 setup_count = max(drives[0].drive_data, 201 recovery_count = 16;
233 drives[1].drive_data);
234 cmdprintk("Secondary interface, setup_count = %d\n",
235 setup_count);
236 } 202 }
203 if (active_count > 16) /* shouldn't actually happen... */
204 active_count = 16;
205
206 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
207 cycle_count, active_count, recovery_count);
237 208
238 /* 209 /*
239 * Convert values to internal chipset representation 210 * Convert values to internal chipset representation
240 */ 211 */
241 setup_count = (setup_count > 5) ? 0xc0 : (int) setup_counts[setup_count]; 212 recovery_count = recovery_values[recovery_count];
242 active_count &= 0xf; /* Remember, max value is 16 */ 213 active_count &= 0x0f;
243 recovery_count = (int) recovery_counts[recovery_count];
244 214
245 cmdprintk("Final values = %d,%d,%d\n", 215 /* Program the active/recovery counts into the DRWTIM register */
246 setup_count, active_count, recovery_count); 216 drwtim = (active_count << 4) | recovery_count;
247 217 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
248 /* 218 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
249 * Now that everything is ready, program the new timings
250 */
251 local_irq_save(flags);
252 /*
253 * Program the address_setup clocks into ARTTIM reg,
254 * and then the active/recovery counts into the DRWTIM reg
255 */
256 (void) pci_read_config_byte(dev, arttim_regs[channel][slave], &temp_b);
257 (void) pci_write_config_byte(dev, arttim_regs[channel][slave],
258 ((u8) setup_count) | (temp_b & 0x3f));
259 (void) pci_write_config_byte(dev, drwtim_regs[channel][slave],
260 (u8) ((active_count << 4) | recovery_count));
261 cmdprintk ("Write %x to %x\n",
262 ((u8) setup_count) | (temp_b & 0x3f),
263 arttim_regs[channel][slave]);
264 cmdprintk ("Write %x to %x\n",
265 (u8) ((active_count << 4) | recovery_count),
266 drwtim_regs[channel][slave]);
267 local_irq_restore(flags);
268} 219}
269 220
270/* 221/*
271 * This routine selects drive's best PIO mode, calculates setup/active/recovery 222 * This routine selects drive's best PIO mode and writes into the chipset
272 * counts, and then writes them into the chipset registers. 223 * registers setup/active/recovery timings.
273 */ 224 */
274static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted) 225static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted)
275{ 226{
276 int setup_time, active_time, cycle_time; 227 ide_hwif_t *hwif = HWIF(drive);
277 u8 cycle_count, setup_count, active_count, recovery_count; 228 struct pci_dev *dev = hwif->pci_dev;
278 u8 pio_mode;
279 int clock_time = 1000 / system_bus_clock();
280 ide_pio_data_t pio; 229 ide_pio_data_t pio;
281 230 u8 pio_mode, setup_count, arttim = 0;
231 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
232 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
282 pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio); 233 pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio);
283 cycle_time = pio.cycle_time;
284 234
285 setup_time = ide_pio_timings[pio_mode].setup_time; 235 cmdprintk("%s: PIO mode wanted %d, selected %d (%d ns)%s\n",
286 active_time = ide_pio_timings[pio_mode].active_time; 236 drive->name, mode_wanted, pio_mode, pio.cycle_time,
237 pio.overridden ? " (overriding vendor mode)" : "");
287 238
288 setup_count = quantize_timing( setup_time, clock_time); 239 program_cycle_times(drive, pio.cycle_time,
289 cycle_count = quantize_timing( cycle_time, clock_time); 240 ide_pio_timings[pio_mode].active_time);
290 active_count = quantize_timing(active_time, clock_time);
291 241
292 recovery_count = cycle_count - active_count; 242 setup_count = quantize_timing(ide_pio_timings[pio_mode].setup_time,
293 /* program_drive_counts() takes care of zero recovery cycles */ 243 1000 / system_bus_clock());
294 if (recovery_count > 16) { 244
295 active_count += recovery_count - 16; 245 /*
296 recovery_count = 16; 246 * The primary channel has individual address setup timing registers
247 * for each drive and the hardware selects the slowest timing itself.
248 * The secondary channel has one common register and we have to select
249 * the slowest address setup timing ourselves.
250 */
251 if (hwif->channel) {
252 ide_drive_t *drives = hwif->drives;
253
254 drive->drive_data = setup_count;
255 setup_count = max(drives[0].drive_data, drives[1].drive_data);
297 } 256 }
298 if (active_count > 16)
299 active_count = 16; /* maximum allowed by cmd64x */
300 257
301 program_drive_counts (drive, setup_count, active_count, recovery_count); 258 if (setup_count > 5) /* shouldn't actually happen... */
259 setup_count = 5;
260 cmdprintk("Final address setup count: %d\n", setup_count);
302 261
303 cmdprintk("%s: PIO mode wanted %d, selected %d (%dns)%s, " 262 /*
304 "clocks=%d/%d/%d\n", 263 * Program the address setup clocks into the ARTTIM registers.
305 drive->name, mode_wanted, pio_mode, cycle_time, 264 * Avoid clearing the secondary channel's interrupt bit.
306 pio.overridden ? " (overriding vendor mode)" : "", 265 */
307 setup_count, active_count, recovery_count); 266 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
267 if (hwif->channel)
268 arttim &= ~ARTTIM23_INTR_CH1;
269 arttim &= ~0xc0;
270 arttim |= setup_values[setup_count];
271 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
272 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
308 273
309 return pio_mode; 274 return pio_mode;
310} 275}
@@ -376,61 +341,64 @@ static u8 cmd64x_ratemask (ide_drive_t *drive)
376 return mode; 341 return mode;
377} 342}
378 343
379static int cmd64x_tune_chipset (ide_drive_t *drive, u8 xferspeed) 344static int cmd64x_tune_chipset (ide_drive_t *drive, u8 speed)
380{ 345{
381 ide_hwif_t *hwif = HWIF(drive); 346 ide_hwif_t *hwif = HWIF(drive);
382 struct pci_dev *dev = hwif->pci_dev; 347 struct pci_dev *dev = hwif->pci_dev;
348 u8 unit = drive->dn & 0x01;
349 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
383 350
384 u8 unit = (drive->select.b.unit & 0x01); 351 speed = ide_rate_filter(cmd64x_ratemask(drive), speed);
385 u8 regU = 0, pciU = (hwif->channel) ? UDIDETCR1 : UDIDETCR0;
386 u8 regD = 0, pciD = (hwif->channel) ? BMIDESR1 : BMIDESR0;
387
388 u8 speed = ide_rate_filter(cmd64x_ratemask(drive), xferspeed);
389 352
390 if (speed >= XFER_SW_DMA_0) { 353 if (speed >= XFER_SW_DMA_0) {
391 (void) pci_read_config_byte(dev, pciD, &regD);
392 (void) pci_read_config_byte(dev, pciU, &regU); 354 (void) pci_read_config_byte(dev, pciU, &regU);
393 regD &= ~(unit ? 0x40 : 0x20);
394 regU &= ~(unit ? 0xCA : 0x35); 355 regU &= ~(unit ? 0xCA : 0x35);
395 (void) pci_write_config_byte(dev, pciD, regD);
396 (void) pci_write_config_byte(dev, pciU, regU);
397 (void) pci_read_config_byte(dev, pciD, &regD);
398 (void) pci_read_config_byte(dev, pciU, &regU);
399 } 356 }
400 357
401 switch(speed) { 358 switch(speed) {
402 case XFER_UDMA_5: regU |= (unit ? 0x0A : 0x05); break; 359 case XFER_UDMA_5:
403 case XFER_UDMA_4: regU |= (unit ? 0x4A : 0x15); break; 360 regU |= unit ? 0x0A : 0x05;
404 case XFER_UDMA_3: regU |= (unit ? 0x8A : 0x25); break; 361 break;
405 case XFER_UDMA_2: regU |= (unit ? 0x42 : 0x11); break; 362 case XFER_UDMA_4:
406 case XFER_UDMA_1: regU |= (unit ? 0x82 : 0x21); break; 363 regU |= unit ? 0x4A : 0x15;
407 case XFER_UDMA_0: regU |= (unit ? 0xC2 : 0x31); break; 364 break;
408 case XFER_MW_DMA_2: regD |= (unit ? 0x40 : 0x10); break; 365 case XFER_UDMA_3:
409 case XFER_MW_DMA_1: regD |= (unit ? 0x80 : 0x20); break; 366 regU |= unit ? 0x8A : 0x25;
410 case XFER_MW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break; 367 break;
411 case XFER_SW_DMA_2: regD |= (unit ? 0x40 : 0x10); break; 368 case XFER_UDMA_2:
412 case XFER_SW_DMA_1: regD |= (unit ? 0x80 : 0x20); break; 369 regU |= unit ? 0x42 : 0x11;
413 case XFER_SW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break; 370 break;
414 case XFER_PIO_5: 371 case XFER_UDMA_1:
415 case XFER_PIO_4: 372 regU |= unit ? 0x82 : 0x21;
416 case XFER_PIO_3: 373 break;
417 case XFER_PIO_2: 374 case XFER_UDMA_0:
418 case XFER_PIO_1: 375 regU |= unit ? 0xC2 : 0x31;
419 case XFER_PIO_0: 376 break;
420 (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0); 377 case XFER_MW_DMA_2:
421 break; 378 program_cycle_times(drive, 120, 70);
422 379 break;
423 default: 380 case XFER_MW_DMA_1:
424 return 1; 381 program_cycle_times(drive, 150, 80);
382 break;
383 case XFER_MW_DMA_0:
384 program_cycle_times(drive, 480, 215);
385 break;
386 case XFER_PIO_5:
387 case XFER_PIO_4:
388 case XFER_PIO_3:
389 case XFER_PIO_2:
390 case XFER_PIO_1:
391 case XFER_PIO_0:
392 (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0);
393 break;
394 default:
395 return 1;
425 } 396 }
426 397
427 if (speed >= XFER_SW_DMA_0) { 398 if (speed >= XFER_SW_DMA_0)
428 (void) pci_write_config_byte(dev, pciU, regU); 399 (void) pci_write_config_byte(dev, pciU, regU);
429 regD |= (unit ? 0x40 : 0x20);
430 (void) pci_write_config_byte(dev, pciD, regD);
431 }
432 400
433 return (ide_config_drive_speed(drive, speed)); 401 return ide_config_drive_speed(drive, speed);
434} 402}
435 403
436static int config_chipset_for_dma (ide_drive_t *drive) 404static int config_chipset_for_dma (ide_drive_t *drive)
@@ -457,67 +425,80 @@ static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
457 return -1; 425 return -1;
458} 426}
459 427
460static int cmd64x_alt_dma_status (struct pci_dev *dev) 428static int cmd648_ide_dma_end (ide_drive_t *drive)
461{ 429{
462 switch(dev->device) { 430 ide_hwif_t *hwif = HWIF(drive);
463 case PCI_DEVICE_ID_CMD_648: 431 int err = __ide_dma_end(drive);
464 case PCI_DEVICE_ID_CMD_649: 432 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
465 return 1; 433 MRDMODE_INTR_CH0;
466 default: 434 u8 mrdmode = inb(hwif->dma_master + 0x01);
467 break; 435
468 } 436 /* clear the interrupt bit */
469 return 0; 437 outb(mrdmode | irq_mask, hwif->dma_master + 0x01);
438
439 return err;
470} 440}
471 441
472static int cmd64x_ide_dma_end (ide_drive_t *drive) 442static int cmd64x_ide_dma_end (ide_drive_t *drive)
473{ 443{
474 u8 dma_stat = 0, dma_cmd = 0;
475 ide_hwif_t *hwif = HWIF(drive); 444 ide_hwif_t *hwif = HWIF(drive);
476 struct pci_dev *dev = hwif->pci_dev; 445 struct pci_dev *dev = hwif->pci_dev;
446 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
447 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
448 CFR_INTR_CH0;
449 u8 irq_stat = 0;
450 int err = __ide_dma_end(drive);
477 451
478 drive->waiting_for_dma = 0; 452 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
479 /* read DMA command state */ 453 /* clear the interrupt bit */
480 dma_cmd = inb(hwif->dma_command); 454 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
481 /* stop DMA */ 455
482 outb(dma_cmd & ~1, hwif->dma_command); 456 return err;
483 /* get DMA status */ 457}
484 dma_stat = inb(hwif->dma_status); 458
485 /* clear the INTR & ERROR bits */ 459static int cmd648_ide_dma_test_irq (ide_drive_t *drive)
486 outb(dma_stat | 6, hwif->dma_status); 460{
487 if (cmd64x_alt_dma_status(dev)) { 461 ide_hwif_t *hwif = HWIF(drive);
488 u8 dma_intr = 0; 462 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
489 u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 : 463 MRDMODE_INTR_CH0;
490 CFR_INTR_CH0; 464 u8 dma_stat = inb(hwif->dma_status);
491 u8 dma_reg = (hwif->channel) ? ARTTIM2 : CFR; 465 u8 mrdmode = inb(hwif->dma_master + 0x01);
492 (void) pci_read_config_byte(dev, dma_reg, &dma_intr); 466
493 /* clear the INTR bit */ 467#ifdef DEBUG
494 (void) pci_write_config_byte(dev, dma_reg, dma_intr|dma_mask); 468 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
495 } 469 drive->name, dma_stat, mrdmode, irq_mask);
496 /* purge DMA mappings */ 470#endif
497 ide_destroy_dmatable(drive); 471 if (!(mrdmode & irq_mask))
498 /* verify good DMA status */ 472 return 0;
499 return (dma_stat & 7) != 4; 473
474 /* return 1 if INTR asserted */
475 if (dma_stat & 4)
476 return 1;
477
478 return 0;
500} 479}
501 480
502static int cmd64x_ide_dma_test_irq (ide_drive_t *drive) 481static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
503{ 482{
504 ide_hwif_t *hwif = HWIF(drive); 483 ide_hwif_t *hwif = HWIF(drive);
505 struct pci_dev *dev = hwif->pci_dev; 484 struct pci_dev *dev = hwif->pci_dev;
506 u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 : 485 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
507 MRDMODE_INTR_CH0; 486 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
508 u8 dma_stat = inb(hwif->dma_status); 487 CFR_INTR_CH0;
488 u8 dma_stat = inb(hwif->dma_status);
489 u8 irq_stat = 0;
490
491 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
509 492
510 (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat);
511#ifdef DEBUG 493#ifdef DEBUG
512 printk("%s: dma_stat: 0x%02x dma_alt_stat: " 494 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
513 "0x%02x mask: 0x%02x\n", drive->name, 495 drive->name, dma_stat, irq_stat, irq_mask);
514 dma_stat, dma_alt_stat, mask);
515#endif 496#endif
516 if (!(dma_alt_stat & mask)) 497 if (!(irq_stat & irq_mask))
517 return 0; 498 return 0;
518 499
519 /* return 1 if INTR asserted */ 500 /* return 1 if INTR asserted */
520 if ((dma_stat & 4) == 4) 501 if (dma_stat & 4)
521 return 1; 502 return 1;
522 503
523 return 0; 504 return 0;
@@ -665,7 +646,6 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
665 646
666 hwif->ultra_mask = 0x3f; 647 hwif->ultra_mask = 0x3f;
667 hwif->mwdma_mask = 0x07; 648 hwif->mwdma_mask = 0x07;
668 hwif->swdma_mask = 0x07;
669 649
670 if (dev->device == PCI_DEVICE_ID_CMD_643) 650 if (dev->device == PCI_DEVICE_ID_CMD_643)
671 hwif->ultra_mask = 0x80; 651 hwif->ultra_mask = 0x80;
@@ -678,17 +658,25 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
678 if (!(hwif->udma_four)) 658 if (!(hwif->udma_four))
679 hwif->udma_four = ata66_cmd64x(hwif); 659 hwif->udma_four = ata66_cmd64x(hwif);
680 660
681 if (dev->device == PCI_DEVICE_ID_CMD_646) { 661 switch(dev->device) {
662 case PCI_DEVICE_ID_CMD_648:
663 case PCI_DEVICE_ID_CMD_649:
664 alt_irq_bits:
665 hwif->ide_dma_end = &cmd648_ide_dma_end;
666 hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq;
667 break;
668 case PCI_DEVICE_ID_CMD_646:
682 hwif->chipset = ide_cmd646; 669 hwif->chipset = ide_cmd646;
683 if (class_rev == 0x01) { 670 if (class_rev == 0x01) {
684 hwif->ide_dma_end = &cmd646_1_ide_dma_end; 671 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
685 } else { 672 break;
686 hwif->ide_dma_end = &cmd64x_ide_dma_end; 673 } else if (class_rev >= 0x03)
687 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq; 674 goto alt_irq_bits;
688 } 675 /* fall thru */
689 } else { 676 default:
690 hwif->ide_dma_end = &cmd64x_ide_dma_end; 677 hwif->ide_dma_end = &cmd64x_ide_dma_end;
691 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq; 678 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
679 break;
692 } 680 }
693 681
694 682
@@ -698,42 +686,75 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
698 hwif->drives[1].autodma = hwif->autodma; 686 hwif->drives[1].autodma = hwif->autodma;
699} 687}
700 688
689static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d)
690{
691 return ide_setup_pci_device(dev, d);
692}
693
694static int __devinit init_setup_cmd646(struct pci_dev *dev, ide_pci_device_t *d)
695{
696 u8 rev = 0;
697
698 /*
699 * The original PCI0646 didn't have the primary channel enable bit,
700 * it appeared starting with PCI0646U (i.e. revision ID 3).
701 */
702 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
703 if (rev < 3)
704 d->enablebits[0].reg = 0;
705
706 return ide_setup_pci_device(dev, d);
707}
708
701static ide_pci_device_t cmd64x_chipsets[] __devinitdata = { 709static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
702 { /* 0 */ 710 { /* 0 */
703 .name = "CMD643", 711 .name = "CMD643",
712 .init_setup = init_setup_cmd64x,
704 .init_chipset = init_chipset_cmd64x, 713 .init_chipset = init_chipset_cmd64x,
705 .init_hwif = init_hwif_cmd64x, 714 .init_hwif = init_hwif_cmd64x,
706 .channels = 2, 715 .channels = 2,
707 .autodma = AUTODMA, 716 .autodma = AUTODMA,
717 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
708 .bootable = ON_BOARD, 718 .bootable = ON_BOARD,
709 },{ /* 1 */ 719 },{ /* 1 */
710 .name = "CMD646", 720 .name = "CMD646",
721 .init_setup = init_setup_cmd646,
711 .init_chipset = init_chipset_cmd64x, 722 .init_chipset = init_chipset_cmd64x,
712 .init_hwif = init_hwif_cmd64x, 723 .init_hwif = init_hwif_cmd64x,
713 .channels = 2, 724 .channels = 2,
714 .autodma = AUTODMA, 725 .autodma = AUTODMA,
715 .enablebits = {{0x00,0x00,0x00}, {0x51,0x80,0x80}}, 726 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
716 .bootable = ON_BOARD, 727 .bootable = ON_BOARD,
717 },{ /* 2 */ 728 },{ /* 2 */
718 .name = "CMD648", 729 .name = "CMD648",
730 .init_setup = init_setup_cmd64x,
719 .init_chipset = init_chipset_cmd64x, 731 .init_chipset = init_chipset_cmd64x,
720 .init_hwif = init_hwif_cmd64x, 732 .init_hwif = init_hwif_cmd64x,
721 .channels = 2, 733 .channels = 2,
722 .autodma = AUTODMA, 734 .autodma = AUTODMA,
735 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
723 .bootable = ON_BOARD, 736 .bootable = ON_BOARD,
724 },{ /* 3 */ 737 },{ /* 3 */
725 .name = "CMD649", 738 .name = "CMD649",
739 .init_setup = init_setup_cmd64x,
726 .init_chipset = init_chipset_cmd64x, 740 .init_chipset = init_chipset_cmd64x,
727 .init_hwif = init_hwif_cmd64x, 741 .init_hwif = init_hwif_cmd64x,
728 .channels = 2, 742 .channels = 2,
729 .autodma = AUTODMA, 743 .autodma = AUTODMA,
744 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
730 .bootable = ON_BOARD, 745 .bootable = ON_BOARD,
731 } 746 }
732}; 747};
733 748
749/*
750 * We may have to modify enablebits for PCI0646, so we'd better pass
751 * a local copy of the ide_pci_device_t structure down the call chain...
752 */
734static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id) 753static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
735{ 754{
736 return ide_setup_pci_device(dev, &cmd64x_chipsets[id->driver_data]); 755 ide_pci_device_t d = cmd64x_chipsets[id->driver_data];
756
757 return d.init_setup(dev, &d);
737} 758}
738 759
739static struct pci_device_id cmd64x_pci_tbl[] = { 760static struct pci_device_id cmd64x_pci_tbl[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 03:30:02 -0400