diff options
Diffstat (limited to 'drivers/ide/pci/amd74xx.c')
-rw-r--r-- | drivers/ide/pci/amd74xx.c | 118 |
1 files changed, 54 insertions, 64 deletions
diff --git a/drivers/ide/pci/amd74xx.c b/drivers/ide/pci/amd74xx.c index a2be65fcf89c..a7443f15b27a 100644 --- a/drivers/ide/pci/amd74xx.c +++ b/drivers/ide/pci/amd74xx.c | |||
@@ -1,10 +1,11 @@ | |||
1 | /* | 1 | /* |
2 | * Version 2.16 | 2 | * Version 2.20 |
3 | * | 3 | * |
4 | * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04 | 4 | * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04 |
5 | * IDE driver for Linux. | 5 | * IDE driver for Linux. |
6 | * | 6 | * |
7 | * Copyright (c) 2000-2002 Vojtech Pavlik | 7 | * Copyright (c) 2000-2002 Vojtech Pavlik |
8 | * Copyright (c) 2007 Bartlomiej Zolnierkiewicz | ||
8 | * | 9 | * |
9 | * Based on the work of: | 10 | * Based on the work of: |
10 | * Andre Hedrick | 11 | * Andre Hedrick |
@@ -37,11 +38,6 @@ | |||
37 | #define AMD_ADDRESS_SETUP (0x0c + amd_config->base) | 38 | #define AMD_ADDRESS_SETUP (0x0c + amd_config->base) |
38 | #define AMD_UDMA_TIMING (0x10 + amd_config->base) | 39 | #define AMD_UDMA_TIMING (0x10 + amd_config->base) |
39 | 40 | ||
40 | #define AMD_UDMA 0x07 | ||
41 | #define AMD_UDMA_33 0x01 | ||
42 | #define AMD_UDMA_66 0x02 | ||
43 | #define AMD_UDMA_100 0x03 | ||
44 | #define AMD_UDMA_133 0x04 | ||
45 | #define AMD_CHECK_SWDMA 0x08 | 41 | #define AMD_CHECK_SWDMA 0x08 |
46 | #define AMD_BAD_SWDMA 0x10 | 42 | #define AMD_BAD_SWDMA 0x10 |
47 | #define AMD_BAD_FIFO 0x20 | 43 | #define AMD_BAD_FIFO 0x20 |
@@ -53,32 +49,33 @@ | |||
53 | 49 | ||
54 | static struct amd_ide_chip { | 50 | static struct amd_ide_chip { |
55 | unsigned short id; | 51 | unsigned short id; |
56 | unsigned long base; | 52 | u8 base; |
57 | unsigned char flags; | 53 | u8 udma_mask; |
54 | u8 flags; | ||
58 | } amd_ide_chips[] = { | 55 | } amd_ide_chips[] = { |
59 | { PCI_DEVICE_ID_AMD_COBRA_7401, 0x40, AMD_UDMA_33 | AMD_BAD_SWDMA }, | 56 | { PCI_DEVICE_ID_AMD_COBRA_7401, 0x40, ATA_UDMA2, AMD_BAD_SWDMA }, |
60 | { PCI_DEVICE_ID_AMD_VIPER_7409, 0x40, AMD_UDMA_66 | AMD_CHECK_SWDMA }, | 57 | { PCI_DEVICE_ID_AMD_VIPER_7409, 0x40, ATA_UDMA4, AMD_CHECK_SWDMA }, |
61 | { PCI_DEVICE_ID_AMD_VIPER_7411, 0x40, AMD_UDMA_100 | AMD_BAD_FIFO }, | 58 | { PCI_DEVICE_ID_AMD_VIPER_7411, 0x40, ATA_UDMA5, AMD_BAD_FIFO }, |
62 | { PCI_DEVICE_ID_AMD_OPUS_7441, 0x40, AMD_UDMA_100 }, | 59 | { PCI_DEVICE_ID_AMD_OPUS_7441, 0x40, ATA_UDMA5, }, |
63 | { PCI_DEVICE_ID_AMD_8111_IDE, 0x40, AMD_UDMA_133 | AMD_CHECK_SERENADE }, | 60 | { PCI_DEVICE_ID_AMD_8111_IDE, 0x40, ATA_UDMA6, AMD_CHECK_SERENADE }, |
64 | { PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, 0x50, AMD_UDMA_100 }, | 61 | { PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, 0x50, ATA_UDMA5, }, |
65 | { PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, 0x50, AMD_UDMA_133 }, | 62 | { PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, 0x50, ATA_UDMA6, }, |
66 | { PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, 0x50, AMD_UDMA_133 }, | 63 | { PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, 0x50, ATA_UDMA6, }, |
67 | { PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, 0x50, AMD_UDMA_133 }, | 64 | { PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, 0x50, ATA_UDMA6, }, |
68 | { PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, 0x50, AMD_UDMA_133 }, | 65 | { PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, 0x50, ATA_UDMA6, }, |
69 | { PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, 0x50, AMD_UDMA_133 }, | 66 | { PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, 0x50, ATA_UDMA6, }, |
70 | { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, 0x50, AMD_UDMA_133 }, | 67 | { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, 0x50, ATA_UDMA6, }, |
71 | { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, 0x50, AMD_UDMA_133 }, | 68 | { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, 0x50, ATA_UDMA6, }, |
72 | { PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, 0x50, AMD_UDMA_133 }, | 69 | { PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, 0x50, ATA_UDMA6, }, |
73 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, 0x50, AMD_UDMA_133 }, | 70 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, 0x50, ATA_UDMA6, }, |
74 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, 0x50, AMD_UDMA_133 }, | 71 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, 0x50, ATA_UDMA6, }, |
75 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, 0x50, AMD_UDMA_133 }, | 72 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, 0x50, ATA_UDMA6, }, |
76 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE, 0x50, AMD_UDMA_133 }, | 73 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE, 0x50, ATA_UDMA6, }, |
77 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE, 0x50, AMD_UDMA_133 }, | 74 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE, 0x50, ATA_UDMA6, }, |
78 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE, 0x50, AMD_UDMA_133 }, | 75 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE, 0x50, ATA_UDMA6, }, |
79 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE, 0x50, AMD_UDMA_133 }, | 76 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE, 0x50, ATA_UDMA6, }, |
80 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE, 0x50, AMD_UDMA_133 }, | 77 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE, 0x50, ATA_UDMA6, }, |
81 | { PCI_DEVICE_ID_AMD_CS5536_IDE, 0x40, AMD_UDMA_100 }, | 78 | { PCI_DEVICE_ID_AMD_CS5536_IDE, 0x40, ATA_UDMA5, }, |
82 | { 0 } | 79 | { 0 } |
83 | }; | 80 | }; |
84 | 81 | ||
@@ -87,7 +84,7 @@ static ide_pci_device_t *amd_chipset; | |||
87 | static unsigned int amd_80w; | 84 | static unsigned int amd_80w; |
88 | static unsigned int amd_clock; | 85 | static unsigned int amd_clock; |
89 | 86 | ||
90 | static char *amd_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" }; | 87 | static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" }; |
91 | static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 }; | 88 | static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 }; |
92 | 89 | ||
93 | /* | 90 | /* |
@@ -128,7 +125,7 @@ static int amd74xx_get_info(char *buffer, char **addr, off_t offset, int count) | |||
128 | 125 | ||
129 | pci_read_config_byte(dev, PCI_REVISION_ID, &t); | 126 | pci_read_config_byte(dev, PCI_REVISION_ID, &t); |
130 | amd_print("Revision: IDE %#x", t); | 127 | amd_print("Revision: IDE %#x", t); |
131 | amd_print("Highest DMA rate: %s", amd_dma[amd_config->flags & AMD_UDMA]); | 128 | amd_print("Highest DMA rate: UDMA%s", amd_dma[fls(amd_config->udma_mask) - 1]); |
132 | 129 | ||
133 | amd_print("BM-DMA base: %#lx", amd_base); | 130 | amd_print("BM-DMA base: %#lx", amd_base); |
134 | amd_print("PCI clock: %d.%dMHz", amd_clock / 1000, amd_clock / 100 % 10); | 131 | amd_print("PCI clock: %d.%dMHz", amd_clock / 1000, amd_clock / 100 % 10); |
@@ -221,12 +218,12 @@ static void amd_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timi | |||
221 | pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn), | 218 | pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn), |
222 | ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1)); | 219 | ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1)); |
223 | 220 | ||
224 | switch (amd_config->flags & AMD_UDMA) { | 221 | switch (amd_config->udma_mask) { |
225 | case AMD_UDMA_33: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break; | 222 | case ATA_UDMA2: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break; |
226 | case AMD_UDMA_66: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break; | 223 | case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break; |
227 | case AMD_UDMA_100: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break; | 224 | case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break; |
228 | case AMD_UDMA_133: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break; | 225 | case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break; |
229 | default: return; | 226 | default: return; |
230 | } | 227 | } |
231 | 228 | ||
232 | pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t); | 229 | pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t); |
@@ -248,7 +245,7 @@ static int amd_set_drive(ide_drive_t *drive, u8 speed) | |||
248 | ide_config_drive_speed(drive, speed); | 245 | ide_config_drive_speed(drive, speed); |
249 | 246 | ||
250 | T = 1000000000 / amd_clock; | 247 | T = 1000000000 / amd_clock; |
251 | UT = T / min_t(int, max_t(int, amd_config->flags & AMD_UDMA, 1), 2); | 248 | UT = (amd_config->udma_mask == ATA_UDMA2) ? T : (T / 2); |
252 | 249 | ||
253 | ide_timing_compute(drive, speed, &t, T, UT); | 250 | ide_timing_compute(drive, speed, &t, T, UT); |
254 | 251 | ||
@@ -277,29 +274,19 @@ static int amd_set_drive(ide_drive_t *drive, u8 speed) | |||
277 | static void amd74xx_tune_drive(ide_drive_t *drive, u8 pio) | 274 | static void amd74xx_tune_drive(ide_drive_t *drive, u8 pio) |
278 | { | 275 | { |
279 | if (pio == 255) { | 276 | if (pio == 255) { |
280 | amd_set_drive(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO)); | 277 | amd_set_drive(drive, ide_find_best_pio_mode(drive)); |
281 | return; | 278 | return; |
282 | } | 279 | } |
283 | 280 | ||
284 | amd_set_drive(drive, XFER_PIO_0 + min_t(byte, pio, 5)); | 281 | amd_set_drive(drive, XFER_PIO_0 + min_t(byte, pio, 5)); |
285 | } | 282 | } |
286 | 283 | ||
287 | /* | ||
288 | * amd74xx_dmaproc() is a callback from upper layers that can do | ||
289 | * a lot, but we use it for DMA/PIO tuning only, delegating everything | ||
290 | * else to the default ide_dmaproc(). | ||
291 | */ | ||
292 | |||
293 | static int amd74xx_ide_dma_check(ide_drive_t *drive) | 284 | static int amd74xx_ide_dma_check(ide_drive_t *drive) |
294 | { | 285 | { |
295 | int w80 = HWIF(drive)->udma_four; | 286 | u8 speed = ide_max_dma_mode(drive); |
296 | 287 | ||
297 | u8 speed = ide_find_best_mode(drive, | 288 | if (speed == 0) |
298 | XFER_PIO | XFER_EPIO | XFER_MWDMA | XFER_UDMA | | 289 | speed = ide_find_best_pio_mode(drive); |
299 | ((amd_config->flags & AMD_BAD_SWDMA) ? 0 : XFER_SWDMA) | | ||
300 | (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_66 ? XFER_UDMA_66 : 0) | | ||
301 | (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_100 ? XFER_UDMA_100 : 0) | | ||
302 | (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_133 ? XFER_UDMA_133 : 0)); | ||
303 | 290 | ||
304 | amd_set_drive(drive, speed); | 291 | amd_set_drive(drive, speed); |
305 | 292 | ||
@@ -334,10 +321,10 @@ static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const ch | |||
334 | * Check 80-wire cable presence. | 321 | * Check 80-wire cable presence. |
335 | */ | 322 | */ |
336 | 323 | ||
337 | switch (amd_config->flags & AMD_UDMA) { | 324 | switch (amd_config->udma_mask) { |
338 | 325 | ||
339 | case AMD_UDMA_133: | 326 | case ATA_UDMA6: |
340 | case AMD_UDMA_100: | 327 | case ATA_UDMA5: |
341 | pci_read_config_byte(dev, AMD_CABLE_DETECT, &t); | 328 | pci_read_config_byte(dev, AMD_CABLE_DETECT, &t); |
342 | pci_read_config_dword(dev, AMD_UDMA_TIMING, &u); | 329 | pci_read_config_dword(dev, AMD_UDMA_TIMING, &u); |
343 | amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0); | 330 | amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0); |
@@ -349,7 +336,7 @@ static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const ch | |||
349 | } | 336 | } |
350 | break; | 337 | break; |
351 | 338 | ||
352 | case AMD_UDMA_66: | 339 | case ATA_UDMA4: |
353 | /* no host side cable detection */ | 340 | /* no host side cable detection */ |
354 | amd_80w = 0x03; | 341 | amd_80w = 0x03; |
355 | break; | 342 | break; |
@@ -370,7 +357,7 @@ static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const ch | |||
370 | if ((amd_config->flags & AMD_CHECK_SERENADE) && | 357 | if ((amd_config->flags & AMD_CHECK_SERENADE) && |
371 | dev->subsystem_vendor == PCI_VENDOR_ID_AMD && | 358 | dev->subsystem_vendor == PCI_VENDOR_ID_AMD && |
372 | dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE) | 359 | dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE) |
373 | amd_config->flags = AMD_UDMA_100; | 360 | amd_config->udma_mask = ATA_UDMA5; |
374 | 361 | ||
375 | /* | 362 | /* |
376 | * Determine the system bus clock. | 363 | * Determine the system bus clock. |
@@ -395,8 +382,9 @@ static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const ch | |||
395 | */ | 382 | */ |
396 | 383 | ||
397 | pci_read_config_byte(dev, PCI_REVISION_ID, &t); | 384 | pci_read_config_byte(dev, PCI_REVISION_ID, &t); |
398 | printk(KERN_INFO "%s: %s (rev %02x) %s controller\n", | 385 | printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n", |
399 | amd_chipset->name, pci_name(dev), t, amd_dma[amd_config->flags & AMD_UDMA]); | 386 | amd_chipset->name, pci_name(dev), t, |
387 | amd_dma[fls(amd_config->udma_mask) - 1]); | ||
400 | 388 | ||
401 | /* | 389 | /* |
402 | * Register /proc/ide/amd74xx entry | 390 | * Register /proc/ide/amd74xx entry |
@@ -437,9 +425,11 @@ static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif) | |||
437 | return; | 425 | return; |
438 | 426 | ||
439 | hwif->atapi_dma = 1; | 427 | hwif->atapi_dma = 1; |
440 | hwif->ultra_mask = 0x7f; | 428 | |
441 | hwif->mwdma_mask = 0x07; | 429 | hwif->ultra_mask = amd_config->udma_mask; |
442 | hwif->swdma_mask = 0x07; | 430 | hwif->mwdma_mask = 0x07; |
431 | if ((amd_config->flags & AMD_BAD_SWDMA) == 0) | ||
432 | hwif->swdma_mask = 0x07; | ||
443 | 433 | ||
444 | if (!hwif->udma_four) | 434 | if (!hwif->udma_four) |
445 | hwif->udma_four = (amd_80w >> hwif->channel) & 1; | 435 | hwif->udma_four = (amd_80w >> hwif->channel) & 1; |