diff options
Diffstat (limited to 'drivers/ide/pci/alim15x3.c')
-rw-r--r-- | drivers/ide/pci/alim15x3.c | 109 |
1 files changed, 54 insertions, 55 deletions
diff --git a/drivers/ide/pci/alim15x3.c b/drivers/ide/pci/alim15x3.c index 8ee2b48d105d..a607dd31a64c 100644 --- a/drivers/ide/pci/alim15x3.c +++ b/drivers/ide/pci/alim15x3.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * linux/drivers/ide/pci/alim15x3.c Version 0.27 Aug 27 2007 | 2 | * linux/drivers/ide/pci/alim15x3.c Version 0.29 Sep 16 2007 |
3 | * | 3 | * |
4 | * Copyright (C) 1998-2000 Michel Aubry, Maintainer | 4 | * Copyright (C) 1998-2000 Michel Aubry, Maintainer |
5 | * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer | 5 | * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer |
@@ -492,6 +492,13 @@ static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const c | |||
492 | * clear bit 7 | 492 | * clear bit 7 |
493 | */ | 493 | */ |
494 | pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F); | 494 | pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F); |
495 | /* | ||
496 | * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010 | ||
497 | */ | ||
498 | if (m5229_revision >= 0x20 && isa_dev) { | ||
499 | pci_read_config_byte(isa_dev, 0x5e, &tmpbyte); | ||
500 | chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0; | ||
501 | } | ||
495 | goto out; | 502 | goto out; |
496 | } | 503 | } |
497 | 504 | ||
@@ -537,7 +544,30 @@ static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const c | |||
537 | pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02); | 544 | pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02); |
538 | } | 545 | } |
539 | } | 546 | } |
547 | |||
540 | out: | 548 | out: |
549 | /* | ||
550 | * CD_ROM DMA on (m5229, 0x53, bit0) | ||
551 | * Enable this bit even if we want to use PIO. | ||
552 | * PIO FIFO off (m5229, 0x53, bit1) | ||
553 | * The hardware will use 0x54h and 0x55h to control PIO FIFO. | ||
554 | * (Not on later devices it seems) | ||
555 | * | ||
556 | * 0x53 changes meaning on later revs - we must no touch | ||
557 | * bit 1 on them. Need to check if 0x20 is the right break. | ||
558 | */ | ||
559 | if (m5229_revision >= 0x20) { | ||
560 | pci_read_config_byte(dev, 0x53, &tmpbyte); | ||
561 | |||
562 | if (m5229_revision <= 0x20) | ||
563 | tmpbyte = (tmpbyte & (~0x02)) | 0x01; | ||
564 | else if (m5229_revision == 0xc7 || m5229_revision == 0xc8) | ||
565 | tmpbyte |= 0x03; | ||
566 | else | ||
567 | tmpbyte |= 0x01; | ||
568 | |||
569 | pci_write_config_byte(dev, 0x53, tmpbyte); | ||
570 | } | ||
541 | pci_dev_put(north); | 571 | pci_dev_put(north); |
542 | pci_dev_put(isa_dev); | 572 | pci_dev_put(isa_dev); |
543 | local_irq_restore(flags); | 573 | local_irq_restore(flags); |
@@ -616,36 +646,8 @@ static u8 __devinit ata66_ali15x3(ide_hwif_t *hwif) | |||
616 | if ((tmpbyte & (1 << hwif->channel)) == 0) | 646 | if ((tmpbyte & (1 << hwif->channel)) == 0) |
617 | cbl = ATA_CBL_PATA80; | 647 | cbl = ATA_CBL_PATA80; |
618 | } | 648 | } |
619 | } else { | ||
620 | /* | ||
621 | * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010 | ||
622 | */ | ||
623 | pci_read_config_byte(isa_dev, 0x5e, &tmpbyte); | ||
624 | chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0; | ||
625 | } | 649 | } |
626 | 650 | ||
627 | /* | ||
628 | * CD_ROM DMA on (m5229, 0x53, bit0) | ||
629 | * Enable this bit even if we want to use PIO | ||
630 | * PIO FIFO off (m5229, 0x53, bit1) | ||
631 | * The hardware will use 0x54h and 0x55h to control PIO FIFO | ||
632 | * (Not on later devices it seems) | ||
633 | * | ||
634 | * 0x53 changes meaning on later revs - we must no touch | ||
635 | * bit 1 on them. Need to check if 0x20 is the right break | ||
636 | */ | ||
637 | |||
638 | pci_read_config_byte(dev, 0x53, &tmpbyte); | ||
639 | |||
640 | if(m5229_revision <= 0x20) | ||
641 | tmpbyte = (tmpbyte & (~0x02)) | 0x01; | ||
642 | else if (m5229_revision == 0xc7 || m5229_revision == 0xc8) | ||
643 | tmpbyte |= 0x03; | ||
644 | else | ||
645 | tmpbyte |= 0x01; | ||
646 | |||
647 | pci_write_config_byte(dev, 0x53, tmpbyte); | ||
648 | |||
649 | local_irq_restore(flags); | 651 | local_irq_restore(flags); |
650 | 652 | ||
651 | return cbl; | 653 | return cbl; |
@@ -664,31 +666,9 @@ static void __devinit init_hwif_common_ali15x3 (ide_hwif_t *hwif) | |||
664 | hwif->set_dma_mode = &ali_set_dma_mode; | 666 | hwif->set_dma_mode = &ali_set_dma_mode; |
665 | hwif->udma_filter = &ali_udma_filter; | 667 | hwif->udma_filter = &ali_udma_filter; |
666 | 668 | ||
667 | /* don't use LBA48 DMA on ALi devices before rev 0xC5 */ | ||
668 | if (m5229_revision <= 0xC4) | ||
669 | hwif->host_flags |= IDE_HFLAG_NO_LBA48_DMA; | ||
670 | |||
671 | if (hwif->dma_base == 0) | 669 | if (hwif->dma_base == 0) |
672 | return; | 670 | return; |
673 | 671 | ||
674 | /* | ||
675 | * check in ->init_dma guarantees m5229_revision >= 0x20 here | ||
676 | */ | ||
677 | |||
678 | if (m5229_revision == 0x20) | ||
679 | hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; | ||
680 | |||
681 | if (m5229_revision <= 0x20) | ||
682 | hwif->ultra_mask = 0x00; /* no udma */ | ||
683 | else if (m5229_revision < 0xC2) | ||
684 | hwif->ultra_mask = ATA_UDMA2; | ||
685 | else if (m5229_revision == 0xC2 || m5229_revision == 0xC3) | ||
686 | hwif->ultra_mask = ATA_UDMA4; | ||
687 | else if (m5229_revision == 0xC4) | ||
688 | hwif->ultra_mask = ATA_UDMA5; | ||
689 | else | ||
690 | hwif->ultra_mask = ATA_UDMA6; | ||
691 | |||
692 | hwif->dma_setup = &ali15x3_dma_setup; | 672 | hwif->dma_setup = &ali15x3_dma_setup; |
693 | 673 | ||
694 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) | 674 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
@@ -766,7 +746,7 @@ static void __devinit init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase) | |||
766 | ide_setup_dma(hwif, dmabase, 8); | 746 | ide_setup_dma(hwif, dmabase, 8); |
767 | } | 747 | } |
768 | 748 | ||
769 | static ide_pci_device_t ali15x3_chipset __devinitdata = { | 749 | static const struct ide_port_info ali15x3_chipset __devinitdata = { |
770 | .name = "ALI15X3", | 750 | .name = "ALI15X3", |
771 | .init_chipset = init_chipset_ali15x3, | 751 | .init_chipset = init_chipset_ali15x3, |
772 | .init_hwif = init_hwif_ali15x3, | 752 | .init_hwif = init_hwif_ali15x3, |
@@ -792,15 +772,34 @@ static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_dev | |||
792 | { }, | 772 | { }, |
793 | }; | 773 | }; |
794 | 774 | ||
795 | ide_pci_device_t *d = &ali15x3_chipset; | 775 | struct ide_port_info d = ali15x3_chipset; |
776 | u8 rev = dev->revision; | ||
796 | 777 | ||
797 | if (pci_dev_present(ati_rs100)) | 778 | if (pci_dev_present(ati_rs100)) |
798 | printk(KERN_WARNING "alim15x3: ATI Radeon IGP Northbridge is not yet fully tested.\n"); | 779 | printk(KERN_WARNING "alim15x3: ATI Radeon IGP Northbridge is not yet fully tested.\n"); |
799 | 780 | ||
781 | /* don't use LBA48 DMA on ALi devices before rev 0xC5 */ | ||
782 | if (rev <= 0xC4) | ||
783 | d.host_flags |= IDE_HFLAG_NO_LBA48_DMA; | ||
784 | |||
785 | if (rev >= 0x20) { | ||
786 | if (rev == 0x20) | ||
787 | d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA; | ||
788 | |||
789 | if (rev < 0xC2) | ||
790 | d.udma_mask = ATA_UDMA2; | ||
791 | else if (rev == 0xC2 || rev == 0xC3) | ||
792 | d.udma_mask = ATA_UDMA4; | ||
793 | else if (rev == 0xC4) | ||
794 | d.udma_mask = ATA_UDMA5; | ||
795 | else | ||
796 | d.udma_mask = ATA_UDMA6; | ||
797 | } | ||
798 | |||
800 | #if defined(CONFIG_SPARC64) | 799 | #if defined(CONFIG_SPARC64) |
801 | d->init_hwif = init_hwif_common_ali15x3; | 800 | d.init_hwif = init_hwif_common_ali15x3; |
802 | #endif /* CONFIG_SPARC64 */ | 801 | #endif /* CONFIG_SPARC64 */ |
803 | return ide_setup_pci_device(dev, d); | 802 | return ide_setup_pci_device(dev, &d); |
804 | } | 803 | } |
805 | 804 | ||
806 | 805 | ||