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path: root/drivers/ide/ide-timings.c
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-rw-r--r--drivers/ide/ide-timings.c22
1 files changed, 10 insertions, 12 deletions
diff --git a/drivers/ide/ide-timings.c b/drivers/ide/ide-timings.c
index 8c2f8327f487..81f527af8fae 100644
--- a/drivers/ide/ide-timings.c
+++ b/drivers/ide/ide-timings.c
@@ -22,7 +22,6 @@
22 */ 22 */
23 23
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/hdreg.h>
26#include <linux/ide.h> 25#include <linux/ide.h>
27#include <linux/module.h> 26#include <linux/module.h>
28 27
@@ -78,15 +77,15 @@ EXPORT_SYMBOL_GPL(ide_timing_find_mode);
78 77
79u16 ide_pio_cycle_time(ide_drive_t *drive, u8 pio) 78u16 ide_pio_cycle_time(ide_drive_t *drive, u8 pio)
80{ 79{
81 struct hd_driveid *id = drive->id; 80 u16 *id = drive->id;
82 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); 81 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
83 u16 cycle = 0; 82 u16 cycle = 0;
84 83
85 if (id->field_valid & 2) { 84 if (id[ATA_ID_FIELD_VALID] & 2) {
86 if (id->capability & 8) 85 if (ata_id_has_iordy(drive->id))
87 cycle = id->eide_pio_iordy; 86 cycle = id[ATA_ID_EIDE_PIO_IORDY];
88 else 87 else
89 cycle = id->eide_pio; 88 cycle = id[ATA_ID_EIDE_PIO];
90 89
91 /* conservative "downgrade" for all pre-ATA2 drives */ 90 /* conservative "downgrade" for all pre-ATA2 drives */
92 if (pio < 3 && cycle < t->cycle) 91 if (pio < 3 && cycle < t->cycle)
@@ -138,7 +137,7 @@ EXPORT_SYMBOL_GPL(ide_timing_merge);
138int ide_timing_compute(ide_drive_t *drive, u8 speed, 137int ide_timing_compute(ide_drive_t *drive, u8 speed,
139 struct ide_timing *t, int T, int UT) 138 struct ide_timing *t, int T, int UT)
140{ 139{
141 struct hd_driveid *id = drive->id; 140 u16 *id = drive->id;
142 struct ide_timing *s, p; 141 struct ide_timing *s, p;
143 142
144 /* 143 /*
@@ -157,16 +156,15 @@ int ide_timing_compute(ide_drive_t *drive, u8 speed,
157 * If the drive is an EIDE drive, it can tell us it needs extended 156 * If the drive is an EIDE drive, it can tell us it needs extended
158 * PIO/MWDMA cycle timing. 157 * PIO/MWDMA cycle timing.
159 */ 158 */
160 if (id && id->field_valid & 2) { /* EIDE drive */ 159 if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
161
162 memset(&p, 0, sizeof(p)); 160 memset(&p, 0, sizeof(p));
163 161
164 if (speed <= XFER_PIO_2) 162 if (speed <= XFER_PIO_2)
165 p.cycle = p.cyc8b = id->eide_pio; 163 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
166 else if (speed <= XFER_PIO_5) 164 else if (speed <= XFER_PIO_5)
167 p.cycle = p.cyc8b = id->eide_pio_iordy; 165 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
168 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) 166 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
169 p.cycle = id->eide_dma_min; 167 p.cycle = id[ATA_ID_EIDE_DMA_MIN];
170 168
171 ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B); 169 ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
172 } 170 }