diff options
Diffstat (limited to 'drivers/ide/ide-timings.c')
-rw-r--r-- | drivers/ide/ide-timings.c | 183 |
1 files changed, 183 insertions, 0 deletions
diff --git a/drivers/ide/ide-timings.c b/drivers/ide/ide-timings.c new file mode 100644 index 000000000000..ebef6d4e3f63 --- /dev/null +++ b/drivers/ide/ide-timings.c | |||
@@ -0,0 +1,183 @@ | |||
1 | /* | ||
2 | * Copyright (c) 1999-2001 Vojtech Pavlik | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
17 | * | ||
18 | * Should you need to contact me, the author, you can do so either by | ||
19 | * e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail: | ||
20 | * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic | ||
21 | */ | ||
22 | |||
23 | #include <linux/kernel.h> | ||
24 | #include <linux/hdreg.h> | ||
25 | #include <linux/ide.h> | ||
26 | #include <linux/module.h> | ||
27 | |||
28 | /* | ||
29 | * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds). | ||
30 | * These were taken from ATA/ATAPI-6 standard, rev 0a, except | ||
31 | * for PIO 5, which is a nonstandard extension and UDMA6, which | ||
32 | * is currently supported only by Maxtor drives. | ||
33 | */ | ||
34 | |||
35 | static struct ide_timing ide_timing[] = { | ||
36 | |||
37 | { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 }, | ||
38 | { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 }, | ||
39 | { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 }, | ||
40 | { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 }, | ||
41 | |||
42 | { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 }, | ||
43 | { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 }, | ||
44 | { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 }, | ||
45 | |||
46 | { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 }, | ||
47 | { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 }, | ||
48 | { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 }, | ||
49 | |||
50 | { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 }, | ||
51 | { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 }, | ||
52 | { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 }, | ||
53 | |||
54 | { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, | ||
55 | { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 }, | ||
56 | { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 }, | ||
57 | |||
58 | { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 }, | ||
59 | { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 }, | ||
60 | { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 }, | ||
61 | |||
62 | { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, | ||
63 | |||
64 | { 0xff } | ||
65 | }; | ||
66 | |||
67 | struct ide_timing *ide_timing_find_mode(u8 speed) | ||
68 | { | ||
69 | struct ide_timing *t; | ||
70 | |||
71 | for (t = ide_timing; t->mode != speed; t++) | ||
72 | if (t->mode == 0xff) | ||
73 | return NULL; | ||
74 | return t; | ||
75 | } | ||
76 | EXPORT_SYMBOL_GPL(ide_timing_find_mode); | ||
77 | |||
78 | #define ENOUGH(v, unit) (((v) - 1) / (unit) + 1) | ||
79 | #define EZ(v, unit) ((v) ? ENOUGH(v, unit) : 0) | ||
80 | |||
81 | static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q, | ||
82 | int T, int UT) | ||
83 | { | ||
84 | q->setup = EZ(t->setup * 1000, T); | ||
85 | q->act8b = EZ(t->act8b * 1000, T); | ||
86 | q->rec8b = EZ(t->rec8b * 1000, T); | ||
87 | q->cyc8b = EZ(t->cyc8b * 1000, T); | ||
88 | q->active = EZ(t->active * 1000, T); | ||
89 | q->recover = EZ(t->recover * 1000, T); | ||
90 | q->cycle = EZ(t->cycle * 1000, T); | ||
91 | q->udma = EZ(t->udma * 1000, UT); | ||
92 | } | ||
93 | |||
94 | void ide_timing_merge(struct ide_timing *a, struct ide_timing *b, | ||
95 | struct ide_timing *m, unsigned int what) | ||
96 | { | ||
97 | if (what & IDE_TIMING_SETUP) | ||
98 | m->setup = max(a->setup, b->setup); | ||
99 | if (what & IDE_TIMING_ACT8B) | ||
100 | m->act8b = max(a->act8b, b->act8b); | ||
101 | if (what & IDE_TIMING_REC8B) | ||
102 | m->rec8b = max(a->rec8b, b->rec8b); | ||
103 | if (what & IDE_TIMING_CYC8B) | ||
104 | m->cyc8b = max(a->cyc8b, b->cyc8b); | ||
105 | if (what & IDE_TIMING_ACTIVE) | ||
106 | m->active = max(a->active, b->active); | ||
107 | if (what & IDE_TIMING_RECOVER) | ||
108 | m->recover = max(a->recover, b->recover); | ||
109 | if (what & IDE_TIMING_CYCLE) | ||
110 | m->cycle = max(a->cycle, b->cycle); | ||
111 | if (what & IDE_TIMING_UDMA) | ||
112 | m->udma = max(a->udma, b->udma); | ||
113 | } | ||
114 | EXPORT_SYMBOL_GPL(ide_timing_merge); | ||
115 | |||
116 | int ide_timing_compute(ide_drive_t *drive, u8 speed, | ||
117 | struct ide_timing *t, int T, int UT) | ||
118 | { | ||
119 | struct hd_driveid *id = drive->id; | ||
120 | struct ide_timing *s, p; | ||
121 | |||
122 | /* | ||
123 | * Find the mode. | ||
124 | */ | ||
125 | s = ide_timing_find_mode(speed); | ||
126 | if (s == NULL) | ||
127 | return -EINVAL; | ||
128 | |||
129 | /* | ||
130 | * Copy the timing from the table. | ||
131 | */ | ||
132 | *t = *s; | ||
133 | |||
134 | /* | ||
135 | * If the drive is an EIDE drive, it can tell us it needs extended | ||
136 | * PIO/MWDMA cycle timing. | ||
137 | */ | ||
138 | if (id && id->field_valid & 2) { /* EIDE drive */ | ||
139 | |||
140 | memset(&p, 0, sizeof(p)); | ||
141 | |||
142 | if (speed <= XFER_PIO_2) | ||
143 | p.cycle = p.cyc8b = id->eide_pio; | ||
144 | else if (speed <= XFER_PIO_5) | ||
145 | p.cycle = p.cyc8b = id->eide_pio_iordy; | ||
146 | else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) | ||
147 | p.cycle = id->eide_dma_min; | ||
148 | |||
149 | ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B); | ||
150 | } | ||
151 | |||
152 | /* | ||
153 | * Convert the timing to bus clock counts. | ||
154 | */ | ||
155 | ide_timing_quantize(t, t, T, UT); | ||
156 | |||
157 | /* | ||
158 | * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, | ||
159 | * S.M.A.R.T and some other commands. We have to ensure that the | ||
160 | * DMA cycle timing is slower/equal than the fastest PIO timing. | ||
161 | */ | ||
162 | if (speed >= XFER_SW_DMA_0) { | ||
163 | u8 pio = ide_get_best_pio_mode(drive, 255, 5); | ||
164 | ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT); | ||
165 | ide_timing_merge(&p, t, t, IDE_TIMING_ALL); | ||
166 | } | ||
167 | |||
168 | /* | ||
169 | * Lengthen active & recovery time so that cycle time is correct. | ||
170 | */ | ||
171 | if (t->act8b + t->rec8b < t->cyc8b) { | ||
172 | t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2; | ||
173 | t->rec8b = t->cyc8b - t->act8b; | ||
174 | } | ||
175 | |||
176 | if (t->active + t->recover < t->cycle) { | ||
177 | t->active += (t->cycle - (t->active + t->recover)) / 2; | ||
178 | t->recover = t->cycle - t->active; | ||
179 | } | ||
180 | |||
181 | return 0; | ||
182 | } | ||
183 | EXPORT_SYMBOL_GPL(ide_timing_compute); | ||