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path: root/drivers/ide/cs5530.c
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Diffstat (limited to 'drivers/ide/cs5530.c')
-rw-r--r--drivers/ide/cs5530.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/ide/cs5530.c b/drivers/ide/cs5530.c
index 40bf05eddf6e..4dc4eb92b076 100644
--- a/drivers/ide/cs5530.c
+++ b/drivers/ide/cs5530.c
@@ -41,8 +41,8 @@ static unsigned int cs5530_pio_timings[2][5] = {
41 41
42/** 42/**
43 * cs5530_set_pio_mode - set host controller for PIO mode 43 * cs5530_set_pio_mode - set host controller for PIO mode
44 * @hwif: port
44 * @drive: drive 45 * @drive: drive
45 * @pio: PIO mode number
46 * 46 *
47 * Handles setting of PIO mode for the chipset. 47 * Handles setting of PIO mode for the chipset.
48 * 48 *
@@ -50,10 +50,11 @@ static unsigned int cs5530_pio_timings[2][5] = {
50 * will have valid default PIO timings set up before we get here. 50 * will have valid default PIO timings set up before we get here.
51 */ 51 */
52 52
53static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio) 53static void cs5530_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
54{ 54{
55 unsigned long basereg = CS5530_BASEREG(drive->hwif); 55 unsigned long basereg = CS5530_BASEREG(hwif);
56 unsigned int format = (inl(basereg + 4) >> 31) & 1; 56 unsigned int format = (inl(basereg + 4) >> 31) & 1;
57 const u8 pio = drive->pio_mode - XFER_PIO_0;
57 58
58 outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3)); 59 outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
59} 60}
@@ -99,12 +100,12 @@ out:
99 return mask; 100 return mask;
100} 101}
101 102
102static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode) 103static void cs5530_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
103{ 104{
104 unsigned long basereg; 105 unsigned long basereg;
105 unsigned int reg, timings = 0; 106 unsigned int reg, timings = 0;
106 107
107 switch (mode) { 108 switch (drive->dma_mode) {
108 case XFER_UDMA_0: timings = 0x00921250; break; 109 case XFER_UDMA_0: timings = 0x00921250; break;
109 case XFER_UDMA_1: timings = 0x00911140; break; 110 case XFER_UDMA_1: timings = 0x00911140; break;
110 case XFER_UDMA_2: timings = 0x00911030; break; 111 case XFER_UDMA_2: timings = 0x00911030; break;
@@ -112,7 +113,7 @@ static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
112 case XFER_MW_DMA_1: timings = 0x00012121; break; 113 case XFER_MW_DMA_1: timings = 0x00012121; break;
113 case XFER_MW_DMA_2: timings = 0x00002020; break; 114 case XFER_MW_DMA_2: timings = 0x00002020; break;
114 } 115 }
115 basereg = CS5530_BASEREG(drive->hwif); 116 basereg = CS5530_BASEREG(hwif);
116 reg = inl(basereg + 4); /* get drive0 config register */ 117 reg = inl(basereg + 4); /* get drive0 config register */
117 timings |= reg & 0x80000000; /* preserve PIO format bit */ 118 timings |= reg & 0x80000000; /* preserve PIO format bit */
118 if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */ 119 if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */