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path: root/drivers/ide/cmd64x.c
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Diffstat (limited to 'drivers/ide/cmd64x.c')
-rw-r--r--drivers/ide/cmd64x.c23
1 files changed, 14 insertions, 9 deletions
diff --git a/drivers/ide/cmd64x.c b/drivers/ide/cmd64x.c
index 3623bf013bcf..2f9688d87ecd 100644
--- a/drivers/ide/cmd64x.c
+++ b/drivers/ide/cmd64x.c
@@ -115,7 +115,7 @@ static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_
115 */ 115 */
116static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio) 116static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
117{ 117{
118 ide_hwif_t *hwif = HWIF(drive); 118 ide_hwif_t *hwif = drive->hwif;
119 struct pci_dev *dev = to_pci_dev(hwif->dev); 119 struct pci_dev *dev = to_pci_dev(hwif->dev);
120 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); 120 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
121 unsigned int cycle_time; 121 unsigned int cycle_time;
@@ -138,10 +138,12 @@ static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
138 * the slowest address setup timing ourselves. 138 * the slowest address setup timing ourselves.
139 */ 139 */
140 if (hwif->channel) { 140 if (hwif->channel) {
141 ide_drive_t *drives = hwif->drives; 141 ide_drive_t *pair = ide_get_pair_dev(drive);
142 142
143 drive->drive_data = setup_count; 143 drive->drive_data = setup_count;
144 setup_count = max(drives[0].drive_data, drives[1].drive_data); 144
145 if (pair)
146 setup_count = max_t(u8, setup_count, pair->drive_data);
145 } 147 }
146 148
147 if (setup_count > 5) /* shouldn't actually happen... */ 149 if (setup_count > 5) /* shouldn't actually happen... */
@@ -180,7 +182,7 @@ static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
180 182
181static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed) 183static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
182{ 184{
183 ide_hwif_t *hwif = HWIF(drive); 185 ide_hwif_t *hwif = drive->hwif;
184 struct pci_dev *dev = to_pci_dev(hwif->dev); 186 struct pci_dev *dev = to_pci_dev(hwif->dev);
185 u8 unit = drive->dn & 0x01; 187 u8 unit = drive->dn & 0x01;
186 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0; 188 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
@@ -226,7 +228,7 @@ static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
226 228
227static int cmd648_dma_end(ide_drive_t *drive) 229static int cmd648_dma_end(ide_drive_t *drive)
228{ 230{
229 ide_hwif_t *hwif = HWIF(drive); 231 ide_hwif_t *hwif = drive->hwif;
230 unsigned long base = hwif->dma_base - (hwif->channel * 8); 232 unsigned long base = hwif->dma_base - (hwif->channel * 8);
231 int err = ide_dma_end(drive); 233 int err = ide_dma_end(drive);
232 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : 234 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
@@ -242,7 +244,7 @@ static int cmd648_dma_end(ide_drive_t *drive)
242 244
243static int cmd64x_dma_end(ide_drive_t *drive) 245static int cmd64x_dma_end(ide_drive_t *drive)
244{ 246{
245 ide_hwif_t *hwif = HWIF(drive); 247 ide_hwif_t *hwif = drive->hwif;
246 struct pci_dev *dev = to_pci_dev(hwif->dev); 248 struct pci_dev *dev = to_pci_dev(hwif->dev);
247 int irq_reg = hwif->channel ? ARTTIM23 : CFR; 249 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
248 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : 250 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
@@ -259,7 +261,7 @@ static int cmd64x_dma_end(ide_drive_t *drive)
259 261
260static int cmd648_dma_test_irq(ide_drive_t *drive) 262static int cmd648_dma_test_irq(ide_drive_t *drive)
261{ 263{
262 ide_hwif_t *hwif = HWIF(drive); 264 ide_hwif_t *hwif = drive->hwif;
263 unsigned long base = hwif->dma_base - (hwif->channel * 8); 265 unsigned long base = hwif->dma_base - (hwif->channel * 8);
264 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : 266 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
265 MRDMODE_INTR_CH0; 267 MRDMODE_INTR_CH0;
@@ -282,7 +284,7 @@ static int cmd648_dma_test_irq(ide_drive_t *drive)
282 284
283static int cmd64x_dma_test_irq(ide_drive_t *drive) 285static int cmd64x_dma_test_irq(ide_drive_t *drive)
284{ 286{
285 ide_hwif_t *hwif = HWIF(drive); 287 ide_hwif_t *hwif = drive->hwif;
286 struct pci_dev *dev = to_pci_dev(hwif->dev); 288 struct pci_dev *dev = to_pci_dev(hwif->dev);
287 int irq_reg = hwif->channel ? ARTTIM23 : CFR; 289 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
288 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : 290 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
@@ -313,7 +315,7 @@ static int cmd64x_dma_test_irq(ide_drive_t *drive)
313 315
314static int cmd646_1_dma_end(ide_drive_t *drive) 316static int cmd646_1_dma_end(ide_drive_t *drive)
315{ 317{
316 ide_hwif_t *hwif = HWIF(drive); 318 ide_hwif_t *hwif = drive->hwif;
317 u8 dma_stat = 0, dma_cmd = 0; 319 u8 dma_stat = 0, dma_cmd = 0;
318 320
319 drive->waiting_for_dma = 0; 321 drive->waiting_for_dma = 0;
@@ -383,6 +385,7 @@ static const struct ide_dma_ops cmd64x_dma_ops = {
383 .dma_test_irq = cmd64x_dma_test_irq, 385 .dma_test_irq = cmd64x_dma_test_irq,
384 .dma_lost_irq = ide_dma_lost_irq, 386 .dma_lost_irq = ide_dma_lost_irq,
385 .dma_timeout = ide_dma_timeout, 387 .dma_timeout = ide_dma_timeout,
388 .dma_sff_read_status = ide_dma_sff_read_status,
386}; 389};
387 390
388static const struct ide_dma_ops cmd646_rev1_dma_ops = { 391static const struct ide_dma_ops cmd646_rev1_dma_ops = {
@@ -394,6 +397,7 @@ static const struct ide_dma_ops cmd646_rev1_dma_ops = {
394 .dma_test_irq = ide_dma_test_irq, 397 .dma_test_irq = ide_dma_test_irq,
395 .dma_lost_irq = ide_dma_lost_irq, 398 .dma_lost_irq = ide_dma_lost_irq,
396 .dma_timeout = ide_dma_timeout, 399 .dma_timeout = ide_dma_timeout,
400 .dma_sff_read_status = ide_dma_sff_read_status,
397}; 401};
398 402
399static const struct ide_dma_ops cmd648_dma_ops = { 403static const struct ide_dma_ops cmd648_dma_ops = {
@@ -405,6 +409,7 @@ static const struct ide_dma_ops cmd648_dma_ops = {
405 .dma_test_irq = cmd648_dma_test_irq, 409 .dma_test_irq = cmd648_dma_test_irq,
406 .dma_lost_irq = ide_dma_lost_irq, 410 .dma_lost_irq = ide_dma_lost_irq,
407 .dma_timeout = ide_dma_timeout, 411 .dma_timeout = ide_dma_timeout,
412 .dma_sff_read_status = ide_dma_sff_read_status,
408}; 413};
409 414
410static const struct ide_port_info cmd64x_chipsets[] __devinitdata = { 415static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {