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-rw-r--r--drivers/i2c/busses/Kconfig30
-rw-r--r--drivers/i2c/busses/Makefile3
-rw-r--r--drivers/i2c/busses/i2c-cpm.c9
-rw-r--r--drivers/i2c/busses/i2c-eg20t.c1
-rw-r--r--drivers/i2c/busses/i2c-ibm_iic.c9
-rw-r--r--drivers/i2c/busses/i2c-mpc.c22
-rw-r--r--drivers/i2c/busses/i2c-mxs.c412
-rw-r--r--drivers/i2c/busses/i2c-ocores.c16
-rw-r--r--drivers/i2c/busses/i2c-omap.c39
-rw-r--r--drivers/i2c/busses/i2c-puv3.c306
-rw-r--r--drivers/i2c/busses/i2c-stu300.c2
-rw-r--r--drivers/i2c/busses/i2c-tegra.c700
-rw-r--r--drivers/i2c/i2c-core.c2
13 files changed, 1508 insertions, 43 deletions
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 113505a6434e..230601e8853f 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -433,7 +433,7 @@ config I2C_IXP2000
433 433
434config I2C_MPC 434config I2C_MPC
435 tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" 435 tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
436 depends on PPC32 436 depends on PPC
437 help 437 help
438 If you say yes to this option, support will be included for the 438 If you say yes to this option, support will be included for the
439 built-in I2C interface on the MPC107, Tsi107, MPC512x, MPC52xx, 439 built-in I2C interface on the MPC107, Tsi107, MPC512x, MPC52xx,
@@ -452,6 +452,16 @@ config I2C_MV64XXX
452 This driver can also be built as a module. If so, the module 452 This driver can also be built as a module. If so, the module
453 will be called i2c-mv64xxx. 453 will be called i2c-mv64xxx.
454 454
455config I2C_MXS
456 tristate "Freescale i.MX28 I2C interface"
457 depends on SOC_IMX28
458 help
459 Say Y here if you want to use the I2C bus controller on
460 the Freescale i.MX28 processors.
461
462 This driver can also be built as a module. If so, the module
463 will be called i2c-mxs.
464
455config I2C_NOMADIK 465config I2C_NOMADIK
456 tristate "ST-Ericsson Nomadik/Ux500 I2C Controller" 466 tristate "ST-Ericsson Nomadik/Ux500 I2C Controller"
457 depends on PLAT_NOMADIK 467 depends on PLAT_NOMADIK
@@ -523,6 +533,17 @@ config I2C_PNX
523 This driver can also be built as a module. If so, the module 533 This driver can also be built as a module. If so, the module
524 will be called i2c-pnx. 534 will be called i2c-pnx.
525 535
536config I2C_PUV3
537 tristate "PKUnity v3 I2C bus support"
538 depends on UNICORE32 && ARCH_PUV3
539 select I2C_ALGOBIT
540 help
541 This driver supports the I2C IP inside the PKUnity-v3 SoC.
542 This I2C bus controller is under AMBA/AXI bus.
543
544 This driver can also be built as a module. If so, the module
545 will be called i2c-puv3.
546
526config I2C_PXA 547config I2C_PXA
527 tristate "Intel PXA2XX I2C adapter" 548 tristate "Intel PXA2XX I2C adapter"
528 depends on ARCH_PXA || ARCH_MMP 549 depends on ARCH_PXA || ARCH_MMP
@@ -607,6 +628,13 @@ config I2C_STU300
607 This driver can also be built as a module. If so, the module 628 This driver can also be built as a module. If so, the module
608 will be called i2c-stu300. 629 will be called i2c-stu300.
609 630
631config I2C_TEGRA
632 tristate "NVIDIA Tegra internal I2C controller"
633 depends on ARCH_TEGRA
634 help
635 If you say yes to this option, support will be included for the
636 I2C controller embedded in NVIDIA Tegra SOCs
637
610config I2C_VERSATILE 638config I2C_VERSATILE
611 tristate "ARM Versatile/Realview I2C bus support" 639 tristate "ARM Versatile/Realview I2C bus support"
612 depends on ARCH_VERSATILE || ARCH_REALVIEW || ARCH_VEXPRESS 640 depends on ARCH_VERSATILE || ARCH_REALVIEW || ARCH_VEXPRESS
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 9d2d0ec7fb23..3878c959d4fa 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
43obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o 43obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o
44obj-$(CONFIG_I2C_MPC) += i2c-mpc.o 44obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
45obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o 45obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o
46obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
46obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o 47obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
47obj-$(CONFIG_I2C_NUC900) += i2c-nuc900.o 48obj-$(CONFIG_I2C_NUC900) += i2c-nuc900.o
48obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o 49obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o
@@ -51,6 +52,7 @@ obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
51obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pca-platform.o 52obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pca-platform.o
52obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o 53obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o
53obj-$(CONFIG_I2C_PNX) += i2c-pnx.o 54obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
55obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
54obj-$(CONFIG_I2C_PXA) += i2c-pxa.o 56obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
55obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o 57obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o
56obj-$(CONFIG_I2C_S6000) += i2c-s6000.o 58obj-$(CONFIG_I2C_S6000) += i2c-s6000.o
@@ -58,6 +60,7 @@ obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o
58obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o 60obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
59obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o 61obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o
60obj-$(CONFIG_I2C_STU300) += i2c-stu300.o 62obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
63obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o
61obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o 64obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
62obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o 65obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
63obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o 66obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
diff --git a/drivers/i2c/busses/i2c-cpm.c b/drivers/i2c/busses/i2c-cpm.c
index f2de3be35df3..3a20961bef1e 100644
--- a/drivers/i2c/busses/i2c-cpm.c
+++ b/drivers/i2c/busses/i2c-cpm.c
@@ -634,8 +634,7 @@ static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
634 cpm_muram_free(cpm->i2c_addr); 634 cpm_muram_free(cpm->i2c_addr);
635} 635}
636 636
637static int __devinit cpm_i2c_probe(struct platform_device *ofdev, 637static int __devinit cpm_i2c_probe(struct platform_device *ofdev)
638 const struct of_device_id *match)
639{ 638{
640 int result, len; 639 int result, len;
641 struct cpm_i2c *cpm; 640 struct cpm_i2c *cpm;
@@ -718,7 +717,7 @@ static const struct of_device_id cpm_i2c_match[] = {
718 717
719MODULE_DEVICE_TABLE(of, cpm_i2c_match); 718MODULE_DEVICE_TABLE(of, cpm_i2c_match);
720 719
721static struct of_platform_driver cpm_i2c_driver = { 720static struct platform_driver cpm_i2c_driver = {
722 .probe = cpm_i2c_probe, 721 .probe = cpm_i2c_probe,
723 .remove = __devexit_p(cpm_i2c_remove), 722 .remove = __devexit_p(cpm_i2c_remove),
724 .driver = { 723 .driver = {
@@ -730,12 +729,12 @@ static struct of_platform_driver cpm_i2c_driver = {
730 729
731static int __init cpm_i2c_init(void) 730static int __init cpm_i2c_init(void)
732{ 731{
733 return of_register_platform_driver(&cpm_i2c_driver); 732 return platform_driver_register(&cpm_i2c_driver);
734} 733}
735 734
736static void __exit cpm_i2c_exit(void) 735static void __exit cpm_i2c_exit(void)
737{ 736{
738 of_unregister_platform_driver(&cpm_i2c_driver); 737 platform_driver_unregister(&cpm_i2c_driver);
739} 738}
740 739
741module_init(cpm_i2c_init); 740module_init(cpm_i2c_init);
diff --git a/drivers/i2c/busses/i2c-eg20t.c b/drivers/i2c/busses/i2c-eg20t.c
index 2e067dd2ee51..50ea1f43bdc1 100644
--- a/drivers/i2c/busses/i2c-eg20t.c
+++ b/drivers/i2c/busses/i2c-eg20t.c
@@ -29,6 +29,7 @@
29#include <linux/pci.h> 29#include <linux/pci.h>
30#include <linux/mutex.h> 30#include <linux/mutex.h>
31#include <linux/ktime.h> 31#include <linux/ktime.h>
32#include <linux/slab.h>
32 33
33#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */ 34#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
34#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */ 35#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
diff --git a/drivers/i2c/busses/i2c-ibm_iic.c b/drivers/i2c/busses/i2c-ibm_iic.c
index 6e3c38240336..e4f88dca99b5 100644
--- a/drivers/i2c/busses/i2c-ibm_iic.c
+++ b/drivers/i2c/busses/i2c-ibm_iic.c
@@ -691,8 +691,7 @@ static int __devinit iic_request_irq(struct platform_device *ofdev,
691/* 691/*
692 * Register single IIC interface 692 * Register single IIC interface
693 */ 693 */
694static int __devinit iic_probe(struct platform_device *ofdev, 694static int __devinit iic_probe(struct platform_device *ofdev)
695 const struct of_device_id *match)
696{ 695{
697 struct device_node *np = ofdev->dev.of_node; 696 struct device_node *np = ofdev->dev.of_node;
698 struct ibm_iic_private *dev; 697 struct ibm_iic_private *dev;
@@ -806,7 +805,7 @@ static const struct of_device_id ibm_iic_match[] = {
806 {} 805 {}
807}; 806};
808 807
809static struct of_platform_driver ibm_iic_driver = { 808static struct platform_driver ibm_iic_driver = {
810 .driver = { 809 .driver = {
811 .name = "ibm-iic", 810 .name = "ibm-iic",
812 .owner = THIS_MODULE, 811 .owner = THIS_MODULE,
@@ -818,12 +817,12 @@ static struct of_platform_driver ibm_iic_driver = {
818 817
819static int __init iic_init(void) 818static int __init iic_init(void)
820{ 819{
821 return of_register_platform_driver(&ibm_iic_driver); 820 return platform_driver_register(&ibm_iic_driver);
822} 821}
823 822
824static void __exit iic_exit(void) 823static void __exit iic_exit(void)
825{ 824{
826 of_unregister_platform_driver(&ibm_iic_driver); 825 platform_driver_unregister(&ibm_iic_driver);
827} 826}
828 827
829module_init(iic_init); 828module_init(iic_init);
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index b74e6dc6886c..75b984c519ac 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -560,8 +560,7 @@ static struct i2c_adapter mpc_ops = {
560 .timeout = HZ, 560 .timeout = HZ,
561}; 561};
562 562
563static int __devinit fsl_i2c_probe(struct platform_device *op, 563static int __devinit fsl_i2c_probe(struct platform_device *op)
564 const struct of_device_id *match)
565{ 564{
566 struct mpc_i2c *i2c; 565 struct mpc_i2c *i2c;
567 const u32 *prop; 566 const u32 *prop;
@@ -569,6 +568,9 @@ static int __devinit fsl_i2c_probe(struct platform_device *op,
569 int result = 0; 568 int result = 0;
570 int plen; 569 int plen;
571 570
571 if (!op->dev.of_match)
572 return -EINVAL;
573
572 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); 574 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
573 if (!i2c) 575 if (!i2c)
574 return -ENOMEM; 576 return -ENOMEM;
@@ -603,8 +605,8 @@ static int __devinit fsl_i2c_probe(struct platform_device *op,
603 clock = *prop; 605 clock = *prop;
604 } 606 }
605 607
606 if (match->data) { 608 if (op->dev.of_match->data) {
607 struct mpc_i2c_data *data = match->data; 609 struct mpc_i2c_data *data = op->dev.of_match->data;
608 data->setup(op->dev.of_node, i2c, clock, data->prescaler); 610 data->setup(op->dev.of_node, i2c, clock, data->prescaler);
609 } else { 611 } else {
610 /* Backwards compatibility */ 612 /* Backwards compatibility */
@@ -700,7 +702,7 @@ static const struct of_device_id mpc_i2c_of_match[] = {
700MODULE_DEVICE_TABLE(of, mpc_i2c_of_match); 702MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
701 703
702/* Structure for a device driver */ 704/* Structure for a device driver */
703static struct of_platform_driver mpc_i2c_driver = { 705static struct platform_driver mpc_i2c_driver = {
704 .probe = fsl_i2c_probe, 706 .probe = fsl_i2c_probe,
705 .remove = __devexit_p(fsl_i2c_remove), 707 .remove = __devexit_p(fsl_i2c_remove),
706 .driver = { 708 .driver = {
@@ -712,18 +714,12 @@ static struct of_platform_driver mpc_i2c_driver = {
712 714
713static int __init fsl_i2c_init(void) 715static int __init fsl_i2c_init(void)
714{ 716{
715 int rv; 717 return platform_driver_register(&mpc_i2c_driver);
716
717 rv = of_register_platform_driver(&mpc_i2c_driver);
718 if (rv)
719 printk(KERN_ERR DRV_NAME
720 " of_register_platform_driver failed (%i)\n", rv);
721 return rv;
722} 718}
723 719
724static void __exit fsl_i2c_exit(void) 720static void __exit fsl_i2c_exit(void)
725{ 721{
726 of_unregister_platform_driver(&mpc_i2c_driver); 722 platform_driver_unregister(&mpc_i2c_driver);
727} 723}
728 724
729module_init(fsl_i2c_init); 725module_init(fsl_i2c_init);
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
new file mode 100644
index 000000000000..8022e2390a5a
--- /dev/null
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -0,0 +1,412 @@
1/*
2 * Freescale MXS I2C bus driver
3 *
4 * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
5 *
6 * based on a (non-working) driver which was:
7 *
8 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9 *
10 * TODO: add dma-support if platform-support for it is available
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 */
18
19#include <linux/slab.h>
20#include <linux/device.h>
21#include <linux/module.h>
22#include <linux/i2c.h>
23#include <linux/err.h>
24#include <linux/interrupt.h>
25#include <linux/completion.h>
26#include <linux/platform_device.h>
27#include <linux/jiffies.h>
28#include <linux/io.h>
29
30#include <mach/common.h>
31
32#define DRIVER_NAME "mxs-i2c"
33
34#define MXS_I2C_CTRL0 (0x00)
35#define MXS_I2C_CTRL0_SET (0x04)
36
37#define MXS_I2C_CTRL0_SFTRST 0x80000000
38#define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
39#define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
40#define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
41#define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
42#define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
43#define MXS_I2C_CTRL0_DIRECTION 0x00010000
44#define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
45
46#define MXS_I2C_CTRL1 (0x40)
47#define MXS_I2C_CTRL1_SET (0x44)
48#define MXS_I2C_CTRL1_CLR (0x48)
49
50#define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
51#define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
52#define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
53#define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
54#define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
55#define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
56#define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
57#define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
58
59#define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
60 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
61 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
62 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
63 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
64 MXS_I2C_CTRL1_SLAVE_IRQ)
65
66#define MXS_I2C_QUEUECTRL (0x60)
67#define MXS_I2C_QUEUECTRL_SET (0x64)
68#define MXS_I2C_QUEUECTRL_CLR (0x68)
69
70#define MXS_I2C_QUEUECTRL_QUEUE_RUN 0x20
71#define MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE 0x04
72
73#define MXS_I2C_QUEUESTAT (0x70)
74#define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000
75
76#define MXS_I2C_QUEUECMD (0x80)
77
78#define MXS_I2C_QUEUEDATA (0x90)
79
80#define MXS_I2C_DATA (0xa0)
81
82
83#define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
84 MXS_I2C_CTRL0_PRE_SEND_START | \
85 MXS_I2C_CTRL0_MASTER_MODE | \
86 MXS_I2C_CTRL0_DIRECTION | \
87 MXS_I2C_CTRL0_XFER_COUNT(1))
88
89#define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
90 MXS_I2C_CTRL0_MASTER_MODE | \
91 MXS_I2C_CTRL0_DIRECTION)
92
93#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
94 MXS_I2C_CTRL0_MASTER_MODE)
95
96/**
97 * struct mxs_i2c_dev - per device, private MXS-I2C data
98 *
99 * @dev: driver model device node
100 * @regs: IO registers pointer
101 * @cmd_complete: completion object for transaction wait
102 * @cmd_err: error code for last transaction
103 * @adapter: i2c subsystem adapter node
104 */
105struct mxs_i2c_dev {
106 struct device *dev;
107 void __iomem *regs;
108 struct completion cmd_complete;
109 u32 cmd_err;
110 struct i2c_adapter adapter;
111};
112
113/*
114 * TODO: check if calls to here are really needed. If not, we could get rid of
115 * mxs_reset_block and the mach-dependency. Needs an I2C analyzer, probably.
116 */
117static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
118{
119 mxs_reset_block(i2c->regs);
120 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
121}
122
123static void mxs_i2c_pioq_setup_read(struct mxs_i2c_dev *i2c, u8 addr, int len,
124 int flags)
125{
126 u32 data;
127
128 writel(MXS_CMD_I2C_SELECT, i2c->regs + MXS_I2C_QUEUECMD);
129
130 data = (addr << 1) | I2C_SMBUS_READ;
131 writel(data, i2c->regs + MXS_I2C_DATA);
132
133 data = MXS_CMD_I2C_READ | MXS_I2C_CTRL0_XFER_COUNT(len) | flags;
134 writel(data, i2c->regs + MXS_I2C_QUEUECMD);
135}
136
137static void mxs_i2c_pioq_setup_write(struct mxs_i2c_dev *i2c,
138 u8 addr, u8 *buf, int len, int flags)
139{
140 u32 data;
141 int i, shifts_left;
142
143 data = MXS_CMD_I2C_WRITE | MXS_I2C_CTRL0_XFER_COUNT(len + 1) | flags;
144 writel(data, i2c->regs + MXS_I2C_QUEUECMD);
145
146 /*
147 * We have to copy the slave address (u8) and buffer (arbitrary number
148 * of u8) into the data register (u32). To achieve that, the u8 are put
149 * into the MSBs of 'data' which is then shifted for the next u8. When
150 * apropriate, 'data' is written to MXS_I2C_DATA. So, the first u32
151 * looks like this:
152 *
153 * 3 2 1 0
154 * 10987654|32109876|54321098|76543210
155 * --------+--------+--------+--------
156 * buffer+2|buffer+1|buffer+0|slave_addr
157 */
158
159 data = ((addr << 1) | I2C_SMBUS_WRITE) << 24;
160
161 for (i = 0; i < len; i++) {
162 data >>= 8;
163 data |= buf[i] << 24;
164 if ((i & 3) == 2)
165 writel(data, i2c->regs + MXS_I2C_DATA);
166 }
167
168 /* Write out the remaining bytes if any */
169 shifts_left = 24 - (i & 3) * 8;
170 if (shifts_left)
171 writel(data >> shifts_left, i2c->regs + MXS_I2C_DATA);
172}
173
174/*
175 * TODO: should be replaceable with a waitqueue and RD_QUEUE_IRQ (setting the
176 * rd_threshold to 1). Couldn't get this to work, though.
177 */
178static int mxs_i2c_wait_for_data(struct mxs_i2c_dev *i2c)
179{
180 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
181
182 while (readl(i2c->regs + MXS_I2C_QUEUESTAT)
183 & MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY) {
184 if (time_after(jiffies, timeout))
185 return -ETIMEDOUT;
186 cond_resched();
187 }
188
189 return 0;
190}
191
192static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len)
193{
194 u32 data;
195 int i;
196
197 for (i = 0; i < len; i++) {
198 if ((i & 3) == 0) {
199 if (mxs_i2c_wait_for_data(i2c))
200 return -ETIMEDOUT;
201 data = readl(i2c->regs + MXS_I2C_QUEUEDATA);
202 }
203 buf[i] = data & 0xff;
204 data >>= 8;
205 }
206
207 return 0;
208}
209
210/*
211 * Low level master read/write transaction.
212 */
213static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
214 int stop)
215{
216 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
217 int ret;
218 int flags;
219
220 init_completion(&i2c->cmd_complete);
221
222 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
223 msg->addr, msg->len, msg->flags, stop);
224
225 if (msg->len == 0)
226 return -EINVAL;
227
228 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
229
230 if (msg->flags & I2C_M_RD)
231 mxs_i2c_pioq_setup_read(i2c, msg->addr, msg->len, flags);
232 else
233 mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, msg->len,
234 flags);
235
236 writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
237 i2c->regs + MXS_I2C_QUEUECTRL_SET);
238
239 ret = wait_for_completion_timeout(&i2c->cmd_complete,
240 msecs_to_jiffies(1000));
241 if (ret == 0)
242 goto timeout;
243
244 if ((!i2c->cmd_err) && (msg->flags & I2C_M_RD)) {
245 ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len);
246 if (ret)
247 goto timeout;
248 }
249
250 if (i2c->cmd_err == -ENXIO)
251 mxs_i2c_reset(i2c);
252
253 dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
254
255 return i2c->cmd_err;
256
257timeout:
258 dev_dbg(i2c->dev, "Timeout!\n");
259 mxs_i2c_reset(i2c);
260 return -ETIMEDOUT;
261}
262
263static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
264 int num)
265{
266 int i;
267 int err;
268
269 for (i = 0; i < num; i++) {
270 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
271 if (err)
272 return err;
273 }
274
275 return num;
276}
277
278static u32 mxs_i2c_func(struct i2c_adapter *adap)
279{
280 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
281}
282
283static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
284{
285 struct mxs_i2c_dev *i2c = dev_id;
286 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
287
288 if (!stat)
289 return IRQ_NONE;
290
291 if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
292 i2c->cmd_err = -ENXIO;
293 else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
294 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
295 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
296 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
297 i2c->cmd_err = -EIO;
298 else
299 i2c->cmd_err = 0;
300
301 complete(&i2c->cmd_complete);
302
303 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
304 return IRQ_HANDLED;
305}
306
307static const struct i2c_algorithm mxs_i2c_algo = {
308 .master_xfer = mxs_i2c_xfer,
309 .functionality = mxs_i2c_func,
310};
311
312static int __devinit mxs_i2c_probe(struct platform_device *pdev)
313{
314 struct device *dev = &pdev->dev;
315 struct mxs_i2c_dev *i2c;
316 struct i2c_adapter *adap;
317 struct resource *res;
318 resource_size_t res_size;
319 int err, irq;
320
321 i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
322 if (!i2c)
323 return -ENOMEM;
324
325 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
326 if (!res)
327 return -ENOENT;
328
329 res_size = resource_size(res);
330 if (!devm_request_mem_region(dev, res->start, res_size, res->name))
331 return -EBUSY;
332
333 i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
334 if (!i2c->regs)
335 return -EBUSY;
336
337 irq = platform_get_irq(pdev, 0);
338 if (irq < 0)
339 return irq;
340
341 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
342 if (err)
343 return err;
344
345 i2c->dev = dev;
346 platform_set_drvdata(pdev, i2c);
347
348 /* Do reset to enforce correct startup after pinmuxing */
349 mxs_i2c_reset(i2c);
350 writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
351 i2c->regs + MXS_I2C_QUEUECTRL_SET);
352
353 adap = &i2c->adapter;
354 strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
355 adap->owner = THIS_MODULE;
356 adap->algo = &mxs_i2c_algo;
357 adap->dev.parent = dev;
358 adap->nr = pdev->id;
359 i2c_set_adapdata(adap, i2c);
360 err = i2c_add_numbered_adapter(adap);
361 if (err) {
362 dev_err(dev, "Failed to add adapter (%d)\n", err);
363 writel(MXS_I2C_CTRL0_SFTRST,
364 i2c->regs + MXS_I2C_CTRL0_SET);
365 return err;
366 }
367
368 return 0;
369}
370
371static int __devexit mxs_i2c_remove(struct platform_device *pdev)
372{
373 struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
374 int ret;
375
376 ret = i2c_del_adapter(&i2c->adapter);
377 if (ret)
378 return -EBUSY;
379
380 writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
381 i2c->regs + MXS_I2C_QUEUECTRL_CLR);
382 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
383
384 platform_set_drvdata(pdev, NULL);
385
386 return 0;
387}
388
389static struct platform_driver mxs_i2c_driver = {
390 .driver = {
391 .name = DRIVER_NAME,
392 .owner = THIS_MODULE,
393 },
394 .remove = __devexit_p(mxs_i2c_remove),
395};
396
397static int __init mxs_i2c_init(void)
398{
399 return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
400}
401subsys_initcall(mxs_i2c_init);
402
403static void __exit mxs_i2c_exit(void)
404{
405 platform_driver_unregister(&mxs_i2c_driver);
406}
407module_exit(mxs_i2c_exit);
408
409MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
410MODULE_DESCRIPTION("MXS I2C Bus Driver");
411MODULE_LICENSE("GPL");
412MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
index ef3bcb1ce864..1b46a9d9f907 100644
--- a/drivers/i2c/busses/i2c-ocores.c
+++ b/drivers/i2c/busses/i2c-ocores.c
@@ -249,7 +249,7 @@ static struct i2c_adapter ocores_adapter = {
249static int ocores_i2c_of_probe(struct platform_device* pdev, 249static int ocores_i2c_of_probe(struct platform_device* pdev,
250 struct ocores_i2c* i2c) 250 struct ocores_i2c* i2c)
251{ 251{
252 __be32* val; 252 const __be32* val;
253 253
254 val = of_get_property(pdev->dev.of_node, "regstep", NULL); 254 val = of_get_property(pdev->dev.of_node, "regstep", NULL);
255 if (!val) { 255 if (!val) {
@@ -330,9 +330,7 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
330 i2c->adap = ocores_adapter; 330 i2c->adap = ocores_adapter;
331 i2c_set_adapdata(&i2c->adap, i2c); 331 i2c_set_adapdata(&i2c->adap, i2c);
332 i2c->adap.dev.parent = &pdev->dev; 332 i2c->adap.dev.parent = &pdev->dev;
333#ifdef CONFIG_OF
334 i2c->adap.dev.of_node = pdev->dev.of_node; 333 i2c->adap.dev.of_node = pdev->dev.of_node;
335#endif
336 334
337 /* add i2c adapter to i2c tree */ 335 /* add i2c adapter to i2c tree */
338 ret = i2c_add_adapter(&i2c->adap); 336 ret = i2c_add_adapter(&i2c->adap);
@@ -390,15 +388,11 @@ static int ocores_i2c_resume(struct platform_device *pdev)
390#define ocores_i2c_resume NULL 388#define ocores_i2c_resume NULL
391#endif 389#endif
392 390
393#ifdef CONFIG_OF
394static struct of_device_id ocores_i2c_match[] = { 391static struct of_device_id ocores_i2c_match[] = {
395 { 392 { .compatible = "opencores,i2c-ocores", },
396 .compatible = "opencores,i2c-ocores", 393 {},
397 },
398 {},
399}; 394};
400MODULE_DEVICE_TABLE(of, ocores_i2c_match); 395MODULE_DEVICE_TABLE(of, ocores_i2c_match);
401#endif
402 396
403/* work with hotplug and coldplug */ 397/* work with hotplug and coldplug */
404MODULE_ALIAS("platform:ocores-i2c"); 398MODULE_ALIAS("platform:ocores-i2c");
@@ -411,9 +405,7 @@ static struct platform_driver ocores_i2c_driver = {
411 .driver = { 405 .driver = {
412 .owner = THIS_MODULE, 406 .owner = THIS_MODULE,
413 .name = "ocores-i2c", 407 .name = "ocores-i2c",
414#ifdef CONFIG_OF 408 .of_match_table = ocores_i2c_match,
415 .of_match_table = ocores_i2c_match,
416#endif
417 }, 409 },
418}; 410};
419 411
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index b605ff3a1fa0..58a58c7eaa17 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -378,9 +378,7 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
378 * REVISIT: Some wkup sources might not be needed. 378 * REVISIT: Some wkup sources might not be needed.
379 */ 379 */
380 dev->westate = OMAP_I2C_WE_ALL; 380 dev->westate = OMAP_I2C_WE_ALL;
381 if (dev->rev < OMAP_I2C_REV_ON_4430) 381 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
382 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
383 dev->westate);
384 } 382 }
385 } 383 }
386 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 384 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
@@ -847,11 +845,15 @@ complete:
847 dev_err(dev->dev, "Arbitration lost\n"); 845 dev_err(dev->dev, "Arbitration lost\n");
848 err |= OMAP_I2C_STAT_AL; 846 err |= OMAP_I2C_STAT_AL;
849 } 847 }
848 /*
849 * ProDB0017052: Clear ARDY bit twice
850 */
850 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | 851 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
851 OMAP_I2C_STAT_AL)) { 852 OMAP_I2C_STAT_AL)) {
852 omap_i2c_ack_stat(dev, stat & 853 omap_i2c_ack_stat(dev, stat &
853 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | 854 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
854 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); 855 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR |
856 OMAP_I2C_STAT_ARDY));
855 omap_i2c_complete_cmd(dev, err); 857 omap_i2c_complete_cmd(dev, err);
856 return IRQ_HANDLED; 858 return IRQ_HANDLED;
857 } 859 }
@@ -1137,12 +1139,41 @@ omap_i2c_remove(struct platform_device *pdev)
1137 return 0; 1139 return 0;
1138} 1140}
1139 1141
1142#ifdef CONFIG_SUSPEND
1143static int omap_i2c_suspend(struct device *dev)
1144{
1145 if (!pm_runtime_suspended(dev))
1146 if (dev->bus && dev->bus->pm && dev->bus->pm->runtime_suspend)
1147 dev->bus->pm->runtime_suspend(dev);
1148
1149 return 0;
1150}
1151
1152static int omap_i2c_resume(struct device *dev)
1153{
1154 if (!pm_runtime_suspended(dev))
1155 if (dev->bus && dev->bus->pm && dev->bus->pm->runtime_resume)
1156 dev->bus->pm->runtime_resume(dev);
1157
1158 return 0;
1159}
1160
1161static struct dev_pm_ops omap_i2c_pm_ops = {
1162 .suspend = omap_i2c_suspend,
1163 .resume = omap_i2c_resume,
1164};
1165#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1166#else
1167#define OMAP_I2C_PM_OPS NULL
1168#endif
1169
1140static struct platform_driver omap_i2c_driver = { 1170static struct platform_driver omap_i2c_driver = {
1141 .probe = omap_i2c_probe, 1171 .probe = omap_i2c_probe,
1142 .remove = omap_i2c_remove, 1172 .remove = omap_i2c_remove,
1143 .driver = { 1173 .driver = {
1144 .name = "omap_i2c", 1174 .name = "omap_i2c",
1145 .owner = THIS_MODULE, 1175 .owner = THIS_MODULE,
1176 .pm = OMAP_I2C_PM_OPS,
1146 }, 1177 },
1147}; 1178};
1148 1179
diff --git a/drivers/i2c/busses/i2c-puv3.c b/drivers/i2c/busses/i2c-puv3.c
new file mode 100644
index 000000000000..fac673940849
--- /dev/null
+++ b/drivers/i2c/busses/i2c-puv3.c
@@ -0,0 +1,306 @@
1/*
2 * I2C driver for PKUnity-v3 SoC
3 * Code specific to PKUnity SoC and UniCore ISA
4 *
5 * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn>
6 * Copyright (C) 2001-2010 Guan Xuetao
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/err.h>
16#include <linux/slab.h>
17#include <linux/types.h>
18#include <linux/delay.h>
19#include <linux/i2c.h>
20#include <linux/init.h>
21#include <linux/clk.h>
22#include <linux/platform_device.h>
23#include <linux/io.h>
24#include <mach/hardware.h>
25
26/*
27 * Poll the i2c status register until the specified bit is set.
28 * Returns 0 if timed out (100 msec).
29 */
30static short poll_status(unsigned long bit)
31{
32 int loop_cntr = 1000;
33
34 if (bit & I2C_STATUS_TFNF) {
35 do {
36 udelay(10);
37 } while (!(readl(I2C_STATUS) & bit) && (--loop_cntr > 0));
38 } else {
39 /* RXRDY handler */
40 do {
41 if (readl(I2C_TAR) == I2C_TAR_EEPROM)
42 msleep(20);
43 else
44 udelay(10);
45 } while (!(readl(I2C_RXFLR) & 0xf) && (--loop_cntr > 0));
46 }
47
48 return (loop_cntr > 0);
49}
50
51static int xfer_read(struct i2c_adapter *adap, unsigned char *buf, int length)
52{
53 int i2c_reg = *buf;
54
55 /* Read data */
56 while (length--) {
57 if (!poll_status(I2C_STATUS_TFNF)) {
58 dev_dbg(&adap->dev, "Tx FIFO Not Full timeout\n");
59 return -ETIMEDOUT;
60 }
61
62 /* send addr */
63 writel(i2c_reg | I2C_DATACMD_WRITE, I2C_DATACMD);
64
65 /* get ready to next write */
66 i2c_reg++;
67
68 /* send read CMD */
69 writel(I2C_DATACMD_READ, I2C_DATACMD);
70
71 /* wait until the Rx FIFO have available */
72 if (!poll_status(I2C_STATUS_RFNE)) {
73 dev_dbg(&adap->dev, "RXRDY timeout\n");
74 return -ETIMEDOUT;
75 }
76
77 /* read the data to buf */
78 *buf = (readl(I2C_DATACMD) & I2C_DATACMD_DAT_MASK);
79 buf++;
80 }
81
82 return 0;
83}
84
85static int xfer_write(struct i2c_adapter *adap, unsigned char *buf, int length)
86{
87 int i2c_reg = *buf;
88
89 /* Do nothing but storing the reg_num to a static variable */
90 if (i2c_reg == -1) {
91 printk(KERN_WARNING "Error i2c reg\n");
92 return -ETIMEDOUT;
93 }
94
95 if (length == 1)
96 return 0;
97
98 buf++;
99 length--;
100 while (length--) {
101 /* send addr */
102 writel(i2c_reg | I2C_DATACMD_WRITE, I2C_DATACMD);
103
104 /* send write CMD */
105 writel(*buf | I2C_DATACMD_WRITE, I2C_DATACMD);
106
107 /* wait until the Rx FIFO have available */
108 msleep(20);
109
110 /* read the data to buf */
111 i2c_reg++;
112 buf++;
113 }
114
115 return 0;
116}
117
118/*
119 * Generic i2c master transfer entrypoint.
120 *
121 */
122static int puv3_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *pmsg,
123 int num)
124{
125 int i, ret;
126 unsigned char swap;
127
128 /* Disable i2c */
129 writel(I2C_ENABLE_DISABLE, I2C_ENABLE);
130
131 /* Set the work mode and speed*/
132 writel(I2C_CON_MASTER | I2C_CON_SPEED_STD | I2C_CON_SLAVEDISABLE, I2C_CON);
133
134 writel(pmsg->addr, I2C_TAR);
135
136 /* Enable i2c */
137 writel(I2C_ENABLE_ENABLE, I2C_ENABLE);
138
139 dev_dbg(&adap->dev, "puv3_i2c_xfer: processing %d messages:\n", num);
140
141 for (i = 0; i < num; i++) {
142 dev_dbg(&adap->dev, " #%d: %sing %d byte%s %s 0x%02x\n", i,
143 pmsg->flags & I2C_M_RD ? "read" : "writ",
144 pmsg->len, pmsg->len > 1 ? "s" : "",
145 pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr);
146
147 if (pmsg->len && pmsg->buf) { /* sanity check */
148 if (pmsg->flags & I2C_M_RD)
149 ret = xfer_read(adap, pmsg->buf, pmsg->len);
150 else
151 ret = xfer_write(adap, pmsg->buf, pmsg->len);
152
153 if (ret)
154 return ret;
155
156 }
157 dev_dbg(&adap->dev, "transfer complete\n");
158 pmsg++; /* next message */
159 }
160
161 /* XXX: fixup be16_to_cpu in bq27x00_battery.c */
162 if (pmsg->addr == I2C_TAR_PWIC) {
163 swap = pmsg->buf[0];
164 pmsg->buf[0] = pmsg->buf[1];
165 pmsg->buf[1] = swap;
166 }
167
168 return i;
169}
170
171/*
172 * Return list of supported functionality.
173 */
174static u32 puv3_i2c_func(struct i2c_adapter *adapter)
175{
176 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
177}
178
179static struct i2c_algorithm puv3_i2c_algorithm = {
180 .master_xfer = puv3_i2c_xfer,
181 .functionality = puv3_i2c_func,
182};
183
184/*
185 * Main initialization routine.
186 */
187static int __devinit puv3_i2c_probe(struct platform_device *pdev)
188{
189 struct i2c_adapter *adapter;
190 struct resource *mem;
191 int rc;
192
193 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
194 if (!mem)
195 return -ENODEV;
196
197 if (!request_mem_region(mem->start, resource_size(mem), "puv3_i2c"))
198 return -EBUSY;
199
200 adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
201 if (adapter == NULL) {
202 dev_err(&pdev->dev, "can't allocate inteface!\n");
203 rc = -ENOMEM;
204 goto fail_nomem;
205 }
206 snprintf(adapter->name, sizeof(adapter->name), "PUV3-I2C at 0x%08x",
207 mem->start);
208 adapter->algo = &puv3_i2c_algorithm;
209 adapter->class = I2C_CLASS_HWMON;
210 adapter->dev.parent = &pdev->dev;
211
212 platform_set_drvdata(pdev, adapter);
213
214 adapter->nr = pdev->id;
215 rc = i2c_add_numbered_adapter(adapter);
216 if (rc) {
217 dev_err(&pdev->dev, "Adapter '%s' registration failed\n",
218 adapter->name);
219 goto fail_add_adapter;
220 }
221
222 dev_info(&pdev->dev, "PKUnity v3 i2c bus adapter.\n");
223 return 0;
224
225fail_add_adapter:
226 platform_set_drvdata(pdev, NULL);
227 kfree(adapter);
228fail_nomem:
229 release_mem_region(mem->start, resource_size(mem));
230
231 return rc;
232}
233
234static int __devexit puv3_i2c_remove(struct platform_device *pdev)
235{
236 struct i2c_adapter *adapter = platform_get_drvdata(pdev);
237 struct resource *mem;
238 int rc;
239
240 rc = i2c_del_adapter(adapter);
241 if (rc) {
242 dev_err(&pdev->dev, "Adapter '%s' delete fail\n",
243 adapter->name);
244 return rc;
245 }
246
247 put_device(&pdev->dev);
248 platform_set_drvdata(pdev, NULL);
249
250 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
251 release_mem_region(mem->start, resource_size(mem));
252
253 return rc;
254}
255
256#ifdef CONFIG_PM
257static int puv3_i2c_suspend(struct platform_device *dev, pm_message_t state)
258{
259 int poll_count;
260 /* Disable the IIC */
261 writel(I2C_ENABLE_DISABLE, I2C_ENABLE);
262 for (poll_count = 0; poll_count < 50; poll_count++) {
263 if (readl(I2C_ENSTATUS) & I2C_ENSTATUS_ENABLE)
264 udelay(25);
265 }
266
267 return 0;
268}
269
270static int puv3_i2c_resume(struct platform_device *dev)
271{
272 return 0 ;
273}
274#else
275#define puv3_i2c_suspend NULL
276#define puv3_i2c_resume NULL
277#endif
278
279MODULE_ALIAS("platform:puv3_i2c");
280
281static struct platform_driver puv3_i2c_driver = {
282 .probe = puv3_i2c_probe,
283 .remove = __devexit_p(puv3_i2c_remove),
284 .suspend = puv3_i2c_suspend,
285 .resume = puv3_i2c_resume,
286 .driver = {
287 .name = "PKUnity-v3-I2C",
288 .owner = THIS_MODULE,
289 }
290};
291
292static int __init puv3_i2c_init(void)
293{
294 return platform_driver_register(&puv3_i2c_driver);
295}
296
297static void __exit puv3_i2c_exit(void)
298{
299 platform_driver_unregister(&puv3_i2c_driver);
300}
301
302module_init(puv3_i2c_init);
303module_exit(puv3_i2c_exit);
304
305MODULE_DESCRIPTION("PKUnity v3 I2C driver");
306MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c
index 495be451d326..266135ddf7fa 100644
--- a/drivers/i2c/busses/i2c-stu300.c
+++ b/drivers/i2c/busses/i2c-stu300.c
@@ -942,7 +942,7 @@ stu300_probe(struct platform_device *pdev)
942 adap->owner = THIS_MODULE; 942 adap->owner = THIS_MODULE;
943 /* DDC class but actually often used for more generic I2C */ 943 /* DDC class but actually often used for more generic I2C */
944 adap->class = I2C_CLASS_DDC; 944 adap->class = I2C_CLASS_DDC;
945 strncpy(adap->name, "ST Microelectronics DDC I2C adapter", 945 strlcpy(adap->name, "ST Microelectronics DDC I2C adapter",
946 sizeof(adap->name)); 946 sizeof(adap->name));
947 adap->nr = bus_nr; 947 adap->nr = bus_nr;
948 adap->algo = &stu300_algo; 948 adap->algo = &stu300_algo;
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
new file mode 100644
index 000000000000..3921f664c9c3
--- /dev/null
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -0,0 +1,700 @@
1/*
2 * drivers/i2c/busses/i2c-tegra.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/err.h>
23#include <linux/i2c.h>
24#include <linux/io.h>
25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/slab.h>
28#include <linux/i2c-tegra.h>
29
30#include <asm/unaligned.h>
31
32#include <mach/clk.h>
33
34#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
35#define BYTES_PER_FIFO_WORD 4
36
37#define I2C_CNFG 0x000
38#define I2C_CNFG_PACKET_MODE_EN (1<<10)
39#define I2C_CNFG_NEW_MASTER_FSM (1<<11)
40#define I2C_SL_CNFG 0x020
41#define I2C_SL_CNFG_NEWSL (1<<2)
42#define I2C_SL_ADDR1 0x02c
43#define I2C_TX_FIFO 0x050
44#define I2C_RX_FIFO 0x054
45#define I2C_PACKET_TRANSFER_STATUS 0x058
46#define I2C_FIFO_CONTROL 0x05c
47#define I2C_FIFO_CONTROL_TX_FLUSH (1<<1)
48#define I2C_FIFO_CONTROL_RX_FLUSH (1<<0)
49#define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
50#define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
51#define I2C_FIFO_STATUS 0x060
52#define I2C_FIFO_STATUS_TX_MASK 0xF0
53#define I2C_FIFO_STATUS_TX_SHIFT 4
54#define I2C_FIFO_STATUS_RX_MASK 0x0F
55#define I2C_FIFO_STATUS_RX_SHIFT 0
56#define I2C_INT_MASK 0x064
57#define I2C_INT_STATUS 0x068
58#define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
59#define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
60#define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
61#define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
62#define I2C_INT_NO_ACK (1<<3)
63#define I2C_INT_ARBITRATION_LOST (1<<2)
64#define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
65#define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
66#define I2C_CLK_DIVISOR 0x06c
67
68#define DVC_CTRL_REG1 0x000
69#define DVC_CTRL_REG1_INTR_EN (1<<10)
70#define DVC_CTRL_REG2 0x004
71#define DVC_CTRL_REG3 0x008
72#define DVC_CTRL_REG3_SW_PROG (1<<26)
73#define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
74#define DVC_STATUS 0x00c
75#define DVC_STATUS_I2C_DONE_INTR (1<<30)
76
77#define I2C_ERR_NONE 0x00
78#define I2C_ERR_NO_ACK 0x01
79#define I2C_ERR_ARBITRATION_LOST 0x02
80
81#define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
82#define PACKET_HEADER0_PACKET_ID_SHIFT 16
83#define PACKET_HEADER0_CONT_ID_SHIFT 12
84#define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
85
86#define I2C_HEADER_HIGHSPEED_MODE (1<<22)
87#define I2C_HEADER_CONT_ON_NAK (1<<21)
88#define I2C_HEADER_SEND_START_BYTE (1<<20)
89#define I2C_HEADER_READ (1<<19)
90#define I2C_HEADER_10BIT_ADDR (1<<18)
91#define I2C_HEADER_IE_ENABLE (1<<17)
92#define I2C_HEADER_REPEAT_START (1<<16)
93#define I2C_HEADER_MASTER_ADDR_SHIFT 12
94#define I2C_HEADER_SLAVE_ADDR_SHIFT 1
95
96/**
97 * struct tegra_i2c_dev - per device i2c context
98 * @dev: device reference for power management
99 * @adapter: core i2c layer adapter information
100 * @clk: clock reference for i2c controller
101 * @i2c_clk: clock reference for i2c bus
102 * @iomem: memory resource for registers
103 * @base: ioremapped registers cookie
104 * @cont_id: i2c controller id, used for for packet header
105 * @irq: irq number of transfer complete interrupt
106 * @is_dvc: identifies the DVC i2c controller, has a different register layout
107 * @msg_complete: transfer completion notifier
108 * @msg_err: error code for completed message
109 * @msg_buf: pointer to current message data
110 * @msg_buf_remaining: size of unsent data in the message buffer
111 * @msg_read: identifies read transfers
112 * @bus_clk_rate: current i2c bus clock rate
113 * @is_suspended: prevents i2c controller accesses after suspend is called
114 */
115struct tegra_i2c_dev {
116 struct device *dev;
117 struct i2c_adapter adapter;
118 struct clk *clk;
119 struct clk *i2c_clk;
120 struct resource *iomem;
121 void __iomem *base;
122 int cont_id;
123 int irq;
124 int is_dvc;
125 struct completion msg_complete;
126 int msg_err;
127 u8 *msg_buf;
128 size_t msg_buf_remaining;
129 int msg_read;
130 unsigned long bus_clk_rate;
131 bool is_suspended;
132};
133
134static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
135{
136 writel(val, i2c_dev->base + reg);
137}
138
139static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
140{
141 return readl(i2c_dev->base + reg);
142}
143
144/*
145 * i2c_writel and i2c_readl will offset the register if necessary to talk
146 * to the I2C block inside the DVC block
147 */
148static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
149 unsigned long reg)
150{
151 if (i2c_dev->is_dvc)
152 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
153 return reg;
154}
155
156static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
157 unsigned long reg)
158{
159 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
160}
161
162static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
163{
164 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
165}
166
167static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
168 unsigned long reg, int len)
169{
170 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
171}
172
173static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
174 unsigned long reg, int len)
175{
176 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
177}
178
179static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
180{
181 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
182 int_mask &= ~mask;
183 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
184}
185
186static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
187{
188 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
189 int_mask |= mask;
190 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
191}
192
193static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
194{
195 unsigned long timeout = jiffies + HZ;
196 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
197 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
198 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
199
200 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
201 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
202 if (time_after(jiffies, timeout)) {
203 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
204 return -ETIMEDOUT;
205 }
206 msleep(1);
207 }
208 return 0;
209}
210
211static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
212{
213 u32 val;
214 int rx_fifo_avail;
215 u8 *buf = i2c_dev->msg_buf;
216 size_t buf_remaining = i2c_dev->msg_buf_remaining;
217 int words_to_transfer;
218
219 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
220 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
221 I2C_FIFO_STATUS_RX_SHIFT;
222
223 /* Rounds down to not include partial word at the end of buf */
224 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
225 if (words_to_transfer > rx_fifo_avail)
226 words_to_transfer = rx_fifo_avail;
227
228 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
229
230 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
231 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
232 rx_fifo_avail -= words_to_transfer;
233
234 /*
235 * If there is a partial word at the end of buf, handle it manually to
236 * prevent overwriting past the end of buf
237 */
238 if (rx_fifo_avail > 0 && buf_remaining > 0) {
239 BUG_ON(buf_remaining > 3);
240 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
241 memcpy(buf, &val, buf_remaining);
242 buf_remaining = 0;
243 rx_fifo_avail--;
244 }
245
246 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
247 i2c_dev->msg_buf_remaining = buf_remaining;
248 i2c_dev->msg_buf = buf;
249 return 0;
250}
251
252static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
253{
254 u32 val;
255 int tx_fifo_avail;
256 u8 *buf = i2c_dev->msg_buf;
257 size_t buf_remaining = i2c_dev->msg_buf_remaining;
258 int words_to_transfer;
259
260 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
261 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
262 I2C_FIFO_STATUS_TX_SHIFT;
263
264 /* Rounds down to not include partial word at the end of buf */
265 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
266 if (words_to_transfer > tx_fifo_avail)
267 words_to_transfer = tx_fifo_avail;
268
269 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
270
271 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
272 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
273 tx_fifo_avail -= words_to_transfer;
274
275 /*
276 * If there is a partial word at the end of buf, handle it manually to
277 * prevent reading past the end of buf, which could cross a page
278 * boundary and fault.
279 */
280 if (tx_fifo_avail > 0 && buf_remaining > 0) {
281 BUG_ON(buf_remaining > 3);
282 memcpy(&val, buf, buf_remaining);
283 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
284 buf_remaining = 0;
285 tx_fifo_avail--;
286 }
287
288 BUG_ON(tx_fifo_avail > 0 && buf_remaining > 0);
289 i2c_dev->msg_buf_remaining = buf_remaining;
290 i2c_dev->msg_buf = buf;
291 return 0;
292}
293
294/*
295 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
296 * block. This block is identical to the rest of the I2C blocks, except that
297 * it only supports master mode, it has registers moved around, and it needs
298 * some extra init to get it into I2C mode. The register moves are handled
299 * by i2c_readl and i2c_writel
300 */
301static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
302{
303 u32 val = 0;
304 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
305 val |= DVC_CTRL_REG3_SW_PROG;
306 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
307 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
308
309 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
310 val |= DVC_CTRL_REG1_INTR_EN;
311 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
312}
313
314static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
315{
316 u32 val;
317 int err = 0;
318
319 clk_enable(i2c_dev->clk);
320
321 tegra_periph_reset_assert(i2c_dev->clk);
322 udelay(2);
323 tegra_periph_reset_deassert(i2c_dev->clk);
324
325 if (i2c_dev->is_dvc)
326 tegra_dvc_init(i2c_dev);
327
328 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN;
329 i2c_writel(i2c_dev, val, I2C_CNFG);
330 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
331 clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
332
333 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
334 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
335 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
336
337 if (tegra_i2c_flush_fifos(i2c_dev))
338 err = -ETIMEDOUT;
339
340 clk_disable(i2c_dev->clk);
341 return err;
342}
343
344static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
345{
346 u32 status;
347 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
348 struct tegra_i2c_dev *i2c_dev = dev_id;
349
350 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
351
352 if (status == 0) {
353 dev_warn(i2c_dev->dev, "interrupt with no status\n");
354 return IRQ_NONE;
355 }
356
357 if (unlikely(status & status_err)) {
358 if (status & I2C_INT_NO_ACK)
359 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
360 if (status & I2C_INT_ARBITRATION_LOST)
361 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
362 complete(&i2c_dev->msg_complete);
363 goto err;
364 }
365
366 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
367 if (i2c_dev->msg_buf_remaining)
368 tegra_i2c_empty_rx_fifo(i2c_dev);
369 else
370 BUG();
371 }
372
373 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
374 if (i2c_dev->msg_buf_remaining)
375 tegra_i2c_fill_tx_fifo(i2c_dev);
376 else
377 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
378 }
379
380 if ((status & I2C_INT_PACKET_XFER_COMPLETE) &&
381 !i2c_dev->msg_buf_remaining)
382 complete(&i2c_dev->msg_complete);
383
384 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
385 if (i2c_dev->is_dvc)
386 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
387 return IRQ_HANDLED;
388err:
389 /* An error occured, mask all interrupts */
390 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
391 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
392 I2C_INT_RX_FIFO_DATA_REQ);
393 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
394 return IRQ_HANDLED;
395}
396
397static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
398 struct i2c_msg *msg, int stop)
399{
400 u32 packet_header;
401 u32 int_mask;
402 int ret;
403
404 tegra_i2c_flush_fifos(i2c_dev);
405 i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS);
406
407 if (msg->len == 0)
408 return -EINVAL;
409
410 i2c_dev->msg_buf = msg->buf;
411 i2c_dev->msg_buf_remaining = msg->len;
412 i2c_dev->msg_err = I2C_ERR_NONE;
413 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
414 INIT_COMPLETION(i2c_dev->msg_complete);
415
416 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
417 PACKET_HEADER0_PROTOCOL_I2C |
418 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
419 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
420 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
421
422 packet_header = msg->len - 1;
423 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
424
425 packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
426 packet_header |= I2C_HEADER_IE_ENABLE;
427 if (msg->flags & I2C_M_TEN)
428 packet_header |= I2C_HEADER_10BIT_ADDR;
429 if (msg->flags & I2C_M_IGNORE_NAK)
430 packet_header |= I2C_HEADER_CONT_ON_NAK;
431 if (msg->flags & I2C_M_NOSTART)
432 packet_header |= I2C_HEADER_REPEAT_START;
433 if (msg->flags & I2C_M_RD)
434 packet_header |= I2C_HEADER_READ;
435 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
436
437 if (!(msg->flags & I2C_M_RD))
438 tegra_i2c_fill_tx_fifo(i2c_dev);
439
440 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
441 if (msg->flags & I2C_M_RD)
442 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
443 else if (i2c_dev->msg_buf_remaining)
444 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
445 tegra_i2c_unmask_irq(i2c_dev, int_mask);
446 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
447 i2c_readl(i2c_dev, I2C_INT_MASK));
448
449 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
450 tegra_i2c_mask_irq(i2c_dev, int_mask);
451
452 if (WARN_ON(ret == 0)) {
453 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
454
455 tegra_i2c_init(i2c_dev);
456 return -ETIMEDOUT;
457 }
458
459 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
460 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
461
462 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
463 return 0;
464
465 tegra_i2c_init(i2c_dev);
466 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
467 if (msg->flags & I2C_M_IGNORE_NAK)
468 return 0;
469 return -EREMOTEIO;
470 }
471
472 return -EIO;
473}
474
475static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
476 int num)
477{
478 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
479 int i;
480 int ret = 0;
481
482 if (i2c_dev->is_suspended)
483 return -EBUSY;
484
485 clk_enable(i2c_dev->clk);
486 for (i = 0; i < num; i++) {
487 int stop = (i == (num - 1)) ? 1 : 0;
488 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
489 if (ret)
490 break;
491 }
492 clk_disable(i2c_dev->clk);
493 return ret ?: i;
494}
495
496static u32 tegra_i2c_func(struct i2c_adapter *adap)
497{
498 return I2C_FUNC_I2C;
499}
500
501static const struct i2c_algorithm tegra_i2c_algo = {
502 .master_xfer = tegra_i2c_xfer,
503 .functionality = tegra_i2c_func,
504};
505
506static int tegra_i2c_probe(struct platform_device *pdev)
507{
508 struct tegra_i2c_dev *i2c_dev;
509 struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
510 struct resource *res;
511 struct resource *iomem;
512 struct clk *clk;
513 struct clk *i2c_clk;
514 void *base;
515 int irq;
516 int ret = 0;
517
518 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
519 if (!res) {
520 dev_err(&pdev->dev, "no mem resource\n");
521 return -EINVAL;
522 }
523 iomem = request_mem_region(res->start, resource_size(res), pdev->name);
524 if (!iomem) {
525 dev_err(&pdev->dev, "I2C region already claimed\n");
526 return -EBUSY;
527 }
528
529 base = ioremap(iomem->start, resource_size(iomem));
530 if (!base) {
531 dev_err(&pdev->dev, "Cannot ioremap I2C region\n");
532 return -ENOMEM;
533 }
534
535 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
536 if (!res) {
537 dev_err(&pdev->dev, "no irq resource\n");
538 ret = -EINVAL;
539 goto err_iounmap;
540 }
541 irq = res->start;
542
543 clk = clk_get(&pdev->dev, NULL);
544 if (IS_ERR(clk)) {
545 dev_err(&pdev->dev, "missing controller clock");
546 ret = PTR_ERR(clk);
547 goto err_release_region;
548 }
549
550 i2c_clk = clk_get(&pdev->dev, "i2c");
551 if (IS_ERR(i2c_clk)) {
552 dev_err(&pdev->dev, "missing bus clock");
553 ret = PTR_ERR(i2c_clk);
554 goto err_clk_put;
555 }
556
557 i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev), GFP_KERNEL);
558 if (!i2c_dev) {
559 ret = -ENOMEM;
560 goto err_i2c_clk_put;
561 }
562
563 i2c_dev->base = base;
564 i2c_dev->clk = clk;
565 i2c_dev->i2c_clk = i2c_clk;
566 i2c_dev->iomem = iomem;
567 i2c_dev->adapter.algo = &tegra_i2c_algo;
568 i2c_dev->irq = irq;
569 i2c_dev->cont_id = pdev->id;
570 i2c_dev->dev = &pdev->dev;
571 i2c_dev->bus_clk_rate = pdata ? pdata->bus_clk_rate : 100000;
572
573 if (pdev->id == 3)
574 i2c_dev->is_dvc = 1;
575 init_completion(&i2c_dev->msg_complete);
576
577 platform_set_drvdata(pdev, i2c_dev);
578
579 ret = tegra_i2c_init(i2c_dev);
580 if (ret) {
581 dev_err(&pdev->dev, "Failed to initialize i2c controller");
582 goto err_free;
583 }
584
585 ret = request_irq(i2c_dev->irq, tegra_i2c_isr, 0, pdev->name, i2c_dev);
586 if (ret) {
587 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
588 goto err_free;
589 }
590
591 clk_enable(i2c_dev->i2c_clk);
592
593 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
594 i2c_dev->adapter.owner = THIS_MODULE;
595 i2c_dev->adapter.class = I2C_CLASS_HWMON;
596 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
597 sizeof(i2c_dev->adapter.name));
598 i2c_dev->adapter.algo = &tegra_i2c_algo;
599 i2c_dev->adapter.dev.parent = &pdev->dev;
600 i2c_dev->adapter.nr = pdev->id;
601
602 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
603 if (ret) {
604 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
605 goto err_free_irq;
606 }
607
608 return 0;
609err_free_irq:
610 free_irq(i2c_dev->irq, i2c_dev);
611err_free:
612 kfree(i2c_dev);
613err_i2c_clk_put:
614 clk_put(i2c_clk);
615err_clk_put:
616 clk_put(clk);
617err_release_region:
618 release_mem_region(iomem->start, resource_size(iomem));
619err_iounmap:
620 iounmap(base);
621 return ret;
622}
623
624static int tegra_i2c_remove(struct platform_device *pdev)
625{
626 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
627 i2c_del_adapter(&i2c_dev->adapter);
628 free_irq(i2c_dev->irq, i2c_dev);
629 clk_put(i2c_dev->i2c_clk);
630 clk_put(i2c_dev->clk);
631 release_mem_region(i2c_dev->iomem->start,
632 resource_size(i2c_dev->iomem));
633 iounmap(i2c_dev->base);
634 kfree(i2c_dev);
635 return 0;
636}
637
638#ifdef CONFIG_PM
639static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
640{
641 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
642
643 i2c_lock_adapter(&i2c_dev->adapter);
644 i2c_dev->is_suspended = true;
645 i2c_unlock_adapter(&i2c_dev->adapter);
646
647 return 0;
648}
649
650static int tegra_i2c_resume(struct platform_device *pdev)
651{
652 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
653 int ret;
654
655 i2c_lock_adapter(&i2c_dev->adapter);
656
657 ret = tegra_i2c_init(i2c_dev);
658
659 if (ret) {
660 i2c_unlock_adapter(&i2c_dev->adapter);
661 return ret;
662 }
663
664 i2c_dev->is_suspended = false;
665
666 i2c_unlock_adapter(&i2c_dev->adapter);
667
668 return 0;
669}
670#endif
671
672static struct platform_driver tegra_i2c_driver = {
673 .probe = tegra_i2c_probe,
674 .remove = tegra_i2c_remove,
675#ifdef CONFIG_PM
676 .suspend = tegra_i2c_suspend,
677 .resume = tegra_i2c_resume,
678#endif
679 .driver = {
680 .name = "tegra-i2c",
681 .owner = THIS_MODULE,
682 },
683};
684
685static int __init tegra_i2c_init_driver(void)
686{
687 return platform_driver_register(&tegra_i2c_driver);
688}
689
690static void __exit tegra_i2c_exit_driver(void)
691{
692 platform_driver_unregister(&tegra_i2c_driver);
693}
694
695subsys_initcall(tegra_i2c_init_driver);
696module_exit(tegra_i2c_exit_driver);
697
698MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
699MODULE_AUTHOR("Colin Cross");
700MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index f0bd5bcdf563..045ba6efea48 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -537,9 +537,7 @@ i2c_new_device(struct i2c_adapter *adap, struct i2c_board_info const *info)
537 client->dev.parent = &client->adapter->dev; 537 client->dev.parent = &client->adapter->dev;
538 client->dev.bus = &i2c_bus_type; 538 client->dev.bus = &i2c_bus_type;
539 client->dev.type = &i2c_client_type; 539 client->dev.type = &i2c_client_type;
540#ifdef CONFIG_OF
541 client->dev.of_node = info->of_node; 540 client->dev.of_node = info->of_node;
542#endif
543 541
544 dev_set_name(&client->dev, "%d-%04x", i2c_adapter_id(adap), 542 dev_set_name(&client->dev, "%d-%04x", i2c_adapter_id(adap),
545 client->addr); 543 client->addr);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 10:53:50 -0500