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-rw-r--r--drivers/i2c/busses/Kconfig2
-rw-r--r--drivers/i2c/busses/i2c-bfin-twi.c283
2 files changed, 177 insertions, 108 deletions
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 495c971ce5bf..7d538ddfd37e 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -100,7 +100,7 @@ config I2C_AU1550
100 100
101config I2C_BLACKFIN_TWI 101config I2C_BLACKFIN_TWI
102 tristate "Blackfin TWI I2C support" 102 tristate "Blackfin TWI I2C support"
103 depends on BF534 || BF536 || BF537 103 depends on BF534 || BF536 || BF537 || BF54x
104 help 104 help
105 This is the TWI I2C device driver for Blackfin 534/536/537/54x. 105 This is the TWI I2C device driver for Blackfin 534/536/537/54x.
106 This driver can also be built as a module. If so, the module 106 This driver can also be built as a module. If so, the module
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c
index 86956a8f0ae5..f2b558f17ca2 100644
--- a/drivers/i2c/busses/i2c-bfin-twi.c
+++ b/drivers/i2c/busses/i2c-bfin-twi.c
@@ -62,43 +62,66 @@ struct bfin_twi_iface {
62 struct i2c_msg *pmsg; 62 struct i2c_msg *pmsg;
63 int msg_num; 63 int msg_num;
64 int cur_msg; 64 int cur_msg;
65 void __iomem *regs_base;
65}; 66};
66 67
67static struct bfin_twi_iface twi_iface; 68
69#define DEFINE_TWI_REG(reg, off) \
70static inline u16 read_##reg(struct bfin_twi_iface *iface) \
71 { return bfin_read16(iface->regs_base + (off)); } \
72static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
73 { bfin_write16(iface->regs_base + (off), v); }
74
75DEFINE_TWI_REG(CLKDIV, 0x00)
76DEFINE_TWI_REG(CONTROL, 0x04)
77DEFINE_TWI_REG(SLAVE_CTL, 0x08)
78DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
79DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
80DEFINE_TWI_REG(MASTER_CTL, 0x14)
81DEFINE_TWI_REG(MASTER_STAT, 0x18)
82DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
83DEFINE_TWI_REG(INT_STAT, 0x20)
84DEFINE_TWI_REG(INT_MASK, 0x24)
85DEFINE_TWI_REG(FIFO_CTL, 0x28)
86DEFINE_TWI_REG(FIFO_STAT, 0x2C)
87DEFINE_TWI_REG(XMT_DATA8, 0x80)
88DEFINE_TWI_REG(XMT_DATA16, 0x84)
89DEFINE_TWI_REG(RCV_DATA8, 0x88)
90DEFINE_TWI_REG(RCV_DATA16, 0x8C)
68 91
69static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface) 92static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
70{ 93{
71 unsigned short twi_int_status = bfin_read_TWI_INT_STAT(); 94 unsigned short twi_int_status = read_INT_STAT(iface);
72 unsigned short mast_stat = bfin_read_TWI_MASTER_STAT(); 95 unsigned short mast_stat = read_MASTER_STAT(iface);
73 96
74 if (twi_int_status & XMTSERV) { 97 if (twi_int_status & XMTSERV) {
75 /* Transmit next data */ 98 /* Transmit next data */
76 if (iface->writeNum > 0) { 99 if (iface->writeNum > 0) {
77 bfin_write_TWI_XMT_DATA8(*(iface->transPtr++)); 100 write_XMT_DATA8(iface, *(iface->transPtr++));
78 iface->writeNum--; 101 iface->writeNum--;
79 } 102 }
80 /* start receive immediately after complete sending in 103 /* start receive immediately after complete sending in
81 * combine mode. 104 * combine mode.
82 */ 105 */
83 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) 106 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
84 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() 107 write_MASTER_CTL(iface,
85 | MDIR | RSTART); 108 read_MASTER_CTL(iface) | MDIR | RSTART);
86 else if (iface->manual_stop) 109 else if (iface->manual_stop)
87 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() 110 write_MASTER_CTL(iface,
88 | STOP); 111 read_MASTER_CTL(iface) | STOP);
89 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && 112 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
90 iface->cur_msg+1 < iface->msg_num) 113 iface->cur_msg+1 < iface->msg_num)
91 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() 114 write_MASTER_CTL(iface,
92 | RSTART); 115 read_MASTER_CTL(iface) | RSTART);
93 SSYNC(); 116 SSYNC();
94 /* Clear status */ 117 /* Clear status */
95 bfin_write_TWI_INT_STAT(XMTSERV); 118 write_INT_STAT(iface, XMTSERV);
96 SSYNC(); 119 SSYNC();
97 } 120 }
98 if (twi_int_status & RCVSERV) { 121 if (twi_int_status & RCVSERV) {
99 if (iface->readNum > 0) { 122 if (iface->readNum > 0) {
100 /* Receive next data */ 123 /* Receive next data */
101 *(iface->transPtr) = bfin_read_TWI_RCV_DATA8(); 124 *(iface->transPtr) = read_RCV_DATA8(iface);
102 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { 125 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
103 /* Change combine mode into sub mode after 126 /* Change combine mode into sub mode after
104 * read first data. 127 * read first data.
@@ -113,33 +136,33 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
113 iface->transPtr++; 136 iface->transPtr++;
114 iface->readNum--; 137 iface->readNum--;
115 } else if (iface->manual_stop) { 138 } else if (iface->manual_stop) {
116 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() 139 write_MASTER_CTL(iface,
117 | STOP); 140 read_MASTER_CTL(iface) | STOP);
118 SSYNC(); 141 SSYNC();
119 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && 142 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
120 iface->cur_msg+1 < iface->msg_num) { 143 iface->cur_msg+1 < iface->msg_num) {
121 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() 144 write_MASTER_CTL(iface,
122 | RSTART); 145 read_MASTER_CTL(iface) | RSTART);
123 SSYNC(); 146 SSYNC();
124 } 147 }
125 /* Clear interrupt source */ 148 /* Clear interrupt source */
126 bfin_write_TWI_INT_STAT(RCVSERV); 149 write_INT_STAT(iface, RCVSERV);
127 SSYNC(); 150 SSYNC();
128 } 151 }
129 if (twi_int_status & MERR) { 152 if (twi_int_status & MERR) {
130 bfin_write_TWI_INT_STAT(MERR); 153 write_INT_STAT(iface, MERR);
131 bfin_write_TWI_INT_MASK(0); 154 write_INT_MASK(iface, 0);
132 bfin_write_TWI_MASTER_STAT(0x3e); 155 write_MASTER_STAT(iface, 0x3e);
133 bfin_write_TWI_MASTER_CTL(0); 156 write_MASTER_CTL(iface, 0);
134 SSYNC(); 157 SSYNC();
135 iface->result = -EIO; 158 iface->result = -EIO;
136 /* if both err and complete int stats are set, return proper 159 /* if both err and complete int stats are set, return proper
137 * results. 160 * results.
138 */ 161 */
139 if (twi_int_status & MCOMP) { 162 if (twi_int_status & MCOMP) {
140 bfin_write_TWI_INT_STAT(MCOMP); 163 write_INT_STAT(iface, MCOMP);
141 bfin_write_TWI_INT_MASK(0); 164 write_INT_MASK(iface, 0);
142 bfin_write_TWI_MASTER_CTL(0); 165 write_MASTER_CTL(iface, 0);
143 SSYNC(); 166 SSYNC();
144 /* If it is a quick transfer, only address bug no data, 167 /* If it is a quick transfer, only address bug no data,
145 * not an err, return 1. 168 * not an err, return 1.
@@ -156,7 +179,7 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
156 return; 179 return;
157 } 180 }
158 if (twi_int_status & MCOMP) { 181 if (twi_int_status & MCOMP) {
159 bfin_write_TWI_INT_STAT(MCOMP); 182 write_INT_STAT(iface, MCOMP);
160 SSYNC(); 183 SSYNC();
161 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { 184 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
162 if (iface->readNum == 0) { 185 if (iface->readNum == 0) {
@@ -165,23 +188,22 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
165 */ 188 */
166 iface->readNum = 1; 189 iface->readNum = 1;
167 iface->manual_stop = 1; 190 iface->manual_stop = 1;
168 bfin_write_TWI_MASTER_CTL( 191 write_MASTER_CTL(iface,
169 bfin_read_TWI_MASTER_CTL() 192 read_MASTER_CTL(iface) | (0xff << 6));
170 | (0xff << 6));
171 } else { 193 } else {
172 /* set the readd number in other 194 /* set the readd number in other
173 * combine mode. 195 * combine mode.
174 */ 196 */
175 bfin_write_TWI_MASTER_CTL( 197 write_MASTER_CTL(iface,
176 (bfin_read_TWI_MASTER_CTL() & 198 (read_MASTER_CTL(iface) &
177 (~(0xff << 6))) | 199 (~(0xff << 6))) |
178 ( iface->readNum << 6)); 200 (iface->readNum << 6));
179 } 201 }
180 /* remove restart bit and enable master receive */ 202 /* remove restart bit and enable master receive */
181 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() & 203 write_MASTER_CTL(iface,
182 ~RSTART); 204 read_MASTER_CTL(iface) & ~RSTART);
183 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | 205 write_MASTER_CTL(iface,
184 MEN | MDIR); 206 read_MASTER_CTL(iface) | MEN | MDIR);
185 SSYNC(); 207 SSYNC();
186 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && 208 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
187 iface->cur_msg+1 < iface->msg_num) { 209 iface->cur_msg+1 < iface->msg_num) {
@@ -190,7 +212,7 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
190 iface->writeNum = iface->readNum = 212 iface->writeNum = iface->readNum =
191 iface->pmsg[iface->cur_msg].len; 213 iface->pmsg[iface->cur_msg].len;
192 /* Set Transmit device address */ 214 /* Set Transmit device address */
193 bfin_write_TWI_MASTER_ADDR( 215 write_MASTER_ADDR(iface,
194 iface->pmsg[iface->cur_msg].addr); 216 iface->pmsg[iface->cur_msg].addr);
195 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD) 217 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
196 iface->read_write = I2C_SMBUS_READ; 218 iface->read_write = I2C_SMBUS_READ;
@@ -198,7 +220,7 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
198 iface->read_write = I2C_SMBUS_WRITE; 220 iface->read_write = I2C_SMBUS_WRITE;
199 /* Transmit first data */ 221 /* Transmit first data */
200 if (iface->writeNum > 0) { 222 if (iface->writeNum > 0) {
201 bfin_write_TWI_XMT_DATA8( 223 write_XMT_DATA8(iface,
202 *(iface->transPtr++)); 224 *(iface->transPtr++));
203 iface->writeNum--; 225 iface->writeNum--;
204 SSYNC(); 226 SSYNC();
@@ -206,23 +228,23 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
206 } 228 }
207 229
208 if (iface->pmsg[iface->cur_msg].len <= 255) 230 if (iface->pmsg[iface->cur_msg].len <= 255)
209 bfin_write_TWI_MASTER_CTL( 231 write_MASTER_CTL(iface,
210 iface->pmsg[iface->cur_msg].len << 6); 232 iface->pmsg[iface->cur_msg].len << 6);
211 else { 233 else {
212 bfin_write_TWI_MASTER_CTL(0xff << 6); 234 write_MASTER_CTL(iface, 0xff << 6);
213 iface->manual_stop = 1; 235 iface->manual_stop = 1;
214 } 236 }
215 /* remove restart bit and enable master receive */ 237 /* remove restart bit and enable master receive */
216 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() & 238 write_MASTER_CTL(iface,
217 ~RSTART); 239 read_MASTER_CTL(iface) & ~RSTART);
218 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | 240 write_MASTER_CTL(iface, read_MASTER_CTL(iface) |
219 MEN | ((iface->read_write == I2C_SMBUS_READ) ? 241 MEN | ((iface->read_write == I2C_SMBUS_READ) ?
220 MDIR : 0)); 242 MDIR : 0));
221 SSYNC(); 243 SSYNC();
222 } else { 244 } else {
223 iface->result = 1; 245 iface->result = 1;
224 bfin_write_TWI_INT_MASK(0); 246 write_INT_MASK(iface, 0);
225 bfin_write_TWI_MASTER_CTL(0); 247 write_MASTER_CTL(iface, 0);
226 SSYNC(); 248 SSYNC();
227 complete(&iface->complete); 249 complete(&iface->complete);
228 } 250 }
@@ -272,12 +294,11 @@ static int bfin_twi_master_xfer(struct i2c_adapter *adap,
272 struct i2c_msg *pmsg; 294 struct i2c_msg *pmsg;
273 int rc = 0; 295 int rc = 0;
274 296
275 if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) 297 if (!(read_CONTROL(iface) & TWI_ENA))
276 return -ENXIO; 298 return -ENXIO;
277 299
278 while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) { 300 while (read_MASTER_STAT(iface) & BUSBUSY)
279 yield(); 301 yield();
280 }
281 302
282 iface->pmsg = msgs; 303 iface->pmsg = msgs;
283 iface->msg_num = num; 304 iface->msg_num = num;
@@ -296,14 +317,14 @@ static int bfin_twi_master_xfer(struct i2c_adapter *adap,
296 iface->result = 0; 317 iface->result = 0;
297 iface->timeout_count = 10; 318 iface->timeout_count = 10;
298 /* Set Transmit device address */ 319 /* Set Transmit device address */
299 bfin_write_TWI_MASTER_ADDR(pmsg->addr); 320 write_MASTER_ADDR(iface, pmsg->addr);
300 321
301 /* FIFO Initiation. Data in FIFO should be 322 /* FIFO Initiation. Data in FIFO should be
302 * discarded before start a new operation. 323 * discarded before start a new operation.
303 */ 324 */
304 bfin_write_TWI_FIFO_CTL(0x3); 325 write_FIFO_CTL(iface, 0x3);
305 SSYNC(); 326 SSYNC();
306 bfin_write_TWI_FIFO_CTL(0); 327 write_FIFO_CTL(iface, 0);
307 SSYNC(); 328 SSYNC();
308 329
309 if (pmsg->flags & I2C_M_RD) 330 if (pmsg->flags & I2C_M_RD)
@@ -312,23 +333,23 @@ static int bfin_twi_master_xfer(struct i2c_adapter *adap,
312 iface->read_write = I2C_SMBUS_WRITE; 333 iface->read_write = I2C_SMBUS_WRITE;
313 /* Transmit first data */ 334 /* Transmit first data */
314 if (iface->writeNum > 0) { 335 if (iface->writeNum > 0) {
315 bfin_write_TWI_XMT_DATA8(*(iface->transPtr++)); 336 write_XMT_DATA8(iface, *(iface->transPtr++));
316 iface->writeNum--; 337 iface->writeNum--;
317 SSYNC(); 338 SSYNC();
318 } 339 }
319 } 340 }
320 341
321 /* clear int stat */ 342 /* clear int stat */
322 bfin_write_TWI_INT_STAT(MERR | MCOMP | XMTSERV | RCVSERV); 343 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
323 344
324 /* Interrupt mask . Enable XMT, RCV interrupt */ 345 /* Interrupt mask . Enable XMT, RCV interrupt */
325 bfin_write_TWI_INT_MASK(MCOMP | MERR | RCVSERV | XMTSERV); 346 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
326 SSYNC(); 347 SSYNC();
327 348
328 if (pmsg->len <= 255) 349 if (pmsg->len <= 255)
329 bfin_write_TWI_MASTER_CTL(pmsg->len << 6); 350 write_MASTER_CTL(iface, pmsg->len << 6);
330 else { 351 else {
331 bfin_write_TWI_MASTER_CTL(0xff << 6); 352 write_MASTER_CTL(iface, 0xff << 6);
332 iface->manual_stop = 1; 353 iface->manual_stop = 1;
333 } 354 }
334 355
@@ -336,7 +357,7 @@ static int bfin_twi_master_xfer(struct i2c_adapter *adap,
336 add_timer(&iface->timeout_timer); 357 add_timer(&iface->timeout_timer);
337 358
338 /* Master enable */ 359 /* Master enable */
339 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | 360 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
340 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | 361 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
341 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); 362 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
342 SSYNC(); 363 SSYNC();
@@ -362,12 +383,11 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
362 struct bfin_twi_iface *iface = adap->algo_data; 383 struct bfin_twi_iface *iface = adap->algo_data;
363 int rc = 0; 384 int rc = 0;
364 385
365 if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) 386 if (!(read_CONTROL(iface) & TWI_ENA))
366 return -ENXIO; 387 return -ENXIO;
367 388
368 while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) { 389 while (read_MASTER_STAT(iface) & BUSBUSY)
369 yield(); 390 yield();
370 }
371 391
372 iface->writeNum = 0; 392 iface->writeNum = 0;
373 iface->readNum = 0; 393 iface->readNum = 0;
@@ -439,15 +459,15 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
439 /* FIFO Initiation. Data in FIFO should be discarded before 459 /* FIFO Initiation. Data in FIFO should be discarded before
440 * start a new operation. 460 * start a new operation.
441 */ 461 */
442 bfin_write_TWI_FIFO_CTL(0x3); 462 write_FIFO_CTL(iface, 0x3);
443 SSYNC(); 463 SSYNC();
444 bfin_write_TWI_FIFO_CTL(0); 464 write_FIFO_CTL(iface, 0);
445 465
446 /* clear int stat */ 466 /* clear int stat */
447 bfin_write_TWI_INT_STAT(MERR|MCOMP|XMTSERV|RCVSERV); 467 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
448 468
449 /* Set Transmit device address */ 469 /* Set Transmit device address */
450 bfin_write_TWI_MASTER_ADDR(addr); 470 write_MASTER_ADDR(iface, addr);
451 SSYNC(); 471 SSYNC();
452 472
453 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT; 473 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
@@ -455,60 +475,64 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
455 475
456 switch (iface->cur_mode) { 476 switch (iface->cur_mode) {
457 case TWI_I2C_MODE_STANDARDSUB: 477 case TWI_I2C_MODE_STANDARDSUB:
458 bfin_write_TWI_XMT_DATA8(iface->command); 478 write_XMT_DATA8(iface, iface->command);
459 bfin_write_TWI_INT_MASK(MCOMP | MERR | 479 write_INT_MASK(iface, MCOMP | MERR |
460 ((iface->read_write == I2C_SMBUS_READ) ? 480 ((iface->read_write == I2C_SMBUS_READ) ?
461 RCVSERV : XMTSERV)); 481 RCVSERV : XMTSERV));
462 SSYNC(); 482 SSYNC();
463 483
464 if (iface->writeNum + 1 <= 255) 484 if (iface->writeNum + 1 <= 255)
465 bfin_write_TWI_MASTER_CTL((iface->writeNum + 1) << 6); 485 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
466 else { 486 else {
467 bfin_write_TWI_MASTER_CTL(0xff << 6); 487 write_MASTER_CTL(iface, 0xff << 6);
468 iface->manual_stop = 1; 488 iface->manual_stop = 1;
469 } 489 }
470 /* Master enable */ 490 /* Master enable */
471 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | 491 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
472 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); 492 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
473 break; 493 break;
474 case TWI_I2C_MODE_COMBINED: 494 case TWI_I2C_MODE_COMBINED:
475 bfin_write_TWI_XMT_DATA8(iface->command); 495 write_XMT_DATA8(iface, iface->command);
476 bfin_write_TWI_INT_MASK(MCOMP | MERR | RCVSERV | XMTSERV); 496 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
477 SSYNC(); 497 SSYNC();
478 498
479 if (iface->writeNum > 0) 499 if (iface->writeNum > 0)
480 bfin_write_TWI_MASTER_CTL((iface->writeNum + 1) << 6); 500 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
481 else 501 else
482 bfin_write_TWI_MASTER_CTL(0x1 << 6); 502 write_MASTER_CTL(iface, 0x1 << 6);
483 /* Master enable */ 503 /* Master enable */
484 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | 504 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
485 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); 505 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
486 break; 506 break;
487 default: 507 default:
488 bfin_write_TWI_MASTER_CTL(0); 508 write_MASTER_CTL(iface, 0);
489 if (size != I2C_SMBUS_QUICK) { 509 if (size != I2C_SMBUS_QUICK) {
490 /* Don't access xmit data register when this is a 510 /* Don't access xmit data register when this is a
491 * read operation. 511 * read operation.
492 */ 512 */
493 if (iface->read_write != I2C_SMBUS_READ) { 513 if (iface->read_write != I2C_SMBUS_READ) {
494 if (iface->writeNum > 0) { 514 if (iface->writeNum > 0) {
495 bfin_write_TWI_XMT_DATA8(*(iface->transPtr++)); 515 write_XMT_DATA8(iface,
516 *(iface->transPtr++));
496 if (iface->writeNum <= 255) 517 if (iface->writeNum <= 255)
497 bfin_write_TWI_MASTER_CTL(iface->writeNum << 6); 518 write_MASTER_CTL(iface,
519 iface->writeNum << 6);
498 else { 520 else {
499 bfin_write_TWI_MASTER_CTL(0xff << 6); 521 write_MASTER_CTL(iface,
522 0xff << 6);
500 iface->manual_stop = 1; 523 iface->manual_stop = 1;
501 } 524 }
502 iface->writeNum--; 525 iface->writeNum--;
503 } else { 526 } else {
504 bfin_write_TWI_XMT_DATA8(iface->command); 527 write_XMT_DATA8(iface, iface->command);
505 bfin_write_TWI_MASTER_CTL(1 << 6); 528 write_MASTER_CTL(iface, 1 << 6);
506 } 529 }
507 } else { 530 } else {
508 if (iface->readNum > 0 && iface->readNum <= 255) 531 if (iface->readNum > 0 && iface->readNum <= 255)
509 bfin_write_TWI_MASTER_CTL(iface->readNum << 6); 532 write_MASTER_CTL(iface,
533 iface->readNum << 6);
510 else if (iface->readNum > 255) { 534 else if (iface->readNum > 255) {
511 bfin_write_TWI_MASTER_CTL(0xff << 6); 535 write_MASTER_CTL(iface, 0xff << 6);
512 iface->manual_stop = 1; 536 iface->manual_stop = 1;
513 } else { 537 } else {
514 del_timer(&iface->timeout_timer); 538 del_timer(&iface->timeout_timer);
@@ -516,13 +540,13 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
516 } 540 }
517 } 541 }
518 } 542 }
519 bfin_write_TWI_INT_MASK(MCOMP | MERR | 543 write_INT_MASK(iface, MCOMP | MERR |
520 ((iface->read_write == I2C_SMBUS_READ) ? 544 ((iface->read_write == I2C_SMBUS_READ) ?
521 RCVSERV : XMTSERV)); 545 RCVSERV : XMTSERV));
522 SSYNC(); 546 SSYNC();
523 547
524 /* Master enable */ 548 /* Master enable */
525 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | 549 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
526 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | 550 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
527 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); 551 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
528 break; 552 break;
@@ -557,10 +581,10 @@ static struct i2c_algorithm bfin_twi_algorithm = {
557 581
558static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state) 582static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state)
559{ 583{
560/* struct bfin_twi_iface *iface = platform_get_drvdata(dev);*/ 584 struct bfin_twi_iface *iface = platform_get_drvdata(dev);
561 585
562 /* Disable TWI */ 586 /* Disable TWI */
563 bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() & ~TWI_ENA); 587 write_CONTROL(iface, read_CONTROL(iface) & ~TWI_ENA);
564 SSYNC(); 588 SSYNC();
565 589
566 return 0; 590 return 0;
@@ -568,24 +592,53 @@ static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state)
568 592
569static int i2c_bfin_twi_resume(struct platform_device *dev) 593static int i2c_bfin_twi_resume(struct platform_device *dev)
570{ 594{
571/* struct bfin_twi_iface *iface = platform_get_drvdata(dev);*/ 595 struct bfin_twi_iface *iface = platform_get_drvdata(dev);
572 596
573 /* Enable TWI */ 597 /* Enable TWI */
574 bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA); 598 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
575 SSYNC(); 599 SSYNC();
576 600
577 return 0; 601 return 0;
578} 602}
579 603
580static int i2c_bfin_twi_probe(struct platform_device *dev) 604static int i2c_bfin_twi_probe(struct platform_device *pdev)
581{ 605{
582 struct bfin_twi_iface *iface = &twi_iface; 606 struct bfin_twi_iface *iface;
583 struct i2c_adapter *p_adap; 607 struct i2c_adapter *p_adap;
608 struct resource *res;
584 int rc; 609 int rc;
585 610
611 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
612 if (!iface) {
613 dev_err(&pdev->dev, "Cannot allocate memory\n");
614 rc = -ENOMEM;
615 goto out_error_nomem;
616 }
617
586 spin_lock_init(&(iface->lock)); 618 spin_lock_init(&(iface->lock));
587 init_completion(&(iface->complete)); 619 init_completion(&(iface->complete));
588 iface->irq = IRQ_TWI; 620
621 /* Find and map our resources */
622 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
623 if (res == NULL) {
624 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
625 rc = -ENOENT;
626 goto out_error_get_res;
627 }
628
629 iface->regs_base = ioremap(res->start, res->end - res->start + 1);
630 if (iface->regs_base == NULL) {
631 dev_err(&pdev->dev, "Cannot map IO\n");
632 rc = -ENXIO;
633 goto out_error_ioremap;
634 }
635
636 iface->irq = platform_get_irq(pdev, 0);
637 if (iface->irq < 0) {
638 dev_err(&pdev->dev, "No IRQ specified\n");
639 rc = -ENOENT;
640 goto out_error_no_irq;
641 }
589 642
590 init_timer(&(iface->timeout_timer)); 643 init_timer(&(iface->timeout_timer));
591 iface->timeout_timer.function = bfin_twi_timeout; 644 iface->timeout_timer.function = bfin_twi_timeout;
@@ -593,39 +646,55 @@ static int i2c_bfin_twi_probe(struct platform_device *dev)
593 646
594 p_adap = &iface->adap; 647 p_adap = &iface->adap;
595 p_adap->id = I2C_HW_BLACKFIN; 648 p_adap->id = I2C_HW_BLACKFIN;
596 p_adap->nr = dev->id; 649 p_adap->nr = pdev->id;
597 strlcpy(p_adap->name, dev->name, sizeof(p_adap->name)); 650 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
598 p_adap->algo = &bfin_twi_algorithm; 651 p_adap->algo = &bfin_twi_algorithm;
599 p_adap->algo_data = iface; 652 p_adap->algo_data = iface;
600 p_adap->class = I2C_CLASS_ALL; 653 p_adap->class = I2C_CLASS_ALL;
601 p_adap->dev.parent = &dev->dev; 654 p_adap->dev.parent = &pdev->dev;
602 655
603 rc = request_irq(iface->irq, bfin_twi_interrupt_entry, 656 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
604 IRQF_DISABLED, dev->name, iface); 657 IRQF_DISABLED, pdev->name, iface);
605 if (rc) { 658 if (rc) {
606 dev_err(&(p_adap->dev), "i2c-bfin-twi: can't get IRQ %d !\n", 659 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
607 iface->irq); 660 rc = -ENODEV;
608 return -ENODEV; 661 goto out_error_req_irq;
609 } 662 }
610 663
611 /* Set TWI internal clock as 10MHz */ 664 /* Set TWI internal clock as 10MHz */
612 bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F); 665 write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
613 666
614 /* Set Twi interface clock as specified */ 667 /* Set Twi interface clock as specified */
615 bfin_write_TWI_CLKDIV((( 5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ ) 668 write_CLKDIV(iface, ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
616 << 8) | (( 5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ ) 669 << 8) | ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
617 & 0xFF)); 670 & 0xFF));
618 671
619 /* Enable TWI */ 672 /* Enable TWI */
620 bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA); 673 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
621 SSYNC(); 674 SSYNC();
622 675
623 rc = i2c_add_numbered_adapter(p_adap); 676 rc = i2c_add_numbered_adapter(p_adap);
624 if (rc < 0) 677 if (rc < 0) {
625 free_irq(iface->irq, iface); 678 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
626 else 679 goto out_error_add_adapter;
627 platform_set_drvdata(dev, iface); 680 }
681
682 platform_set_drvdata(pdev, iface);
628 683
684 dev_info(&pdev->dev, "Blackfin I2C TWI controller, regs_base@%p\n",
685 iface->regs_base);
686
687 return 0;
688
689out_error_add_adapter:
690 free_irq(iface->irq, iface);
691out_error_req_irq:
692out_error_no_irq:
693 iounmap(iface->regs_base);
694out_error_ioremap:
695out_error_get_res:
696 kfree(iface);
697out_error_nomem:
629 return rc; 698 return rc;
630} 699}
631 700
@@ -637,6 +706,8 @@ static int i2c_bfin_twi_remove(struct platform_device *pdev)
637 706
638 i2c_del_adapter(&(iface->adap)); 707 i2c_del_adapter(&(iface->adap));
639 free_irq(iface->irq, iface); 708 free_irq(iface->irq, iface);
709 iounmap(iface->regs_base);
710 kfree(iface);
640 711
641 return 0; 712 return 0;
642} 713}
@@ -654,8 +725,6 @@ static struct platform_driver i2c_bfin_twi_driver = {
654 725
655static int __init i2c_bfin_twi_init(void) 726static int __init i2c_bfin_twi_init(void)
656{ 727{
657 pr_info("I2C: Blackfin I2C TWI driver\n");
658
659 return platform_driver_register(&i2c_bfin_twi_driver); 728 return platform_driver_register(&i2c_bfin_twi_driver);
660} 729}
661 730
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 13:45:55 -0500