4 files changed, 1131 insertions, 0 deletions

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 107d5c201b6b..a6ac86e09a85 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -452,6 +452,16 @@ config I2C_MV64XXX
           This driver can also be built as a module.  If so, the module
           will be called i2c-mv64xxx.
 
+config I2C_MXS
+        tristate "Freescale i.MX28 I2C interface"
+        depends on SOC_IMX28
+        help
+          Say Y here if you want to use the I2C bus controller on
+          the Freescale i.MX28 processors.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-mxs.
+
 config I2C_NOMADIK
         tristate "ST-Ericsson Nomadik/Ux500 I2C Controller"
         depends on PLAT_NOMADIK
@@ -607,6 +617,13 @@ config I2C_STU300
           This driver can also be built as a module. If so, the module
           will be called i2c-stu300.
 
+config I2C_TEGRA
+        tristate "NVIDIA Tegra internal I2C controller"
+        depends on ARCH_TEGRA
+        help
+          If you say yes to this option, support will be included for the
+          I2C controller embedded in NVIDIA Tegra SOCs
+
 config I2C_VERSATILE
         tristate "ARM Versatile/Realview I2C bus support"
         depends on ARCH_VERSATILE || ARCH_REALVIEW || ARCH_VEXPRESS
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 9d2d0ec7fb23..94ab2665665f 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_I2C_IOP3XX)	+= i2c-iop3xx.o
 obj-$(CONFIG_I2C_IXP2000)       += i2c-ixp2000.o
 obj-$(CONFIG_I2C_MPC)           += i2c-mpc.o
 obj-$(CONFIG_I2C_MV64XXX)       += i2c-mv64xxx.o
+obj-$(CONFIG_I2C_MXS)           += i2c-mxs.o
 obj-$(CONFIG_I2C_NOMADIK)       += i2c-nomadik.o
 obj-$(CONFIG_I2C_NUC900)        += i2c-nuc900.o
 obj-$(CONFIG_I2C_OCORES)        += i2c-ocores.o
@@ -58,6 +59,7 @@ obj-$(CONFIG_I2C_SH7760)	+= i2c-sh7760.o
 obj-$(CONFIG_I2C_SH_MOBILE)     += i2c-sh_mobile.o
 obj-$(CONFIG_I2C_SIMTEC)        += i2c-simtec.o
 obj-$(CONFIG_I2C_STU300)        += i2c-stu300.o
+obj-$(CONFIG_I2C_TEGRA)         += i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)     += i2c-versatile.o
 obj-$(CONFIG_I2C_OCTEON)        += i2c-octeon.o
 obj-$(CONFIG_I2C_XILINX)        += i2c-xiic.o
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
new file mode 100644
index 000000000000..8022e2390a5a
--- /dev/null
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -0,0 +1,412 @@
+/*
+ * Freescale MXS I2C bus driver
+ *
+ * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
+ *
+ * based on a (non-working) driver which was:
+ *
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * TODO: add dma-support if platform-support for it is available
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/platform_device.h>
+#include <linux/jiffies.h>
+#include <linux/io.h>
+
+#include <mach/common.h>
+
+#define DRIVER_NAME "mxs-i2c"
+
+#define MXS_I2C_CTRL0           (0x00)
+#define MXS_I2C_CTRL0_SET       (0x04)
+
+#define MXS_I2C_CTRL0_SFTRST                    0x80000000
+#define MXS_I2C_CTRL0_SEND_NAK_ON_LAST          0x02000000
+#define MXS_I2C_CTRL0_RETAIN_CLOCK              0x00200000
+#define MXS_I2C_CTRL0_POST_SEND_STOP            0x00100000
+#define MXS_I2C_CTRL0_PRE_SEND_START            0x00080000
+#define MXS_I2C_CTRL0_MASTER_MODE               0x00020000
+#define MXS_I2C_CTRL0_DIRECTION                 0x00010000
+#define MXS_I2C_CTRL0_XFER_COUNT(v)             ((v) & 0x0000FFFF)
+
+#define MXS_I2C_CTRL1           (0x40)
+#define MXS_I2C_CTRL1_SET       (0x44)
+#define MXS_I2C_CTRL1_CLR       (0x48)
+
+#define MXS_I2C_CTRL1_BUS_FREE_IRQ              0x80
+#define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ     0x40
+#define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ          0x20
+#define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ    0x10
+#define MXS_I2C_CTRL1_EARLY_TERM_IRQ            0x08
+#define MXS_I2C_CTRL1_MASTER_LOSS_IRQ           0x04
+#define MXS_I2C_CTRL1_SLAVE_STOP_IRQ            0x02
+#define MXS_I2C_CTRL1_SLAVE_IRQ                 0x01
+
+#define MXS_I2C_IRQ_MASK        (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
+                                 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
+                                 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
+                                 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
+                                 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
+                                 MXS_I2C_CTRL1_SLAVE_IRQ)
+
+#define MXS_I2C_QUEUECTRL       (0x60)
+#define MXS_I2C_QUEUECTRL_SET   (0x64)
+#define MXS_I2C_QUEUECTRL_CLR   (0x68)
+
+#define MXS_I2C_QUEUECTRL_QUEUE_RUN             0x20
+#define MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE        0x04
+
+#define MXS_I2C_QUEUESTAT       (0x70)
+#define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY        0x00002000
+
+#define MXS_I2C_QUEUECMD        (0x80)
+
+#define MXS_I2C_QUEUEDATA       (0x90)
+
+#define MXS_I2C_DATA            (0xa0)
+
+
+#define MXS_CMD_I2C_SELECT      (MXS_I2C_CTRL0_RETAIN_CLOCK |   \
+                                 MXS_I2C_CTRL0_PRE_SEND_START | \
+                                 MXS_I2C_CTRL0_MASTER_MODE |    \
+                                 MXS_I2C_CTRL0_DIRECTION |      \
+                                 MXS_I2C_CTRL0_XFER_COUNT(1))
+
+#define MXS_CMD_I2C_WRITE       (MXS_I2C_CTRL0_PRE_SEND_START | \
+                                 MXS_I2C_CTRL0_MASTER_MODE |    \
+                                 MXS_I2C_CTRL0_DIRECTION)
+
+#define MXS_CMD_I2C_READ        (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
+                                 MXS_I2C_CTRL0_MASTER_MODE)
+
+/**
+ * struct mxs_i2c_dev - per device, private MXS-I2C data
+ *
+ * @dev: driver model device node
+ * @regs: IO registers pointer
+ * @cmd_complete: completion object for transaction wait
+ * @cmd_err: error code for last transaction
+ * @adapter: i2c subsystem adapter node
+ */
+struct mxs_i2c_dev {
+        struct device *dev;
+        void __iomem *regs;
+        struct completion cmd_complete;
+        u32 cmd_err;
+        struct i2c_adapter adapter;
+};
+
+/*
+ * TODO: check if calls to here are really needed. If not, we could get rid of
+ * mxs_reset_block and the mach-dependency. Needs an I2C analyzer, probably.
+ */
+static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
+{
+        mxs_reset_block(i2c->regs);
+        writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
+}
+
+static void mxs_i2c_pioq_setup_read(struct mxs_i2c_dev *i2c, u8 addr, int len,
+                                        int flags)
+{
+        u32 data;
+
+        writel(MXS_CMD_I2C_SELECT, i2c->regs + MXS_I2C_QUEUECMD);
+
+        data = (addr << 1) | I2C_SMBUS_READ;
+        writel(data, i2c->regs + MXS_I2C_DATA);
+
+        data = MXS_CMD_I2C_READ | MXS_I2C_CTRL0_XFER_COUNT(len) | flags;
+        writel(data, i2c->regs + MXS_I2C_QUEUECMD);
+}
+
+static void mxs_i2c_pioq_setup_write(struct mxs_i2c_dev *i2c,
+                                    u8 addr, u8 *buf, int len, int flags)
+{
+        u32 data;
+        int i, shifts_left;
+
+        data = MXS_CMD_I2C_WRITE | MXS_I2C_CTRL0_XFER_COUNT(len + 1) | flags;
+        writel(data, i2c->regs + MXS_I2C_QUEUECMD);
+
+        /*
+         * We have to copy the slave address (u8) and buffer (arbitrary number
+         * of u8) into the data register (u32). To achieve that, the u8 are put
+         * into the MSBs of 'data' which is then shifted for the next u8. When
+         * apropriate, 'data' is written to MXS_I2C_DATA. So, the first u32
+         * looks like this:
+         *
+         *  3          2          1          0
+         * 10987654|32109876|54321098|76543210
+         * --------+--------+--------+--------
+         * buffer+2|buffer+1|buffer+0|slave_addr
+         */
+
+        data = ((addr << 1) | I2C_SMBUS_WRITE) << 24;
+
+        for (i = 0; i < len; i++) {
+                data >>= 8;
+                data |= buf[i] << 24;
+                if ((i & 3) == 2)
+                        writel(data, i2c->regs + MXS_I2C_DATA);
+        }
+
+        /* Write out the remaining bytes if any */
+        shifts_left = 24 - (i & 3) * 8;
+        if (shifts_left)
+                writel(data >> shifts_left, i2c->regs + MXS_I2C_DATA);
+}
+
+/*
+ * TODO: should be replaceable with a waitqueue and RD_QUEUE_IRQ (setting the
+ * rd_threshold to 1). Couldn't get this to work, though.
+ */
+static int mxs_i2c_wait_for_data(struct mxs_i2c_dev *i2c)
+{
+        unsigned long timeout = jiffies + msecs_to_jiffies(1000);
+
+        while (readl(i2c->regs + MXS_I2C_QUEUESTAT)
+                        & MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY) {
+                        if (time_after(jiffies, timeout))
+                                return -ETIMEDOUT;
+                        cond_resched();
+        }
+
+        return 0;
+}
+
+static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len)
+{
+        u32 data;
+        int i;
+
+        for (i = 0; i < len; i++) {
+                if ((i & 3) == 0) {
+                        if (mxs_i2c_wait_for_data(i2c))
+                                return -ETIMEDOUT;
+                        data = readl(i2c->regs + MXS_I2C_QUEUEDATA);
+                }
+                buf[i] = data & 0xff;
+                data >>= 8;
+        }
+
+        return 0;
+}
+
+/*
+ * Low level master read/write transaction.
+ */
+static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
+                                int stop)
+{
+        struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
+        int ret;
+        int flags;
+
+        init_completion(&i2c->cmd_complete);
+
+        dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
+                msg->addr, msg->len, msg->flags, stop);
+
+        if (msg->len == 0)
+                return -EINVAL;
+
+        flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
+
+        if (msg->flags & I2C_M_RD)
+                mxs_i2c_pioq_setup_read(i2c, msg->addr, msg->len, flags);
+        else
+                mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, msg->len,
+                                        flags);
+
+        writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
+                        i2c->regs + MXS_I2C_QUEUECTRL_SET);
+
+        ret = wait_for_completion_timeout(&i2c->cmd_complete,
+                                                msecs_to_jiffies(1000));
+        if (ret == 0)
+                goto timeout;
+
+        if ((!i2c->cmd_err) && (msg->flags & I2C_M_RD)) {
+                ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len);
+                if (ret)
+                        goto timeout;
+        }
+
+        if (i2c->cmd_err == -ENXIO)
+                mxs_i2c_reset(i2c);
+
+        dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
+
+        return i2c->cmd_err;
+
+timeout:
+        dev_dbg(i2c->dev, "Timeout!\n");
+        mxs_i2c_reset(i2c);
+        return -ETIMEDOUT;
+}
+
+static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
+                        int num)
+{
+        int i;
+        int err;
+
+        for (i = 0; i < num; i++) {
+                err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
+                if (err)
+                        return err;
+        }
+
+        return num;
+}
+
+static u32 mxs_i2c_func(struct i2c_adapter *adap)
+{
+        return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
+}
+
+static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
+{
+        struct mxs_i2c_dev *i2c = dev_id;
+        u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
+
+        if (!stat)
+                return IRQ_NONE;
+
+        if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
+                i2c->cmd_err = -ENXIO;
+        else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
+                    MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
+                    MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
+                /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
+                i2c->cmd_err = -EIO;
+        else
+                i2c->cmd_err = 0;
+
+        complete(&i2c->cmd_complete);
+
+        writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
+        return IRQ_HANDLED;
+}
+
+static const struct i2c_algorithm mxs_i2c_algo = {
+        .master_xfer = mxs_i2c_xfer,
+        .functionality = mxs_i2c_func,
+};
+
+static int __devinit mxs_i2c_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct mxs_i2c_dev *i2c;
+        struct i2c_adapter *adap;
+        struct resource *res;
+        resource_size_t res_size;
+        int err, irq;
+
+        i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
+        if (!i2c)
+                return -ENOMEM;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
+                return -ENOENT;
+
+        res_size = resource_size(res);
+        if (!devm_request_mem_region(dev, res->start, res_size, res->name))
+                return -EBUSY;
+
+        i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
+        if (!i2c->regs)
+                return -EBUSY;
+
+        irq = platform_get_irq(pdev, 0);
+        if (irq < 0)
+                return irq;
+
+        err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
+        if (err)
+                return err;
+
+        i2c->dev = dev;
+        platform_set_drvdata(pdev, i2c);
+
+        /* Do reset to enforce correct startup after pinmuxing */
+        mxs_i2c_reset(i2c);
+        writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
+                        i2c->regs + MXS_I2C_QUEUECTRL_SET);
+
+        adap = &i2c->adapter;
+        strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
+        adap->owner = THIS_MODULE;
+        adap->algo = &mxs_i2c_algo;
+        adap->dev.parent = dev;
+        adap->nr = pdev->id;
+        i2c_set_adapdata(adap, i2c);
+        err = i2c_add_numbered_adapter(adap);
+        if (err) {
+                dev_err(dev, "Failed to add adapter (%d)\n", err);
+                writel(MXS_I2C_CTRL0_SFTRST,
+                                i2c->regs + MXS_I2C_CTRL0_SET);
+                return err;
+        }
+
+        return 0;
+}
+
+static int __devexit mxs_i2c_remove(struct platform_device *pdev)
+{
+        struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
+        int ret;
+
+        ret = i2c_del_adapter(&i2c->adapter);
+        if (ret)
+                return -EBUSY;
+
+        writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
+                        i2c->regs + MXS_I2C_QUEUECTRL_CLR);
+        writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
+
+        platform_set_drvdata(pdev, NULL);
+
+        return 0;
+}
+
+static struct platform_driver mxs_i2c_driver = {
+        .driver = {
+                   .name = DRIVER_NAME,
+                   .owner = THIS_MODULE,
+                   },
+        .remove = __devexit_p(mxs_i2c_remove),
+};
+
+static int __init mxs_i2c_init(void)
+{
+        return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
+}
+subsys_initcall(mxs_i2c_init);
+
+static void __exit mxs_i2c_exit(void)
+{
+        platform_driver_unregister(&mxs_i2c_driver);
+}
+module_exit(mxs_i2c_exit);
+
+MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
+MODULE_DESCRIPTION("MXS I2C Bus Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
new file mode 100644
index 000000000000..3921f664c9c3
--- /dev/null
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -0,0 +1,700 @@
+/*
+ * drivers/i2c/busses/i2c-tegra.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/i2c-tegra.h>
+
+#include <asm/unaligned.h>
+
+#include <mach/clk.h>
+
+#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
+#define BYTES_PER_FIFO_WORD 4
+
+#define I2C_CNFG                                0x000
+#define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
+#define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
+#define I2C_SL_CNFG                             0x020
+#define I2C_SL_CNFG_NEWSL                       (1<<2)
+#define I2C_SL_ADDR1                            0x02c
+#define I2C_TX_FIFO                             0x050
+#define I2C_RX_FIFO                             0x054
+#define I2C_PACKET_TRANSFER_STATUS              0x058
+#define I2C_FIFO_CONTROL                        0x05c
+#define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
+#define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
+#define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
+#define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
+#define I2C_FIFO_STATUS                         0x060
+#define I2C_FIFO_STATUS_TX_MASK                 0xF0
+#define I2C_FIFO_STATUS_TX_SHIFT                4
+#define I2C_FIFO_STATUS_RX_MASK                 0x0F
+#define I2C_FIFO_STATUS_RX_SHIFT                0
+#define I2C_INT_MASK                            0x064
+#define I2C_INT_STATUS                          0x068
+#define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
+#define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
+#define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
+#define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
+#define I2C_INT_NO_ACK                          (1<<3)
+#define I2C_INT_ARBITRATION_LOST                (1<<2)
+#define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
+#define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
+#define I2C_CLK_DIVISOR                         0x06c
+
+#define DVC_CTRL_REG1                           0x000
+#define DVC_CTRL_REG1_INTR_EN                   (1<<10)
+#define DVC_CTRL_REG2                           0x004
+#define DVC_CTRL_REG3                           0x008
+#define DVC_CTRL_REG3_SW_PROG                   (1<<26)
+#define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
+#define DVC_STATUS                              0x00c
+#define DVC_STATUS_I2C_DONE_INTR                (1<<30)
+
+#define I2C_ERR_NONE                            0x00
+#define I2C_ERR_NO_ACK                          0x01
+#define I2C_ERR_ARBITRATION_LOST                0x02
+
+#define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
+#define PACKET_HEADER0_PACKET_ID_SHIFT          16
+#define PACKET_HEADER0_CONT_ID_SHIFT            12
+#define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
+
+#define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
+#define I2C_HEADER_CONT_ON_NAK                  (1<<21)
+#define I2C_HEADER_SEND_START_BYTE              (1<<20)
+#define I2C_HEADER_READ                         (1<<19)
+#define I2C_HEADER_10BIT_ADDR                   (1<<18)
+#define I2C_HEADER_IE_ENABLE                    (1<<17)
+#define I2C_HEADER_REPEAT_START                 (1<<16)
+#define I2C_HEADER_MASTER_ADDR_SHIFT            12
+#define I2C_HEADER_SLAVE_ADDR_SHIFT             1
+
+/**
+ * struct tegra_i2c_dev - per device i2c context
+ * @dev: device reference for power management
+ * @adapter: core i2c layer adapter information
+ * @clk: clock reference for i2c controller
+ * @i2c_clk: clock reference for i2c bus
+ * @iomem: memory resource for registers
+ * @base: ioremapped registers cookie
+ * @cont_id: i2c controller id, used for for packet header
+ * @irq: irq number of transfer complete interrupt
+ * @is_dvc: identifies the DVC i2c controller, has a different register layout
+ * @msg_complete: transfer completion notifier
+ * @msg_err: error code for completed message
+ * @msg_buf: pointer to current message data
+ * @msg_buf_remaining: size of unsent data in the message buffer
+ * @msg_read: identifies read transfers
+ * @bus_clk_rate: current i2c bus clock rate
+ * @is_suspended: prevents i2c controller accesses after suspend is called
+ */
+struct tegra_i2c_dev {
+        struct device *dev;
+        struct i2c_adapter adapter;
+        struct clk *clk;
+        struct clk *i2c_clk;
+        struct resource *iomem;
+        void __iomem *base;
+        int cont_id;
+        int irq;
+        int is_dvc;
+        struct completion msg_complete;
+        int msg_err;
+        u8 *msg_buf;
+        size_t msg_buf_remaining;
+        int msg_read;
+        unsigned long bus_clk_rate;
+        bool is_suspended;
+};
+
+static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
+{
+        writel(val, i2c_dev->base + reg);
+}
+
+static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
+{
+        return readl(i2c_dev->base + reg);
+}
+
+/*
+ * i2c_writel and i2c_readl will offset the register if necessary to talk
+ * to the I2C block inside the DVC block
+ */
+static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
+        unsigned long reg)
+{
+        if (i2c_dev->is_dvc)
+                reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
+        return reg;
+}
+
+static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
+        unsigned long reg)
+{
+        writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
+}
+
+static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
+{
+        return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
+}
+
+static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
+        unsigned long reg, int len)
+{
+        writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
+}
+
+static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
+        unsigned long reg, int len)
+{
+        readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
+}
+
+static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
+{
+        u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
+        int_mask &= ~mask;
+        i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
+}
+
+static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
+{
+        u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
+        int_mask |= mask;
+        i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
+}
+
+static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
+{
+        unsigned long timeout = jiffies + HZ;
+        u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
+        val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
+        i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
+
+        while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
+                (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
+                if (time_after(jiffies, timeout)) {
+                        dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
+                        return -ETIMEDOUT;
+                }
+                msleep(1);
+        }
+        return 0;
+}
+
+static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
+{
+        u32 val;
+        int rx_fifo_avail;
+        u8 *buf = i2c_dev->msg_buf;
+        size_t buf_remaining = i2c_dev->msg_buf_remaining;
+        int words_to_transfer;
+
+        val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
+        rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
+                I2C_FIFO_STATUS_RX_SHIFT;
+
+        /* Rounds down to not include partial word at the end of buf */
+        words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
+        if (words_to_transfer > rx_fifo_avail)
+                words_to_transfer = rx_fifo_avail;
+
+        i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
+
+        buf += words_to_transfer * BYTES_PER_FIFO_WORD;
+        buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
+        rx_fifo_avail -= words_to_transfer;
+
+        /*
+         * If there is a partial word at the end of buf, handle it manually to
+         * prevent overwriting past the end of buf
+         */
+        if (rx_fifo_avail > 0 && buf_remaining > 0) {
+                BUG_ON(buf_remaining > 3);
+                val = i2c_readl(i2c_dev, I2C_RX_FIFO);
+                memcpy(buf, &val, buf_remaining);
+                buf_remaining = 0;
+                rx_fifo_avail--;
+        }
+
+        BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
+        i2c_dev->msg_buf_remaining = buf_remaining;
+        i2c_dev->msg_buf = buf;
+        return 0;
+}
+
+static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
+{
+        u32 val;
+        int tx_fifo_avail;
+        u8 *buf = i2c_dev->msg_buf;
+        size_t buf_remaining = i2c_dev->msg_buf_remaining;
+        int words_to_transfer;
+
+        val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
+        tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
+                I2C_FIFO_STATUS_TX_SHIFT;
+
+        /* Rounds down to not include partial word at the end of buf */
+        words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
+        if (words_to_transfer > tx_fifo_avail)
+                words_to_transfer = tx_fifo_avail;
+
+        i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
+
+        buf += words_to_transfer * BYTES_PER_FIFO_WORD;
+        buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
+        tx_fifo_avail -= words_to_transfer;
+
+        /*
+         * If there is a partial word at the end of buf, handle it manually to
+         * prevent reading past the end of buf, which could cross a page
+         * boundary and fault.
+         */
+        if (tx_fifo_avail > 0 && buf_remaining > 0) {
+                BUG_ON(buf_remaining > 3);
+                memcpy(&val, buf, buf_remaining);
+                i2c_writel(i2c_dev, val, I2C_TX_FIFO);
+                buf_remaining = 0;
+                tx_fifo_avail--;
+        }
+
+        BUG_ON(tx_fifo_avail > 0 && buf_remaining > 0);
+        i2c_dev->msg_buf_remaining = buf_remaining;
+        i2c_dev->msg_buf = buf;
+        return 0;
+}
+
+/*
+ * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
+ * block.  This block is identical to the rest of the I2C blocks, except that
+ * it only supports master mode, it has registers moved around, and it needs
+ * some extra init to get it into I2C mode.  The register moves are handled
+ * by i2c_readl and i2c_writel
+ */
+static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
+{
+        u32 val = 0;
+        val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
+        val |= DVC_CTRL_REG3_SW_PROG;
+        val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
+        dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
+
+        val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
+        val |= DVC_CTRL_REG1_INTR_EN;
+        dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
+}
+
+static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
+{
+        u32 val;
+        int err = 0;
+
+        clk_enable(i2c_dev->clk);
+
+        tegra_periph_reset_assert(i2c_dev->clk);
+        udelay(2);
+        tegra_periph_reset_deassert(i2c_dev->clk);
+
+        if (i2c_dev->is_dvc)
+                tegra_dvc_init(i2c_dev);
+
+        val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN;
+        i2c_writel(i2c_dev, val, I2C_CNFG);
+        i2c_writel(i2c_dev, 0, I2C_INT_MASK);
+        clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
+
+        val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
+                0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
+        i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
+
+        if (tegra_i2c_flush_fifos(i2c_dev))
+                err = -ETIMEDOUT;
+
+        clk_disable(i2c_dev->clk);
+        return err;
+}
+
+static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
+{
+        u32 status;
+        const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
+        struct tegra_i2c_dev *i2c_dev = dev_id;
+
+        status = i2c_readl(i2c_dev, I2C_INT_STATUS);
+
+        if (status == 0) {
+                dev_warn(i2c_dev->dev, "interrupt with no status\n");
+                return IRQ_NONE;
+        }
+
+        if (unlikely(status & status_err)) {
+                if (status & I2C_INT_NO_ACK)
+                        i2c_dev->msg_err |= I2C_ERR_NO_ACK;
+                if (status & I2C_INT_ARBITRATION_LOST)
+                        i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
+                complete(&i2c_dev->msg_complete);
+                goto err;
+        }
+
+        if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
+                if (i2c_dev->msg_buf_remaining)
+                        tegra_i2c_empty_rx_fifo(i2c_dev);
+                else
+                        BUG();
+        }
+
+        if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
+                if (i2c_dev->msg_buf_remaining)
+                        tegra_i2c_fill_tx_fifo(i2c_dev);
+                else
+                        tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
+        }
+
+        if ((status & I2C_INT_PACKET_XFER_COMPLETE) &&
+                        !i2c_dev->msg_buf_remaining)
+                complete(&i2c_dev->msg_complete);
+
+        i2c_writel(i2c_dev, status, I2C_INT_STATUS);
+        if (i2c_dev->is_dvc)
+                dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
+        return IRQ_HANDLED;
+err:
+        /* An error occured, mask all interrupts */
+        tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
+                I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
+                I2C_INT_RX_FIFO_DATA_REQ);
+        i2c_writel(i2c_dev, status, I2C_INT_STATUS);
+        return IRQ_HANDLED;
+}
+
+static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
+        struct i2c_msg *msg, int stop)
+{
+        u32 packet_header;
+        u32 int_mask;
+        int ret;
+
+        tegra_i2c_flush_fifos(i2c_dev);
+        i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS);
+
+        if (msg->len == 0)
+                return -EINVAL;
+
+        i2c_dev->msg_buf = msg->buf;
+        i2c_dev->msg_buf_remaining = msg->len;
+        i2c_dev->msg_err = I2C_ERR_NONE;
+        i2c_dev->msg_read = (msg->flags & I2C_M_RD);
+        INIT_COMPLETION(i2c_dev->msg_complete);
+
+        packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
+                        PACKET_HEADER0_PROTOCOL_I2C |
+                        (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
+                        (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
+        i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
+
+        packet_header = msg->len - 1;
+        i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
+
+        packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
+        packet_header |= I2C_HEADER_IE_ENABLE;
+        if (msg->flags & I2C_M_TEN)
+                packet_header |= I2C_HEADER_10BIT_ADDR;
+        if (msg->flags & I2C_M_IGNORE_NAK)
+                packet_header |= I2C_HEADER_CONT_ON_NAK;
+        if (msg->flags & I2C_M_NOSTART)
+                packet_header |= I2C_HEADER_REPEAT_START;
+        if (msg->flags & I2C_M_RD)
+                packet_header |= I2C_HEADER_READ;
+        i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
+
+        if (!(msg->flags & I2C_M_RD))
+                tegra_i2c_fill_tx_fifo(i2c_dev);
+
+        int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
+        if (msg->flags & I2C_M_RD)
+                int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
+        else if (i2c_dev->msg_buf_remaining)
+                int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
+        tegra_i2c_unmask_irq(i2c_dev, int_mask);
+        dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
+                i2c_readl(i2c_dev, I2C_INT_MASK));
+
+        ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
+        tegra_i2c_mask_irq(i2c_dev, int_mask);
+
+        if (WARN_ON(ret == 0)) {
+                dev_err(i2c_dev->dev, "i2c transfer timed out\n");
+
+                tegra_i2c_init(i2c_dev);
+                return -ETIMEDOUT;
+        }
+
+        dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
+                ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
+
+        if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
+                return 0;
+
+        tegra_i2c_init(i2c_dev);
+        if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
+                if (msg->flags & I2C_M_IGNORE_NAK)
+                        return 0;
+                return -EREMOTEIO;
+        }
+
+        return -EIO;
+}
+
+static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
+        int num)
+{
+        struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+        int i;
+        int ret = 0;
+
+        if (i2c_dev->is_suspended)
+                return -EBUSY;
+
+        clk_enable(i2c_dev->clk);
+        for (i = 0; i < num; i++) {
+                int stop = (i == (num - 1)) ? 1  : 0;
+                ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
+                if (ret)
+                        break;
+        }
+        clk_disable(i2c_dev->clk);
+        return ret ?: i;
+}
+
+static u32 tegra_i2c_func(struct i2c_adapter *adap)
+{
+        return I2C_FUNC_I2C;
+}
+
+static const struct i2c_algorithm tegra_i2c_algo = {
+        .master_xfer    = tegra_i2c_xfer,
+        .functionality  = tegra_i2c_func,
+};
+
+static int tegra_i2c_probe(struct platform_device *pdev)
+{
+        struct tegra_i2c_dev *i2c_dev;
+        struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
+        struct resource *res;
+        struct resource *iomem;
+        struct clk *clk;
+        struct clk *i2c_clk;
+        void *base;
+        int irq;
+        int ret = 0;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "no mem resource\n");
+                return -EINVAL;
+        }
+        iomem = request_mem_region(res->start, resource_size(res), pdev->name);
+        if (!iomem) {
+                dev_err(&pdev->dev, "I2C region already claimed\n");
+                return -EBUSY;
+        }
+
+        base = ioremap(iomem->start, resource_size(iomem));
+        if (!base) {
+                dev_err(&pdev->dev, "Cannot ioremap I2C region\n");
+                return -ENOMEM;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "no irq resource\n");
+                ret = -EINVAL;
+                goto err_iounmap;
+        }
+        irq = res->start;
+
+        clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(clk)) {
+                dev_err(&pdev->dev, "missing controller clock");
+                ret = PTR_ERR(clk);
+                goto err_release_region;
+        }
+
+        i2c_clk = clk_get(&pdev->dev, "i2c");
+        if (IS_ERR(i2c_clk)) {
+                dev_err(&pdev->dev, "missing bus clock");
+                ret = PTR_ERR(i2c_clk);
+                goto err_clk_put;
+        }
+
+        i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev), GFP_KERNEL);
+        if (!i2c_dev) {
+                ret = -ENOMEM;
+                goto err_i2c_clk_put;
+        }
+
+        i2c_dev->base = base;
+        i2c_dev->clk = clk;
+        i2c_dev->i2c_clk = i2c_clk;
+        i2c_dev->iomem = iomem;
+        i2c_dev->adapter.algo = &tegra_i2c_algo;
+        i2c_dev->irq = irq;
+        i2c_dev->cont_id = pdev->id;
+        i2c_dev->dev = &pdev->dev;
+        i2c_dev->bus_clk_rate = pdata ? pdata->bus_clk_rate : 100000;
+
+        if (pdev->id == 3)
+                i2c_dev->is_dvc = 1;
+        init_completion(&i2c_dev->msg_complete);
+
+        platform_set_drvdata(pdev, i2c_dev);
+
+        ret = tegra_i2c_init(i2c_dev);
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to initialize i2c controller");
+                goto err_free;
+        }
+
+        ret = request_irq(i2c_dev->irq, tegra_i2c_isr, 0, pdev->name, i2c_dev);
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
+                goto err_free;
+        }
+
+        clk_enable(i2c_dev->i2c_clk);
+
+        i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
+        i2c_dev->adapter.owner = THIS_MODULE;
+        i2c_dev->adapter.class = I2C_CLASS_HWMON;
+        strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
+                sizeof(i2c_dev->adapter.name));
+        i2c_dev->adapter.algo = &tegra_i2c_algo;
+        i2c_dev->adapter.dev.parent = &pdev->dev;
+        i2c_dev->adapter.nr = pdev->id;
+
+        ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to add I2C adapter\n");
+                goto err_free_irq;
+        }
+
+        return 0;
+err_free_irq:
+        free_irq(i2c_dev->irq, i2c_dev);
+err_free:
+        kfree(i2c_dev);
+err_i2c_clk_put:
+        clk_put(i2c_clk);
+err_clk_put:
+        clk_put(clk);
+err_release_region:
+        release_mem_region(iomem->start, resource_size(iomem));
+err_iounmap:
+        iounmap(base);
+        return ret;
+}
+
+static int tegra_i2c_remove(struct platform_device *pdev)
+{
+        struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+        i2c_del_adapter(&i2c_dev->adapter);
+        free_irq(i2c_dev->irq, i2c_dev);
+        clk_put(i2c_dev->i2c_clk);
+        clk_put(i2c_dev->clk);
+        release_mem_region(i2c_dev->iomem->start,
+                resource_size(i2c_dev->iomem));
+        iounmap(i2c_dev->base);
+        kfree(i2c_dev);
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
+{
+        struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+
+        i2c_lock_adapter(&i2c_dev->adapter);
+        i2c_dev->is_suspended = true;
+        i2c_unlock_adapter(&i2c_dev->adapter);
+
+        return 0;
+}
+
+static int tegra_i2c_resume(struct platform_device *pdev)
+{
+        struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+        int ret;
+
+        i2c_lock_adapter(&i2c_dev->adapter);
+
+        ret = tegra_i2c_init(i2c_dev);
+
+        if (ret) {
+                i2c_unlock_adapter(&i2c_dev->adapter);
+                return ret;
+        }
+
+        i2c_dev->is_suspended = false;
+
+        i2c_unlock_adapter(&i2c_dev->adapter);
+
+        return 0;
+}
+#endif
+
+static struct platform_driver tegra_i2c_driver = {
+        .probe   = tegra_i2c_probe,
+        .remove  = tegra_i2c_remove,
+#ifdef CONFIG_PM
+        .suspend = tegra_i2c_suspend,
+        .resume  = tegra_i2c_resume,
+#endif
+        .driver  = {
+                .name  = "tegra-i2c",
+                .owner = THIS_MODULE,
+        },
+};
+
+static int __init tegra_i2c_init_driver(void)
+{
+        return platform_driver_register(&tegra_i2c_driver);
+}
+
+static void __exit tegra_i2c_exit_driver(void)
+{
+        platform_driver_unregister(&tegra_i2c_driver);
+}
+
+subsys_initcall(tegra_i2c_init_driver);
+module_exit(tegra_i2c_exit_driver);
+
+MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
+MODULE_AUTHOR("Colin Cross");
+MODULE_LICENSE("GPL v2");