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-rw-r--r--drivers/i2c/busses/Kconfig23
-rw-r--r--drivers/i2c/busses/Makefile1
-rw-r--r--drivers/i2c/busses/i2c-amd8111.c2
-rw-r--r--drivers/i2c/busses/i2c-au1550.c11
-rw-r--r--drivers/i2c/busses/i2c-bfin-twi.c16
-rw-r--r--drivers/i2c/busses/i2c-davinci.c586
-rw-r--r--drivers/i2c/busses/i2c-i801.c5
-rw-r--r--drivers/i2c/busses/i2c-ibm_iic.c9
-rw-r--r--drivers/i2c/busses/i2c-iop3xx.c8
-rw-r--r--drivers/i2c/busses/i2c-nforce2.c83
-rw-r--r--drivers/i2c/busses/i2c-stub.c79
11 files changed, 749 insertions, 74 deletions
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 9f3a4cd0b07f..de95c75efb41 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -75,11 +75,19 @@ config I2C_AMD8111
75 75
76config I2C_AT91 76config I2C_AT91
77 tristate "Atmel AT91 I2C Two-Wire interface (TWI)" 77 tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
78 depends on ARCH_AT91 && EXPERIMENTAL 78 depends on ARCH_AT91 && EXPERIMENTAL && BROKEN
79 help 79 help
80 This supports the use of the I2C interface on Atmel AT91 80 This supports the use of the I2C interface on Atmel AT91
81 processors. 81 processors.
82 82
83 This driver is BROKEN because the controller which it uses
84 will easily trigger RX overrun and TX underrun errors. Using
85 low I2C clock rates may partially work around those issues
86 on some systems. Another serious problem is that there is no
87 documented way to issue repeated START conditions, as needed
88 to support combined I2C messages. Use the i2c-gpio driver
89 unless your system can cope with those limitations.
90
83config I2C_AU1550 91config I2C_AU1550
84 tristate "Au1550/Au1200 SMBus interface" 92 tristate "Au1550/Au1200 SMBus interface"
85 depends on SOC_AU1550 || SOC_AU1200 93 depends on SOC_AU1550 || SOC_AU1200
@@ -106,6 +114,19 @@ config I2C_BLACKFIN_TWI_CLK_KHZ
106 help 114 help
107 The unit of the TWI clock is kHz. 115 The unit of the TWI clock is kHz.
108 116
117config I2C_DAVINCI
118 tristate "DaVinci I2C driver"
119 depends on ARCH_DAVINCI
120 help
121 Support for TI DaVinci I2C controller driver.
122
123 This driver can also be built as a module. If so, the module
124 will be called i2c-davinci.
125
126 Please note that this driver might be needed to bring up other
127 devices such as DaVinci NIC.
128 For details please see http://www.ti.com/davinci
129
109config I2C_ELEKTOR 130config I2C_ELEKTOR
110 tristate "Elektor ISA card" 131 tristate "Elektor ISA card"
111 depends on ISA && BROKEN_ON_SMP 132 depends on ISA && BROKEN_ON_SMP
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 5b752e4e1918..81d43c27cf93 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_I2C_AMD8111) += i2c-amd8111.o
11obj-$(CONFIG_I2C_AT91) += i2c-at91.o 11obj-$(CONFIG_I2C_AT91) += i2c-at91.o
12obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o 12obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
13obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o 13obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
14obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o
14obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o 15obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
15obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o 16obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
16obj-$(CONFIG_I2C_HYDRA) += i2c-hydra.o 17obj-$(CONFIG_I2C_HYDRA) += i2c-hydra.o
diff --git a/drivers/i2c/busses/i2c-amd8111.c b/drivers/i2c/busses/i2c-amd8111.c
index c9fca7b49267..5d1a27ef2504 100644
--- a/drivers/i2c/busses/i2c-amd8111.c
+++ b/drivers/i2c/busses/i2c-amd8111.c
@@ -326,7 +326,7 @@ static u32 amd8111_func(struct i2c_adapter *adapter)
326 I2C_FUNC_SMBUS_BYTE_DATA | 326 I2C_FUNC_SMBUS_BYTE_DATA |
327 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA | 327 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
328 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 328 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
329 I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_HWPEC_CALC; 329 I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_PEC;
330} 330}
331 331
332static const struct i2c_algorithm smbus_algorithm = { 332static const struct i2c_algorithm smbus_algorithm = {
diff --git a/drivers/i2c/busses/i2c-au1550.c b/drivers/i2c/busses/i2c-au1550.c
index d7e7c359fc36..2f684166c43d 100644
--- a/drivers/i2c/busses/i2c-au1550.c
+++ b/drivers/i2c/busses/i2c-au1550.c
@@ -48,17 +48,14 @@ wait_xfer_done(struct i2c_au1550_data *adap)
48 48
49 sp = (volatile psc_smb_t *)(adap->psc_base); 49 sp = (volatile psc_smb_t *)(adap->psc_base);
50 50
51 /* Wait for Tx FIFO Underflow. 51 /* Wait for Tx Buffer Empty
52 */ 52 */
53 for (i = 0; i < adap->xfer_timeout; i++) { 53 for (i = 0; i < adap->xfer_timeout; i++) {
54 stat = sp->psc_smbevnt; 54 stat = sp->psc_smbstat;
55 au_sync(); 55 au_sync();
56 if ((stat & PSC_SMBEVNT_TU) != 0) { 56 if ((stat & PSC_SMBSTAT_TE) != 0)
57 /* Clear it. */
58 sp->psc_smbevnt = PSC_SMBEVNT_TU;
59 au_sync();
60 return 0; 57 return 0;
61 } 58
62 udelay(1); 59 udelay(1);
63 } 60 }
64 61
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c
index 6311039dfe60..67224a424aba 100644
--- a/drivers/i2c/busses/i2c-bfin-twi.c
+++ b/drivers/i2c/busses/i2c-bfin-twi.c
@@ -44,7 +44,6 @@
44#define TWI_I2C_MODE_COMBINED 0x04 44#define TWI_I2C_MODE_COMBINED 0x04
45 45
46struct bfin_twi_iface { 46struct bfin_twi_iface {
47 struct mutex twi_lock;
48 int irq; 47 int irq;
49 spinlock_t lock; 48 spinlock_t lock;
50 char read_write; 49 char read_write;
@@ -228,12 +227,8 @@ static int bfin_twi_master_xfer(struct i2c_adapter *adap,
228 if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) 227 if (!(bfin_read_TWI_CONTROL() & TWI_ENA))
229 return -ENXIO; 228 return -ENXIO;
230 229
231 mutex_lock(&iface->twi_lock);
232
233 while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) { 230 while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) {
234 mutex_unlock(&iface->twi_lock);
235 yield(); 231 yield();
236 mutex_lock(&iface->twi_lock);
237 } 232 }
238 233
239 ret = 0; 234 ret = 0;
@@ -310,9 +305,6 @@ static int bfin_twi_master_xfer(struct i2c_adapter *adap,
310 break; 305 break;
311 } 306 }
312 307
313 /* Release mutex */
314 mutex_unlock(&iface->twi_lock);
315
316 return ret; 308 return ret;
317} 309}
318 310
@@ -330,12 +322,8 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
330 if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) 322 if (!(bfin_read_TWI_CONTROL() & TWI_ENA))
331 return -ENXIO; 323 return -ENXIO;
332 324
333 mutex_lock(&iface->twi_lock);
334
335 while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) { 325 while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) {
336 mutex_unlock(&iface->twi_lock);
337 yield(); 326 yield();
338 mutex_lock(&iface->twi_lock);
339 } 327 }
340 328
341 iface->writeNum = 0; 329 iface->writeNum = 0;
@@ -502,9 +490,6 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
502 490
503 rc = (iface->result >= 0) ? 0 : -1; 491 rc = (iface->result >= 0) ? 0 : -1;
504 492
505 /* Release mutex */
506 mutex_unlock(&iface->twi_lock);
507
508 return rc; 493 return rc;
509} 494}
510 495
@@ -555,7 +540,6 @@ static int i2c_bfin_twi_probe(struct platform_device *dev)
555 struct i2c_adapter *p_adap; 540 struct i2c_adapter *p_adap;
556 int rc; 541 int rc;
557 542
558 mutex_init(&(iface->twi_lock));
559 spin_lock_init(&(iface->lock)); 543 spin_lock_init(&(iface->lock));
560 init_completion(&(iface->complete)); 544 init_completion(&(iface->complete));
561 iface->irq = IRQ_TWI; 545 iface->irq = IRQ_TWI;
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
new file mode 100644
index 000000000000..bd7aaff35240
--- /dev/null
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -0,0 +1,586 @@
1/*
2 * TI DAVINCI I2C adapter driver.
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software Inc.
6 *
7 * Updated by Vinod & Sudhakar Feb 2005
8 *
9 * ----------------------------------------------------------------------------
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * ----------------------------------------------------------------------------
25 *
26 */
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/delay.h>
30#include <linux/i2c.h>
31#include <linux/clk.h>
32#include <linux/errno.h>
33#include <linux/sched.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/platform_device.h>
37#include <linux/io.h>
38
39#include <asm/hardware.h>
40#include <asm/mach-types.h>
41
42#include <asm/arch/i2c.h>
43
44/* ----- global defines ----------------------------------------------- */
45
46#define DAVINCI_I2C_TIMEOUT (1*HZ)
47#define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \
48 DAVINCI_I2C_IMR_SCD | \
49 DAVINCI_I2C_IMR_ARDY | \
50 DAVINCI_I2C_IMR_NACK | \
51 DAVINCI_I2C_IMR_AL)
52
53#define DAVINCI_I2C_OAR_REG 0x00
54#define DAVINCI_I2C_IMR_REG 0x04
55#define DAVINCI_I2C_STR_REG 0x08
56#define DAVINCI_I2C_CLKL_REG 0x0c
57#define DAVINCI_I2C_CLKH_REG 0x10
58#define DAVINCI_I2C_CNT_REG 0x14
59#define DAVINCI_I2C_DRR_REG 0x18
60#define DAVINCI_I2C_SAR_REG 0x1c
61#define DAVINCI_I2C_DXR_REG 0x20
62#define DAVINCI_I2C_MDR_REG 0x24
63#define DAVINCI_I2C_IVR_REG 0x28
64#define DAVINCI_I2C_EMDR_REG 0x2c
65#define DAVINCI_I2C_PSC_REG 0x30
66
67#define DAVINCI_I2C_IVR_AAS 0x07
68#define DAVINCI_I2C_IVR_SCD 0x06
69#define DAVINCI_I2C_IVR_XRDY 0x05
70#define DAVINCI_I2C_IVR_RDR 0x04
71#define DAVINCI_I2C_IVR_ARDY 0x03
72#define DAVINCI_I2C_IVR_NACK 0x02
73#define DAVINCI_I2C_IVR_AL 0x01
74
75#define DAVINCI_I2C_STR_BB (1 << 12)
76#define DAVINCI_I2C_STR_RSFULL (1 << 11)
77#define DAVINCI_I2C_STR_SCD (1 << 5)
78#define DAVINCI_I2C_STR_ARDY (1 << 2)
79#define DAVINCI_I2C_STR_NACK (1 << 1)
80#define DAVINCI_I2C_STR_AL (1 << 0)
81
82#define DAVINCI_I2C_MDR_NACK (1 << 15)
83#define DAVINCI_I2C_MDR_STT (1 << 13)
84#define DAVINCI_I2C_MDR_STP (1 << 11)
85#define DAVINCI_I2C_MDR_MST (1 << 10)
86#define DAVINCI_I2C_MDR_TRX (1 << 9)
87#define DAVINCI_I2C_MDR_XA (1 << 8)
88#define DAVINCI_I2C_MDR_IRS (1 << 5)
89
90#define DAVINCI_I2C_IMR_AAS (1 << 6)
91#define DAVINCI_I2C_IMR_SCD (1 << 5)
92#define DAVINCI_I2C_IMR_XRDY (1 << 4)
93#define DAVINCI_I2C_IMR_RRDY (1 << 3)
94#define DAVINCI_I2C_IMR_ARDY (1 << 2)
95#define DAVINCI_I2C_IMR_NACK (1 << 1)
96#define DAVINCI_I2C_IMR_AL (1 << 0)
97
98#define MOD_REG_BIT(val, mask, set) do { \
99 if (set) { \
100 val |= mask; \
101 } else { \
102 val &= ~mask; \
103 } \
104} while (0)
105
106struct davinci_i2c_dev {
107 struct device *dev;
108 void __iomem *base;
109 struct completion cmd_complete;
110 struct clk *clk;
111 int cmd_err;
112 u8 *buf;
113 size_t buf_len;
114 int irq;
115 struct i2c_adapter adapter;
116};
117
118/* default platform data to use if not supplied in the platform_device */
119static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
120 .bus_freq = 100,
121 .bus_delay = 0,
122};
123
124static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
125 int reg, u16 val)
126{
127 __raw_writew(val, i2c_dev->base + reg);
128}
129
130static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
131{
132 return __raw_readw(i2c_dev->base + reg);
133}
134
135/*
136 * This functions configures I2C and brings I2C out of reset.
137 * This function is called during I2C init function. This function
138 * also gets called if I2C encounters any errors.
139 */
140static int i2c_davinci_init(struct davinci_i2c_dev *dev)
141{
142 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
143 u16 psc;
144 u32 clk;
145 u32 clkh;
146 u32 clkl;
147 u32 input_clock = clk_get_rate(dev->clk);
148 u16 w;
149
150 if (!pdata)
151 pdata = &davinci_i2c_platform_data_default;
152
153 /* put I2C into reset */
154 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
155 MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 0);
156 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
157
158 /* NOTE: I2C Clock divider programming info
159 * As per I2C specs the following formulas provide prescaler
160 * and low/high divider values
161 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
162 * module clk
163 *
164 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
165 *
166 * Thus,
167 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
168 *
169 * where if PSC == 0, d = 7,
170 * if PSC == 1, d = 6
171 * if PSC > 1 , d = 5
172 */
173
174 psc = 26; /* To get 1MHz clock */
175
176 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - 10;
177 clkh = (50 * clk) / 100;
178 clkl = clk - clkh;
179
180 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
181 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
182 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
183
184 dev_dbg(dev->dev, "CLK = %d\n", clk);
185 dev_dbg(dev->dev, "PSC = %d\n",
186 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
187 dev_dbg(dev->dev, "CLKL = %d\n",
188 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
189 dev_dbg(dev->dev, "CLKH = %d\n",
190 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
191
192 /* Take the I2C module out of reset: */
193 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
194 MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 1);
195 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
196
197 /* Enable interrupts */
198 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
199
200 return 0;
201}
202
203/*
204 * Waiting for bus not busy
205 */
206static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
207 char allow_sleep)
208{
209 unsigned long timeout;
210
211 timeout = jiffies + DAVINCI_I2C_TIMEOUT;
212 while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
213 & DAVINCI_I2C_STR_BB) {
214 if (time_after(jiffies, timeout)) {
215 dev_warn(dev->dev,
216 "timeout waiting for bus ready\n");
217 return -ETIMEDOUT;
218 }
219 if (allow_sleep)
220 schedule_timeout(1);
221 }
222
223 return 0;
224}
225
226/*
227 * Low level master read/write transaction. This function is called
228 * from i2c_davinci_xfer.
229 */
230static int
231i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
232{
233 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
234 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
235 u32 flag;
236 u32 stat;
237 u16 w;
238 int r;
239
240 if (msg->len == 0)
241 return -EINVAL;
242
243 if (!pdata)
244 pdata = &davinci_i2c_platform_data_default;
245 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
246 if (pdata->bus_delay)
247 udelay(pdata->bus_delay);
248
249 /* set the slave address */
250 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
251
252 dev->buf = msg->buf;
253 dev->buf_len = msg->len;
254
255 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
256
257 init_completion(&dev->cmd_complete);
258 dev->cmd_err = 0;
259
260 /* Clear any pending interrupts by reading the IVR */
261 stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG);
262
263 /* Take I2C out of reset, configure it as master and set the
264 * start bit */
265 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST | DAVINCI_I2C_MDR_STT;
266
267 /* if the slave address is ten bit address, enable XA bit */
268 if (msg->flags & I2C_M_TEN)
269 flag |= DAVINCI_I2C_MDR_XA;
270 if (!(msg->flags & I2C_M_RD))
271 flag |= DAVINCI_I2C_MDR_TRX;
272 if (stop)
273 flag |= DAVINCI_I2C_MDR_STP;
274
275 /* Enable receive or transmit interrupts */
276 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
277 if (msg->flags & I2C_M_RD)
278 MOD_REG_BIT(w, DAVINCI_I2C_IMR_RRDY, 1);
279 else
280 MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 1);
281 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
282
283 /* write the data into mode register */
284 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
285
286 r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
287 DAVINCI_I2C_TIMEOUT);
288 dev->buf_len = 0;
289 if (r < 0)
290 return r;
291
292 if (r == 0) {
293 dev_err(dev->dev, "controller timed out\n");
294 i2c_davinci_init(dev);
295 return -ETIMEDOUT;
296 }
297
298 /* no error */
299 if (likely(!dev->cmd_err))
300 return msg->len;
301
302 /* We have an error */
303 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
304 i2c_davinci_init(dev);
305 return -EIO;
306 }
307
308 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
309 if (msg->flags & I2C_M_IGNORE_NAK)
310 return msg->len;
311 if (stop) {
312 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
313 MOD_REG_BIT(w, DAVINCI_I2C_MDR_STP, 1);
314 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
315 }
316 return -EREMOTEIO;
317 }
318 return -EIO;
319}
320
321/*
322 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
323 */
324static int
325i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
326{
327 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
328 int i;
329 int ret;
330
331 dev_dbg(dev->dev, "%s: msgs: %d\n", __FUNCTION__, num);
332
333 ret = i2c_davinci_wait_bus_not_busy(dev, 1);
334 if (ret < 0) {
335 dev_warn(dev->dev, "timeout waiting for bus ready\n");
336 return ret;
337 }
338
339 for (i = 0; i < num; i++) {
340 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
341 if (ret < 0)
342 return ret;
343 }
344
345 dev_dbg(dev->dev, "%s:%d ret: %d\n", __FUNCTION__, __LINE__, ret);
346
347 return num;
348}
349
350static u32 i2c_davinci_func(struct i2c_adapter *adap)
351{
352 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
353}
354
355/*
356 * Interrupt service routine. This gets called whenever an I2C interrupt
357 * occurs.
358 */
359static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
360{
361 struct davinci_i2c_dev *dev = dev_id;
362 u32 stat;
363 int count = 0;
364 u16 w;
365
366 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
367 dev_dbg(dev->dev, "%s: stat=0x%x\n", __FUNCTION__, stat);
368 if (count++ == 100) {
369 dev_warn(dev->dev, "Too much work in one IRQ\n");
370 break;
371 }
372
373 switch (stat) {
374 case DAVINCI_I2C_IVR_AL:
375 dev->cmd_err |= DAVINCI_I2C_STR_AL;
376 complete(&dev->cmd_complete);
377 break;
378
379 case DAVINCI_I2C_IVR_NACK:
380 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
381 complete(&dev->cmd_complete);
382 break;
383
384 case DAVINCI_I2C_IVR_ARDY:
385 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG);
386 MOD_REG_BIT(w, DAVINCI_I2C_STR_ARDY, 1);
387 davinci_i2c_write_reg(dev, DAVINCI_I2C_STR_REG, w);
388 complete(&dev->cmd_complete);
389 break;
390
391 case DAVINCI_I2C_IVR_RDR:
392 if (dev->buf_len) {
393 *dev->buf++ =
394 davinci_i2c_read_reg(dev,
395 DAVINCI_I2C_DRR_REG);
396 dev->buf_len--;
397 if (dev->buf_len)
398 continue;
399
400 w = davinci_i2c_read_reg(dev,
401 DAVINCI_I2C_STR_REG);
402 MOD_REG_BIT(w, DAVINCI_I2C_IMR_RRDY, 0);
403 davinci_i2c_write_reg(dev,
404 DAVINCI_I2C_STR_REG,
405 w);
406 } else
407 dev_err(dev->dev, "RDR IRQ while no"
408 "data requested\n");
409 break;
410
411 case DAVINCI_I2C_IVR_XRDY:
412 if (dev->buf_len) {
413 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
414 *dev->buf++);
415 dev->buf_len--;
416 if (dev->buf_len)
417 continue;
418
419 w = davinci_i2c_read_reg(dev,
420 DAVINCI_I2C_IMR_REG);
421 MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 0);
422 davinci_i2c_write_reg(dev,
423 DAVINCI_I2C_IMR_REG,
424 w);
425 } else
426 dev_err(dev->dev, "TDR IRQ while no data to"
427 "send\n");
428 break;
429
430 case DAVINCI_I2C_IVR_SCD:
431 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG);
432 MOD_REG_BIT(w, DAVINCI_I2C_STR_SCD, 1);
433 davinci_i2c_write_reg(dev, DAVINCI_I2C_STR_REG, w);
434 complete(&dev->cmd_complete);
435 break;
436
437 case DAVINCI_I2C_IVR_AAS:
438 dev_warn(dev->dev, "Address as slave interrupt\n");
439 }/* switch */
440 }/* while */
441
442 return count ? IRQ_HANDLED : IRQ_NONE;
443}
444
445static struct i2c_algorithm i2c_davinci_algo = {
446 .master_xfer = i2c_davinci_xfer,
447 .functionality = i2c_davinci_func,
448};
449
450static int davinci_i2c_probe(struct platform_device *pdev)
451{
452 struct davinci_i2c_dev *dev;
453 struct i2c_adapter *adap;
454 struct resource *mem, *irq, *ioarea;
455 int r;
456
457 /* NOTE: driver uses the static register mapping */
458 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
459 if (!mem) {
460 dev_err(&pdev->dev, "no mem resource?\n");
461 return -ENODEV;
462 }
463
464 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
465 if (!irq) {
466 dev_err(&pdev->dev, "no irq resource?\n");
467 return -ENODEV;
468 }
469
470 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
471 pdev->name);
472 if (!ioarea) {
473 dev_err(&pdev->dev, "I2C region already claimed\n");
474 return -EBUSY;
475 }
476
477 dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL);
478 if (!dev) {
479 r = -ENOMEM;
480 goto err_release_region;
481 }
482
483 dev->dev = get_device(&pdev->dev);
484 dev->irq = irq->start;
485 platform_set_drvdata(pdev, dev);
486
487 dev->clk = clk_get(&pdev->dev, "I2CCLK");
488 if (IS_ERR(dev->clk)) {
489 r = -ENODEV;
490 goto err_free_mem;
491 }
492 clk_enable(dev->clk);
493
494 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
495 i2c_davinci_init(dev);
496
497 r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev);
498 if (r) {
499 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
500 goto err_unuse_clocks;
501 }
502
503 adap = &dev->adapter;
504 i2c_set_adapdata(adap, dev);
505 adap->owner = THIS_MODULE;
506 adap->class = I2C_CLASS_HWMON;
507 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
508 adap->algo = &i2c_davinci_algo;
509 adap->dev.parent = &pdev->dev;
510
511 /* FIXME */
512 adap->timeout = 1;
513 adap->retries = 1;
514
515 adap->nr = pdev->id;
516 r = i2c_add_numbered_adapter(adap);
517 if (r) {
518 dev_err(&pdev->dev, "failure adding adapter\n");
519 goto err_free_irq;
520 }
521
522 return 0;
523
524err_free_irq:
525 free_irq(dev->irq, dev);
526err_unuse_clocks:
527 clk_disable(dev->clk);
528 clk_put(dev->clk);
529 dev->clk = NULL;
530err_free_mem:
531 platform_set_drvdata(pdev, NULL);
532 put_device(&pdev->dev);
533 kfree(dev);
534err_release_region:
535 release_mem_region(mem->start, (mem->end - mem->start) + 1);
536
537 return r;
538}
539
540static int davinci_i2c_remove(struct platform_device *pdev)
541{
542 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
543 struct resource *mem;
544
545 platform_set_drvdata(pdev, NULL);
546 i2c_del_adapter(&dev->adapter);
547 put_device(&pdev->dev);
548
549 clk_disable(dev->clk);
550 clk_put(dev->clk);
551 dev->clk = NULL;
552
553 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
554 free_irq(IRQ_I2C, dev);
555 kfree(dev);
556
557 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
558 release_mem_region(mem->start, (mem->end - mem->start) + 1);
559 return 0;
560}
561
562static struct platform_driver davinci_i2c_driver = {
563 .probe = davinci_i2c_probe,
564 .remove = davinci_i2c_remove,
565 .driver = {
566 .name = "i2c_davinci",
567 .owner = THIS_MODULE,
568 },
569};
570
571/* I2C may be needed to bring up other drivers */
572static int __init davinci_i2c_init_driver(void)
573{
574 return platform_driver_register(&davinci_i2c_driver);
575}
576subsys_initcall(davinci_i2c_init_driver);
577
578static void __exit davinci_i2c_exit_driver(void)
579{
580 platform_driver_unregister(&davinci_i2c_driver);
581}
582module_exit(davinci_i2c_exit_driver);
583
584MODULE_AUTHOR("Texas Instruments India");
585MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
586MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 289816db52ae..ac27e5f84ebe 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -34,6 +34,7 @@
34 ESB2 269B 34 ESB2 269B
35 ICH8 283E 35 ICH8 283E
36 ICH9 2930 36 ICH9 2930
37 Tolapai 5032
37 This driver supports several versions of Intel's I/O Controller Hubs (ICH). 38 This driver supports several versions of Intel's I/O Controller Hubs (ICH).
38 For SMBus support, they are similar to the PIIX4 and are part 39 For SMBus support, they are similar to the PIIX4 and are part
39 of Intel's '810' and other chipsets. 40 of Intel's '810' and other chipsets.
@@ -515,7 +516,7 @@ static u32 i801_func(struct i2c_adapter *adapter)
515 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 516 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
516 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 517 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
517 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 518 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
518 | (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0); 519 | (isich4 ? I2C_FUNC_SMBUS_PEC : 0);
519} 520}
520 521
521static const struct i2c_algorithm smbus_algorithm = { 522static const struct i2c_algorithm smbus_algorithm = {
@@ -543,6 +544,7 @@ static struct pci_device_id i801_ids[] = {
543 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 544 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
544 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 545 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
545 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 546 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
547 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) },
546 { 0, } 548 { 0, }
547}; 549};
548 550
@@ -563,6 +565,7 @@ static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id
563 case PCI_DEVICE_ID_INTEL_ESB2_17: 565 case PCI_DEVICE_ID_INTEL_ESB2_17:
564 case PCI_DEVICE_ID_INTEL_ICH8_5: 566 case PCI_DEVICE_ID_INTEL_ICH8_5:
565 case PCI_DEVICE_ID_INTEL_ICH9_6: 567 case PCI_DEVICE_ID_INTEL_ICH9_6:
568 case PCI_DEVICE_ID_INTEL_TOLAPAI_1:
566 isich4 = 1; 569 isich4 = 1;
567 break; 570 break;
568 default: 571 default:
diff --git a/drivers/i2c/busses/i2c-ibm_iic.c b/drivers/i2c/busses/i2c-ibm_iic.c
index 8b14d14e60ca..e08bacadd6bc 100644
--- a/drivers/i2c/busses/i2c-ibm_iic.c
+++ b/drivers/i2c/busses/i2c-ibm_iic.c
@@ -738,7 +738,14 @@ static int __devinit iic_probe(struct ocp_device *ocp){
738 adap->timeout = 1; 738 adap->timeout = 1;
739 adap->retries = 1; 739 adap->retries = 1;
740 740
741 if ((ret = i2c_add_adapter(adap)) != 0){ 741 /*
742 * If "dev->idx" is negative we consider it as zero.
743 * The reason to do so is to avoid sysfs names that only make
744 * sense when there are multiple adapters.
745 */
746 adap->nr = dev->idx >= 0 ? dev->idx : 0;
747
748 if ((ret = i2c_add_numbered_adapter(adap)) < 0) {
742 printk(KERN_CRIT "ibm-iic%d: failed to register i2c adapter\n", 749 printk(KERN_CRIT "ibm-iic%d: failed to register i2c adapter\n",
743 dev->idx); 750 dev->idx);
744 goto fail; 751 goto fail;
diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c
index ace644e21b14..c70146e4c2c0 100644
--- a/drivers/i2c/busses/i2c-iop3xx.c
+++ b/drivers/i2c/busses/i2c-iop3xx.c
@@ -389,13 +389,6 @@ iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
389 return im; 389 return im;
390} 390}
391 391
392static int
393iop3xx_i2c_algo_control(struct i2c_adapter *adapter, unsigned int cmd,
394 unsigned long arg)
395{
396 return 0;
397}
398
399static u32 392static u32
400iop3xx_i2c_func(struct i2c_adapter *adap) 393iop3xx_i2c_func(struct i2c_adapter *adap)
401{ 394{
@@ -404,7 +397,6 @@ iop3xx_i2c_func(struct i2c_adapter *adap)
404 397
405static const struct i2c_algorithm iop3xx_i2c_algo = { 398static const struct i2c_algorithm iop3xx_i2c_algo = {
406 .master_xfer = iop3xx_i2c_master_xfer, 399 .master_xfer = iop3xx_i2c_master_xfer,
407 .algo_control = iop3xx_i2c_algo_control,
408 .functionality = iop3xx_i2c_func, 400 .functionality = iop3xx_i2c_func,
409}; 401};
410 402
diff --git a/drivers/i2c/busses/i2c-nforce2.c b/drivers/i2c/busses/i2c-nforce2.c
index c48140f782d0..1bf590c74166 100644
--- a/drivers/i2c/busses/i2c-nforce2.c
+++ b/drivers/i2c/busses/i2c-nforce2.c
@@ -62,6 +62,7 @@ struct nforce2_smbus {
62 int base; 62 int base;
63 int size; 63 int size;
64 int blockops; 64 int blockops;
65 int can_abort;
65}; 66};
66 67
67 68
@@ -83,7 +84,14 @@ struct nforce2_smbus {
83#define NVIDIA_SMB_DATA (smbus->base + 0x04) /* 32 data registers */ 84#define NVIDIA_SMB_DATA (smbus->base + 0x04) /* 32 data registers */
84#define NVIDIA_SMB_BCNT (smbus->base + 0x24) /* number of data 85#define NVIDIA_SMB_BCNT (smbus->base + 0x24) /* number of data
85 bytes */ 86 bytes */
86 87#define NVIDIA_SMB_STATUS_ABRT (smbus->base + 0x3c) /* register used to
88 check the status of
89 the abort command */
90#define NVIDIA_SMB_CTRL (smbus->base + 0x3e) /* control register */
91
92#define NVIDIA_SMB_STATUS_ABRT_STS 0x01 /* Bit to notify that
93 abort succeeded */
94#define NVIDIA_SMB_CTRL_ABORT 0x20
87#define NVIDIA_SMB_STS_DONE 0x80 95#define NVIDIA_SMB_STS_DONE 0x80
88#define NVIDIA_SMB_STS_ALRM 0x40 96#define NVIDIA_SMB_STS_ALRM 0x40
89#define NVIDIA_SMB_STS_RES 0x20 97#define NVIDIA_SMB_STS_RES 0x20
@@ -98,15 +106,61 @@ struct nforce2_smbus {
98#define NVIDIA_SMB_PRTCL_BLOCK_DATA 0x0a 106#define NVIDIA_SMB_PRTCL_BLOCK_DATA 0x0a
99#define NVIDIA_SMB_PRTCL_PEC 0x80 107#define NVIDIA_SMB_PRTCL_PEC 0x80
100 108
109/* Misc definitions */
110#define MAX_TIMEOUT 100
111
101static struct pci_driver nforce2_driver; 112static struct pci_driver nforce2_driver;
102 113
114static void nforce2_abort(struct i2c_adapter *adap)
115{
116 struct nforce2_smbus *smbus = adap->algo_data;
117 int timeout = 0;
118 unsigned char temp;
119
120 dev_dbg(&adap->dev, "Aborting current transaction\n");
121
122 outb_p(NVIDIA_SMB_CTRL_ABORT, NVIDIA_SMB_CTRL);
123 do {
124 msleep(1);
125 temp = inb_p(NVIDIA_SMB_STATUS_ABRT);
126 } while (!(temp & NVIDIA_SMB_STATUS_ABRT_STS) &&
127 (timeout++ < MAX_TIMEOUT));
128 if (!(temp & NVIDIA_SMB_STATUS_ABRT_STS))
129 dev_err(&adap->dev, "Can't reset the smbus\n");
130 outb_p(NVIDIA_SMB_STATUS_ABRT_STS, NVIDIA_SMB_STATUS_ABRT);
131}
132
133static int nforce2_check_status(struct i2c_adapter *adap)
134{
135 struct nforce2_smbus *smbus = adap->algo_data;
136 int timeout = 0;
137 unsigned char temp;
138
139 do {
140 msleep(1);
141 temp = inb_p(NVIDIA_SMB_STS);
142 } while ((!temp) && (timeout++ < MAX_TIMEOUT));
143
144 if (timeout >= MAX_TIMEOUT) {
145 dev_dbg(&adap->dev, "SMBus Timeout!\n");
146 if (smbus->can_abort)
147 nforce2_abort(adap);
148 return -1;
149 }
150 if (!(temp & NVIDIA_SMB_STS_DONE) || (temp & NVIDIA_SMB_STS_STATUS)) {
151 dev_dbg(&adap->dev, "Transaction failed (0x%02x)!\n", temp);
152 return -1;
153 }
154 return 0;
155}
156
103/* Return -1 on error */ 157/* Return -1 on error */
104static s32 nforce2_access(struct i2c_adapter * adap, u16 addr, 158static s32 nforce2_access(struct i2c_adapter * adap, u16 addr,
105 unsigned short flags, char read_write, 159 unsigned short flags, char read_write,
106 u8 command, int size, union i2c_smbus_data * data) 160 u8 command, int size, union i2c_smbus_data * data)
107{ 161{
108 struct nforce2_smbus *smbus = adap->algo_data; 162 struct nforce2_smbus *smbus = adap->algo_data;
109 unsigned char protocol, pec, temp; 163 unsigned char protocol, pec;
110 u8 len; 164 u8 len;
111 int i; 165 int i;
112 166
@@ -170,21 +224,8 @@ static s32 nforce2_access(struct i2c_adapter * adap, u16 addr,
170 outb_p((addr & 0x7f) << 1, NVIDIA_SMB_ADDR); 224 outb_p((addr & 0x7f) << 1, NVIDIA_SMB_ADDR);
171 outb_p(protocol, NVIDIA_SMB_PRTCL); 225 outb_p(protocol, NVIDIA_SMB_PRTCL);
172 226
173 temp = inb_p(NVIDIA_SMB_STS); 227 if (nforce2_check_status(adap))
174
175 if (~temp & NVIDIA_SMB_STS_DONE) {
176 udelay(500);
177 temp = inb_p(NVIDIA_SMB_STS);
178 }
179 if (~temp & NVIDIA_SMB_STS_DONE) {
180 msleep(10);
181 temp = inb_p(NVIDIA_SMB_STS);
182 }
183
184 if ((~temp & NVIDIA_SMB_STS_DONE) || (temp & NVIDIA_SMB_STS_STATUS)) {
185 dev_dbg(&adap->dev, "SMBus Timeout! (0x%02x)\n", temp);
186 return -1; 228 return -1;
187 }
188 229
189 if (read_write == I2C_SMBUS_WRITE) 230 if (read_write == I2C_SMBUS_WRITE)
190 return 0; 231 return 0;
@@ -202,7 +243,12 @@ static s32 nforce2_access(struct i2c_adapter * adap, u16 addr,
202 243
203 case I2C_SMBUS_BLOCK_DATA: 244 case I2C_SMBUS_BLOCK_DATA:
204 len = inb_p(NVIDIA_SMB_BCNT); 245 len = inb_p(NVIDIA_SMB_BCNT);
205 len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX); 246 if ((len <= 0) || (len > I2C_SMBUS_BLOCK_MAX)) {
247 dev_err(&adap->dev, "Transaction failed "
248 "(received block size: 0x%02x)\n",
249 len);
250 return -1;
251 }
206 for (i = 0; i < len; i++) 252 for (i = 0; i < len; i++)
207 data->block[i+1] = inb_p(NVIDIA_SMB_DATA + i); 253 data->block[i+1] = inb_p(NVIDIA_SMB_DATA + i);
208 data->block[0] = len; 254 data->block[0] = len;
@@ -218,6 +264,7 @@ static u32 nforce2_func(struct i2c_adapter *adapter)
218 /* other functionality might be possible, but is not tested */ 264 /* other functionality might be possible, but is not tested */
219 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 265 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
220 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 266 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
267 I2C_FUNC_SMBUS_PEC |
221 (((struct nforce2_smbus*)adapter->algo_data)->blockops ? 268 (((struct nforce2_smbus*)adapter->algo_data)->blockops ?
222 I2C_FUNC_SMBUS_BLOCK_DATA : 0); 269 I2C_FUNC_SMBUS_BLOCK_DATA : 0);
223} 270}
@@ -308,6 +355,8 @@ static int __devinit nforce2_probe(struct pci_dev *dev, const struct pci_device_
308 case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS: 355 case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS:
309 smbuses[0].blockops = 1; 356 smbuses[0].blockops = 1;
310 smbuses[1].blockops = 1; 357 smbuses[1].blockops = 1;
358 smbuses[0].can_abort = 1;
359 smbuses[1].can_abort = 1;
311 } 360 }
312 361
313 /* SMBus adapter 1 */ 362 /* SMBus adapter 1 */
diff --git a/drivers/i2c/busses/i2c-stub.c b/drivers/i2c/busses/i2c-stub.c
index a54adc50d162..84df29da1ddc 100644
--- a/drivers/i2c/busses/i2c-stub.c
+++ b/drivers/i2c/busses/i2c-stub.c
@@ -24,24 +24,41 @@
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/module.h> 25#include <linux/module.h>
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/slab.h>
27#include <linux/errno.h> 28#include <linux/errno.h>
28#include <linux/i2c.h> 29#include <linux/i2c.h>
29 30
30static unsigned short chip_addr; 31#define MAX_CHIPS 10
31module_param(chip_addr, ushort, S_IRUGO);
32MODULE_PARM_DESC(chip_addr, "Chip address (between 0x03 and 0x77)\n");
33 32
34static u8 stub_pointer; 33static unsigned short chip_addr[MAX_CHIPS];
35static u8 stub_bytes[256]; 34module_param_array(chip_addr, ushort, NULL, S_IRUGO);
36static u16 stub_words[256]; 35MODULE_PARM_DESC(chip_addr,
36 "Chip addresses (up to 10, between 0x03 and 0x77)\n");
37
38struct stub_chip {
39 u8 pointer;
40 u8 bytes[256];
41 u16 words[256];
42};
43
44static struct stub_chip *stub_chips;
37 45
38/* Return -1 on error. */ 46/* Return -1 on error. */
39static s32 stub_xfer(struct i2c_adapter * adap, u16 addr, unsigned short flags, 47static s32 stub_xfer(struct i2c_adapter * adap, u16 addr, unsigned short flags,
40 char read_write, u8 command, int size, union i2c_smbus_data * data) 48 char read_write, u8 command, int size, union i2c_smbus_data * data)
41{ 49{
42 s32 ret; 50 s32 ret;
43 51 int i;
44 if (addr != chip_addr) 52 struct stub_chip *chip = NULL;
53
54 /* Search for the right chip */
55 for (i = 0; i < MAX_CHIPS && chip_addr[i]; i++) {
56 if (addr == chip_addr[i]) {
57 chip = stub_chips + i;
58 break;
59 }
60 }
61 if (!chip)
45 return -ENODEV; 62 return -ENODEV;
46 63
47 switch (size) { 64 switch (size) {
@@ -53,12 +70,12 @@ static s32 stub_xfer(struct i2c_adapter * adap, u16 addr, unsigned short flags,
53 70
54 case I2C_SMBUS_BYTE: 71 case I2C_SMBUS_BYTE:
55 if (read_write == I2C_SMBUS_WRITE) { 72 if (read_write == I2C_SMBUS_WRITE) {
56 stub_pointer = command; 73 chip->pointer = command;
57 dev_dbg(&adap->dev, "smbus byte - addr 0x%02x, " 74 dev_dbg(&adap->dev, "smbus byte - addr 0x%02x, "
58 "wrote 0x%02x.\n", 75 "wrote 0x%02x.\n",
59 addr, command); 76 addr, command);
60 } else { 77 } else {
61 data->byte = stub_bytes[stub_pointer++]; 78 data->byte = chip->bytes[chip->pointer++];
62 dev_dbg(&adap->dev, "smbus byte - addr 0x%02x, " 79 dev_dbg(&adap->dev, "smbus byte - addr 0x%02x, "
63 "read 0x%02x.\n", 80 "read 0x%02x.\n",
64 addr, data->byte); 81 addr, data->byte);
@@ -69,29 +86,29 @@ static s32 stub_xfer(struct i2c_adapter * adap, u16 addr, unsigned short flags,
69 86
70 case I2C_SMBUS_BYTE_DATA: 87 case I2C_SMBUS_BYTE_DATA:
71 if (read_write == I2C_SMBUS_WRITE) { 88 if (read_write == I2C_SMBUS_WRITE) {
72 stub_bytes[command] = data->byte; 89 chip->bytes[command] = data->byte;
73 dev_dbg(&adap->dev, "smbus byte data - addr 0x%02x, " 90 dev_dbg(&adap->dev, "smbus byte data - addr 0x%02x, "
74 "wrote 0x%02x at 0x%02x.\n", 91 "wrote 0x%02x at 0x%02x.\n",
75 addr, data->byte, command); 92 addr, data->byte, command);
76 } else { 93 } else {
77 data->byte = stub_bytes[command]; 94 data->byte = chip->bytes[command];
78 dev_dbg(&adap->dev, "smbus byte data - addr 0x%02x, " 95 dev_dbg(&adap->dev, "smbus byte data - addr 0x%02x, "
79 "read 0x%02x at 0x%02x.\n", 96 "read 0x%02x at 0x%02x.\n",
80 addr, data->byte, command); 97 addr, data->byte, command);
81 } 98 }
82 stub_pointer = command + 1; 99 chip->pointer = command + 1;
83 100
84 ret = 0; 101 ret = 0;
85 break; 102 break;
86 103
87 case I2C_SMBUS_WORD_DATA: 104 case I2C_SMBUS_WORD_DATA:
88 if (read_write == I2C_SMBUS_WRITE) { 105 if (read_write == I2C_SMBUS_WRITE) {
89 stub_words[command] = data->word; 106 chip->words[command] = data->word;
90 dev_dbg(&adap->dev, "smbus word data - addr 0x%02x, " 107 dev_dbg(&adap->dev, "smbus word data - addr 0x%02x, "
91 "wrote 0x%04x at 0x%02x.\n", 108 "wrote 0x%04x at 0x%02x.\n",
92 addr, data->word, command); 109 addr, data->word, command);
93 } else { 110 } else {
94 data->word = stub_words[command]; 111 data->word = chip->words[command];
95 dev_dbg(&adap->dev, "smbus word data - addr 0x%02x, " 112 dev_dbg(&adap->dev, "smbus word data - addr 0x%02x, "
96 "read 0x%04x at 0x%02x.\n", 113 "read 0x%04x at 0x%02x.\n",
97 addr, data->word, command); 114 addr, data->word, command);
@@ -129,23 +146,41 @@ static struct i2c_adapter stub_adapter = {
129 146
130static int __init i2c_stub_init(void) 147static int __init i2c_stub_init(void)
131{ 148{
132 if (!chip_addr) { 149 int i, ret;
150
151 if (!chip_addr[0]) {
133 printk(KERN_ERR "i2c-stub: Please specify a chip address\n"); 152 printk(KERN_ERR "i2c-stub: Please specify a chip address\n");
134 return -ENODEV; 153 return -ENODEV;
135 } 154 }
136 if (chip_addr < 0x03 || chip_addr > 0x77) { 155
137 printk(KERN_ERR "i2c-stub: Invalid chip address 0x%02x\n", 156 for (i = 0; i < MAX_CHIPS && chip_addr[i]; i++) {
138 chip_addr); 157 if (chip_addr[i] < 0x03 || chip_addr[i] > 0x77) {
139 return -EINVAL; 158 printk(KERN_ERR "i2c-stub: Invalid chip address "
159 "0x%02x\n", chip_addr[i]);
160 return -EINVAL;
161 }
162
163 printk(KERN_INFO "i2c-stub: Virtual chip at 0x%02x\n",
164 chip_addr[i]);
140 } 165 }
141 166
142 printk(KERN_INFO "i2c-stub: Virtual chip at 0x%02x\n", chip_addr); 167 /* Allocate memory for all chips at once */
143 return i2c_add_adapter(&stub_adapter); 168 stub_chips = kzalloc(i * sizeof(struct stub_chip), GFP_KERNEL);
169 if (!stub_chips) {
170 printk(KERN_ERR "i2c-stub: Out of memory\n");
171 return -ENOMEM;
172 }
173
174 ret = i2c_add_adapter(&stub_adapter);
175 if (ret)
176 kfree(stub_chips);
177 return ret;
144} 178}
145 179
146static void __exit i2c_stub_exit(void) 180static void __exit i2c_stub_exit(void)
147{ 181{
148 i2c_del_adapter(&stub_adapter); 182 i2c_del_adapter(&stub_adapter);
183 kfree(stub_chips);
149} 184}
150 185
151MODULE_AUTHOR("Mark M. Hoffman <mhoffman@lightlink.com>"); 186MODULE_AUTHOR("Mark M. Hoffman <mhoffman@lightlink.com>");