diff options
Diffstat (limited to 'drivers/i2c/busses/i2c-mxs.c')
-rw-r--r-- | drivers/i2c/busses/i2c-mxs.c | 186 |
1 files changed, 14 insertions, 172 deletions
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c index 1f58197062cf..286ca1917820 100644 --- a/drivers/i2c/busses/i2c-mxs.c +++ b/drivers/i2c/busses/i2c-mxs.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Freescale MXS I2C bus driver | 2 | * Freescale MXS I2C bus driver |
3 | * | 3 | * |
4 | * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. | 4 | * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K. |
5 | * | 5 | * |
6 | * based on a (non-working) driver which was: | 6 | * based on a (non-working) driver which was: |
7 | * | 7 | * |
@@ -35,10 +35,6 @@ | |||
35 | 35 | ||
36 | #define DRIVER_NAME "mxs-i2c" | 36 | #define DRIVER_NAME "mxs-i2c" |
37 | 37 | ||
38 | static bool use_pioqueue; | ||
39 | module_param(use_pioqueue, bool, 0); | ||
40 | MODULE_PARM_DESC(use_pioqueue, "Use PIOQUEUE mode for transfer instead of DMA"); | ||
41 | |||
42 | #define MXS_I2C_CTRL0 (0x00) | 38 | #define MXS_I2C_CTRL0 (0x00) |
43 | #define MXS_I2C_CTRL0_SET (0x04) | 39 | #define MXS_I2C_CTRL0_SET (0x04) |
44 | 40 | ||
@@ -75,23 +71,6 @@ MODULE_PARM_DESC(use_pioqueue, "Use PIOQUEUE mode for transfer instead of DMA"); | |||
75 | MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \ | 71 | MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \ |
76 | MXS_I2C_CTRL1_SLAVE_IRQ) | 72 | MXS_I2C_CTRL1_SLAVE_IRQ) |
77 | 73 | ||
78 | #define MXS_I2C_QUEUECTRL (0x60) | ||
79 | #define MXS_I2C_QUEUECTRL_SET (0x64) | ||
80 | #define MXS_I2C_QUEUECTRL_CLR (0x68) | ||
81 | |||
82 | #define MXS_I2C_QUEUECTRL_QUEUE_RUN 0x20 | ||
83 | #define MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE 0x04 | ||
84 | |||
85 | #define MXS_I2C_QUEUESTAT (0x70) | ||
86 | #define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000 | ||
87 | #define MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK 0x0000001F | ||
88 | |||
89 | #define MXS_I2C_QUEUECMD (0x80) | ||
90 | |||
91 | #define MXS_I2C_QUEUEDATA (0x90) | ||
92 | |||
93 | #define MXS_I2C_DATA (0xa0) | ||
94 | |||
95 | 74 | ||
96 | #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \ | 75 | #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \ |
97 | MXS_I2C_CTRL0_PRE_SEND_START | \ | 76 | MXS_I2C_CTRL0_PRE_SEND_START | \ |
@@ -153,7 +132,6 @@ struct mxs_i2c_dev { | |||
153 | const struct mxs_i2c_speed_config *speed; | 132 | const struct mxs_i2c_speed_config *speed; |
154 | 133 | ||
155 | /* DMA support components */ | 134 | /* DMA support components */ |
156 | bool dma_mode; | ||
157 | int dma_channel; | 135 | int dma_channel; |
158 | struct dma_chan *dmach; | 136 | struct dma_chan *dmach; |
159 | struct mxs_dma_data dma_data; | 137 | struct mxs_dma_data dma_data; |
@@ -172,99 +150,6 @@ static void mxs_i2c_reset(struct mxs_i2c_dev *i2c) | |||
172 | writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2); | 150 | writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2); |
173 | 151 | ||
174 | writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); | 152 | writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); |
175 | if (i2c->dma_mode) | ||
176 | writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE, | ||
177 | i2c->regs + MXS_I2C_QUEUECTRL_CLR); | ||
178 | else | ||
179 | writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE, | ||
180 | i2c->regs + MXS_I2C_QUEUECTRL_SET); | ||
181 | } | ||
182 | |||
183 | static void mxs_i2c_pioq_setup_read(struct mxs_i2c_dev *i2c, u8 addr, int len, | ||
184 | int flags) | ||
185 | { | ||
186 | u32 data; | ||
187 | |||
188 | writel(MXS_CMD_I2C_SELECT, i2c->regs + MXS_I2C_QUEUECMD); | ||
189 | |||
190 | data = (addr << 1) | I2C_SMBUS_READ; | ||
191 | writel(data, i2c->regs + MXS_I2C_DATA); | ||
192 | |||
193 | data = MXS_CMD_I2C_READ | MXS_I2C_CTRL0_XFER_COUNT(len) | flags; | ||
194 | writel(data, i2c->regs + MXS_I2C_QUEUECMD); | ||
195 | } | ||
196 | |||
197 | static void mxs_i2c_pioq_setup_write(struct mxs_i2c_dev *i2c, | ||
198 | u8 addr, u8 *buf, int len, int flags) | ||
199 | { | ||
200 | u32 data; | ||
201 | int i, shifts_left; | ||
202 | |||
203 | data = MXS_CMD_I2C_WRITE | MXS_I2C_CTRL0_XFER_COUNT(len + 1) | flags; | ||
204 | writel(data, i2c->regs + MXS_I2C_QUEUECMD); | ||
205 | |||
206 | /* | ||
207 | * We have to copy the slave address (u8) and buffer (arbitrary number | ||
208 | * of u8) into the data register (u32). To achieve that, the u8 are put | ||
209 | * into the MSBs of 'data' which is then shifted for the next u8. When | ||
210 | * appropriate, 'data' is written to MXS_I2C_DATA. So, the first u32 | ||
211 | * looks like this: | ||
212 | * | ||
213 | * 3 2 1 0 | ||
214 | * 10987654|32109876|54321098|76543210 | ||
215 | * --------+--------+--------+-------- | ||
216 | * buffer+2|buffer+1|buffer+0|slave_addr | ||
217 | */ | ||
218 | |||
219 | data = ((addr << 1) | I2C_SMBUS_WRITE) << 24; | ||
220 | |||
221 | for (i = 0; i < len; i++) { | ||
222 | data >>= 8; | ||
223 | data |= buf[i] << 24; | ||
224 | if ((i & 3) == 2) | ||
225 | writel(data, i2c->regs + MXS_I2C_DATA); | ||
226 | } | ||
227 | |||
228 | /* Write out the remaining bytes if any */ | ||
229 | shifts_left = 24 - (i & 3) * 8; | ||
230 | if (shifts_left) | ||
231 | writel(data >> shifts_left, i2c->regs + MXS_I2C_DATA); | ||
232 | } | ||
233 | |||
234 | /* | ||
235 | * TODO: should be replaceable with a waitqueue and RD_QUEUE_IRQ (setting the | ||
236 | * rd_threshold to 1). Couldn't get this to work, though. | ||
237 | */ | ||
238 | static int mxs_i2c_wait_for_data(struct mxs_i2c_dev *i2c) | ||
239 | { | ||
240 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); | ||
241 | |||
242 | while (readl(i2c->regs + MXS_I2C_QUEUESTAT) | ||
243 | & MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY) { | ||
244 | if (time_after(jiffies, timeout)) | ||
245 | return -ETIMEDOUT; | ||
246 | cond_resched(); | ||
247 | } | ||
248 | |||
249 | return 0; | ||
250 | } | ||
251 | |||
252 | static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len) | ||
253 | { | ||
254 | u32 uninitialized_var(data); | ||
255 | int i; | ||
256 | |||
257 | for (i = 0; i < len; i++) { | ||
258 | if ((i & 3) == 0) { | ||
259 | if (mxs_i2c_wait_for_data(i2c)) | ||
260 | return -ETIMEDOUT; | ||
261 | data = readl(i2c->regs + MXS_I2C_QUEUEDATA); | ||
262 | } | ||
263 | buf[i] = data & 0xff; | ||
264 | data >>= 8; | ||
265 | } | ||
266 | |||
267 | return 0; | ||
268 | } | 153 | } |
269 | 154 | ||
270 | static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c) | 155 | static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c) |
@@ -432,39 +317,17 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, | |||
432 | init_completion(&i2c->cmd_complete); | 317 | init_completion(&i2c->cmd_complete); |
433 | i2c->cmd_err = 0; | 318 | i2c->cmd_err = 0; |
434 | 319 | ||
435 | if (i2c->dma_mode) { | 320 | ret = mxs_i2c_dma_setup_xfer(adap, msg, flags); |
436 | ret = mxs_i2c_dma_setup_xfer(adap, msg, flags); | 321 | if (ret) |
437 | if (ret) | 322 | return ret; |
438 | return ret; | ||
439 | } else { | ||
440 | if (msg->flags & I2C_M_RD) { | ||
441 | mxs_i2c_pioq_setup_read(i2c, msg->addr, | ||
442 | msg->len, flags); | ||
443 | } else { | ||
444 | mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, | ||
445 | msg->len, flags); | ||
446 | } | ||
447 | |||
448 | writel(MXS_I2C_QUEUECTRL_QUEUE_RUN, | ||
449 | i2c->regs + MXS_I2C_QUEUECTRL_SET); | ||
450 | } | ||
451 | 323 | ||
452 | ret = wait_for_completion_timeout(&i2c->cmd_complete, | 324 | ret = wait_for_completion_timeout(&i2c->cmd_complete, |
453 | msecs_to_jiffies(1000)); | 325 | msecs_to_jiffies(1000)); |
454 | if (ret == 0) | 326 | if (ret == 0) |
455 | goto timeout; | 327 | goto timeout; |
456 | 328 | ||
457 | if (!i2c->dma_mode && !i2c->cmd_err && (msg->flags & I2C_M_RD)) { | ||
458 | ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len); | ||
459 | if (ret) | ||
460 | goto timeout; | ||
461 | } | ||
462 | |||
463 | if (i2c->cmd_err == -ENXIO) | 329 | if (i2c->cmd_err == -ENXIO) |
464 | mxs_i2c_reset(i2c); | 330 | mxs_i2c_reset(i2c); |
465 | else | ||
466 | writel(MXS_I2C_QUEUECTRL_QUEUE_RUN, | ||
467 | i2c->regs + MXS_I2C_QUEUECTRL_CLR); | ||
468 | 331 | ||
469 | dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err); | 332 | dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err); |
470 | 333 | ||
@@ -472,8 +335,7 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, | |||
472 | 335 | ||
473 | timeout: | 336 | timeout: |
474 | dev_dbg(i2c->dev, "Timeout!\n"); | 337 | dev_dbg(i2c->dev, "Timeout!\n"); |
475 | if (i2c->dma_mode) | 338 | mxs_i2c_dma_finish(i2c); |
476 | mxs_i2c_dma_finish(i2c); | ||
477 | mxs_i2c_reset(i2c); | 339 | mxs_i2c_reset(i2c); |
478 | return -ETIMEDOUT; | 340 | return -ETIMEDOUT; |
479 | } | 341 | } |
@@ -502,7 +364,6 @@ static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id) | |||
502 | { | 364 | { |
503 | struct mxs_i2c_dev *i2c = dev_id; | 365 | struct mxs_i2c_dev *i2c = dev_id; |
504 | u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK; | 366 | u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK; |
505 | bool is_last_cmd; | ||
506 | 367 | ||
507 | if (!stat) | 368 | if (!stat) |
508 | return IRQ_NONE; | 369 | return IRQ_NONE; |
@@ -515,14 +376,6 @@ static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id) | |||
515 | /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */ | 376 | /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */ |
516 | i2c->cmd_err = -EIO; | 377 | i2c->cmd_err = -EIO; |
517 | 378 | ||
518 | if (!i2c->dma_mode) { | ||
519 | is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) & | ||
520 | MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0; | ||
521 | |||
522 | if (is_last_cmd || i2c->cmd_err) | ||
523 | complete(&i2c->cmd_complete); | ||
524 | } | ||
525 | |||
526 | writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR); | 379 | writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR); |
527 | 380 | ||
528 | return IRQ_HANDLED; | 381 | return IRQ_HANDLED; |
@@ -556,23 +409,14 @@ static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c) | |||
556 | int ret; | 409 | int ret; |
557 | 410 | ||
558 | /* | 411 | /* |
559 | * The MXS I2C DMA mode is prefered and enabled by default. | ||
560 | * The PIO mode is still supported, but should be used only | ||
561 | * for debuging purposes etc. | ||
562 | */ | ||
563 | i2c->dma_mode = !use_pioqueue; | ||
564 | if (!i2c->dma_mode) | ||
565 | dev_info(dev, "Using PIOQUEUE mode for I2C transfers!\n"); | ||
566 | |||
567 | /* | ||
568 | * TODO: This is a temporary solution and should be changed | 412 | * TODO: This is a temporary solution and should be changed |
569 | * to use generic DMA binding later when the helpers get in. | 413 | * to use generic DMA binding later when the helpers get in. |
570 | */ | 414 | */ |
571 | ret = of_property_read_u32(node, "fsl,i2c-dma-channel", | 415 | ret = of_property_read_u32(node, "fsl,i2c-dma-channel", |
572 | &i2c->dma_channel); | 416 | &i2c->dma_channel); |
573 | if (ret) { | 417 | if (ret) { |
574 | dev_warn(dev, "Failed to get DMA channel, using PIOQUEUE!\n"); | 418 | dev_err(dev, "Failed to get DMA channel!\n"); |
575 | i2c->dma_mode = 0; | 419 | return -ENODEV; |
576 | } | 420 | } |
577 | 421 | ||
578 | ret = of_property_read_u32(node, "clock-frequency", &speed); | 422 | ret = of_property_read_u32(node, "clock-frequency", &speed); |
@@ -634,15 +478,13 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev) | |||
634 | } | 478 | } |
635 | 479 | ||
636 | /* Setup the DMA */ | 480 | /* Setup the DMA */ |
637 | if (i2c->dma_mode) { | 481 | dma_cap_zero(mask); |
638 | dma_cap_zero(mask); | 482 | dma_cap_set(DMA_SLAVE, mask); |
639 | dma_cap_set(DMA_SLAVE, mask); | 483 | i2c->dma_data.chan_irq = dmairq; |
640 | i2c->dma_data.chan_irq = dmairq; | 484 | i2c->dmach = dma_request_channel(mask, mxs_i2c_dma_filter, i2c); |
641 | i2c->dmach = dma_request_channel(mask, mxs_i2c_dma_filter, i2c); | 485 | if (!i2c->dmach) { |
642 | if (!i2c->dmach) { | 486 | dev_err(dev, "Failed to request dma\n"); |
643 | dev_err(dev, "Failed to request dma\n"); | 487 | return -ENODEV; |
644 | return -ENODEV; | ||
645 | } | ||
646 | } | 488 | } |
647 | 489 | ||
648 | platform_set_drvdata(pdev, i2c); | 490 | platform_set_drvdata(pdev, i2c); |