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-rw-r--r--drivers/i2c/busses/i2c-bfin-twi.c475
1 files changed, 295 insertions, 180 deletions
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c
index 7dbdaeb707a9..48d084bdf7c8 100644
--- a/drivers/i2c/busses/i2c-bfin-twi.c
+++ b/drivers/i2c/busses/i2c-bfin-twi.c
@@ -1,25 +1,11 @@
1/* 1/*
2 * drivers/i2c/busses/i2c-bfin-twi.c 2 * Blackfin On-Chip Two Wire Interface Driver
3 * 3 *
4 * Description: Driver for Blackfin Two Wire Interface 4 * Copyright 2005-2007 Analog Devices Inc.
5 * 5 *
6 * Author: sonicz <sonic.zhang@analog.com> 6 * Enter bugs at http://blackfin.uclinux.org/
7 * 7 *
8 * Copyright (c) 2005-2007 Analog Devices, Inc. 8 * Licensed under the GPL-2 or later.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */ 9 */
24 10
25#include <linux/module.h> 11#include <linux/module.h>
@@ -34,14 +20,16 @@
34#include <linux/platform_device.h> 20#include <linux/platform_device.h>
35 21
36#include <asm/blackfin.h> 22#include <asm/blackfin.h>
23#include <asm/portmux.h>
37#include <asm/irq.h> 24#include <asm/irq.h>
38 25
39#define POLL_TIMEOUT (2 * HZ) 26#define POLL_TIMEOUT (2 * HZ)
40 27
41/* SMBus mode*/ 28/* SMBus mode*/
42#define TWI_I2C_MODE_STANDARD 0x01 29#define TWI_I2C_MODE_STANDARD 1
43#define TWI_I2C_MODE_STANDARDSUB 0x02 30#define TWI_I2C_MODE_STANDARDSUB 2
44#define TWI_I2C_MODE_COMBINED 0x04 31#define TWI_I2C_MODE_COMBINED 3
32#define TWI_I2C_MODE_REPEAT 4
45 33
46struct bfin_twi_iface { 34struct bfin_twi_iface {
47 int irq; 35 int irq;
@@ -58,39 +46,74 @@ struct bfin_twi_iface {
58 struct timer_list timeout_timer; 46 struct timer_list timeout_timer;
59 struct i2c_adapter adap; 47 struct i2c_adapter adap;
60 struct completion complete; 48 struct completion complete;
49 struct i2c_msg *pmsg;
50 int msg_num;
51 int cur_msg;
52 void __iomem *regs_base;
61}; 53};
62 54
63static struct bfin_twi_iface twi_iface; 55
56#define DEFINE_TWI_REG(reg, off) \
57static inline u16 read_##reg(struct bfin_twi_iface *iface) \
58 { return bfin_read16(iface->regs_base + (off)); } \
59static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
60 { bfin_write16(iface->regs_base + (off), v); }
61
62DEFINE_TWI_REG(CLKDIV, 0x00)
63DEFINE_TWI_REG(CONTROL, 0x04)
64DEFINE_TWI_REG(SLAVE_CTL, 0x08)
65DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
66DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
67DEFINE_TWI_REG(MASTER_CTL, 0x14)
68DEFINE_TWI_REG(MASTER_STAT, 0x18)
69DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
70DEFINE_TWI_REG(INT_STAT, 0x20)
71DEFINE_TWI_REG(INT_MASK, 0x24)
72DEFINE_TWI_REG(FIFO_CTL, 0x28)
73DEFINE_TWI_REG(FIFO_STAT, 0x2C)
74DEFINE_TWI_REG(XMT_DATA8, 0x80)
75DEFINE_TWI_REG(XMT_DATA16, 0x84)
76DEFINE_TWI_REG(RCV_DATA8, 0x88)
77DEFINE_TWI_REG(RCV_DATA16, 0x8C)
78
79static const u16 pin_req[2][3] = {
80 {P_TWI0_SCL, P_TWI0_SDA, 0},
81 {P_TWI1_SCL, P_TWI1_SDA, 0},
82};
64 83
65static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface) 84static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
66{ 85{
67 unsigned short twi_int_status = bfin_read_TWI_INT_STAT(); 86 unsigned short twi_int_status = read_INT_STAT(iface);
68 unsigned short mast_stat = bfin_read_TWI_MASTER_STAT(); 87 unsigned short mast_stat = read_MASTER_STAT(iface);
69 88
70 if (twi_int_status & XMTSERV) { 89 if (twi_int_status & XMTSERV) {
71 /* Transmit next data */ 90 /* Transmit next data */
72 if (iface->writeNum > 0) { 91 if (iface->writeNum > 0) {
73 bfin_write_TWI_XMT_DATA8(*(iface->transPtr++)); 92 write_XMT_DATA8(iface, *(iface->transPtr++));
74 iface->writeNum--; 93 iface->writeNum--;
75 } 94 }
76 /* start receive immediately after complete sending in 95 /* start receive immediately after complete sending in
77 * combine mode. 96 * combine mode.
78 */ 97 */
79 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { 98 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
80 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() 99 write_MASTER_CTL(iface,
81 | MDIR | RSTART); 100 read_MASTER_CTL(iface) | MDIR | RSTART);
82 } else if (iface->manual_stop) 101 else if (iface->manual_stop)
83 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() 102 write_MASTER_CTL(iface,
84 | STOP); 103 read_MASTER_CTL(iface) | STOP);
104 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
105 iface->cur_msg+1 < iface->msg_num)
106 write_MASTER_CTL(iface,
107 read_MASTER_CTL(iface) | RSTART);
85 SSYNC(); 108 SSYNC();
86 /* Clear status */ 109 /* Clear status */
87 bfin_write_TWI_INT_STAT(XMTSERV); 110 write_INT_STAT(iface, XMTSERV);
88 SSYNC(); 111 SSYNC();
89 } 112 }
90 if (twi_int_status & RCVSERV) { 113 if (twi_int_status & RCVSERV) {
91 if (iface->readNum > 0) { 114 if (iface->readNum > 0) {
92 /* Receive next data */ 115 /* Receive next data */
93 *(iface->transPtr) = bfin_read_TWI_RCV_DATA8(); 116 *(iface->transPtr) = read_RCV_DATA8(iface);
94 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { 117 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
95 /* Change combine mode into sub mode after 118 /* Change combine mode into sub mode after
96 * read first data. 119 * read first data.
@@ -105,28 +128,33 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
105 iface->transPtr++; 128 iface->transPtr++;
106 iface->readNum--; 129 iface->readNum--;
107 } else if (iface->manual_stop) { 130 } else if (iface->manual_stop) {
108 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() 131 write_MASTER_CTL(iface,
109 | STOP); 132 read_MASTER_CTL(iface) | STOP);
133 SSYNC();
134 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
135 iface->cur_msg+1 < iface->msg_num) {
136 write_MASTER_CTL(iface,
137 read_MASTER_CTL(iface) | RSTART);
110 SSYNC(); 138 SSYNC();
111 } 139 }
112 /* Clear interrupt source */ 140 /* Clear interrupt source */
113 bfin_write_TWI_INT_STAT(RCVSERV); 141 write_INT_STAT(iface, RCVSERV);
114 SSYNC(); 142 SSYNC();
115 } 143 }
116 if (twi_int_status & MERR) { 144 if (twi_int_status & MERR) {
117 bfin_write_TWI_INT_STAT(MERR); 145 write_INT_STAT(iface, MERR);
118 bfin_write_TWI_INT_MASK(0); 146 write_INT_MASK(iface, 0);
119 bfin_write_TWI_MASTER_STAT(0x3e); 147 write_MASTER_STAT(iface, 0x3e);
120 bfin_write_TWI_MASTER_CTL(0); 148 write_MASTER_CTL(iface, 0);
121 SSYNC(); 149 SSYNC();
122 iface->result = -1; 150 iface->result = -EIO;
123 /* if both err and complete int stats are set, return proper 151 /* if both err and complete int stats are set, return proper
124 * results. 152 * results.
125 */ 153 */
126 if (twi_int_status & MCOMP) { 154 if (twi_int_status & MCOMP) {
127 bfin_write_TWI_INT_STAT(MCOMP); 155 write_INT_STAT(iface, MCOMP);
128 bfin_write_TWI_INT_MASK(0); 156 write_INT_MASK(iface, 0);
129 bfin_write_TWI_MASTER_CTL(0); 157 write_MASTER_CTL(iface, 0);
130 SSYNC(); 158 SSYNC();
131 /* If it is a quick transfer, only address bug no data, 159 /* If it is a quick transfer, only address bug no data,
132 * not an err, return 1. 160 * not an err, return 1.
@@ -143,7 +171,7 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
143 return; 171 return;
144 } 172 }
145 if (twi_int_status & MCOMP) { 173 if (twi_int_status & MCOMP) {
146 bfin_write_TWI_INT_STAT(MCOMP); 174 write_INT_STAT(iface, MCOMP);
147 SSYNC(); 175 SSYNC();
148 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { 176 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
149 if (iface->readNum == 0) { 177 if (iface->readNum == 0) {
@@ -152,28 +180,63 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
152 */ 180 */
153 iface->readNum = 1; 181 iface->readNum = 1;
154 iface->manual_stop = 1; 182 iface->manual_stop = 1;
155 bfin_write_TWI_MASTER_CTL( 183 write_MASTER_CTL(iface,
156 bfin_read_TWI_MASTER_CTL() 184 read_MASTER_CTL(iface) | (0xff << 6));
157 | (0xff << 6));
158 } else { 185 } else {
159 /* set the readd number in other 186 /* set the readd number in other
160 * combine mode. 187 * combine mode.
161 */ 188 */
162 bfin_write_TWI_MASTER_CTL( 189 write_MASTER_CTL(iface,
163 (bfin_read_TWI_MASTER_CTL() & 190 (read_MASTER_CTL(iface) &
164 (~(0xff << 6))) | 191 (~(0xff << 6))) |
165 ( iface->readNum << 6)); 192 (iface->readNum << 6));
193 }
194 /* remove restart bit and enable master receive */
195 write_MASTER_CTL(iface,
196 read_MASTER_CTL(iface) & ~RSTART);
197 write_MASTER_CTL(iface,
198 read_MASTER_CTL(iface) | MEN | MDIR);
199 SSYNC();
200 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
201 iface->cur_msg+1 < iface->msg_num) {
202 iface->cur_msg++;
203 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
204 iface->writeNum = iface->readNum =
205 iface->pmsg[iface->cur_msg].len;
206 /* Set Transmit device address */
207 write_MASTER_ADDR(iface,
208 iface->pmsg[iface->cur_msg].addr);
209 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
210 iface->read_write = I2C_SMBUS_READ;
211 else {
212 iface->read_write = I2C_SMBUS_WRITE;
213 /* Transmit first data */
214 if (iface->writeNum > 0) {
215 write_XMT_DATA8(iface,
216 *(iface->transPtr++));
217 iface->writeNum--;
218 SSYNC();
219 }
220 }
221
222 if (iface->pmsg[iface->cur_msg].len <= 255)
223 write_MASTER_CTL(iface,
224 iface->pmsg[iface->cur_msg].len << 6);
225 else {
226 write_MASTER_CTL(iface, 0xff << 6);
227 iface->manual_stop = 1;
166 } 228 }
167 /* remove restart bit and enable master receive */ 229 /* remove restart bit and enable master receive */
168 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() & 230 write_MASTER_CTL(iface,
169 ~RSTART); 231 read_MASTER_CTL(iface) & ~RSTART);
170 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | 232 write_MASTER_CTL(iface, read_MASTER_CTL(iface) |
171 MEN | MDIR); 233 MEN | ((iface->read_write == I2C_SMBUS_READ) ?
234 MDIR : 0));
172 SSYNC(); 235 SSYNC();
173 } else { 236 } else {
174 iface->result = 1; 237 iface->result = 1;
175 bfin_write_TWI_INT_MASK(0); 238 write_INT_MASK(iface, 0);
176 bfin_write_TWI_MASTER_CTL(0); 239 write_MASTER_CTL(iface, 0);
177 SSYNC(); 240 SSYNC();
178 complete(&iface->complete); 241 complete(&iface->complete);
179 } 242 }
@@ -221,91 +284,85 @@ static int bfin_twi_master_xfer(struct i2c_adapter *adap,
221{ 284{
222 struct bfin_twi_iface *iface = adap->algo_data; 285 struct bfin_twi_iface *iface = adap->algo_data;
223 struct i2c_msg *pmsg; 286 struct i2c_msg *pmsg;
224 int i, ret;
225 int rc = 0; 287 int rc = 0;
226 288
227 if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) 289 if (!(read_CONTROL(iface) & TWI_ENA))
228 return -ENXIO; 290 return -ENXIO;
229 291
230 while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) { 292 while (read_MASTER_STAT(iface) & BUSBUSY)
231 yield(); 293 yield();
294
295 iface->pmsg = msgs;
296 iface->msg_num = num;
297 iface->cur_msg = 0;
298
299 pmsg = &msgs[0];
300 if (pmsg->flags & I2C_M_TEN) {
301 dev_err(&adap->dev, "10 bits addr not supported!\n");
302 return -EINVAL;
232 } 303 }
233 304
234 ret = 0; 305 iface->cur_mode = TWI_I2C_MODE_REPEAT;
235 for (i = 0; rc >= 0 && i < num; i++) { 306 iface->manual_stop = 0;
236 pmsg = &msgs[i]; 307 iface->transPtr = pmsg->buf;
237 if (pmsg->flags & I2C_M_TEN) { 308 iface->writeNum = iface->readNum = pmsg->len;
238 dev_err(&(adap->dev), "i2c-bfin-twi: 10 bits addr " 309 iface->result = 0;
239 "not supported !\n"); 310 iface->timeout_count = 10;
240 rc = -EINVAL; 311 init_completion(&(iface->complete));
241 break; 312 /* Set Transmit device address */
242 } 313 write_MASTER_ADDR(iface, pmsg->addr);
243 314
244 iface->cur_mode = TWI_I2C_MODE_STANDARD; 315 /* FIFO Initiation. Data in FIFO should be
245 iface->manual_stop = 0; 316 * discarded before start a new operation.
246 iface->transPtr = pmsg->buf; 317 */
247 iface->writeNum = iface->readNum = pmsg->len; 318 write_FIFO_CTL(iface, 0x3);
248 iface->result = 0; 319 SSYNC();
249 iface->timeout_count = 10; 320 write_FIFO_CTL(iface, 0);
250 /* Set Transmit device address */ 321 SSYNC();
251 bfin_write_TWI_MASTER_ADDR(pmsg->addr);
252
253 /* FIFO Initiation. Data in FIFO should be
254 * discarded before start a new operation.
255 */
256 bfin_write_TWI_FIFO_CTL(0x3);
257 SSYNC();
258 bfin_write_TWI_FIFO_CTL(0);
259 SSYNC();
260 322
261 if (pmsg->flags & I2C_M_RD) 323 if (pmsg->flags & I2C_M_RD)
262 iface->read_write = I2C_SMBUS_READ; 324 iface->read_write = I2C_SMBUS_READ;
263 else { 325 else {
264 iface->read_write = I2C_SMBUS_WRITE; 326 iface->read_write = I2C_SMBUS_WRITE;
265 /* Transmit first data */ 327 /* Transmit first data */
266 if (iface->writeNum > 0) { 328 if (iface->writeNum > 0) {
267 bfin_write_TWI_XMT_DATA8(*(iface->transPtr++)); 329 write_XMT_DATA8(iface, *(iface->transPtr++));
268 iface->writeNum--; 330 iface->writeNum--;
269 SSYNC(); 331 SSYNC();
270 }
271 } 332 }
333 }
272 334
273 /* clear int stat */ 335 /* clear int stat */
274 bfin_write_TWI_INT_STAT(MERR|MCOMP|XMTSERV|RCVSERV); 336 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
275 337
276 /* Interrupt mask . Enable XMT, RCV interrupt */ 338 /* Interrupt mask . Enable XMT, RCV interrupt */
277 bfin_write_TWI_INT_MASK(MCOMP | MERR | 339 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
278 ((iface->read_write == I2C_SMBUS_READ)? 340 SSYNC();
279 RCVSERV : XMTSERV));
280 SSYNC();
281 341
282 if (pmsg->len > 0 && pmsg->len <= 255) 342 if (pmsg->len <= 255)
283 bfin_write_TWI_MASTER_CTL(pmsg->len << 6); 343 write_MASTER_CTL(iface, pmsg->len << 6);
284 else if (pmsg->len > 255) { 344 else {
285 bfin_write_TWI_MASTER_CTL(0xff << 6); 345 write_MASTER_CTL(iface, 0xff << 6);
286 iface->manual_stop = 1; 346 iface->manual_stop = 1;
287 } else 347 }
288 break;
289 348
290 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT; 349 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
291 add_timer(&iface->timeout_timer); 350 add_timer(&iface->timeout_timer);
292 351
293 /* Master enable */ 352 /* Master enable */
294 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | 353 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
295 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | 354 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
296 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); 355 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
297 SSYNC(); 356 SSYNC();
298 357
299 wait_for_completion(&iface->complete); 358 wait_for_completion(&iface->complete);
300 359
301 rc = iface->result; 360 rc = iface->result;
302 if (rc == 1)
303 ret++;
304 else if (rc == -1)
305 break;
306 }
307 361
308 return ret; 362 if (rc == 1)
363 return num;
364 else
365 return rc;
309} 366}
310 367
311/* 368/*
@@ -319,12 +376,11 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
319 struct bfin_twi_iface *iface = adap->algo_data; 376 struct bfin_twi_iface *iface = adap->algo_data;
320 int rc = 0; 377 int rc = 0;
321 378
322 if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) 379 if (!(read_CONTROL(iface) & TWI_ENA))
323 return -ENXIO; 380 return -ENXIO;
324 381
325 while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) { 382 while (read_MASTER_STAT(iface) & BUSBUSY)
326 yield(); 383 yield();
327 }
328 384
329 iface->writeNum = 0; 385 iface->writeNum = 0;
330 iface->readNum = 0; 386 iface->readNum = 0;
@@ -392,19 +448,20 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
392 iface->read_write = read_write; 448 iface->read_write = read_write;
393 iface->command = command; 449 iface->command = command;
394 iface->timeout_count = 10; 450 iface->timeout_count = 10;
451 init_completion(&(iface->complete));
395 452
396 /* FIFO Initiation. Data in FIFO should be discarded before 453 /* FIFO Initiation. Data in FIFO should be discarded before
397 * start a new operation. 454 * start a new operation.
398 */ 455 */
399 bfin_write_TWI_FIFO_CTL(0x3); 456 write_FIFO_CTL(iface, 0x3);
400 SSYNC(); 457 SSYNC();
401 bfin_write_TWI_FIFO_CTL(0); 458 write_FIFO_CTL(iface, 0);
402 459
403 /* clear int stat */ 460 /* clear int stat */
404 bfin_write_TWI_INT_STAT(MERR|MCOMP|XMTSERV|RCVSERV); 461 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
405 462
406 /* Set Transmit device address */ 463 /* Set Transmit device address */
407 bfin_write_TWI_MASTER_ADDR(addr); 464 write_MASTER_ADDR(iface, addr);
408 SSYNC(); 465 SSYNC();
409 466
410 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT; 467 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
@@ -412,60 +469,64 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
412 469
413 switch (iface->cur_mode) { 470 switch (iface->cur_mode) {
414 case TWI_I2C_MODE_STANDARDSUB: 471 case TWI_I2C_MODE_STANDARDSUB:
415 bfin_write_TWI_XMT_DATA8(iface->command); 472 write_XMT_DATA8(iface, iface->command);
416 bfin_write_TWI_INT_MASK(MCOMP | MERR | 473 write_INT_MASK(iface, MCOMP | MERR |
417 ((iface->read_write == I2C_SMBUS_READ) ? 474 ((iface->read_write == I2C_SMBUS_READ) ?
418 RCVSERV : XMTSERV)); 475 RCVSERV : XMTSERV));
419 SSYNC(); 476 SSYNC();
420 477
421 if (iface->writeNum + 1 <= 255) 478 if (iface->writeNum + 1 <= 255)
422 bfin_write_TWI_MASTER_CTL((iface->writeNum + 1) << 6); 479 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
423 else { 480 else {
424 bfin_write_TWI_MASTER_CTL(0xff << 6); 481 write_MASTER_CTL(iface, 0xff << 6);
425 iface->manual_stop = 1; 482 iface->manual_stop = 1;
426 } 483 }
427 /* Master enable */ 484 /* Master enable */
428 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | 485 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
429 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); 486 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
430 break; 487 break;
431 case TWI_I2C_MODE_COMBINED: 488 case TWI_I2C_MODE_COMBINED:
432 bfin_write_TWI_XMT_DATA8(iface->command); 489 write_XMT_DATA8(iface, iface->command);
433 bfin_write_TWI_INT_MASK(MCOMP | MERR | RCVSERV | XMTSERV); 490 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
434 SSYNC(); 491 SSYNC();
435 492
436 if (iface->writeNum > 0) 493 if (iface->writeNum > 0)
437 bfin_write_TWI_MASTER_CTL((iface->writeNum + 1) << 6); 494 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
438 else 495 else
439 bfin_write_TWI_MASTER_CTL(0x1 << 6); 496 write_MASTER_CTL(iface, 0x1 << 6);
440 /* Master enable */ 497 /* Master enable */
441 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | 498 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
442 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); 499 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
443 break; 500 break;
444 default: 501 default:
445 bfin_write_TWI_MASTER_CTL(0); 502 write_MASTER_CTL(iface, 0);
446 if (size != I2C_SMBUS_QUICK) { 503 if (size != I2C_SMBUS_QUICK) {
447 /* Don't access xmit data register when this is a 504 /* Don't access xmit data register when this is a
448 * read operation. 505 * read operation.
449 */ 506 */
450 if (iface->read_write != I2C_SMBUS_READ) { 507 if (iface->read_write != I2C_SMBUS_READ) {
451 if (iface->writeNum > 0) { 508 if (iface->writeNum > 0) {
452 bfin_write_TWI_XMT_DATA8(*(iface->transPtr++)); 509 write_XMT_DATA8(iface,
510 *(iface->transPtr++));
453 if (iface->writeNum <= 255) 511 if (iface->writeNum <= 255)
454 bfin_write_TWI_MASTER_CTL(iface->writeNum << 6); 512 write_MASTER_CTL(iface,
513 iface->writeNum << 6);
455 else { 514 else {
456 bfin_write_TWI_MASTER_CTL(0xff << 6); 515 write_MASTER_CTL(iface,
516 0xff << 6);
457 iface->manual_stop = 1; 517 iface->manual_stop = 1;
458 } 518 }
459 iface->writeNum--; 519 iface->writeNum--;
460 } else { 520 } else {
461 bfin_write_TWI_XMT_DATA8(iface->command); 521 write_XMT_DATA8(iface, iface->command);
462 bfin_write_TWI_MASTER_CTL(1 << 6); 522 write_MASTER_CTL(iface, 1 << 6);
463 } 523 }
464 } else { 524 } else {
465 if (iface->readNum > 0 && iface->readNum <= 255) 525 if (iface->readNum > 0 && iface->readNum <= 255)
466 bfin_write_TWI_MASTER_CTL(iface->readNum << 6); 526 write_MASTER_CTL(iface,
527 iface->readNum << 6);
467 else if (iface->readNum > 255) { 528 else if (iface->readNum > 255) {
468 bfin_write_TWI_MASTER_CTL(0xff << 6); 529 write_MASTER_CTL(iface, 0xff << 6);
469 iface->manual_stop = 1; 530 iface->manual_stop = 1;
470 } else { 531 } else {
471 del_timer(&iface->timeout_timer); 532 del_timer(&iface->timeout_timer);
@@ -473,13 +534,13 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
473 } 534 }
474 } 535 }
475 } 536 }
476 bfin_write_TWI_INT_MASK(MCOMP | MERR | 537 write_INT_MASK(iface, MCOMP | MERR |
477 ((iface->read_write == I2C_SMBUS_READ) ? 538 ((iface->read_write == I2C_SMBUS_READ) ?
478 RCVSERV : XMTSERV)); 539 RCVSERV : XMTSERV));
479 SSYNC(); 540 SSYNC();
480 541
481 /* Master enable */ 542 /* Master enable */
482 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | 543 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
483 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | 544 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
484 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); 545 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
485 break; 546 break;
@@ -514,10 +575,10 @@ static struct i2c_algorithm bfin_twi_algorithm = {
514 575
515static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state) 576static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state)
516{ 577{
517/* struct bfin_twi_iface *iface = platform_get_drvdata(dev);*/ 578 struct bfin_twi_iface *iface = platform_get_drvdata(dev);
518 579
519 /* Disable TWI */ 580 /* Disable TWI */
520 bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() & ~TWI_ENA); 581 write_CONTROL(iface, read_CONTROL(iface) & ~TWI_ENA);
521 SSYNC(); 582 SSYNC();
522 583
523 return 0; 584 return 0;
@@ -525,24 +586,52 @@ static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state)
525 586
526static int i2c_bfin_twi_resume(struct platform_device *dev) 587static int i2c_bfin_twi_resume(struct platform_device *dev)
527{ 588{
528/* struct bfin_twi_iface *iface = platform_get_drvdata(dev);*/ 589 struct bfin_twi_iface *iface = platform_get_drvdata(dev);
529 590
530 /* Enable TWI */ 591 /* Enable TWI */
531 bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA); 592 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
532 SSYNC(); 593 SSYNC();
533 594
534 return 0; 595 return 0;
535} 596}
536 597
537static int i2c_bfin_twi_probe(struct platform_device *dev) 598static int i2c_bfin_twi_probe(struct platform_device *pdev)
538{ 599{
539 struct bfin_twi_iface *iface = &twi_iface; 600 struct bfin_twi_iface *iface;
540 struct i2c_adapter *p_adap; 601 struct i2c_adapter *p_adap;
602 struct resource *res;
541 int rc; 603 int rc;
542 604
605 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
606 if (!iface) {
607 dev_err(&pdev->dev, "Cannot allocate memory\n");
608 rc = -ENOMEM;
609 goto out_error_nomem;
610 }
611
543 spin_lock_init(&(iface->lock)); 612 spin_lock_init(&(iface->lock));
544 init_completion(&(iface->complete)); 613
545 iface->irq = IRQ_TWI; 614 /* Find and map our resources */
615 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
616 if (res == NULL) {
617 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
618 rc = -ENOENT;
619 goto out_error_get_res;
620 }
621
622 iface->regs_base = ioremap(res->start, res->end - res->start + 1);
623 if (iface->regs_base == NULL) {
624 dev_err(&pdev->dev, "Cannot map IO\n");
625 rc = -ENXIO;
626 goto out_error_ioremap;
627 }
628
629 iface->irq = platform_get_irq(pdev, 0);
630 if (iface->irq < 0) {
631 dev_err(&pdev->dev, "No IRQ specified\n");
632 rc = -ENOENT;
633 goto out_error_no_irq;
634 }
546 635
547 init_timer(&(iface->timeout_timer)); 636 init_timer(&(iface->timeout_timer));
548 iface->timeout_timer.function = bfin_twi_timeout; 637 iface->timeout_timer.function = bfin_twi_timeout;
@@ -550,39 +639,63 @@ static int i2c_bfin_twi_probe(struct platform_device *dev)
550 639
551 p_adap = &iface->adap; 640 p_adap = &iface->adap;
552 p_adap->id = I2C_HW_BLACKFIN; 641 p_adap->id = I2C_HW_BLACKFIN;
553 p_adap->nr = dev->id; 642 p_adap->nr = pdev->id;
554 strlcpy(p_adap->name, dev->name, sizeof(p_adap->name)); 643 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
555 p_adap->algo = &bfin_twi_algorithm; 644 p_adap->algo = &bfin_twi_algorithm;
556 p_adap->algo_data = iface; 645 p_adap->algo_data = iface;
557 p_adap->class = I2C_CLASS_ALL; 646 p_adap->class = I2C_CLASS_ALL;
558 p_adap->dev.parent = &dev->dev; 647 p_adap->dev.parent = &pdev->dev;
648
649 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
650 if (rc) {
651 dev_err(&pdev->dev, "Can't setup pin mux!\n");
652 goto out_error_pin_mux;
653 }
559 654
560 rc = request_irq(iface->irq, bfin_twi_interrupt_entry, 655 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
561 IRQF_DISABLED, dev->name, iface); 656 IRQF_DISABLED, pdev->name, iface);
562 if (rc) { 657 if (rc) {
563 dev_err(&(p_adap->dev), "i2c-bfin-twi: can't get IRQ %d !\n", 658 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
564 iface->irq); 659 rc = -ENODEV;
565 return -ENODEV; 660 goto out_error_req_irq;
566 } 661 }
567 662
568 /* Set TWI internal clock as 10MHz */ 663 /* Set TWI internal clock as 10MHz */
569 bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F); 664 write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
570 665
571 /* Set Twi interface clock as specified */ 666 /* Set Twi interface clock as specified */
572 bfin_write_TWI_CLKDIV((( 5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ ) 667 write_CLKDIV(iface, ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
573 << 8) | (( 5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ ) 668 << 8) | ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
574 & 0xFF)); 669 & 0xFF));
575 670
576 /* Enable TWI */ 671 /* Enable TWI */
577 bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA); 672 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
578 SSYNC(); 673 SSYNC();
579 674
580 rc = i2c_add_numbered_adapter(p_adap); 675 rc = i2c_add_numbered_adapter(p_adap);
581 if (rc < 0) 676 if (rc < 0) {
582 free_irq(iface->irq, iface); 677 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
583 else 678 goto out_error_add_adapter;
584 platform_set_drvdata(dev, iface); 679 }
680
681 platform_set_drvdata(pdev, iface);
585 682
683 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
684 "regs_base@%p\n", iface->regs_base);
685
686 return 0;
687
688out_error_add_adapter:
689 free_irq(iface->irq, iface);
690out_error_req_irq:
691out_error_no_irq:
692 peripheral_free_list(pin_req[pdev->id]);
693out_error_pin_mux:
694 iounmap(iface->regs_base);
695out_error_ioremap:
696out_error_get_res:
697 kfree(iface);
698out_error_nomem:
586 return rc; 699 return rc;
587} 700}
588 701
@@ -594,6 +707,9 @@ static int i2c_bfin_twi_remove(struct platform_device *pdev)
594 707
595 i2c_del_adapter(&(iface->adap)); 708 i2c_del_adapter(&(iface->adap));
596 free_irq(iface->irq, iface); 709 free_irq(iface->irq, iface);
710 peripheral_free_list(pin_req[pdev->id]);
711 iounmap(iface->regs_base);
712 kfree(iface);
597 713
598 return 0; 714 return 0;
599} 715}
@@ -611,8 +727,6 @@ static struct platform_driver i2c_bfin_twi_driver = {
611 727
612static int __init i2c_bfin_twi_init(void) 728static int __init i2c_bfin_twi_init(void)
613{ 729{
614 pr_info("I2C: Blackfin I2C TWI driver\n");
615
616 return platform_driver_register(&i2c_bfin_twi_driver); 730 return platform_driver_register(&i2c_bfin_twi_driver);
617} 731}
618 732
@@ -621,9 +735,10 @@ static void __exit i2c_bfin_twi_exit(void)
621 platform_driver_unregister(&i2c_bfin_twi_driver); 735 platform_driver_unregister(&i2c_bfin_twi_driver);
622} 736}
623 737
624MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
625MODULE_DESCRIPTION("I2C-Bus adapter routines for Blackfin TWI");
626MODULE_LICENSE("GPL");
627
628module_init(i2c_bfin_twi_init); 738module_init(i2c_bfin_twi_init);
629module_exit(i2c_bfin_twi_exit); 739module_exit(i2c_bfin_twi_exit);
740
741MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
742MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
743MODULE_LICENSE("GPL");
744MODULE_ALIAS("platform:i2c-bfin-twi");
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-28 16:43:31 -0400