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-rw-r--r--drivers/i2c/algos/Kconfig11
-rw-r--r--drivers/i2c/algos/Makefile1
-rw-r--r--drivers/i2c/algos/i2c-algo-ite.c806
-rw-r--r--drivers/i2c/algos/i2c-algo-ite.h117
4 files changed, 0 insertions, 935 deletions
diff --git a/drivers/i2c/algos/Kconfig b/drivers/i2c/algos/Kconfig
index c034820615bb..af0203409dd1 100644
--- a/drivers/i2c/algos/Kconfig
+++ b/drivers/i2c/algos/Kconfig
@@ -38,17 +38,6 @@ config I2C_ALGOPCA
38 This support is also available as a module. If so, the module 38 This support is also available as a module. If so, the module
39 will be called i2c-algo-pca. 39 will be called i2c-algo-pca.
40 40
41config I2C_ALGOITE
42 tristate "ITE I2C Algorithm"
43 depends on MIPS_ITE8172 && I2C
44 help
45 This supports the use of the ITE8172 I2C interface found on some MIPS
46 systems. Say Y if you have one of these. You should also say Y for
47 the ITE I2C peripheral driver support below.
48
49 This support is also available as a module. If so, the module
50 will be called i2c-algo-ite.
51
52config I2C_ALGO8XX 41config I2C_ALGO8XX
53 tristate "MPC8xx CPM I2C interface" 42 tristate "MPC8xx CPM I2C interface"
54 depends on 8xx && I2C 43 depends on 8xx && I2C
diff --git a/drivers/i2c/algos/Makefile b/drivers/i2c/algos/Makefile
index 208be04a3dbd..cac1051bd4f1 100644
--- a/drivers/i2c/algos/Makefile
+++ b/drivers/i2c/algos/Makefile
@@ -5,7 +5,6 @@
5obj-$(CONFIG_I2C_ALGOBIT) += i2c-algo-bit.o 5obj-$(CONFIG_I2C_ALGOBIT) += i2c-algo-bit.o
6obj-$(CONFIG_I2C_ALGOPCF) += i2c-algo-pcf.o 6obj-$(CONFIG_I2C_ALGOPCF) += i2c-algo-pcf.o
7obj-$(CONFIG_I2C_ALGOPCA) += i2c-algo-pca.o 7obj-$(CONFIG_I2C_ALGOPCA) += i2c-algo-pca.o
8obj-$(CONFIG_I2C_ALGOITE) += i2c-algo-ite.o
9obj-$(CONFIG_I2C_ALGO_SGI) += i2c-algo-sgi.o 8obj-$(CONFIG_I2C_ALGO_SGI) += i2c-algo-sgi.o
10 9
11ifeq ($(CONFIG_I2C_DEBUG_ALGO),y) 10ifeq ($(CONFIG_I2C_DEBUG_ALGO),y)
diff --git a/drivers/i2c/algos/i2c-algo-ite.c b/drivers/i2c/algos/i2c-algo-ite.c
deleted file mode 100644
index 70d8eefb5efc..000000000000
--- a/drivers/i2c/algos/i2c-algo-ite.c
+++ /dev/null
@@ -1,806 +0,0 @@
1/*
2 -------------------------------------------------------------------------
3 i2c-algo-ite.c i2c driver algorithms for ITE adapters
4
5 Hai-Pao Fan, MontaVista Software, Inc.
6 hpfan@mvista.com or source@mvista.com
7
8 Copyright 2000 MontaVista Software Inc.
9
10 ---------------------------------------------------------------------------
11 This file was highly leveraged from i2c-algo-pcf.c, which was created
12 by Simon G. Vogl and Hans Berglund:
13
14
15 Copyright (C) 1995-1997 Simon G. Vogl
16 1998-2000 Hans Berglund
17
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; if not, write to the Free Software
30 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
31/* ------------------------------------------------------------------------- */
32
33/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and
34 Frodo Looijaard <frodol@dds.nl> ,and also from Martin Bailey
35 <mbailey@littlefeet-inc.com> */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/delay.h>
40#include <linux/slab.h>
41#include <linux/init.h>
42#include <asm/uaccess.h>
43#include <linux/ioport.h>
44#include <linux/errno.h>
45#include <linux/sched.h>
46
47#include <linux/i2c.h>
48#include <linux/i2c-algo-ite.h>
49#include "i2c-algo-ite.h"
50
51#define PM_DSR IT8172_PCI_IO_BASE + IT_PM_DSR
52#define PM_IBSR IT8172_PCI_IO_BASE + IT_PM_DSR + 0x04
53#define GPIO_CCR IT8172_PCI_IO_BASE + IT_GPCCR
54
55#define DEB2(x) if (i2c_debug>=2) x
56#define DEB3(x) if (i2c_debug>=3) x /* print several statistical values*/
57#define DEF_TIMEOUT 16
58
59
60/* module parameters:
61 */
62static int i2c_debug;
63static int iic_test; /* see if the line-setting functions work */
64
65/* --- setting states on the bus with the right timing: --------------- */
66
67#define get_clock(adap) adap->getclock(adap->data)
68#define iic_outw(adap, reg, val) adap->setiic(adap->data, reg, val)
69#define iic_inw(adap, reg) adap->getiic(adap->data, reg)
70
71
72/* --- other auxiliary functions -------------------------------------- */
73
74static void iic_start(struct i2c_algo_iic_data *adap)
75{
76 iic_outw(adap,ITE_I2CHCR,ITE_CMD);
77}
78
79static void iic_stop(struct i2c_algo_iic_data *adap)
80{
81 iic_outw(adap,ITE_I2CHCR,0);
82 iic_outw(adap,ITE_I2CHSR,ITE_I2CHSR_TDI);
83}
84
85static void iic_reset(struct i2c_algo_iic_data *adap)
86{
87 iic_outw(adap, PM_IBSR, iic_inw(adap, PM_IBSR) | 0x80);
88}
89
90
91static int wait_for_bb(struct i2c_algo_iic_data *adap)
92{
93 int timeout = DEF_TIMEOUT;
94 short status;
95
96 status = iic_inw(adap, ITE_I2CHSR);
97#ifndef STUB_I2C
98 while (timeout-- && (status & ITE_I2CHSR_HB)) {
99 udelay(1000); /* How much is this? */
100 status = iic_inw(adap, ITE_I2CHSR);
101 }
102#endif
103 if (timeout<=0) {
104 printk(KERN_ERR "Timeout, host is busy\n");
105 iic_reset(adap);
106 }
107 return(timeout<=0);
108}
109
110/* After we issue a transaction on the IIC bus, this function
111 * is called. It puts this process to sleep until we get an interrupt from
112 * from the controller telling us that the transaction we requested in complete.
113 */
114static int wait_for_pin(struct i2c_algo_iic_data *adap, short *status) {
115
116 int timeout = DEF_TIMEOUT;
117
118 timeout = wait_for_bb(adap);
119 if (timeout) {
120 DEB2(printk("Timeout waiting for host not busy\n");)
121 return -EIO;
122 }
123 timeout = DEF_TIMEOUT;
124
125 *status = iic_inw(adap, ITE_I2CHSR);
126#ifndef STUB_I2C
127 while (timeout-- && !(*status & ITE_I2CHSR_TDI)) {
128 adap->waitforpin();
129 *status = iic_inw(adap, ITE_I2CHSR);
130 }
131#endif
132 if (timeout <= 0)
133 return(-1);
134 else
135 return(0);
136}
137
138static int wait_for_fe(struct i2c_algo_iic_data *adap, short *status)
139{
140 int timeout = DEF_TIMEOUT;
141
142 *status = iic_inw(adap, ITE_I2CFSR);
143#ifndef STUB_I2C
144 while (timeout-- && (*status & ITE_I2CFSR_FE)) {
145 udelay(1000);
146 iic_inw(adap, ITE_I2CFSR);
147 }
148#endif
149 if (timeout <= 0)
150 return(-1);
151 else
152 return(0);
153}
154
155static int iic_init (struct i2c_algo_iic_data *adap)
156{
157 short i;
158
159 /* Clear bit 7 to set I2C to normal operation mode */
160 i=iic_inw(adap, PM_DSR)& 0xff7f;
161 iic_outw(adap, PM_DSR, i);
162
163 /* set IT_GPCCR port C bit 2&3 as function 2 */
164 i = iic_inw(adap, GPIO_CCR) & 0xfc0f;
165 iic_outw(adap,GPIO_CCR,i);
166
167 /* Clear slave address/sub-address */
168 iic_outw(adap,ITE_I2CSAR, 0);
169 iic_outw(adap,ITE_I2CSSAR, 0);
170
171 /* Set clock counter register */
172 iic_outw(adap,ITE_I2CCKCNT, get_clock(adap));
173
174 /* Set START/reSTART/STOP time registers */
175 iic_outw(adap,ITE_I2CSHDR, 0x0a);
176 iic_outw(adap,ITE_I2CRSUR, 0x0a);
177 iic_outw(adap,ITE_I2CPSUR, 0x0a);
178
179 /* Enable interrupts on completing the current transaction */
180 iic_outw(adap,ITE_I2CHCR, ITE_I2CHCR_IE | ITE_I2CHCR_HCE);
181
182 /* Clear transfer count */
183 iic_outw(adap,ITE_I2CFBCR, 0x0);
184
185 DEB2(printk("iic_init: Initialized IIC on ITE 0x%x\n",
186 iic_inw(adap, ITE_I2CHSR)));
187 return 0;
188}
189
190
191/*
192 * Sanity check for the adapter hardware - check the reaction of
193 * the bus lines only if it seems to be idle.
194 */
195static int test_bus(struct i2c_algo_iic_data *adap, char *name) {
196#if 0
197 int scl,sda;
198 sda=getsda(adap);
199 if (adap->getscl==NULL) {
200 printk("test_bus: Warning: Adapter can't read from clock line - skipping test.\n");
201 return 0;
202 }
203 scl=getscl(adap);
204 printk("test_bus: Adapter: %s scl: %d sda: %d -- testing...\n",
205 name,getscl(adap),getsda(adap));
206 if (!scl || !sda ) {
207 printk("test_bus: %s seems to be busy.\n",adap->name);
208 goto bailout;
209 }
210 sdalo(adap);
211 printk("test_bus:1 scl: %d sda: %d\n", getscl(adap),
212 getsda(adap));
213 if ( 0 != getsda(adap) ) {
214 printk("test_bus: %s SDA stuck high!\n",name);
215 sdahi(adap);
216 goto bailout;
217 }
218 if ( 0 == getscl(adap) ) {
219 printk("test_bus: %s SCL unexpected low while pulling SDA low!\n",
220 name);
221 goto bailout;
222 }
223 sdahi(adap);
224 printk("test_bus:2 scl: %d sda: %d\n", getscl(adap),
225 getsda(adap));
226 if ( 0 == getsda(adap) ) {
227 printk("test_bus: %s SDA stuck low!\n",name);
228 sdahi(adap);
229 goto bailout;
230 }
231 if ( 0 == getscl(adap) ) {
232 printk("test_bus: %s SCL unexpected low while SDA high!\n",
233 adap->name);
234 goto bailout;
235 }
236 scllo(adap);
237 printk("test_bus:3 scl: %d sda: %d\n", getscl(adap),
238 getsda(adap));
239 if ( 0 != getscl(adap) ) {
240
241 sclhi(adap);
242 goto bailout;
243 }
244 if ( 0 == getsda(adap) ) {
245 printk("test_bus: %s SDA unexpected low while pulling SCL low!\n",
246 name);
247 goto bailout;
248 }
249 sclhi(adap);
250 printk("test_bus:4 scl: %d sda: %d\n", getscl(adap),
251 getsda(adap));
252 if ( 0 == getscl(adap) ) {
253 printk("test_bus: %s SCL stuck low!\n",name);
254 sclhi(adap);
255 goto bailout;
256 }
257 if ( 0 == getsda(adap) ) {
258 printk("test_bus: %s SDA unexpected low while SCL high!\n",
259 name);
260 goto bailout;
261 }
262 printk("test_bus: %s passed test.\n",name);
263 return 0;
264bailout:
265 sdahi(adap);
266 sclhi(adap);
267 return -ENODEV;
268#endif
269 return (0);
270}
271
272/* ----- Utility functions
273 */
274
275
276/* Verify the device we want to talk to on the IIC bus really exists. */
277static inline int try_address(struct i2c_algo_iic_data *adap,
278 unsigned int addr, int retries)
279{
280 int i, ret = -1;
281 short status;
282
283 for (i=0;i<retries;i++) {
284 iic_outw(adap, ITE_I2CSAR, addr);
285 iic_start(adap);
286 if (wait_for_pin(adap, &status) == 0) {
287 if ((status & ITE_I2CHSR_DNE) == 0) {
288 iic_stop(adap);
289 iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH);
290 ret=1;
291 break; /* success! */
292 }
293 }
294 iic_stop(adap);
295 udelay(adap->udelay);
296 }
297 DEB2(if (i) printk("try_address: needed %d retries for 0x%x\n",i,
298 addr));
299 return ret;
300}
301
302
303static int iic_sendbytes(struct i2c_adapter *i2c_adap,const char *buf,
304 int count)
305{
306 struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
307 int wrcount=0, timeout;
308 short status;
309 int loops, remainder, i, j;
310 union {
311 char byte[2];
312 unsigned short word;
313 } tmp;
314
315 iic_outw(adap, ITE_I2CSSAR, (unsigned short)buf[wrcount++]);
316 count--;
317 if (count == 0)
318 return -EIO;
319
320 loops = count / 32; /* 32-byte FIFO */
321 remainder = count % 32;
322
323 if(loops) {
324 for(i=0; i<loops; i++) {
325
326 iic_outw(adap, ITE_I2CFBCR, 32);
327 for(j=0; j<32/2; j++) {
328 tmp.byte[1] = buf[wrcount++];
329 tmp.byte[0] = buf[wrcount++];
330 iic_outw(adap, ITE_I2CFDR, tmp.word);
331 }
332
333 /* status FIFO overrun */
334 iic_inw(adap, ITE_I2CFSR);
335 iic_inw(adap, ITE_I2CFBCR);
336
337 iic_outw(adap, ITE_I2CHCR, ITE_WRITE); /* Issue WRITE command */
338
339 /* Wait for transmission to complete */
340 timeout = wait_for_pin(adap, &status);
341 if(timeout) {
342 iic_stop(adap);
343 printk("iic_sendbytes: %s write timeout.\n", i2c_adap->name);
344 return -EREMOTEIO; /* got a better one ?? */
345 }
346 if (status & ITE_I2CHSR_DB) {
347 iic_stop(adap);
348 printk("iic_sendbytes: %s write error - no ack.\n", i2c_adap->name);
349 return -EREMOTEIO; /* got a better one ?? */
350 }
351 }
352 }
353 if(remainder) {
354 iic_outw(adap, ITE_I2CFBCR, remainder);
355 for(i=0; i<remainder/2; i++) {
356 tmp.byte[1] = buf[wrcount++];
357 tmp.byte[0] = buf[wrcount++];
358 iic_outw(adap, ITE_I2CFDR, tmp.word);
359 }
360
361 /* status FIFO overrun */
362 iic_inw(adap, ITE_I2CFSR);
363 iic_inw(adap, ITE_I2CFBCR);
364
365 iic_outw(adap, ITE_I2CHCR, ITE_WRITE); /* Issue WRITE command */
366
367 timeout = wait_for_pin(adap, &status);
368 if(timeout) {
369 iic_stop(adap);
370 printk("iic_sendbytes: %s write timeout.\n", i2c_adap->name);
371 return -EREMOTEIO; /* got a better one ?? */
372 }
373#ifndef STUB_I2C
374 if (status & ITE_I2CHSR_DB) {
375 iic_stop(adap);
376 printk("iic_sendbytes: %s write error - no ack.\n", i2c_adap->name);
377 return -EREMOTEIO; /* got a better one ?? */
378 }
379#endif
380 }
381 iic_stop(adap);
382 return wrcount;
383}
384
385
386static int iic_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count,
387 int sread)
388{
389 int rdcount=0, i, timeout;
390 short status;
391 struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
392 int loops, remainder, j;
393 union {
394 char byte[2];
395 unsigned short word;
396 } tmp;
397
398 loops = count / 32; /* 32-byte FIFO */
399 remainder = count % 32;
400
401 if(loops) {
402 for(i=0; i<loops; i++) {
403 iic_outw(adap, ITE_I2CFBCR, 32);
404 if (sread)
405 iic_outw(adap, ITE_I2CHCR, ITE_SREAD);
406 else
407 iic_outw(adap, ITE_I2CHCR, ITE_READ); /* Issue READ command */
408
409 timeout = wait_for_pin(adap, &status);
410 if(timeout) {
411 iic_stop(adap);
412 printk("iic_readbytes: %s read timeout.\n", i2c_adap->name);
413 return (-1);
414 }
415#ifndef STUB_I2C
416 if (status & ITE_I2CHSR_DB) {
417 iic_stop(adap);
418 printk("iic_readbytes: %s read error - no ack.\n", i2c_adap->name);
419 return (-1);
420 }
421#endif
422
423 timeout = wait_for_fe(adap, &status);
424 if(timeout) {
425 iic_stop(adap);
426 printk("iic_readbytes: %s FIFO is empty\n", i2c_adap->name);
427 return (-1);
428 }
429
430 for(j=0; j<32/2; j++) {
431 tmp.word = iic_inw(adap, ITE_I2CFDR);
432 buf[rdcount++] = tmp.byte[1];
433 buf[rdcount++] = tmp.byte[0];
434 }
435
436 /* status FIFO underrun */
437 iic_inw(adap, ITE_I2CFSR);
438
439 }
440 }
441
442
443 if(remainder) {
444 remainder=(remainder+1)/2 * 2;
445 iic_outw(adap, ITE_I2CFBCR, remainder);
446 if (sread)
447 iic_outw(adap, ITE_I2CHCR, ITE_SREAD);
448 else
449 iic_outw(adap, ITE_I2CHCR, ITE_READ); /* Issue READ command */
450
451 timeout = wait_for_pin(adap, &status);
452 if(timeout) {
453 iic_stop(adap);
454 printk("iic_readbytes: %s read timeout.\n", i2c_adap->name);
455 return (-1);
456 }
457#ifndef STUB_I2C
458 if (status & ITE_I2CHSR_DB) {
459 iic_stop(adap);
460 printk("iic_readbytes: %s read error - no ack.\n", i2c_adap->name);
461 return (-1);
462 }
463#endif
464 timeout = wait_for_fe(adap, &status);
465 if(timeout) {
466 iic_stop(adap);
467 printk("iic_readbytes: %s FIFO is empty\n", i2c_adap->name);
468 return (-1);
469 }
470
471 for(i=0; i<(remainder+1)/2; i++) {
472 tmp.word = iic_inw(adap, ITE_I2CFDR);
473 buf[rdcount++] = tmp.byte[1];
474 buf[rdcount++] = tmp.byte[0];
475 }
476
477 /* status FIFO underrun */
478 iic_inw(adap, ITE_I2CFSR);
479
480 }
481
482 iic_stop(adap);
483 return rdcount;
484}
485
486
487/* This function implements combined transactions. Combined
488 * transactions consist of combinations of reading and writing blocks of data.
489 * Each transfer (i.e. a read or a write) is separated by a repeated start
490 * condition.
491 */
492#if 0
493static int iic_combined_transaction(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
494{
495 int i;
496 struct i2c_msg *pmsg;
497 int ret;
498
499 DEB2(printk("Beginning combined transaction\n"));
500
501 for(i=0; i<(num-1); i++) {
502 pmsg = &msgs[i];
503 if(pmsg->flags & I2C_M_RD) {
504 DEB2(printk(" This one is a read\n"));
505 ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_COMBINED_XFER);
506 }
507 else if(!(pmsg->flags & I2C_M_RD)) {
508 DEB2(printk("This one is a write\n"));
509 ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_COMBINED_XFER);
510 }
511 }
512 /* Last read or write segment needs to be terminated with a stop */
513 pmsg = &msgs[i];
514
515 if(pmsg->flags & I2C_M_RD) {
516 DEB2(printk("Doing the last read\n"));
517 ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
518 }
519 else if(!(pmsg->flags & I2C_M_RD)) {
520 DEB2(printk("Doing the last write\n"));
521 ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
522 }
523
524 return ret;
525}
526#endif
527
528
529/* Whenever we initiate a transaction, the first byte clocked
530 * onto the bus after the start condition is the address (7 bit) of the
531 * device we want to talk to. This function manipulates the address specified
532 * so that it makes sense to the hardware when written to the IIC peripheral.
533 *
534 * Note: 10 bit addresses are not supported in this driver, although they are
535 * supported by the hardware. This functionality needs to be implemented.
536 */
537static inline int iic_doAddress(struct i2c_algo_iic_data *adap,
538 struct i2c_msg *msg, int retries)
539{
540 unsigned short flags = msg->flags;
541 unsigned int addr;
542 int ret;
543
544/* Ten bit addresses not supported right now */
545 if ( (flags & I2C_M_TEN) ) {
546#if 0
547 addr = 0xf0 | (( msg->addr >> 7) & 0x03);
548 DEB2(printk("addr0: %d\n",addr));
549 ret = try_address(adap, addr, retries);
550 if (ret!=1) {
551 printk("iic_doAddress: died at extended address code.\n");
552 return -EREMOTEIO;
553 }
554 iic_outw(adap,msg->addr & 0x7f);
555 if (ret != 1) {
556 printk("iic_doAddress: died at 2nd address code.\n");
557 return -EREMOTEIO;
558 }
559 if ( flags & I2C_M_RD ) {
560 i2c_repstart(adap);
561 addr |= 0x01;
562 ret = try_address(adap, addr, retries);
563 if (ret!=1) {
564 printk("iic_doAddress: died at extended address code.\n");
565 return -EREMOTEIO;
566 }
567 }
568#endif
569 } else {
570
571 addr = ( msg->addr << 1 );
572
573#if 0
574 if (flags & I2C_M_RD )
575 addr |= 1;
576 if (flags & I2C_M_REV_DIR_ADDR )
577 addr ^= 1;
578#endif
579
580 if (iic_inw(adap, ITE_I2CSAR) != addr) {
581 iic_outw(adap, ITE_I2CSAR, addr);
582 ret = try_address(adap, addr, retries);
583 if (ret!=1) {
584 printk("iic_doAddress: died at address code.\n");
585 return -EREMOTEIO;
586 }
587 }
588
589 }
590
591 return 0;
592}
593
594
595/* Description: Prepares the controller for a transaction (clearing status
596 * registers, data buffers, etc), and then calls either iic_readbytes or
597 * iic_sendbytes to do the actual transaction.
598 *
599 * still to be done: Before we issue a transaction, we should
600 * verify that the bus is not busy or in some unknown state.
601 */
602static int iic_xfer(struct i2c_adapter *i2c_adap,
603 struct i2c_msg *msgs,
604 int num)
605{
606 struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
607 struct i2c_msg *pmsg;
608 int i = 0;
609 int ret, timeout;
610
611 pmsg = &msgs[i];
612
613 if(!pmsg->len) {
614 DEB2(printk("iic_xfer: read/write length is 0\n");)
615 return -EIO;
616 }
617 if(!(pmsg->flags & I2C_M_RD) && (!(pmsg->len)%2) ) {
618 DEB2(printk("iic_xfer: write buffer length is not odd\n");)
619 return -EIO;
620 }
621
622 /* Wait for any pending transfers to complete */
623 timeout = wait_for_bb(adap);
624 if (timeout) {
625 DEB2(printk("iic_xfer: Timeout waiting for host not busy\n");)
626 return -EIO;
627 }
628
629 /* Flush FIFO */
630 iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH);
631
632 /* Load address */
633 ret = iic_doAddress(adap, pmsg, i2c_adap->retries);
634 if (ret)
635 return -EIO;
636
637#if 0
638 /* Combined transaction (read and write) */
639 if(num > 1) {
640 DEB2(printk("iic_xfer: Call combined transaction\n"));
641 ret = iic_combined_transaction(i2c_adap, msgs, num);
642 }
643#endif
644
645 DEB3(printk("iic_xfer: Msg %d, addr=0x%x, flags=0x%x, len=%d\n",
646 i, msgs[i].addr, msgs[i].flags, msgs[i].len);)
647
648 if(pmsg->flags & I2C_M_RD) /* Read */
649 ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, 0);
650 else { /* Write */
651 udelay(1000);
652 ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len);
653 }
654
655 if (ret != pmsg->len)
656 DEB3(printk("iic_xfer: error or fail on read/write %d bytes.\n",ret));
657 else
658 DEB3(printk("iic_xfer: read/write %d bytes.\n",ret));
659
660 return ret;
661}
662
663
664/* Implements device specific ioctls. Higher level ioctls can
665 * be found in i2c-core.c and are typical of any i2c controller (specifying
666 * slave address, timeouts, etc). These ioctls take advantage of any hardware
667 * features built into the controller for which this algorithm-adapter set
668 * was written. These ioctls allow you to take control of the data and clock
669 * lines and set the either high or low,
670 * similar to a GPIO pin.
671 */
672static int algo_control(struct i2c_adapter *adapter,
673 unsigned int cmd, unsigned long arg)
674{
675
676 struct i2c_algo_iic_data *adap = adapter->algo_data;
677 struct i2c_iic_msg s_msg;
678 char *buf;
679 int ret;
680
681 if (cmd == I2C_SREAD) {
682 if(copy_from_user(&s_msg, (struct i2c_iic_msg *)arg,
683 sizeof(struct i2c_iic_msg)))
684 return -EFAULT;
685 buf = kmalloc(s_msg.len, GFP_KERNEL);
686 if (buf== NULL)
687 return -ENOMEM;
688
689 /* Flush FIFO */
690 iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH);
691
692 /* Load address */
693 iic_outw(adap, ITE_I2CSAR,s_msg.addr<<1);
694 iic_outw(adap, ITE_I2CSSAR,s_msg.waddr & 0xff);
695
696 ret = iic_readbytes(adapter, buf, s_msg.len, 1);
697 if (ret>=0) {
698 if(copy_to_user( s_msg.buf, buf, s_msg.len) )
699 ret = -EFAULT;
700 }
701 kfree(buf);
702 }
703 return 0;
704}
705
706
707static u32 iic_func(struct i2c_adapter *adap)
708{
709 return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
710 I2C_FUNC_PROTOCOL_MANGLING;
711}
712
713/* -----exported algorithm data: ------------------------------------- */
714
715static struct i2c_algorithm iic_algo = {
716 .master_xfer = iic_xfer,
717 .algo_control = algo_control, /* ioctl */
718 .functionality = iic_func,
719};
720
721
722/*
723 * registering functions to load algorithms at runtime
724 */
725int i2c_iic_add_bus(struct i2c_adapter *adap)
726{
727 struct i2c_algo_iic_data *iic_adap = adap->algo_data;
728
729 if (iic_test) {
730 int ret = test_bus(iic_adap, adap->name);
731 if (ret<0)
732 return -ENODEV;
733 }
734
735 DEB2(printk("i2c-algo-ite: hw routines for %s registered.\n",
736 adap->name));
737
738 /* register new adapter to i2c module... */
739 adap->algo = &iic_algo;
740
741 adap->timeout = 100; /* default values, should */
742 adap->retries = 3; /* be replaced by defines */
743 adap->flags = 0;
744
745 iic_init(iic_adap);
746 return i2c_add_adapter(adap);
747}
748
749
750int i2c_iic_del_bus(struct i2c_adapter *adap)
751{
752 int res;
753 if ((res = i2c_del_adapter(adap)) < 0)
754 return res;
755 DEB2(printk("i2c-algo-ite: adapter unregistered: %s\n",adap->name));
756
757 return 0;
758}
759
760
761int __init i2c_algo_iic_init (void)
762{
763 printk(KERN_INFO "ITE iic (i2c) algorithm module\n");
764 return 0;
765}
766
767
768void i2c_algo_iic_exit(void)
769{
770 return;
771}
772
773
774EXPORT_SYMBOL(i2c_iic_add_bus);
775EXPORT_SYMBOL(i2c_iic_del_bus);
776
777/* The MODULE_* macros resolve to nothing if MODULES is not defined
778 * when this file is compiled.
779 */
780MODULE_AUTHOR("MontaVista Software <www.mvista.com>");
781MODULE_DESCRIPTION("ITE iic algorithm");
782MODULE_LICENSE("GPL");
783
784module_param(iic_test, bool, 0);
785module_param(i2c_debug, int, S_IRUGO | S_IWUSR);
786
787MODULE_PARM_DESC(iic_test, "Test if the I2C bus is available");
788MODULE_PARM_DESC(i2c_debug,
789 "debug level - 0 off; 1 normal; 2,3 more verbose; 9 iic-protocol");
790
791
792/* This function resolves to init_module (the function invoked when a module
793 * is loaded via insmod) when this file is compiled with MODULES defined.
794 * Otherwise (i.e. if you want this driver statically linked to the kernel),
795 * a pointer to this function is stored in a table and called
796 * during the initialization of the kernel (in do_basic_setup in /init/main.c)
797 *
798 * All this functionality is complements of the macros defined in linux/init.h
799 */
800module_init(i2c_algo_iic_init);
801
802
803/* If MODULES is defined when this file is compiled, then this function will
804 * resolved to cleanup_module.
805 */
806module_exit(i2c_algo_iic_exit);
diff --git a/drivers/i2c/algos/i2c-algo-ite.h b/drivers/i2c/algos/i2c-algo-ite.h
deleted file mode 100644
index a8ca3c9b546a..000000000000
--- a/drivers/i2c/algos/i2c-algo-ite.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 --------------------------------------------------------------------
3 i2c-ite.h: Global defines for the I2C controller on board the
4 ITE MIPS processor.
5 --------------------------------------------------------------------
6 Hai-Pao Fan, MontaVista Software, Inc.
7 hpfan@mvista.com or source@mvista.com
8
9 Copyright 2001 MontaVista Software Inc.
10
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 */
32
33#ifndef I2C_ITE_H
34#define I2C_ITE_H 1
35
36#include <asm/it8172/it8172.h>
37
38/* I2C Registers */
39#define ITE_I2CHCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x30
40#define ITE_I2CHSR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x34
41#define ITE_I2CSAR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x38
42#define ITE_I2CSSAR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x3c
43#define ITE_I2CCKCNT IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x48
44#define ITE_I2CSHDR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x4c
45#define ITE_I2CRSUR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x50
46#define ITE_I2CPSUR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x54
47
48#define ITE_I2CFDR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x70
49#define ITE_I2CFBCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x74
50#define ITE_I2CFCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x78
51#define ITE_I2CFSR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x7c
52
53
54/* Host Control Register ITE_I2CHCR */
55#define ITE_I2CHCR_HCE 0x01 /* Enable I2C Host Controller */
56#define ITE_I2CHCR_IE 0x02 /* Enable the interrupt after completing
57 the current transaction */
58#define ITE_I2CHCR_CP_W 0x00 /* bit2-4 000 - Write */
59#define ITE_I2CHCR_CP_R 0x08 /* 010 - Current address read */
60#define ITE_I2CHCR_CP_S 0x10 /* 100 - Sequential read */
61#define ITE_I2CHCR_ST 0x20 /* Initiates the I2C host controller to execute
62 the command and send the data programmed in
63 all required registers to I2C bus */
64#define ITE_CMD ITE_I2CHCR_HCE | ITE_I2CHCR_IE | ITE_I2CHCR_ST
65#define ITE_WRITE ITE_CMD | ITE_I2CHCR_CP_W
66#define ITE_READ ITE_CMD | ITE_I2CHCR_CP_R
67#define ITE_SREAD ITE_CMD | ITE_I2CHCR_CP_S
68
69/* Host Status Register ITE_I2CHSR */
70#define ITE_I2CHSR_DB 0x01 /* Device is busy, receives NACK response except
71 in the first and last bytes */
72#define ITE_I2CHSR_DNE 0x02 /* Target address on I2C bus does not exist */
73#define ITE_I2CHSR_TDI 0x04 /* R/W Transaction on I2C bus was completed */
74#define ITE_I2CHSR_HB 0x08 /* Host controller is processing transactions */
75#define ITE_I2CHSR_FER 0x10 /* Error occurs in the FIFO */
76
77/* Slave Address Register ITE_I2CSAR */
78#define ITE_I2CSAR_SA_MASK 0xfe /* Target I2C device address */
79#define ITE_I2CSAR_ASO 0x0100 /* Output 1/0 to I2CAS port when the
80 next slave address is addressed */
81
82/* Slave Sub-address Register ITE_I2CSSAR */
83#define ITE_I2CSSAR_SUBA_MASK 0xff /* Target I2C device sub-address */
84
85/* Clock Counter Register ITE_I2CCKCNT */
86#define ITE_I2CCKCNT_STOP 0x00 /* stop I2C clock */
87#define ITE_I2CCKCNT_HPCC_MASK 0x7f /* SCL high period counter */
88#define ITE_I2CCKCNT_LPCC_MASK 0x7f00 /* SCL low period counter */
89
90/* START Hold Time Register ITE_I2CSHDR */
91/* value is counted based on 16 MHz internal clock */
92#define ITE_I2CSHDR_FM 0x0a /* START condition at fast mode */
93#define ITE_I2CSHDR_SM 0x47 /* START contition at standard mode */
94
95/* (Repeated) START Setup Time Register ITE_I2CRSUR */
96/* value is counted based on 16 MHz internal clock */
97#define ITE_I2CRSUR_FM 0x0a /* repeated START condition at fast mode */
98#define ITE_I2CRSUR_SM 0x50 /* repeated START condition at standard mode */
99
100/* STOP setup Time Register ITE_I2CPSUR */
101
102/* FIFO Data Register ITE_I2CFDR */
103#define ITE_I2CFDR_MASK 0xff
104
105/* FIFO Byte Count Register ITE_I2CFBCR */
106#define ITE_I2CFBCR_MASK 0x3f
107
108/* FIFO Control Register ITE_I2CFCR */
109#define ITE_I2CFCR_FLUSH 0x01 /* Flush FIFO and reset the FIFO point
110 and I2CFSR */
111/* FIFO Status Register ITE_I2CFSR */
112#define ITE_I2CFSR_FO 0x01 /* FIFO is overrun when write */
113#define ITE_I2CFSR_FU 0x02 /* FIFO is underrun when read */
114#define ITE_I2CFSR_FF 0x04 /* FIFO is full when write */
115#define ITE_I2CFSR_FE 0x08 /* FIFO is empty when read */
116
117#endif /* I2C_ITE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 17:01:00 -0500