2 files changed, 15 insertions, 3 deletions

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 46c3c566307e..435ae72fc47a 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -392,7 +392,7 @@ config SENSORS_GL520SM
 
 config SENSORS_CORETEMP
         tristate "Intel Core/Core2/Atom temperature sensor"
-        depends on X86 && EXPERIMENTAL
+        depends on X86 && PCI && EXPERIMENTAL
         help
           If you say yes here you get support for the temperature
           sensor inside your CPU. Most of the family 6 CPUs
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index caef39cda8c8..2d7bceeed0bc 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -33,6 +33,7 @@
 #include <linux/list.h>
 #include <linux/platform_device.h>
 #include <linux/cpu.h>
+#include <linux/pci.h>
 #include <asm/msr.h>
 #include <asm/processor.h>
 
@@ -161,6 +162,7 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
         int usemsr_ee = 1;
         int err;
         u32 eax, edx;
+        struct pci_dev *host_bridge;
 
         /* Early chips have no MSR for TjMax */
 
@@ -168,11 +170,21 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
                 usemsr_ee = 0;
         }
 
-        /* Atoms seems to have TjMax at 90C */
+        /* Atom CPUs */
 
         if (c->x86_model == 0x1c) {
                 usemsr_ee = 0;
-                tjmax = 90000;
+
+                host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
+
+                if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL
+                    && (host_bridge->device == 0xa000   /* NM10 based nettop */
+                    || host_bridge->device == 0xa010))  /* NM10 based netbook */
+                        tjmax = 100000;
+                else
+                        tjmax = 90000;
+
+                pci_dev_put(host_bridge);
         }
 
         if ((c->x86_model > 0xe) && (usemsr_ee)) {