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path: root/drivers/hwmon/coretemp.c
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Diffstat (limited to 'drivers/hwmon/coretemp.c')
-rw-r--r--drivers/hwmon/coretemp.c33
1 files changed, 31 insertions, 2 deletions
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index b9d512331ed4..7f1feb2f467a 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -191,6 +191,24 @@ static ssize_t show_temp(struct device *dev,
191 return tdata->valid ? sprintf(buf, "%d\n", tdata->temp) : -EAGAIN; 191 return tdata->valid ? sprintf(buf, "%d\n", tdata->temp) : -EAGAIN;
192} 192}
193 193
194struct tjmax {
195 char const *id;
196 int tjmax;
197};
198
199static struct tjmax __cpuinitconst tjmax_table[] = {
200 { "CPU D410", 100000 },
201 { "CPU D425", 100000 },
202 { "CPU D510", 100000 },
203 { "CPU D525", 100000 },
204 { "CPU N450", 100000 },
205 { "CPU N455", 100000 },
206 { "CPU N470", 100000 },
207 { "CPU N475", 100000 },
208 { "CPU 230", 100000 },
209 { "CPU 330", 125000 },
210};
211
194static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, 212static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id,
195 struct device *dev) 213 struct device *dev)
196{ 214{
@@ -202,6 +220,13 @@ static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id,
202 int err; 220 int err;
203 u32 eax, edx; 221 u32 eax, edx;
204 struct pci_dev *host_bridge; 222 struct pci_dev *host_bridge;
223 int i;
224
225 /* explicit tjmax table entries override heuristics */
226 for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) {
227 if (strstr(c->x86_model_id, tjmax_table[i].id))
228 return tjmax_table[i].tjmax;
229 }
205 230
206 /* Early chips have no MSR for TjMax */ 231 /* Early chips have no MSR for TjMax */
207 232
@@ -210,7 +235,8 @@ static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id,
210 235
211 /* Atom CPUs */ 236 /* Atom CPUs */
212 237
213 if (c->x86_model == 0x1c) { 238 if (c->x86_model == 0x1c || c->x86_model == 0x26
239 || c->x86_model == 0x27) {
214 usemsr_ee = 0; 240 usemsr_ee = 0;
215 241
216 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 242 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
@@ -223,6 +249,9 @@ static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id,
223 tjmax = 90000; 249 tjmax = 90000;
224 250
225 pci_dev_put(host_bridge); 251 pci_dev_put(host_bridge);
252 } else if (c->x86_model == 0x36) {
253 usemsr_ee = 0;
254 tjmax = 100000;
226 } 255 }
227 256
228 if (c->x86_model > 0xe && usemsr_ee) { 257 if (c->x86_model > 0xe && usemsr_ee) {
@@ -772,7 +801,7 @@ MODULE_DEVICE_TABLE(x86cpu, coretemp_ids);
772 801
773static int __init coretemp_init(void) 802static int __init coretemp_init(void)
774{ 803{
775 int i, err = -ENODEV; 804 int i, err;
776 805
777 /* 806 /*
778 * CPUID.06H.EAX[0] indicates whether the CPU has thermal 807 * CPUID.06H.EAX[0] indicates whether the CPU has thermal