138 files changed, 2111 insertions, 1496 deletions

diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c
index 31123b6a0be5..2d2c2f8d6dc6 100644
--- a/drivers/gpu/drm/ast/ast_drv.c
+++ b/drivers/gpu/drm/ast/ast_drv.c
@@ -60,8 +60,7 @@ static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
 
 MODULE_DEVICE_TABLE(pci, pciidlist);
 
-static int __devinit
-ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
         return drm_get_pci_dev(pdev, ent, &driver);
 }
diff --git a/drivers/gpu/drm/cirrus/cirrus_drv.c b/drivers/gpu/drm/cirrus/cirrus_drv.c
index dcd1a8c029eb..8ecb601152ef 100644
--- a/drivers/gpu/drm/cirrus/cirrus_drv.c
+++ b/drivers/gpu/drm/cirrus/cirrus_drv.c
@@ -56,8 +56,8 @@ static int cirrus_kick_out_firmware_fb(struct pci_dev *pdev)
         return 0;
 }
 
-static int __devinit
-cirrus_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+static int cirrus_pci_probe(struct pci_dev *pdev,
+                            const struct pci_device_id *ent)
 {
         int ret;
 
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index 0761a03cdbb2..2aa331499f81 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -184,19 +184,27 @@ EXPORT_SYMBOL(drm_mm_get_block_generic);
  * -ENOSPC if no suitable free area is available. The preallocated memory node
  * must be cleared.
  */
-int drm_mm_insert_node(struct drm_mm *mm, struct drm_mm_node *node,
-                       unsigned long size, unsigned alignment)
+int drm_mm_insert_node_generic(struct drm_mm *mm, struct drm_mm_node *node,
+                               unsigned long size, unsigned alignment,
+                               unsigned long color)
 {
         struct drm_mm_node *hole_node;
 
-        hole_node = drm_mm_search_free(mm, size, alignment, false);
+        hole_node = drm_mm_search_free_generic(mm, size, alignment,
+                                               color, 0);
         if (!hole_node)
                 return -ENOSPC;
 
-        drm_mm_insert_helper(hole_node, node, size, alignment, 0);
-
+        drm_mm_insert_helper(hole_node, node, size, alignment, color);
         return 0;
 }
+EXPORT_SYMBOL(drm_mm_insert_node_generic);
+
+int drm_mm_insert_node(struct drm_mm *mm, struct drm_mm_node *node,
+                       unsigned long size, unsigned alignment)
+{
+        return drm_mm_insert_node_generic(mm, node, size, alignment, 0);
+}
 EXPORT_SYMBOL(drm_mm_insert_node);
 
 static void drm_mm_insert_helper_range(struct drm_mm_node *hole_node,
@@ -213,11 +221,13 @@ static void drm_mm_insert_helper_range(struct drm_mm_node *hole_node,
 
         BUG_ON(!hole_node->hole_follows || node->allocated);
 
-        if (mm->color_adjust)
-                mm->color_adjust(hole_node, color, &adj_start, &adj_end);
-
         if (adj_start < start)
                 adj_start = start;
+        if (adj_end > end)
+                adj_end = end;
+
+        if (mm->color_adjust)
+                mm->color_adjust(hole_node, color, &adj_start, &adj_end);
 
         if (alignment) {
                 unsigned tmp = adj_start % alignment;
@@ -275,22 +285,31 @@ EXPORT_SYMBOL(drm_mm_get_block_range_generic);
  * -ENOSPC if no suitable free area is available. This is for range
  * restricted allocations. The preallocated memory node must be cleared.
  */
-int drm_mm_insert_node_in_range(struct drm_mm *mm, struct drm_mm_node *node,
-                                unsigned long size, unsigned alignment,
-                                unsigned long start, unsigned long end)
+int drm_mm_insert_node_in_range_generic(struct drm_mm *mm, struct drm_mm_node *node,
+                                        unsigned long size, unsigned alignment, unsigned long color,
+                                        unsigned long start, unsigned long end)
 {
         struct drm_mm_node *hole_node;
 
-        hole_node = drm_mm_search_free_in_range(mm, size, alignment,
-                                                start, end, false);
+        hole_node = drm_mm_search_free_in_range_generic(mm,
+                                                        size, alignment, color,
+                                                        start, end, 0);
         if (!hole_node)
                 return -ENOSPC;
 
-        drm_mm_insert_helper_range(hole_node, node, size, alignment, 0,
+        drm_mm_insert_helper_range(hole_node, node,
+                                   size, alignment, color,
                                    start, end);
-
         return 0;
 }
+EXPORT_SYMBOL(drm_mm_insert_node_in_range_generic);
+
+int drm_mm_insert_node_in_range(struct drm_mm *mm, struct drm_mm_node *node,
+                                unsigned long size, unsigned alignment,
+                                unsigned long start, unsigned long end)
+{
+        return drm_mm_insert_node_in_range_generic(mm, node, size, alignment, 0, start, end);
+}
 EXPORT_SYMBOL(drm_mm_insert_node_in_range);
 
 /**
@@ -489,7 +508,7 @@ void drm_mm_init_scan(struct drm_mm *mm,
         mm->scan_size = size;
         mm->scanned_blocks = 0;
         mm->scan_hit_start = 0;
-        mm->scan_hit_size = 0;
+        mm->scan_hit_end = 0;
         mm->scan_check_range = 0;
         mm->prev_scanned_node = NULL;
 }
@@ -516,7 +535,7 @@ void drm_mm_init_scan_with_range(struct drm_mm *mm,
         mm->scan_size = size;
         mm->scanned_blocks = 0;
         mm->scan_hit_start = 0;
-        mm->scan_hit_size = 0;
+        mm->scan_hit_end = 0;
         mm->scan_start = start;
         mm->scan_end = end;
         mm->scan_check_range = 1;
@@ -535,8 +554,7 @@ int drm_mm_scan_add_block(struct drm_mm_node *node)
         struct drm_mm *mm = node->mm;
         struct drm_mm_node *prev_node;
         unsigned long hole_start, hole_end;
-        unsigned long adj_start;
-        unsigned long adj_end;
+        unsigned long adj_start, adj_end;
 
         mm->scanned_blocks++;
 
@@ -553,14 +571,8 @@ int drm_mm_scan_add_block(struct drm_mm_node *node)
         node->node_list.next = &mm->prev_scanned_node->node_list;
         mm->prev_scanned_node = node;
 
-        hole_start = drm_mm_hole_node_start(prev_node);
-        hole_end = drm_mm_hole_node_end(prev_node);
-
-        adj_start = hole_start;
-        adj_end = hole_end;
-
-        if (mm->color_adjust)
-                mm->color_adjust(prev_node, mm->scan_color, &adj_start, &adj_end);
+        adj_start = hole_start = drm_mm_hole_node_start(prev_node);
+        adj_end = hole_end = drm_mm_hole_node_end(prev_node);
 
         if (mm->scan_check_range) {
                 if (adj_start < mm->scan_start)
@@ -569,11 +581,14 @@ int drm_mm_scan_add_block(struct drm_mm_node *node)
                         adj_end = mm->scan_end;
         }
 
+        if (mm->color_adjust)
+                mm->color_adjust(prev_node, mm->scan_color,
+                                 &adj_start, &adj_end);
+
         if (check_free_hole(adj_start, adj_end,
                             mm->scan_size, mm->scan_alignment)) {
                 mm->scan_hit_start = hole_start;
-                mm->scan_hit_size = hole_end;
-
+                mm->scan_hit_end = hole_end;
                 return 1;
         }
 
@@ -609,19 +624,10 @@ int drm_mm_scan_remove_block(struct drm_mm_node *node)
                                node_list);
 
         prev_node->hole_follows = node->scanned_preceeds_hole;
-        INIT_LIST_HEAD(&node->node_list);
         list_add(&node->node_list, &prev_node->node_list);
 
-        /* Only need to check for containement because start&size for the
-         * complete resulting free block (not just the desired part) is
-         * stored. */
-        if (node->start >= mm->scan_hit_start &&
-            node->start + node->size
-                        <= mm->scan_hit_start + mm->scan_hit_size) {
-                return 1;
-        }
-
-        return 0;
+         return (drm_mm_hole_node_end(node) > mm->scan_hit_start &&
+                 node->start < mm->scan_hit_end);
 }
 EXPORT_SYMBOL(drm_mm_scan_remove_block);
 
diff --git a/drivers/gpu/drm/exynos/exynos_ddc.c b/drivers/gpu/drm/exynos/exynos_ddc.c
index bef43e0342a6..4e9b5ba8edff 100644
--- a/drivers/gpu/drm/exynos/exynos_ddc.c
+++ b/drivers/gpu/drm/exynos/exynos_ddc.c
@@ -66,6 +66,6 @@ struct i2c_driver ddc_driver = {
         },
         .id_table       = ddc_idtable,
         .probe          = s5p_ddc_probe,
-        .remove         = __devexit_p(s5p_ddc_remove),
+        .remove         = s5p_ddc_remove,
         .command                = NULL,
 };
diff --git a/drivers/gpu/drm/exynos/exynos_drm_buf.c b/drivers/gpu/drm/exynos/exynos_drm_buf.c
index 9601bad47a2e..57affae9568b 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_buf.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_buf.c
@@ -3,24 +3,10 @@
  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  * Author: Inki Dae <inki.dae@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #include <drm/drmP.h>
@@ -29,6 +15,7 @@
 #include "exynos_drm_drv.h"
 #include "exynos_drm_gem.h"
 #include "exynos_drm_buf.h"
+#include "exynos_drm_iommu.h"
 
 static int lowlevel_buffer_allocate(struct drm_device *dev,
                 unsigned int flags, struct exynos_drm_gem_buf *buf)
@@ -51,7 +38,7 @@ static int lowlevel_buffer_allocate(struct drm_device *dev,
          * region will be allocated else physically contiguous
          * as possible.
          */
-        if (flags & EXYNOS_BO_CONTIG)
+        if (!(flags & EXYNOS_BO_NONCONTIG))
                 dma_set_attr(DMA_ATTR_FORCE_CONTIGUOUS, &buf->dma_attrs);
 
         /*
@@ -66,14 +53,45 @@ static int lowlevel_buffer_allocate(struct drm_device *dev,
         dma_set_attr(attr, &buf->dma_attrs);
         dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &buf->dma_attrs);
 
-        buf->pages = dma_alloc_attrs(dev->dev, buf->size,
-                        &buf->dma_addr, GFP_KERNEL, &buf->dma_attrs);
-        if (!buf->pages) {
-                DRM_ERROR("failed to allocate buffer.\n");
-                return -ENOMEM;
+        nr_pages = buf->size >> PAGE_SHIFT;
+
+        if (!is_drm_iommu_supported(dev)) {
+                dma_addr_t start_addr;
+                unsigned int i = 0;
+
+                buf->pages = kzalloc(sizeof(struct page) * nr_pages,
+                                        GFP_KERNEL);
+                if (!buf->pages) {
+                        DRM_ERROR("failed to allocate pages.\n");
+                        return -ENOMEM;
+                }
+
+                buf->kvaddr = dma_alloc_attrs(dev->dev, buf->size,
+                                        &buf->dma_addr, GFP_KERNEL,
+                                        &buf->dma_attrs);
+                if (!buf->kvaddr) {
+                        DRM_ERROR("failed to allocate buffer.\n");
+                        kfree(buf->pages);
+                        return -ENOMEM;
+                }
+
+                start_addr = buf->dma_addr;
+                while (i < nr_pages) {
+                        buf->pages[i] = phys_to_page(start_addr);
+                        start_addr += PAGE_SIZE;
+                        i++;
+                }
+        } else {
+
+                buf->pages = dma_alloc_attrs(dev->dev, buf->size,
+                                        &buf->dma_addr, GFP_KERNEL,
+                                        &buf->dma_attrs);
+                if (!buf->pages) {
+                        DRM_ERROR("failed to allocate buffer.\n");
+                        return -ENOMEM;
+                }
         }
 
-        nr_pages = buf->size >> PAGE_SHIFT;
         buf->sgt = drm_prime_pages_to_sg(buf->pages, nr_pages);
         if (!buf->sgt) {
                 DRM_ERROR("failed to get sg table.\n");
@@ -92,6 +110,9 @@ err_free_attrs:
                         (dma_addr_t)buf->dma_addr, &buf->dma_attrs);
         buf->dma_addr = (dma_addr_t)NULL;
 
+        if (!is_drm_iommu_supported(dev))
+                kfree(buf->pages);
+
         return ret;
 }
 
@@ -114,8 +135,14 @@ static void lowlevel_buffer_deallocate(struct drm_device *dev,
         kfree(buf->sgt);
         buf->sgt = NULL;
 
-        dma_free_attrs(dev->dev, buf->size, buf->pages,
+        if (!is_drm_iommu_supported(dev)) {
+                dma_free_attrs(dev->dev, buf->size, buf->kvaddr,
                                 (dma_addr_t)buf->dma_addr, &buf->dma_attrs);
+                kfree(buf->pages);
+        } else
+                dma_free_attrs(dev->dev, buf->size, buf->pages,
+                                (dma_addr_t)buf->dma_addr, &buf->dma_attrs);
+
         buf->dma_addr = (dma_addr_t)NULL;
 }
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_buf.h b/drivers/gpu/drm/exynos/exynos_drm_buf.h
index 25cf16285033..a6412f19673c 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_buf.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_buf.h
@@ -3,24 +3,10 @@
  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  * Author: Inki Dae <inki.dae@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_BUF_H_
diff --git a/drivers/gpu/drm/exynos/exynos_drm_connector.c b/drivers/gpu/drm/exynos/exynos_drm_connector.c
index 0f68a2872673..ab37437bad8a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_connector.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_connector.c
@@ -5,24 +5,10 @@
  *      Joonyoung Shim <jy0922.shim@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #include <drm/drmP.h>
diff --git a/drivers/gpu/drm/exynos/exynos_drm_connector.h b/drivers/gpu/drm/exynos/exynos_drm_connector.h
index 22f6cc442c3d..547c6b590357 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_connector.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_connector.h
@@ -5,24 +5,10 @@
  *      Joonyoung Shim <jy0922.shim@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_CONNECTOR_H_
diff --git a/drivers/gpu/drm/exynos/exynos_drm_core.c b/drivers/gpu/drm/exynos/exynos_drm_core.c
index 94026ad76a77..4667c9f67acd 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_core.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_core.c
@@ -6,24 +6,10 @@
  *      Joonyoung Shim <jy0922.shim@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #include <drm/drmP.h>
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 2efa4b031d73..e8894bc9e6d5 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -6,24 +6,10 @@
  *      Joonyoung Shim <jy0922.shim@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #include <drm/drmP.h>
@@ -407,3 +393,33 @@ void exynos_drm_crtc_disable_vblank(struct drm_device *dev, int crtc)
         exynos_drm_fn_encoder(private->crtc[crtc], &crtc,
                         exynos_drm_disable_vblank);
 }
+
+void exynos_drm_crtc_finish_pageflip(struct drm_device *dev, int crtc)
+{
+        struct exynos_drm_private *dev_priv = dev->dev_private;
+        struct drm_pending_vblank_event *e, *t;
+        struct timeval now;
+        unsigned long flags;
+
+        DRM_DEBUG_KMS("%s\n", __FILE__);
+
+        spin_lock_irqsave(&dev->event_lock, flags);
+
+        list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
+                        base.link) {
+                /* if event's pipe isn't same as crtc then ignore it. */
+                if (crtc != e->pipe)
+                        continue;
+
+                do_gettimeofday(&now);
+                e->event.sequence = 0;
+                e->event.tv_sec = now.tv_sec;
+                e->event.tv_usec = now.tv_usec;
+
+                list_move_tail(&e->base.link, &e->base.file_priv->event_list);
+                wake_up_interruptible(&e->base.file_priv->event_wait);
+                drm_vblank_put(dev, crtc);
+        }
+
+        spin_unlock_irqrestore(&dev->event_lock, flags);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index 6bae8d8c250e..3e197e6ae7d9 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -6,24 +6,10 @@
  *      Joonyoung Shim <jy0922.shim@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_CRTC_H_
@@ -32,5 +18,6 @@
 int exynos_drm_crtc_create(struct drm_device *dev, unsigned int nr);
 int exynos_drm_crtc_enable_vblank(struct drm_device *dev, int crtc);
 void exynos_drm_crtc_disable_vblank(struct drm_device *dev, int crtc);
+void exynos_drm_crtc_finish_pageflip(struct drm_device *dev, int crtc);
 
 #endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c
index 61d5a8402eb8..9df97714b6c0 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c
@@ -3,24 +3,10 @@
  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  * Author: Inki Dae <inki.dae@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #include <drm/drmP.h>
@@ -222,7 +208,7 @@ struct dma_buf *exynos_dmabuf_prime_export(struct drm_device *drm_dev,
         struct exynos_drm_gem_obj *exynos_gem_obj = to_exynos_gem_obj(obj);
 
         return dma_buf_export(exynos_gem_obj, &exynos_dmabuf_ops,
-                                exynos_gem_obj->base.size, 0600);
+                                exynos_gem_obj->base.size, flags);
 }
 
 struct drm_gem_object *exynos_dmabuf_prime_import(struct drm_device *drm_dev,
@@ -246,7 +232,12 @@ struct drm_gem_object *exynos_dmabuf_prime_import(struct drm_device *drm_dev,
 
                 /* is it from our device? */
                 if (obj->dev == drm_dev) {
+                        /*
+                         * Importing dmabuf exported from out own gem increases
+                         * refcount on gem itself instead of f_count of dmabuf.
+                         */
                         drm_gem_object_reference(obj);
+                        dma_buf_put(dma_buf);
                         return obj;
                 }
         }
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.h b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.h
index 662a8f98ccdb..49acfafb4fdb 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.h
@@ -3,24 +3,10 @@
  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  * Author: Inki Dae <inki.dae@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_DMABUF_H_
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index e0a8e8024b01..3da5c2d214d8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -5,24 +5,10 @@
  *      Joonyoung Shim <jy0922.shim@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #include <drm/drmP.h>
@@ -325,7 +311,7 @@ static int exynos_drm_platform_remove(struct platform_device *pdev)
 
 static struct platform_driver exynos_drm_platform_driver = {
         .probe          = exynos_drm_platform_probe,
-        .remove         = __devexit_p(exynos_drm_platform_remove),
+        .remove         = exynos_drm_platform_remove,
         .driver         = {
                 .owner  = THIS_MODULE,
                 .name   = "exynos-drm",
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index f5a97745bf93..b9e51bc09e81 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -6,24 +6,10 @@
  *      Joonyoung Shim <jy0922.shim@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_DRV_H_
diff --git a/drivers/gpu/drm/exynos/exynos_drm_encoder.c b/drivers/gpu/drm/exynos/exynos_drm_encoder.c
index 301485215a70..c63721f64aec 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_encoder.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_encoder.c
@@ -6,24 +6,10 @@
  *      Joonyoung Shim <jy0922.shim@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #include <drm/drmP.h>
diff --git a/drivers/gpu/drm/exynos/exynos_drm_encoder.h b/drivers/gpu/drm/exynos/exynos_drm_encoder.h
index 88bb25a2a917..89e2fb0770af 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_encoder.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_encoder.h
@@ -5,24 +5,10 @@
  *      Joonyoung Shim <jy0922.shim@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_ENCODER_H_
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c
index 5426cc5a5e8d..294c0513f587 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fb.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c
@@ -6,24 +6,10 @@
  *      Joonyoung Shim <jy0922.shim@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #include <drm/drmP.h>
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.h b/drivers/gpu/drm/exynos/exynos_drm_fb.h
index 96262e54f76d..517471b37566 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fb.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.h
@@ -5,24 +5,10 @@
  *      Joonyoung Shim <jy0922.shim@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_FB_H_
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index f433eb7533a9..71f867340a88 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -6,24 +6,10 @@
  *      Joonyoung Shim <jy0922.shim@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #include <drm/drmP.h>
@@ -34,6 +20,7 @@
 #include "exynos_drm_drv.h"
 #include "exynos_drm_fb.h"
 #include "exynos_drm_gem.h"
+#include "exynos_drm_iommu.h"
 
 #define MAX_CONNECTOR           4
 #define PREFERRED_BPP           32
@@ -111,9 +98,18 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper *helper,
 
         /* map pages with kernel virtual space. */
         if (!buffer->kvaddr) {
-                unsigned int nr_pages = buffer->size >> PAGE_SHIFT;
-                buffer->kvaddr = vmap(buffer->pages, nr_pages, VM_MAP,
+                if (is_drm_iommu_supported(dev)) {
+                        unsigned int nr_pages = buffer->size >> PAGE_SHIFT;
+
+                        buffer->kvaddr = vmap(buffer->pages, nr_pages, VM_MAP,
                                         pgprot_writecombine(PAGE_KERNEL));
+                } else {
+                        phys_addr_t dma_addr = buffer->dma_addr;
+                        if (dma_addr)
+                                buffer->kvaddr = phys_to_virt(dma_addr);
+                        else
+                                buffer->kvaddr = (void __iomem *)NULL;
+                }
                 if (!buffer->kvaddr) {
                         DRM_ERROR("failed to map pages to kernel space.\n");
                         return -EIO;
@@ -128,8 +124,12 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper *helper,
 
         dev->mode_config.fb_base = (resource_size_t)buffer->dma_addr;
         fbi->screen_base = buffer->kvaddr + offset;
-        fbi->fix.smem_start = (unsigned long)
+        if (is_drm_iommu_supported(dev))
+                fbi->fix.smem_start = (unsigned long)
                         (page_to_phys(sg_page(buffer->sgt->sgl)) + offset);
+        else
+                fbi->fix.smem_start = (unsigned long)buffer->dma_addr;
+
         fbi->screen_size = size;
         fbi->fix.smem_len = size;
 
@@ -320,7 +320,7 @@ static void exynos_drm_fbdev_destroy(struct drm_device *dev,
         struct exynos_drm_gem_obj *exynos_gem_obj = exynos_fbd->exynos_gem_obj;
         struct drm_framebuffer *fb;
 
-        if (exynos_gem_obj->buffer->kvaddr)
+        if (is_drm_iommu_supported(dev) && exynos_gem_obj->buffer->kvaddr)
                 vunmap(exynos_gem_obj->buffer->kvaddr);
 
         /* release drm framebuffer and real buffer */
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.h b/drivers/gpu/drm/exynos/exynos_drm_fbdev.h
index ccfce8a1a451..e16d7f0ae192 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.h
@@ -6,24 +6,10 @@
  *      Joonyoung Shim <jy0922.shim@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_FBDEV_H_
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
index 61ea24296b52..67a83e69544b 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
@@ -25,7 +25,7 @@
 #include "exynos_drm_fimc.h"
 
 /*
- * FIMC is stand for Fully Interactive Mobile Camera and
+ * FIMC stands for Fully Interactive Mobile Camera and
  * supports image scaler/rotator and input/output DMA operations.
  * input DMA reads image data from the memory.
  * output DMA writes image data to memory.
@@ -163,19 +163,29 @@ struct fimc_context {
         bool    suspended;
 };
 
-static void fimc_sw_reset(struct fimc_context *ctx, bool pattern)
+static void fimc_sw_reset(struct fimc_context *ctx)
 {
         u32 cfg;
 
-        DRM_DEBUG_KMS("%s:pattern[%d]\n", __func__, pattern);
+        DRM_DEBUG_KMS("%s\n", __func__);
+
+        /* stop dma operation */
+        cfg = fimc_read(EXYNOS_CISTATUS);
+        if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) {
+                cfg = fimc_read(EXYNOS_MSCTRL);
+                cfg &= ~EXYNOS_MSCTRL_ENVID;
+                fimc_write(cfg, EXYNOS_MSCTRL);
+        }
 
         cfg = fimc_read(EXYNOS_CISRCFMT);
         cfg |= EXYNOS_CISRCFMT_ITU601_8BIT;
-        if (pattern)
-                cfg |= EXYNOS_CIGCTRL_TESTPATTERN_COLOR_BAR;
-
         fimc_write(cfg, EXYNOS_CISRCFMT);
 
+        /* disable image capture */
+        cfg = fimc_read(EXYNOS_CIIMGCPT);
+        cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
+        fimc_write(cfg, EXYNOS_CIIMGCPT);
+
         /* s/w reset */
         cfg = fimc_read(EXYNOS_CIGCTRL);
         cfg |= (EXYNOS_CIGCTRL_SWRST);
@@ -695,7 +705,7 @@ static int fimc_src_set_addr(struct device *dev,
 {
         struct fimc_context *ctx = get_fimc_context(dev);
         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
-        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->cmd;
+        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
         struct drm_exynos_ipp_property *property;
         struct drm_exynos_ipp_config *config;
 
@@ -705,10 +715,6 @@ static int fimc_src_set_addr(struct device *dev,
         }
 
         property = &c_node->property;
-        if (!property) {
-                DRM_ERROR("failed to get property.\n");
-                return -EINVAL;
-        }
 
         DRM_DEBUG_KMS("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
                 property->prop_id, buf_id, buf_type);
@@ -1206,7 +1212,7 @@ static int fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id,
         }
 
         /* sequence id */
-        cfg &= (~mask);
+        cfg &= ~mask;
         cfg |= (enable << buf_id);
         fimc_write(cfg, EXYNOS_CIFCNTSEQ);
 
@@ -1231,7 +1237,7 @@ static int fimc_dst_set_addr(struct device *dev,
 {
         struct fimc_context *ctx = get_fimc_context(dev);
         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
-        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->cmd;
+        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
         struct drm_exynos_ipp_property *property;
         struct drm_exynos_ipp_config *config;
 
@@ -1241,10 +1247,6 @@ static int fimc_dst_set_addr(struct device *dev,
         }
 
         property = &c_node->property;
-        if (!property) {
-                DRM_ERROR("failed to get property.\n");
-                return -EINVAL;
-        }
 
         DRM_DEBUG_KMS("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
                 property->prop_id, buf_id, buf_type);
@@ -1317,7 +1319,7 @@ static irqreturn_t fimc_irq_handler(int irq, void *dev_id)
 {
         struct fimc_context *ctx = dev_id;
         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
-        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->cmd;
+        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
         struct drm_exynos_ipp_event_work *event_work =
                 c_node->event_work;
         int buf_id;
@@ -1395,6 +1397,7 @@ static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip)
         case EXYNOS_DRM_FLIP_NONE:
         case EXYNOS_DRM_FLIP_VERTICAL:
         case EXYNOS_DRM_FLIP_HORIZONTAL:
+        case EXYNOS_DRM_FLIP_BOTH:
                 return true;
         default:
                 DRM_DEBUG_KMS("%s:invalid flip\n", __func__);
@@ -1543,7 +1546,7 @@ static int fimc_ippdrv_reset(struct device *dev)
         DRM_DEBUG_KMS("%s\n", __func__);
 
         /* reset h/w block */
-        fimc_sw_reset(ctx, false);
+        fimc_sw_reset(ctx);
 
         /* reset scaler capability */
         memset(&ctx->sc, 0x0, sizeof(ctx->sc));
@@ -1557,7 +1560,7 @@ static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
 {
         struct fimc_context *ctx = get_fimc_context(dev);
         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
-        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->cmd;
+        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
         struct drm_exynos_ipp_property *property;
         struct drm_exynos_ipp_config *config;
         struct drm_exynos_pos   img_pos[EXYNOS_DRM_OPS_MAX];
@@ -1573,10 +1576,6 @@ static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
         }
 
         property = &c_node->property;
-        if (!property) {
-                DRM_ERROR("failed to get property.\n");
-                return -EINVAL;
-        }
 
         fimc_handle_irq(ctx, true, false, true);
 
@@ -1714,7 +1713,7 @@ static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
         fimc_write(cfg, EXYNOS_CIGCTRL);
 }
 
-static int __devinit fimc_probe(struct platform_device *pdev)
+static int fimc_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct fimc_context *ctx;
@@ -1739,93 +1738,64 @@ static int __devinit fimc_probe(struct platform_device *pdev)
                 platform_get_device_id(pdev)->driver_data;
 
         /* clock control */
-        ctx->sclk_fimc_clk = clk_get(dev, "sclk_fimc");
+        ctx->sclk_fimc_clk = devm_clk_get(dev, "sclk_fimc");
         if (IS_ERR(ctx->sclk_fimc_clk)) {
                 dev_err(dev, "failed to get src fimc clock.\n");
-                ret = PTR_ERR(ctx->sclk_fimc_clk);
-                goto err_ctx;
+                return PTR_ERR(ctx->sclk_fimc_clk);
         }
         clk_enable(ctx->sclk_fimc_clk);
 
-        ctx->fimc_clk = clk_get(dev, "fimc");
+        ctx->fimc_clk = devm_clk_get(dev, "fimc");
         if (IS_ERR(ctx->fimc_clk)) {
                 dev_err(dev, "failed to get fimc clock.\n");
-                ret = PTR_ERR(ctx->fimc_clk);
                 clk_disable(ctx->sclk_fimc_clk);
-                clk_put(ctx->sclk_fimc_clk);
-                goto err_ctx;
+                return PTR_ERR(ctx->fimc_clk);
         }
 
-        ctx->wb_clk = clk_get(dev, "pxl_async0");
+        ctx->wb_clk = devm_clk_get(dev, "pxl_async0");
         if (IS_ERR(ctx->wb_clk)) {
                 dev_err(dev, "failed to get writeback a clock.\n");
-                ret = PTR_ERR(ctx->wb_clk);
                 clk_disable(ctx->sclk_fimc_clk);
-                clk_put(ctx->sclk_fimc_clk);
-                clk_put(ctx->fimc_clk);
-                goto err_ctx;
+                return PTR_ERR(ctx->wb_clk);
         }
 
-        ctx->wb_b_clk = clk_get(dev, "pxl_async1");
+        ctx->wb_b_clk = devm_clk_get(dev, "pxl_async1");
         if (IS_ERR(ctx->wb_b_clk)) {
                 dev_err(dev, "failed to get writeback b clock.\n");
-                ret = PTR_ERR(ctx->wb_b_clk);
                 clk_disable(ctx->sclk_fimc_clk);
-                clk_put(ctx->sclk_fimc_clk);
-                clk_put(ctx->fimc_clk);
-                clk_put(ctx->wb_clk);
-                goto err_ctx;
+                return PTR_ERR(ctx->wb_b_clk);
         }
 
-        parent_clk = clk_get(dev, ddata->parent_clk);
+        parent_clk = devm_clk_get(dev, ddata->parent_clk);
 
         if (IS_ERR(parent_clk)) {
                 dev_err(dev, "failed to get parent clock.\n");
-                ret = PTR_ERR(parent_clk);
                 clk_disable(ctx->sclk_fimc_clk);
-                clk_put(ctx->sclk_fimc_clk);
-                clk_put(ctx->fimc_clk);
-                clk_put(ctx->wb_clk);
-                clk_put(ctx->wb_b_clk);
-                goto err_ctx;
+                return PTR_ERR(parent_clk);
         }
 
         if (clk_set_parent(ctx->sclk_fimc_clk, parent_clk)) {
                 dev_err(dev, "failed to set parent.\n");
-                ret = -EINVAL;
-                clk_put(parent_clk);
                 clk_disable(ctx->sclk_fimc_clk);
-                clk_put(ctx->sclk_fimc_clk);
-                clk_put(ctx->fimc_clk);
-                clk_put(ctx->wb_clk);
-                clk_put(ctx->wb_b_clk);
-                goto err_ctx;
+                return -EINVAL;
         }
 
-        clk_put(parent_clk);
+        devm_clk_put(dev, parent_clk);
         clk_set_rate(ctx->sclk_fimc_clk, pdata->clk_rate);
 
         /* resource memory */
         ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!ctx->regs_res) {
-                dev_err(dev, "failed to find registers.\n");
-                ret = -ENOENT;
-                goto err_clk;
-        }
-
         ctx->regs = devm_request_and_ioremap(dev, ctx->regs_res);
         if (!ctx->regs) {
                 dev_err(dev, "failed to map registers.\n");
-                ret = -ENXIO;
-                goto err_clk;
+                return -ENXIO;
         }
 
         /* resource irq */
         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
         if (!res) {
                 dev_err(dev, "failed to request irq resource.\n");
-                ret = -ENOENT;
-                goto err_get_regs;
+                return -ENOENT;
         }
 
         ctx->irq = res->start;
@@ -1833,7 +1803,7 @@ static int __devinit fimc_probe(struct platform_device *pdev)
                 IRQF_ONESHOT, "drm_fimc", ctx);
         if (ret < 0) {
                 dev_err(dev, "failed to request irq.\n");
-                goto err_get_regs;
+                return ret;
         }
 
         /* context initailization */
@@ -1879,19 +1849,11 @@ err_ippdrv_register:
         pm_runtime_disable(dev);
 err_get_irq:
         free_irq(ctx->irq, ctx);
-err_get_regs:
-        devm_iounmap(dev, ctx->regs);
-err_clk:
-        clk_put(ctx->sclk_fimc_clk);
-        clk_put(ctx->fimc_clk);
-        clk_put(ctx->wb_clk);
-        clk_put(ctx->wb_b_clk);
-err_ctx:
-        devm_kfree(dev, ctx);
+
         return ret;
 }
 
-static int __devexit fimc_remove(struct platform_device *pdev)
+static int fimc_remove(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct fimc_context *ctx = get_fimc_context(dev);
@@ -1905,14 +1867,6 @@ static int __devexit fimc_remove(struct platform_device *pdev)
         pm_runtime_disable(dev);
 
         free_irq(ctx->irq, ctx);
-        devm_iounmap(dev, ctx->regs);
-
-        clk_put(ctx->sclk_fimc_clk);
-        clk_put(ctx->fimc_clk);
-        clk_put(ctx->wb_clk);
-        clk_put(ctx->wb_b_clk);
-
-        devm_kfree(dev, ctx);
 
         return 0;
 }
@@ -1990,7 +1944,7 @@ static const struct dev_pm_ops fimc_pm_ops = {
 
 struct platform_driver fimc_driver = {
         .probe          = fimc_probe,
-        .remove         = __devexit_p(fimc_remove),
+        .remove         = fimc_remove,
         .id_table       = fimc_driver_ids,
         .driver         = {
                 .name   = "exynos-drm-fimc",
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.h b/drivers/gpu/drm/exynos/exynos_drm_fimc.h
index dc970fa0d888..127a424c5fdf 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.h
@@ -6,24 +6,10 @@
  *      Jinyoung Jeon <jy0.jeon@samsung.com>
  *      Sangmin Lee <lsmin.lee@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_FIMC_H_
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index bf0d9baca2bc..9537761931ee 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -663,34 +663,6 @@ static struct exynos_drm_manager fimd_manager = {
         .display_ops    = &fimd_display_ops,
 };
 
-static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc)
-{
-        struct exynos_drm_private *dev_priv = drm_dev->dev_private;
-        struct drm_pending_vblank_event *e, *t;
-        struct timeval now;
-        unsigned long flags;
-
-        spin_lock_irqsave(&drm_dev->event_lock, flags);
-
-        list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
-                        base.link) {
-                /* if event's pipe isn't same as crtc then ignore it. */
-                if (crtc != e->pipe)
-                        continue;
-
-                do_gettimeofday(&now);
-                e->event.sequence = 0;
-                e->event.tv_sec = now.tv_sec;
-                e->event.tv_usec = now.tv_usec;
-
-                list_move_tail(&e->base.link, &e->base.file_priv->event_list);
-                wake_up_interruptible(&e->base.file_priv->event_wait);
-                drm_vblank_put(drm_dev, crtc);
-        }
-
-        spin_unlock_irqrestore(&drm_dev->event_lock, flags);
-}
-
 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 {
         struct fimd_context *ctx = (struct fimd_context *)dev_id;
@@ -710,7 +682,7 @@ static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
                 goto out;
 
         drm_handle_vblank(drm_dev, manager->pipe);
-        fimd_finish_pageflip(drm_dev, manager->pipe);
+        exynos_drm_crtc_finish_pageflip(drm_dev, manager->pipe);
 
         /* set wait vsync event to zero and wake up queue. */
         if (atomic_read(&ctx->wait_vsync_event)) {
@@ -898,7 +870,7 @@ static int fimd_activate(struct fimd_context *ctx, bool enable)
         return 0;
 }
 
-static int __devinit fimd_probe(struct platform_device *pdev)
+static int fimd_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct fimd_context *ctx;
@@ -997,7 +969,7 @@ static int __devinit fimd_probe(struct platform_device *pdev)
         return 0;
 }
 
-static int __devexit fimd_remove(struct platform_device *pdev)
+static int fimd_remove(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct fimd_context *ctx = platform_get_drvdata(pdev);
@@ -1046,7 +1018,7 @@ static int fimd_resume(struct device *dev)
          * of pm runtime would still be 1 so in this case, fimd driver
          * should be on directly not drawing on pm runtime interface.
          */
-        if (pm_runtime_suspended(dev)) {
+        if (!pm_runtime_suspended(dev)) {
                 int ret;
 
                 ret = fimd_activate(ctx, true);
@@ -1105,7 +1077,7 @@ static const struct dev_pm_ops fimd_pm_ops = {
 
 struct platform_driver fimd_driver = {
         .probe          = fimd_probe,
-        .remove         = __devexit_p(fimd_remove),
+        .remove         = fimd_remove,
         .id_table       = fimd_driver_ids,
         .driver         = {
                 .name   = "exynos4-fb",
diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
index 6ffa0763c078..36c3905536a6 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -1090,7 +1090,7 @@ static void g2d_close(struct drm_device *drm_dev, struct device *dev,
         kfree(file_priv->g2d_priv);
 }
 
-static int __devinit g2d_probe(struct platform_device *pdev)
+static int g2d_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct resource *res;
@@ -1188,7 +1188,7 @@ err_destroy_slab:
         return ret;
 }
 
-static int __devexit g2d_remove(struct platform_device *pdev)
+static int g2d_remove(struct platform_device *pdev)
 {
         struct g2d_data *g2d = platform_get_drvdata(pdev);
 
@@ -1242,7 +1242,7 @@ static SIMPLE_DEV_PM_OPS(g2d_pm_ops, g2d_suspend, g2d_resume);
 
 struct platform_driver g2d_driver = {
         .probe          = g2d_probe,
-        .remove         = __devexit_p(g2d_remove),
+        .remove         = g2d_remove,
         .driver         = {
                 .name   = "s5p-g2d",
                 .owner  = THIS_MODULE,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index d48183e7e056..473180776528 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -3,24 +3,10 @@
  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  * Author: Inki Dae <inki.dae@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #include <drm/drmP.h>
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.h b/drivers/gpu/drm/exynos/exynos_drm_gem.h
index f11f2afd5bfc..35ebac47dc2b 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.h
@@ -3,24 +3,10 @@
  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  * Authoer: Inki Dae <inki.dae@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_GEM_H_
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
index 5639353d47b9..8140753ec9c8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
@@ -25,7 +25,7 @@
 #include "exynos_drm_gsc.h"
 
 /*
- * GSC is stand for General SCaler and
+ * GSC stands for General SCaler and
  * supports image scaler/rotator and input/output DMA operations.
  * input DMA reads image data from the memory.
  * output DMA writes image data to memory.
@@ -711,7 +711,7 @@ static int gsc_src_set_addr(struct device *dev,
 {
         struct gsc_context *ctx = get_gsc_context(dev);
         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
-        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->cmd;
+        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
         struct drm_exynos_ipp_property *property;
 
         if (!c_node) {
@@ -720,10 +720,6 @@ static int gsc_src_set_addr(struct device *dev,
         }
 
         property = &c_node->property;
-        if (!property) {
-                DRM_ERROR("failed to get property.\n");
-                return -EFAULT;
-        }
 
         DRM_DEBUG_KMS("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
                 property->prop_id, buf_id, buf_type);
@@ -1171,7 +1167,7 @@ static int gsc_dst_set_addr(struct device *dev,
 {
         struct gsc_context *ctx = get_gsc_context(dev);
         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
-        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->cmd;
+        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
         struct drm_exynos_ipp_property *property;
 
         if (!c_node) {
@@ -1180,10 +1176,6 @@ static int gsc_dst_set_addr(struct device *dev,
         }
 
         property = &c_node->property;
-        if (!property) {
-                DRM_ERROR("failed to get property.\n");
-                return -EFAULT;
-        }
 
         DRM_DEBUG_KMS("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
                 property->prop_id, buf_id, buf_type);
@@ -1312,7 +1304,7 @@ static irqreturn_t gsc_irq_handler(int irq, void *dev_id)
 {
         struct gsc_context *ctx = dev_id;
         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
-        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->cmd;
+        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
         struct drm_exynos_ipp_event_work *event_work =
                 c_node->event_work;
         u32 status;
@@ -1399,7 +1391,7 @@ static inline bool gsc_check_drm_flip(enum drm_exynos_flip flip)
         case EXYNOS_DRM_FLIP_NONE:
         case EXYNOS_DRM_FLIP_VERTICAL:
         case EXYNOS_DRM_FLIP_HORIZONTAL:
-        case EXYNOS_DRM_FLIP_VERTICAL | EXYNOS_DRM_FLIP_HORIZONTAL:
+        case EXYNOS_DRM_FLIP_BOTH:
                 return true;
         default:
                 DRM_DEBUG_KMS("%s:invalid flip\n", __func__);
@@ -1549,7 +1541,7 @@ static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
 {
         struct gsc_context *ctx = get_gsc_context(dev);
         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
-        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->cmd;
+        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
         struct drm_exynos_ipp_property *property;
         struct drm_exynos_ipp_config *config;
         struct drm_exynos_pos   img_pos[EXYNOS_DRM_OPS_MAX];
@@ -1565,10 +1557,6 @@ static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
         }
 
         property = &c_node->property;
-        if (!property) {
-                DRM_ERROR("failed to get property.\n");
-                return -EINVAL;
-        }
 
         gsc_handle_irq(ctx, true, false, true);
 
@@ -1604,7 +1592,7 @@ static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
                 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
 
                 /* src local path */
-                cfg = readl(GSC_IN_CON);
+                cfg = gsc_read(GSC_IN_CON);
                 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
                 cfg |= (GSC_IN_PATH_LOCAL | GSC_IN_LOCAL_FIMD_WB);
                 gsc_write(cfg, GSC_IN_CON);
@@ -1683,7 +1671,7 @@ static void gsc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
         gsc_write(cfg, GSC_ENABLE);
 }
 
-static int __devinit gsc_probe(struct platform_device *pdev)
+static int gsc_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct gsc_context *ctx;
@@ -1696,34 +1684,25 @@ static int __devinit gsc_probe(struct platform_device *pdev)
                 return -ENOMEM;
 
         /* clock control */
-        ctx->gsc_clk = clk_get(dev, "gscl");
+        ctx->gsc_clk = devm_clk_get(dev, "gscl");
         if (IS_ERR(ctx->gsc_clk)) {
                 dev_err(dev, "failed to get gsc clock.\n");
-                ret = PTR_ERR(ctx->gsc_clk);
-                goto err_ctx;
+                return PTR_ERR(ctx->gsc_clk);
         }
 
         /* resource memory */
         ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!ctx->regs_res) {
-                dev_err(dev, "failed to find registers.\n");
-                ret = -ENOENT;
-                goto err_clk;
-        }
-
         ctx->regs = devm_request_and_ioremap(dev, ctx->regs_res);
         if (!ctx->regs) {
                 dev_err(dev, "failed to map registers.\n");
-                ret = -ENXIO;
-                goto err_clk;
+                return -ENXIO;
         }
 
         /* resource irq */
         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
         if (!res) {
                 dev_err(dev, "failed to request irq resource.\n");
-                ret = -ENOENT;
-                goto err_get_regs;
+                return -ENOENT;
         }
 
         ctx->irq = res->start;
@@ -1731,7 +1710,7 @@ static int __devinit gsc_probe(struct platform_device *pdev)
                 IRQF_ONESHOT, "drm_gsc", ctx);
         if (ret < 0) {
                 dev_err(dev, "failed to request irq.\n");
-                goto err_get_regs;
+                return ret;
         }
 
         /* context initailization */
@@ -1775,16 +1754,10 @@ err_ippdrv_register:
         pm_runtime_disable(dev);
 err_get_irq:
         free_irq(ctx->irq, ctx);
-err_get_regs:
-        devm_iounmap(dev, ctx->regs);
-err_clk:
-        clk_put(ctx->gsc_clk);
-err_ctx:
-        devm_kfree(dev, ctx);
         return ret;
 }
 
-static int __devexit gsc_remove(struct platform_device *pdev)
+static int gsc_remove(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct gsc_context *ctx = get_gsc_context(dev);
@@ -1798,11 +1771,6 @@ static int __devexit gsc_remove(struct platform_device *pdev)
         pm_runtime_disable(dev);
 
         free_irq(ctx->irq, ctx);
-        devm_iounmap(dev, ctx->regs);
-
-        clk_put(ctx->gsc_clk);
-
-        devm_kfree(dev, ctx);
 
         return 0;
 }
@@ -1860,7 +1828,7 @@ static const struct dev_pm_ops gsc_pm_ops = {
 
 struct platform_driver gsc_driver = {
         .probe          = gsc_probe,
-        .remove         = __devexit_p(gsc_remove),
+        .remove         = gsc_remove,
         .driver         = {
                 .name   = "exynos-drm-gsc",
                 .owner  = THIS_MODULE,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.h b/drivers/gpu/drm/exynos/exynos_drm_gsc.h
index b3c3bc618c0f..29ec1c5efcf2 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gsc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.h
@@ -6,24 +6,10 @@
  *      Jinyoung Jeon <jy0.jeon@samsung.com>
  *      Sangmin Lee <lsmin.lee@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_GSC_H_
diff --git a/drivers/gpu/drm/exynos/exynos_drm_hdmi.c b/drivers/gpu/drm/exynos/exynos_drm_hdmi.c
index 55793c46e3c2..850e9950b7da 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_hdmi.c
@@ -385,7 +385,7 @@ static void hdmi_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
                 mixer_ops->iommu_on(ctx->mixer_ctx->ctx, false);
 }
 
-static int __devinit exynos_drm_hdmi_probe(struct platform_device *pdev)
+static int exynos_drm_hdmi_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct exynos_drm_subdrv *subdrv;
@@ -413,7 +413,7 @@ static int __devinit exynos_drm_hdmi_probe(struct platform_device *pdev)
         return 0;
 }
 
-static int __devexit exynos_drm_hdmi_remove(struct platform_device *pdev)
+static int exynos_drm_hdmi_remove(struct platform_device *pdev)
 {
         struct drm_hdmi_context *ctx = platform_get_drvdata(pdev);
 
@@ -426,7 +426,7 @@ static int __devexit exynos_drm_hdmi_remove(struct platform_device *pdev)
 
 struct platform_driver exynos_drm_common_hdmi_driver = {
         .probe          = exynos_drm_hdmi_probe,
-        .remove         = __devexit_p(exynos_drm_hdmi_remove),
+        .remove         = exynos_drm_hdmi_remove,
         .driver         = {
                 .name   = "exynos-drm-hdmi",
                 .owner  = THIS_MODULE,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
index fcc3093ec8fe..784a7e9a766c 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
@@ -3,24 +3,10 @@
  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  * Authoer: Inki Dae <inki.dae@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_HDMI_H_
diff --git a/drivers/gpu/drm/exynos/exynos_drm_iommu.c b/drivers/gpu/drm/exynos/exynos_drm_iommu.c
index 2482b7f96341..3799d5c2b5df 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_iommu.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_iommu.c
@@ -3,24 +3,10 @@
  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  * Author: Inki Dae <inki.dae@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #include <drmP.h>
diff --git a/drivers/gpu/drm/exynos/exynos_drm_iommu.h b/drivers/gpu/drm/exynos/exynos_drm_iommu.h
index 18a0ca190b98..53b7deea8ab7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_iommu.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_iommu.h
@@ -3,24 +3,10 @@
  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  * Authoer: Inki Dae <inki.dae@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_IOMMU_H_
diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
index 49eebe948ed2..0bda96454a02 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
@@ -27,7 +27,7 @@
 #include "exynos_drm_iommu.h"
 
 /*
- * IPP is stand for Image Post Processing and
+ * IPP stands for Image Post Processing and
  * supports image scaler/rotator and input/output DMA operations.
  * using FIMC, GSC, Rotator, so on.
  * IPP is integration device driver of same attribute h/w
@@ -1292,7 +1292,7 @@ static int ipp_start_property(struct exynos_drm_ippdrv *ippdrv,
         DRM_DEBUG_KMS("%s:prop_id[%d]\n", __func__, property->prop_id);
 
         /* store command info in ippdrv */
-        ippdrv->cmd = c_node;
+        ippdrv->c_node = c_node;
 
         if (!ipp_check_mem_list(c_node)) {
                 DRM_DEBUG_KMS("%s:empty memory.\n", __func__);
@@ -1303,7 +1303,7 @@ static int ipp_start_property(struct exynos_drm_ippdrv *ippdrv,
         ret = ipp_set_property(ippdrv, property);
         if (ret) {
                 DRM_ERROR("failed to set property.\n");
-                ippdrv->cmd = NULL;
+                ippdrv->c_node = NULL;
                 return ret;
         }
 
@@ -1487,11 +1487,6 @@ void ipp_sched_cmd(struct work_struct *work)
         mutex_lock(&c_node->cmd_lock);
 
         property = &c_node->property;
-        if (!property) {
-                DRM_ERROR("failed to get property:prop_id[%d]\n",
-                        c_node->property.prop_id);
-                goto err_unlock;
-        }
 
         switch (cmd_work->ctrl) {
         case IPP_CTRL_PLAY:
@@ -1704,7 +1699,7 @@ void ipp_sched_event(struct work_struct *work)
                 return;
         }
 
-        c_node = ippdrv->cmd;
+        c_node = ippdrv->c_node;
         if (!c_node) {
                 DRM_ERROR("failed to get command node.\n");
                 return;
@@ -1888,14 +1883,14 @@ err_clear:
         return;
 }
 
-static int __devinit ipp_probe(struct platform_device *pdev)
+static int ipp_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct ipp_context *ctx;
         struct exynos_drm_subdrv *subdrv;
         int ret;
 
-        ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+        ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
         if (!ctx)
                 return -ENOMEM;
 
@@ -1916,8 +1911,7 @@ static int __devinit ipp_probe(struct platform_device *pdev)
         ctx->event_workq = create_singlethread_workqueue("ipp_event");
         if (!ctx->event_workq) {
                 dev_err(dev, "failed to create event workqueue\n");
-                ret = -EINVAL;
-                goto err_clear;
+                return -EINVAL;
         }
 
         /*
@@ -1958,12 +1952,10 @@ err_cmd_workq:
         destroy_workqueue(ctx->cmd_workq);
 err_event_workq:
         destroy_workqueue(ctx->event_workq);
-err_clear:
-        kfree(ctx);
         return ret;
 }
 
-static int __devexit ipp_remove(struct platform_device *pdev)
+static int ipp_remove(struct platform_device *pdev)
 {
         struct ipp_context *ctx = platform_get_drvdata(pdev);
 
@@ -1985,8 +1977,6 @@ static int __devexit ipp_remove(struct platform_device *pdev)
         destroy_workqueue(ctx->cmd_workq);
         destroy_workqueue(ctx->event_workq);
 
-        kfree(ctx);
-
         return 0;
 }
 
@@ -2050,7 +2040,7 @@ static const struct dev_pm_ops ipp_pm_ops = {
 
 struct platform_driver ipp_driver = {
         .probe          = ipp_probe,
-        .remove         = __devexit_p(ipp_remove),
+        .remove         = ipp_remove,
         .driver         = {
                 .name   = "exynos-drm-ipp",
                 .owner  = THIS_MODULE,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.h b/drivers/gpu/drm/exynos/exynos_drm_ipp.h
index 28ffac95386c..4cadbea7dbde 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.h
@@ -6,24 +6,10 @@
  *      Jinyoung Jeon <jy0.jeon@samsung.com>
  *      Sangmin Lee <lsmin.lee@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_IPP_H_
@@ -160,7 +146,7 @@ struct exynos_drm_ipp_ops {
  * @dedicated: dedicated ipp device.
  * @ops: source, destination operations.
  * @event_workq: event work queue.
- * @cmd: current command information.
+ * @c_node: current command information.
  * @cmd_list: list head for command information.
  * @prop_list: property informations of current ipp driver.
  * @check_property: check property about format, size, buffer.
@@ -178,7 +164,7 @@ struct exynos_drm_ippdrv {
         bool    dedicated;
         struct exynos_drm_ipp_ops       *ops[EXYNOS_DRM_OPS_MAX];
         struct workqueue_struct *event_workq;
-        struct drm_exynos_ipp_cmd_node *cmd;
+        struct drm_exynos_ipp_cmd_node *c_node;
         struct list_head        cmd_list;
         struct drm_exynos_ipp_prop_list *prop_list;
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_rotator.c b/drivers/gpu/drm/exynos/exynos_drm_rotator.c
index 1c2366083c70..e9e83ef688f0 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_rotator.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_rotator.c
@@ -139,7 +139,7 @@ static irqreturn_t rotator_irq_handler(int irq, void *arg)
 {
         struct rot_context *rot = arg;
         struct exynos_drm_ippdrv *ippdrv = &rot->ippdrv;
-        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->cmd;
+        struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
         struct drm_exynos_ipp_event_work *event_work = c_node->event_work;
         enum rot_irq_status irq_status;
         u32 val;
@@ -513,6 +513,7 @@ static inline bool rotator_check_drm_flip(enum drm_exynos_flip flip)
         case EXYNOS_DRM_FLIP_NONE:
         case EXYNOS_DRM_FLIP_VERTICAL:
         case EXYNOS_DRM_FLIP_HORIZONTAL:
+        case EXYNOS_DRM_FLIP_BOTH:
                 return true;
         default:
                 DRM_DEBUG_KMS("%s:invalid flip\n", __func__);
@@ -638,7 +639,7 @@ static int rotator_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
         return 0;
 }
 
-static int __devinit rotator_probe(struct platform_device *pdev)
+static int rotator_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct rot_context *rot;
@@ -655,34 +656,26 @@ static int __devinit rotator_probe(struct platform_device *pdev)
                                 platform_get_device_id(pdev)->driver_data;
 
         rot->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!rot->regs_res) {
-                dev_err(dev, "failed to find registers\n");
-                ret = -ENOENT;
-                goto err_get_resource;
-        }
-
         rot->regs = devm_request_and_ioremap(dev, rot->regs_res);
         if (!rot->regs) {
                 dev_err(dev, "failed to map register\n");
-                ret = -ENXIO;
-                goto err_get_resource;
+                return -ENXIO;
         }
 
         rot->irq = platform_get_irq(pdev, 0);
         if (rot->irq < 0) {
                 dev_err(dev, "failed to get irq\n");
-                ret = rot->irq;
-                goto err_get_irq;
+                return rot->irq;
         }
 
         ret = request_threaded_irq(rot->irq, NULL, rotator_irq_handler,
                         IRQF_ONESHOT, "drm_rotator", rot);
         if (ret < 0) {
                 dev_err(dev, "failed to request irq\n");
-                goto err_get_irq;
+                return ret;
         }
 
-        rot->clock = clk_get(dev, "rotator");
+        rot->clock = devm_clk_get(dev, "rotator");
         if (IS_ERR_OR_NULL(rot->clock)) {
                 dev_err(dev, "failed to get clock\n");
                 ret = PTR_ERR(rot->clock);
@@ -720,17 +713,12 @@ static int __devinit rotator_probe(struct platform_device *pdev)
 err_ippdrv_register:
         devm_kfree(dev, ippdrv->prop_list);
         pm_runtime_disable(dev);
-        clk_put(rot->clock);
 err_clk_get:
         free_irq(rot->irq, rot);
-err_get_irq:
-        devm_iounmap(dev, rot->regs);
-err_get_resource:
-        devm_kfree(dev, rot);
         return ret;
 }
 
-static int __devexit rotator_remove(struct platform_device *pdev)
+static int rotator_remove(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct rot_context *rot = dev_get_drvdata(dev);
@@ -740,12 +728,8 @@ static int __devexit rotator_remove(struct platform_device *pdev)
         exynos_drm_ippdrv_unregister(ippdrv);
 
         pm_runtime_disable(dev);
-        clk_put(rot->clock);
 
         free_irq(rot->irq, rot);
-        devm_iounmap(dev, rot->regs);
-
-        devm_kfree(dev, rot);
 
         return 0;
 }
@@ -845,7 +829,7 @@ static const struct dev_pm_ops rotator_pm_ops = {
 
 struct platform_driver rotator_driver = {
         .probe          = rotator_probe,
-        .remove         = __devexit_p(rotator_remove),
+        .remove         = rotator_remove,
         .id_table       = rotator_driver_ids,
         .driver         = {
                 .name   = "exynos-rot",
diff --git a/drivers/gpu/drm/exynos/exynos_drm_rotator.h b/drivers/gpu/drm/exynos/exynos_drm_rotator.h
index a2d7a14a52b6..71a0b4c0c1e8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_rotator.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_rotator.h
@@ -5,24 +5,10 @@
  *      YoungJun Cho <yj44.cho@samsung.com>
  *      Eunchul Kim <chulspro.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_ROTATOR_H_
diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index 99bfc38dfaa2..d0ca3c4e06c6 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -372,34 +372,6 @@ static struct exynos_drm_manager vidi_manager = {
         .display_ops    = &vidi_display_ops,
 };
 
-static void vidi_finish_pageflip(struct drm_device *drm_dev, int crtc)
-{
-        struct exynos_drm_private *dev_priv = drm_dev->dev_private;
-        struct drm_pending_vblank_event *e, *t;
-        struct timeval now;
-        unsigned long flags;
-
-        spin_lock_irqsave(&drm_dev->event_lock, flags);
-
-        list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
-                        base.link) {
-                /* if event's pipe isn't same as crtc then ignore it. */
-                if (crtc != e->pipe)
-                        continue;
-
-                do_gettimeofday(&now);
-                e->event.sequence = 0;
-                e->event.tv_sec = now.tv_sec;
-                e->event.tv_usec = now.tv_usec;
-
-                list_move_tail(&e->base.link, &e->base.file_priv->event_list);
-                wake_up_interruptible(&e->base.file_priv->event_wait);
-                drm_vblank_put(drm_dev, crtc);
-        }
-
-        spin_unlock_irqrestore(&drm_dev->event_lock, flags);
-}
-
 static void vidi_fake_vblank_handler(struct work_struct *work)
 {
         struct vidi_context *ctx = container_of(work, struct vidi_context,
@@ -424,7 +396,7 @@ static void vidi_fake_vblank_handler(struct work_struct *work)
 
         mutex_unlock(&ctx->lock);
 
-        vidi_finish_pageflip(subdrv->drm_dev, manager->pipe);
+        exynos_drm_crtc_finish_pageflip(subdrv->drm_dev, manager->pipe);
 }
 
 static int vidi_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
@@ -609,7 +581,7 @@ int vidi_connection_ioctl(struct drm_device *drm_dev, void *data,
         return 0;
 }
 
-static int __devinit vidi_probe(struct platform_device *pdev)
+static int vidi_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct vidi_context *ctx;
@@ -645,7 +617,7 @@ static int __devinit vidi_probe(struct platform_device *pdev)
         return 0;
 }
 
-static int __devexit vidi_remove(struct platform_device *pdev)
+static int vidi_remove(struct platform_device *pdev)
 {
         struct vidi_context *ctx = platform_get_drvdata(pdev);
 
@@ -683,7 +655,7 @@ static const struct dev_pm_ops vidi_pm_ops = {
 
 struct platform_driver vidi_driver = {
         .probe          = vidi_probe,
-        .remove         = __devexit_p(vidi_remove),
+        .remove         = vidi_remove,
         .driver         = {
                 .name   = "exynos-drm-vidi",
                 .owner  = THIS_MODULE,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.h b/drivers/gpu/drm/exynos/exynos_drm_vidi.h
index a4babe4e65d7..1e5fdaa36ccc 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.h
@@ -3,24 +3,10 @@
  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  * Author: Inki Dae <inki.dae@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_DRM_VIDI_H_
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 2c46b6c0b82c..41ff79d8ac8e 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -2305,7 +2305,7 @@ static irqreturn_t hdmi_internal_irq_thread(int irq, void *arg)
         return IRQ_HANDLED;
 }
 
-static int __devinit hdmi_resources_init(struct hdmi_context *hdata)
+static int hdmi_resources_init(struct hdmi_context *hdata)
 {
         struct device *dev = hdata->dev;
         struct hdmi_resources *res = &hdata->res;
@@ -2451,7 +2451,7 @@ static struct of_device_id hdmi_match_types[] = {
 };
 #endif
 
-static int __devinit hdmi_probe(struct platform_device *pdev)
+static int hdmi_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct exynos_drm_hdmi_context *drm_hdmi_ctx;
@@ -2607,7 +2607,7 @@ err_ddc:
         return ret;
 }
 
-static int __devexit hdmi_remove(struct platform_device *pdev)
+static int hdmi_remove(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct exynos_drm_hdmi_context *ctx = platform_get_drvdata(pdev);
@@ -2708,7 +2708,7 @@ static const struct dev_pm_ops hdmi_pm_ops = {
 
 struct platform_driver hdmi_driver = {
         .probe          = hdmi_probe,
-        .remove         = __devexit_p(hdmi_remove),
+        .remove         = hdmi_remove,
         .id_table = hdmi_driver_types,
         .driver         = {
                 .name   = "exynos-hdmi",
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.h b/drivers/gpu/drm/exynos/exynos_hdmi.h
index 1c3b6d8f1fe7..0ddf3957de15 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.h
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.h
@@ -5,24 +5,10 @@
  *      Inki Dae <inki.dae@samsung.com>
  *      Seung-Woo Kim <sw0312.kim@samsung.com>
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef _EXYNOS_HDMI_H_
diff --git a/drivers/gpu/drm/exynos/exynos_hdmiphy.c b/drivers/gpu/drm/exynos/exynos_hdmiphy.c
index 6206056f4a33..ea49d132ecf6 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmiphy.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmiphy.c
@@ -64,7 +64,7 @@ struct i2c_driver hdmiphy_driver = {
         },
         .id_table = hdmiphy_id,
         .probe          = hdmiphy_probe,
-        .remove         = __devexit_p(hdmiphy_remove),
+        .remove         = hdmiphy_remove,
         .command                = NULL,
 };
 EXPORT_SYMBOL(hdmiphy_driver);
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 21db89530fc7..c187ea33b748 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -35,6 +35,7 @@
 #include <drm/exynos_drm.h>
 
 #include "exynos_drm_drv.h"
+#include "exynos_drm_crtc.h"
 #include "exynos_drm_hdmi.h"
 #include "exynos_drm_iommu.h"
 
@@ -949,35 +950,6 @@ static struct exynos_mixer_ops mixer_ops = {
         .win_disable            = mixer_win_disable,
 };
 
-/* for pageflip event */
-static void mixer_finish_pageflip(struct drm_device *drm_dev, int crtc)
-{
-        struct exynos_drm_private *dev_priv = drm_dev->dev_private;
-        struct drm_pending_vblank_event *e, *t;
-        struct timeval now;
-        unsigned long flags;
-
-        spin_lock_irqsave(&drm_dev->event_lock, flags);
-
-        list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
-                        base.link) {
-                /* if event's pipe isn't same as crtc then ignore it. */
-                if (crtc != e->pipe)
-                        continue;
-
-                do_gettimeofday(&now);
-                e->event.sequence = 0;
-                e->event.tv_sec = now.tv_sec;
-                e->event.tv_usec = now.tv_usec;
-
-                list_move_tail(&e->base.link, &e->base.file_priv->event_list);
-                wake_up_interruptible(&e->base.file_priv->event_wait);
-                drm_vblank_put(drm_dev, crtc);
-        }
-
-        spin_unlock_irqrestore(&drm_dev->event_lock, flags);
-}
-
 static irqreturn_t mixer_irq_handler(int irq, void *arg)
 {
         struct exynos_drm_hdmi_context *drm_hdmi_ctx = arg;
@@ -1006,7 +978,8 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
                 }
 
                 drm_handle_vblank(drm_hdmi_ctx->drm_dev, ctx->pipe);
-                mixer_finish_pageflip(drm_hdmi_ctx->drm_dev, ctx->pipe);
+                exynos_drm_crtc_finish_pageflip(drm_hdmi_ctx->drm_dev,
+                                ctx->pipe);
 
                 /* set wait vsync event to zero and wake up queue. */
                 if (atomic_read(&ctx->wait_vsync_event)) {
@@ -1029,8 +1002,8 @@ out:
         return IRQ_HANDLED;
 }
 
-static int __devinit mixer_resources_init(struct exynos_drm_hdmi_context *ctx,
-                                 struct platform_device *pdev)
+static int mixer_resources_init(struct exynos_drm_hdmi_context *ctx,
+                                struct platform_device *pdev)
 {
         struct mixer_context *mixer_ctx = ctx->ctx;
         struct device *dev = &pdev->dev;
@@ -1081,8 +1054,8 @@ static int __devinit mixer_resources_init(struct exynos_drm_hdmi_context *ctx,
         return 0;
 }
 
-static int __devinit vp_resources_init(struct exynos_drm_hdmi_context *ctx,
-                                 struct platform_device *pdev)
+static int vp_resources_init(struct exynos_drm_hdmi_context *ctx,
+                             struct platform_device *pdev)
 {
         struct mixer_context *mixer_ctx = ctx->ctx;
         struct device *dev = &pdev->dev;
@@ -1155,7 +1128,7 @@ static struct of_device_id mixer_match_types[] = {
         }
 };
 
-static int __devinit mixer_probe(struct platform_device *pdev)
+static int mixer_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct exynos_drm_hdmi_context *drm_hdmi_ctx;
@@ -1316,6 +1289,6 @@ struct platform_driver mixer_driver = {
                 .of_match_table = mixer_match_types,
         },
         .probe = mixer_probe,
-        .remove = __devexit_p(mixer_remove),
+        .remove = mixer_remove,
         .id_table       = mixer_driver_types,
 };
diff --git a/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c b/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c
index 4a07ab596174..771ff66711af 100644
--- a/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c
+++ b/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c
@@ -700,7 +700,7 @@ static struct i2c_driver tc35876x_bridge_i2c_driver = {
         },
         .id_table = tc35876x_bridge_id,
         .probe = tc35876x_bridge_probe,
-        .remove = __devexit_p(tc35876x_bridge_remove),
+        .remove = tc35876x_bridge_remove,
 };
 
 /* LCD panel I2C */
@@ -741,7 +741,7 @@ static struct i2c_driver cmi_lcd_i2c_driver = {
         },
         .id_table = cmi_lcd_i2c_id,
         .probe = cmi_lcd_i2c_probe,
-        .remove = __devexit_p(cmi_lcd_i2c_remove),
+        .remove = cmi_lcd_i2c_remove,
 };
 
 /* HACK to create I2C device while it's not created by platform code */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e6a11ca85eaf..7944d301518a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -641,6 +641,7 @@ static void i915_ring_error_state(struct seq_file *m,
         seq_printf(m, "%s command stream:\n", ring_str(ring));
         seq_printf(m, "  HEAD: 0x%08x\n", error->head[ring]);
         seq_printf(m, "  TAIL: 0x%08x\n", error->tail[ring]);
+        seq_printf(m, "  CTL: 0x%08x\n", error->ctl[ring]);
         seq_printf(m, "  ACTHD: 0x%08x\n", error->acthd[ring]);
         seq_printf(m, "  IPEIR: 0x%08x\n", error->ipeir[ring]);
         seq_printf(m, "  IPEHR: 0x%08x\n", error->ipehr[ring]);
@@ -693,6 +694,8 @@ static int i915_error_state(struct seq_file *m, void *unused)
         seq_printf(m, "EIR: 0x%08x\n", error->eir);
         seq_printf(m, "IER: 0x%08x\n", error->ier);
         seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
+        seq_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
+        seq_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
         seq_printf(m, "CCID: 0x%08x\n", error->ccid);
 
         for (i = 0; i < dev_priv->num_fence_regs; i++)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 8f63cd5de4b4..99daa896105d 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -989,6 +989,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
         case I915_PARAM_HAS_SECURE_BATCHES:
                 value = capable(CAP_SYS_ADMIN);
                 break;
+        case I915_PARAM_HAS_PINNED_BATCHES:
+                value = 1;
+                break;
         default:
                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
                                  param->param);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 530db83ef320..117265840b1f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -877,8 +877,7 @@ int i915_reset(struct drm_device *dev)
         return 0;
 }
 
-static int __devinit
-i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
         struct intel_device_info *intel_info =
                 (struct intel_device_info *) ent->driver_data;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 557843dd4b2e..12ab3bdea54d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -188,10 +188,13 @@ struct drm_i915_error_state {
         u32 pgtbl_er;
         u32 ier;
         u32 ccid;
+        u32 derrmr;
+        u32 forcewake;
         bool waiting[I915_NUM_RINGS];
         u32 pipestat[I915_MAX_PIPES];
         u32 tail[I915_NUM_RINGS];
         u32 head[I915_NUM_RINGS];
+        u32 ctl[I915_NUM_RINGS];
         u32 ipeir[I915_NUM_RINGS];
         u32 ipehr[I915_NUM_RINGS];
         u32 instdone[I915_NUM_RINGS];
@@ -780,6 +783,7 @@ typedef struct drm_i915_private {
                 struct i915_hw_ppgtt *aliasing_ppgtt;
 
                 struct shrinker inactive_shrinker;
+                bool shrinker_no_lock_stealing;
 
                 /**
                  * List of objects currently involved in rendering.
@@ -1100,6 +1104,7 @@ struct drm_i915_gem_object {
          */
         atomic_t pending_flip;
 };
+#define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
 
 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
 
@@ -1166,6 +1171,9 @@ struct drm_i915_file_private {
 #define IS_IVB_GT1(dev)         ((dev)->pci_device == 0x0156 || \
                                  (dev)->pci_device == 0x0152 || \
                                  (dev)->pci_device == 0x015a)
+#define IS_SNB_GT1(dev)         ((dev)->pci_device == 0x0102 || \
+                                 (dev)->pci_device == 0x0106 || \
+                                 (dev)->pci_device == 0x010A)
 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
@@ -1196,6 +1204,9 @@ struct drm_i915_file_private {
 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
 
+/* Early gen2 have a totally busted CS tlb and require pinned batches. */
+#define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
+
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
  */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 742206e45103..8febea6daa08 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1517,9 +1517,11 @@ static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
         if (obj->base.map_list.map)
                 return 0;
 
+        dev_priv->mm.shrinker_no_lock_stealing = true;
+
         ret = drm_gem_create_mmap_offset(&obj->base);
         if (ret != -ENOSPC)
-                return ret;
+                goto out;
 
         /* Badly fragmented mmap space? The only way we can recover
          * space is by destroying unwanted objects. We can't randomly release
@@ -1531,10 +1533,14 @@ static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
         ret = drm_gem_create_mmap_offset(&obj->base);
         if (ret != -ENOSPC)
-                return ret;
+                goto out;
 
         i915_gem_shrink_all(dev_priv);
-        return drm_gem_create_mmap_offset(&obj->base);
+        ret = drm_gem_create_mmap_offset(&obj->base);
+out:
+        dev_priv->mm.shrinker_no_lock_stealing = false;
+
+        return ret;
 }
 
 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
@@ -1711,7 +1717,8 @@ i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
 }
 
 static long
-i915_gem_purge(struct drm_i915_private *dev_priv, long target)
+__i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
+                  bool purgeable_only)
 {
         struct drm_i915_gem_object *obj, *next;
         long count = 0;
@@ -1719,7 +1726,7 @@ i915_gem_purge(struct drm_i915_private *dev_priv, long target)
         list_for_each_entry_safe(obj, next,
                                  &dev_priv->mm.unbound_list,
                                  gtt_list) {
-                if (i915_gem_object_is_purgeable(obj) &&
+                if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
                     i915_gem_object_put_pages(obj) == 0) {
                         count += obj->base.size >> PAGE_SHIFT;
                         if (count >= target)
@@ -1730,7 +1737,7 @@ i915_gem_purge(struct drm_i915_private *dev_priv, long target)
         list_for_each_entry_safe(obj, next,
                                  &dev_priv->mm.inactive_list,
                                  mm_list) {
-                if (i915_gem_object_is_purgeable(obj) &&
+                if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
                     i915_gem_object_unbind(obj) == 0 &&
                     i915_gem_object_put_pages(obj) == 0) {
                         count += obj->base.size >> PAGE_SHIFT;
@@ -1742,6 +1749,12 @@ i915_gem_purge(struct drm_i915_private *dev_priv, long target)
         return count;
 }
 
+static long
+i915_gem_purge(struct drm_i915_private *dev_priv, long target)
+{
+        return __i915_gem_shrink(dev_priv, target, true);
+}
+
 static void
 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
 {
@@ -2890,7 +2903,7 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
 {
         struct drm_device *dev = obj->base.dev;
         drm_i915_private_t *dev_priv = dev->dev_private;
-        struct drm_mm_node *free_space;
+        struct drm_mm_node *node;
         u32 size, fence_size, fence_alignment, unfenced_alignment;
         bool mappable, fenceable;
         int ret;
@@ -2936,66 +2949,54 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
 
         i915_gem_object_pin_pages(obj);
 
+        node = kzalloc(sizeof(*node), GFP_KERNEL);
+        if (node == NULL) {
+                i915_gem_object_unpin_pages(obj);
+                return -ENOMEM;
+        }
+
  search_free:
         if (map_and_fenceable)
-                free_space = drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
-                                                               size, alignment, obj->cache_level,
-                                                               0, dev_priv->mm.gtt_mappable_end,
-                                                               false);
+                ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
+                                                          size, alignment, obj->cache_level,
+                                                          0, dev_priv->mm.gtt_mappable_end);
         else
-                free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
-                                                      size, alignment, obj->cache_level,
-                                                      false);
-
-        if (free_space != NULL) {
-                if (map_and_fenceable)
-                        free_space =
-                                drm_mm_get_block_range_generic(free_space,
-                                                               size, alignment, obj->cache_level,
-                                                               0, dev_priv->mm.gtt_mappable_end,
-                                                               false);
-                else
-                        free_space =
-                                drm_mm_get_block_generic(free_space,
-                                                         size, alignment, obj->cache_level,
-                                                         false);
-        }
-        if (free_space == NULL) {
+                ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node,
+                                                 size, alignment, obj->cache_level);
+        if (ret) {
                 ret = i915_gem_evict_something(dev, size, alignment,
                                                obj->cache_level,
                                                map_and_fenceable,
                                                nonblocking);
-                if (ret) {
-                        i915_gem_object_unpin_pages(obj);
-                        return ret;
-                }
+                if (ret == 0)
+                        goto search_free;
 
-                goto search_free;
+                i915_gem_object_unpin_pages(obj);
+                kfree(node);
+                return ret;
         }
-        if (WARN_ON(!i915_gem_valid_gtt_space(dev,
-                                              free_space,
-                                              obj->cache_level))) {
+        if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) {
                 i915_gem_object_unpin_pages(obj);
-                drm_mm_put_block(free_space);
+                drm_mm_put_block(node);
                 return -EINVAL;
         }
 
         ret = i915_gem_gtt_prepare_object(obj);
         if (ret) {
                 i915_gem_object_unpin_pages(obj);
-                drm_mm_put_block(free_space);
+                drm_mm_put_block(node);
                 return ret;
         }
 
         list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
 
-        obj->gtt_space = free_space;
-        obj->gtt_offset = free_space->start;
+        obj->gtt_space = node;
+        obj->gtt_offset = node->start;
 
         fenceable =
-                free_space->size == fence_size &&
-                (free_space->start & (fence_alignment - 1)) == 0;
+                node->size == fence_size &&
+                (node->start & (fence_alignment - 1)) == 0;
 
         mappable =
                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
@@ -3528,14 +3529,15 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data,
                 goto out;
         }
 
-        obj->user_pin_count++;
-        obj->pin_filp = file;
-        if (obj->user_pin_count == 1) {
+        if (obj->user_pin_count == 0) {
                 ret = i915_gem_object_pin(obj, args->alignment, true, false);
                 if (ret)
                         goto out;
         }
 
+        obj->user_pin_count++;
+        obj->pin_filp = file;
+
         /* XXX - flush the CPU caches for pinned objects
          * as the X server doesn't manage domains yet
          */
@@ -4392,12 +4394,18 @@ i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
                         return 0;
 
+                if (dev_priv->mm.shrinker_no_lock_stealing)
+                        return 0;
+
                 unlock = false;
         }
 
         if (nr_to_scan) {
                 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
                 if (nr_to_scan > 0)
+                        nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
+                                                        false);
+                if (nr_to_scan > 0)
                         i915_gem_shrink_all(dev_priv);
         }
 
@@ -4405,7 +4413,7 @@ i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
         list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
                 if (obj->pages_pin_count == 0)
                         cnt += obj->base.size >> PAGE_SHIFT;
-        list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
+        list_for_each_entry(obj, &dev_priv->mm.inactive_list, gtt_list)
                 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
                         cnt += obj->base.size >> PAGE_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
index 773ef77b6c22..abeaafef6d7e 100644
--- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
@@ -226,7 +226,7 @@ struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
 {
         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
 
-        return dma_buf_export(obj, &i915_dmabuf_ops, obj->base.size, 0600);
+        return dma_buf_export(obj, &i915_dmabuf_ops, obj->base.size, flags);
 }
 
 static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj)
@@ -266,7 +266,12 @@ struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
                 obj = dma_buf->priv;
                 /* is it from our device? */
                 if (obj->base.dev == dev) {
+                        /*
+                         * Importing dmabuf exported from out own gem increases
+                         * refcount on gem itself instead of f_count of dmabuf.
+                         */
                         drm_gem_object_reference(&obj->base);
+                        dma_buf_put(dma_buf);
                         return &obj->base;
                 }
         }
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index ee8f97f0539e..26d08bb58218 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -539,6 +539,8 @@ i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
         total = 0;
         for (i = 0; i < count; i++) {
                 struct drm_i915_gem_relocation_entry __user *user_relocs;
+                u64 invalid_offset = (u64)-1;
+                int j;
 
                 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
 
@@ -549,6 +551,25 @@ i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
                         goto err;
                 }
 
+                /* As we do not update the known relocation offsets after
+                 * relocating (due to the complexities in lock handling),
+                 * we need to mark them as invalid now so that we force the
+                 * relocation processing next time. Just in case the target
+                 * object is evicted and then rebound into its old
+                 * presumed_offset before the next execbuffer - if that
+                 * happened we would make the mistake of assuming that the
+                 * relocations were valid.
+                 */
+                for (j = 0; j < exec[i].relocation_count; j++) {
+                        if (copy_to_user(&user_relocs[j].presumed_offset,
+                                         &invalid_offset,
+                                         sizeof(invalid_offset))) {
+                                ret = -EFAULT;
+                                mutex_lock(&dev->struct_mutex);
+                                goto err;
+                        }
+                }
+
                 reloc_offset[i] = total;
                 total += exec[i].relocation_count;
         }
@@ -808,6 +829,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 
                 flags |= I915_DISPATCH_SECURE;
         }
+        if (args->flags & I915_EXEC_IS_PINNED)
+                flags |= I915_DISPATCH_PINNED;
 
         switch (args->flags & I915_EXEC_RING_MASK) {
         case I915_EXEC_DEFAULT:
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a4dc97f8b9f0..fe843389c7b4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1087,6 +1087,18 @@ i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
         if (!ring->get_seqno)
                 return NULL;
 
+        if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
+                u32 acthd = I915_READ(ACTHD);
+
+                if (WARN_ON(ring->id != RCS))
+                        return NULL;
+
+                obj = ring->private;
+                if (acthd >= obj->gtt_offset &&
+                    acthd < obj->gtt_offset + obj->base.size)
+                        return i915_error_object_create(dev_priv, obj);
+        }
+
         seqno = ring->get_seqno(ring, false);
         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
                 if (obj->ring != ring)
@@ -1145,6 +1157,7 @@ static void i915_record_ring_state(struct drm_device *dev,
         error->acthd[ring->id] = intel_ring_get_active_head(ring);
         error->head[ring->id] = I915_READ_HEAD(ring);
         error->tail[ring->id] = I915_READ_TAIL(ring);
+        error->ctl[ring->id] = I915_READ_CTL(ring);
 
         error->cpu_ring_head[ring->id] = ring->head;
         error->cpu_ring_tail[ring->id] = ring->tail;
@@ -1239,6 +1252,16 @@ static void i915_capture_error_state(struct drm_device *dev)
         else
                 error->ier = I915_READ(IER);
 
+        if (INTEL_INFO(dev)->gen >= 6)
+                error->derrmr = I915_READ(DERRMR);
+
+        if (IS_VALLEYVIEW(dev))
+                error->forcewake = I915_READ(FORCEWAKE_VLV);
+        else if (INTEL_INFO(dev)->gen >= 7)
+                error->forcewake = I915_READ(FORCEWAKE_MT);
+        else if (INTEL_INFO(dev)->gen == 6)
+                error->forcewake = I915_READ(FORCEWAKE);
+
         for_each_pipe(pipe)
                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f75cfaf1c3f..b401788e1791 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -512,11 +512,14 @@
 #define GEN7_ERR_INT    0x44040
 #define   ERR_INT_MMIO_UNCLAIMED (1<<13)
 
+#define DERRMR          0x44050
+
 /* GM45+ chicken bits -- debug workaround bits that may be required
  * for various sorts of correct behavior.  The top 16 bits of each are
  * the enables for writing to the corresponding low bit.
  */
 #define _3D_CHICKEN     0x02084
+#define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB      (1 << 10)
 #define _3D_CHICKEN2    0x0208c
 /* Disables pipelining of read flushes past the SF-WIZ interface.
  * Required on all Ironlake steppings according to the B-Spec, but the
@@ -532,7 +535,8 @@
 # define MI_FLUSH_ENABLE                                (1 << 12)
 
 #define GEN6_GT_MODE    0x20d0
-#define   GEN6_GT_MODE_HI       (1 << 9)
+#define   GEN6_GT_MODE_HI                               (1 << 9)
+#define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE             (1 << 5)
 
 #define GFX_MODE        0x02520
 #define GFX_MODE_GEN7   0x0229c
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5d127e068950..da1ad9c80bb5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8144,10 +8144,6 @@ intel_modeset_stage_output_state(struct drm_device *dev,
                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
                         config->mode_changed = true;
                 }
-
-                /* Disable all disconnected encoders. */
-                if (connector->base.status == connector_status_disconnected)
-                        connector->new_encoder = NULL;
         }
         /* connector->new_encoder is now updated for all connectors. */
 
@@ -8602,19 +8598,30 @@ int intel_framebuffer_init(struct drm_device *dev,
 {
         int ret;
 
-        if (obj->tiling_mode == I915_TILING_Y)
+        if (obj->tiling_mode == I915_TILING_Y) {
+                DRM_DEBUG("hardware does not support tiling Y\n");
                 return -EINVAL;
+        }
 
-        if (mode_cmd->pitches[0] & 63)
+        if (mode_cmd->pitches[0] & 63) {
+                DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
+                          mode_cmd->pitches[0]);
                 return -EINVAL;
+        }
 
         /* FIXME <= Gen4 stride limits are bit unclear */
-        if (mode_cmd->pitches[0] > 32768)
+        if (mode_cmd->pitches[0] > 32768) {
+                DRM_DEBUG("pitch (%d) must be at less than 32768\n",
+                          mode_cmd->pitches[0]);
                 return -EINVAL;
+        }
 
         if (obj->tiling_mode != I915_TILING_NONE &&
-            mode_cmd->pitches[0] != obj->stride)
+            mode_cmd->pitches[0] != obj->stride) {
+                DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
+                          mode_cmd->pitches[0], obj->stride);
                 return -EINVAL;
+        }
 
         /* Reject formats not supported by any plane early. */
         switch (mode_cmd->pixel_format) {
@@ -8625,8 +8632,10 @@ int intel_framebuffer_init(struct drm_device *dev,
                 break;
         case DRM_FORMAT_XRGB1555:
         case DRM_FORMAT_ARGB1555:
-                if (INTEL_INFO(dev)->gen > 3)
+                if (INTEL_INFO(dev)->gen > 3) {
+                        DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
                         return -EINVAL;
+                }
                 break;
         case DRM_FORMAT_XBGR8888:
         case DRM_FORMAT_ABGR8888:
@@ -8634,18 +8643,22 @@ int intel_framebuffer_init(struct drm_device *dev,
         case DRM_FORMAT_ARGB2101010:
         case DRM_FORMAT_XBGR2101010:
         case DRM_FORMAT_ABGR2101010:
-                if (INTEL_INFO(dev)->gen < 4)
+                if (INTEL_INFO(dev)->gen < 4) {
+                        DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
                         return -EINVAL;
+                }
                 break;
         case DRM_FORMAT_YUYV:
         case DRM_FORMAT_UYVY:
         case DRM_FORMAT_YVYU:
         case DRM_FORMAT_VYUY:
-                if (INTEL_INFO(dev)->gen < 6)
+                if (INTEL_INFO(dev)->gen < 5) {
+                        DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
                         return -EINVAL;
+                }
                 break;
         default:
-                DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
+                DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
                 return -EINVAL;
         }
 
@@ -9167,6 +9180,23 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
          * the crtc fixup. */
 }
 
+static void i915_redisable_vga(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 vga_reg;
+
+        if (HAS_PCH_SPLIT(dev))
+                vga_reg = CPU_VGACNTRL;
+        else
+                vga_reg = VGACNTRL;
+
+        if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
+                DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
+                I915_WRITE(vga_reg, VGA_DISP_DISABLE);
+                POSTING_READ(vga_reg);
+        }
+}
+
 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
  * and i915 state tracking structures. */
 void intel_modeset_setup_hw_state(struct drm_device *dev,
@@ -9275,6 +9305,8 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
                         intel_set_mode(&crtc->base, &crtc->base.mode,
                                        crtc->base.x, crtc->base.y, crtc->base.fb);
                 }
+
+                i915_redisable_vga(dev);
         } else {
                 intel_modeset_update_staged_output_state(dev);
         }
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1b63d55318a0..fb3715b4b09d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2579,7 +2579,8 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
 
 static void
 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
-                                    struct intel_dp *intel_dp)
+                                    struct intel_dp *intel_dp,
+                                    struct edp_power_seq *out)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct edp_power_seq cur, vbt, spec, final;
@@ -2650,16 +2651,35 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
 #undef get_delay
 
+        DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
+                      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
+                      intel_dp->panel_power_cycle_delay);
+
+        DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
+                      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
+
+        if (out)
+                *out = final;
+}
+
+static void
+intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
+                                              struct intel_dp *intel_dp,
+                                              struct edp_power_seq *seq)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 pp_on, pp_off, pp_div;
+
         /* And finally store the new values in the power sequencer. */
-        pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
-                (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
-        pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
-                 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
+        pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
+                (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
+        pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
+                 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
         /* Compute the divisor for the pp clock, simply match the Bspec
          * formula. */
         pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
                         << PP_REFERENCE_DIVIDER_SHIFT;
-        pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
+        pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
 
         /* Haswell doesn't have any port selection bits for the panel
@@ -2675,14 +2695,6 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
         I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
         I915_WRITE(PCH_PP_DIVISOR, pp_div);
 
-
-        DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
-                      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
-                      intel_dp->panel_power_cycle_delay);
-
-        DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
-                      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
-
         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
                       I915_READ(PCH_PP_ON_DELAYS),
                       I915_READ(PCH_PP_OFF_DELAYS),
@@ -2699,6 +2711,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
         struct drm_device *dev = intel_encoder->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct drm_display_mode *fixed_mode = NULL;
+        struct edp_power_seq power_seq = { 0 };
         enum port port = intel_dig_port->port;
         const char *name = NULL;
         int type;
@@ -2771,7 +2784,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
         }
 
         if (is_edp(intel_dp))
-                intel_dp_init_panel_power_sequencer(dev, intel_dp);
+                intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
 
         intel_dp_i2c_init(intel_dp, intel_connector, name);
 
@@ -2798,6 +2811,10 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
                         return;
                 }
 
+                /* We now know it's not a ghost, init power sequence regs. */
+                intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
+                                                              &power_seq);
+
                 ironlake_edp_panel_vdd_on(intel_dp);
                 edid = drm_get_edid(connector, &intel_dp->adapter);
                 if (edid) {
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index b9a660a53677..17aee74258ad 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -776,14 +776,6 @@ static const struct dmi_system_id intel_no_lvds[] = {
         },
         {
                 .callback = intel_no_lvds_dmi_callback,
-                .ident = "ZOTAC ZBOXSD-ID12/ID13",
-                .matches = {
-                        DMI_MATCH(DMI_BOARD_VENDOR, "ZOTAC"),
-                        DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),
-                },
-        },
-        {
-                .callback = intel_no_lvds_dmi_callback,
                 .ident = "Gigabyte GA-D525TUD",
                 .matches = {
                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 496caa73eb70..3280cffe50f4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -44,6 +44,14 @@
  * i915.i915_enable_fbc parameter
  */
 
+static bool intel_crtc_active(struct drm_crtc *crtc)
+{
+        /* Be paranoid as we can arrive here with only partial
+         * state retrieved from the hardware during setup.
+         */
+        return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
+}
+
 static void i8xx_disable_fbc(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -405,9 +413,8 @@ void intel_update_fbc(struct drm_device *dev)
          *   - going to an unsupported config (interlace, pixel multiply, etc.)
          */
         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
-                if (tmp_crtc->enabled &&
-                    !to_intel_crtc(tmp_crtc)->primary_disabled &&
-                    tmp_crtc->fb) {
+                if (intel_crtc_active(tmp_crtc) &&
+                    !to_intel_crtc(tmp_crtc)->primary_disabled) {
                         if (crtc) {
                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
@@ -992,7 +999,7 @@ static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
         struct drm_crtc *crtc, *enabled = NULL;
 
         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-                if (crtc->enabled && crtc->fb) {
+                if (intel_crtc_active(crtc)) {
                         if (enabled)
                                 return NULL;
                         enabled = crtc;
@@ -1086,7 +1093,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
         int entries, tlb_miss;
 
         crtc = intel_get_crtc_for_plane(dev, plane);
-        if (crtc->fb == NULL || !crtc->enabled) {
+        if (!intel_crtc_active(crtc)) {
                 *cursor_wm = cursor->guard_size;
                 *plane_wm = display->guard_size;
                 return false;
@@ -1215,7 +1222,7 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
         int entries;
 
         crtc = intel_get_crtc_for_plane(dev, plane);
-        if (crtc->fb == NULL || !crtc->enabled)
+        if (!intel_crtc_active(crtc))
                 return false;
 
         clock = crtc->mode.clock;       /* VESA DOT Clock */
@@ -1286,6 +1293,7 @@ static void valleyview_update_wm(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
         int plane_sr, cursor_sr;
+        int ignore_plane_sr, ignore_cursor_sr;
         unsigned int enabled = 0;
 
         vlv_update_drain_latency(dev);
@@ -1302,17 +1310,23 @@ static void valleyview_update_wm(struct drm_device *dev)
                             &planeb_wm, &cursorb_wm))
                 enabled |= 2;
 
-        plane_sr = cursor_sr = 0;
         if (single_plane_enabled(enabled) &&
             g4x_compute_srwm(dev, ffs(enabled) - 1,
                              sr_latency_ns,
                              &valleyview_wm_info,
                              &valleyview_cursor_wm_info,
-                             &plane_sr, &cursor_sr))
+                             &plane_sr, &ignore_cursor_sr) &&
+            g4x_compute_srwm(dev, ffs(enabled) - 1,
+                             2*sr_latency_ns,
+                             &valleyview_wm_info,
+                             &valleyview_cursor_wm_info,
+                             &ignore_plane_sr, &cursor_sr)) {
                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
-        else
+        } else {
                 I915_WRITE(FW_BLC_SELF_VLV,
                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
+                plane_sr = cursor_sr = 0;
+        }
 
         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
                       planea_wm, cursora_wm,
@@ -1352,17 +1366,18 @@ static void g4x_update_wm(struct drm_device *dev)
                             &planeb_wm, &cursorb_wm))
                 enabled |= 2;
 
-        plane_sr = cursor_sr = 0;
         if (single_plane_enabled(enabled) &&
             g4x_compute_srwm(dev, ffs(enabled) - 1,
                              sr_latency_ns,
                              &g4x_wm_info,
                              &g4x_cursor_wm_info,
-                             &plane_sr, &cursor_sr))
+                             &plane_sr, &cursor_sr)) {
                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
-        else
+        } else {
                 I915_WRITE(FW_BLC_SELF,
                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
+                plane_sr = cursor_sr = 0;
+        }
 
         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
                       planea_wm, cursora_wm,
@@ -1468,7 +1483,7 @@ static void i9xx_update_wm(struct drm_device *dev)
 
         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
         crtc = intel_get_crtc_for_plane(dev, 0);
-        if (crtc->enabled && crtc->fb) {
+        if (intel_crtc_active(crtc)) {
                 int cpp = crtc->fb->bits_per_pixel / 8;
                 if (IS_GEN2(dev))
                         cpp = 4;
@@ -1482,7 +1497,7 @@ static void i9xx_update_wm(struct drm_device *dev)
 
         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
         crtc = intel_get_crtc_for_plane(dev, 1);
-        if (crtc->enabled && crtc->fb) {
+        if (intel_crtc_active(crtc)) {
                 int cpp = crtc->fb->bits_per_pixel / 8;
                 if (IS_GEN2(dev))
                         cpp = 4;
@@ -1811,8 +1826,110 @@ static void sandybridge_update_wm(struct drm_device *dev)
                 enabled |= 2;
         }
 
-        if ((dev_priv->num_pipe == 3) &&
-            g4x_compute_wm0(dev, 2,
+        /*
+         * Calculate and update the self-refresh watermark only when one
+         * display plane is used.
+         *
+         * SNB support 3 levels of watermark.
+         *
+         * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
+         * and disabled in the descending order
+         *
+         */
+        I915_WRITE(WM3_LP_ILK, 0);
+        I915_WRITE(WM2_LP_ILK, 0);
+        I915_WRITE(WM1_LP_ILK, 0);
+
+        if (!single_plane_enabled(enabled) ||
+            dev_priv->sprite_scaling_enabled)
+                return;
+        enabled = ffs(enabled) - 1;
+
+        /* WM1 */
+        if (!ironlake_compute_srwm(dev, 1, enabled,
+                                   SNB_READ_WM1_LATENCY() * 500,
+                                   &sandybridge_display_srwm_info,
+                                   &sandybridge_cursor_srwm_info,
+                                   &fbc_wm, &plane_wm, &cursor_wm))
+                return;
+
+        I915_WRITE(WM1_LP_ILK,
+                   WM1_LP_SR_EN |
+                   (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
+                   (fbc_wm << WM1_LP_FBC_SHIFT) |
+                   (plane_wm << WM1_LP_SR_SHIFT) |
+                   cursor_wm);
+
+        /* WM2 */
+        if (!ironlake_compute_srwm(dev, 2, enabled,
+                                   SNB_READ_WM2_LATENCY() * 500,
+                                   &sandybridge_display_srwm_info,
+                                   &sandybridge_cursor_srwm_info,
+                                   &fbc_wm, &plane_wm, &cursor_wm))
+                return;
+
+        I915_WRITE(WM2_LP_ILK,
+                   WM2_LP_EN |
+                   (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
+                   (fbc_wm << WM1_LP_FBC_SHIFT) |
+                   (plane_wm << WM1_LP_SR_SHIFT) |
+                   cursor_wm);
+
+        /* WM3 */
+        if (!ironlake_compute_srwm(dev, 3, enabled,
+                                   SNB_READ_WM3_LATENCY() * 500,
+                                   &sandybridge_display_srwm_info,
+                                   &sandybridge_cursor_srwm_info,
+                                   &fbc_wm, &plane_wm, &cursor_wm))
+                return;
+
+        I915_WRITE(WM3_LP_ILK,
+                   WM3_LP_EN |
+                   (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
+                   (fbc_wm << WM1_LP_FBC_SHIFT) |
+                   (plane_wm << WM1_LP_SR_SHIFT) |
+                   cursor_wm);
+}
+
+static void ivybridge_update_wm(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
+        u32 val;
+        int fbc_wm, plane_wm, cursor_wm;
+        int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
+        unsigned int enabled;
+
+        enabled = 0;
+        if (g4x_compute_wm0(dev, 0,
+                            &sandybridge_display_wm_info, latency,
+                            &sandybridge_cursor_wm_info, latency,
+                            &plane_wm, &cursor_wm)) {
+                val = I915_READ(WM0_PIPEA_ILK);
+                val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
+                I915_WRITE(WM0_PIPEA_ILK, val |
+                           ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
+                DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
+                              " plane %d, " "cursor: %d\n",
+                              plane_wm, cursor_wm);
+                enabled |= 1;
+        }
+
+        if (g4x_compute_wm0(dev, 1,
+                            &sandybridge_display_wm_info, latency,
+                            &sandybridge_cursor_wm_info, latency,
+                            &plane_wm, &cursor_wm)) {
+                val = I915_READ(WM0_PIPEB_ILK);
+                val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
+                I915_WRITE(WM0_PIPEB_ILK, val |
+                           ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
+                DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
+                              " plane %d, cursor: %d\n",
+                              plane_wm, cursor_wm);
+                enabled |= 2;
+        }
+
+        if (g4x_compute_wm0(dev, 2,
                             &sandybridge_display_wm_info, latency,
                             &sandybridge_cursor_wm_info, latency,
                             &plane_wm, &cursor_wm)) {
@@ -1875,12 +1992,17 @@ static void sandybridge_update_wm(struct drm_device *dev)
                    (plane_wm << WM1_LP_SR_SHIFT) |
                    cursor_wm);
 
-        /* WM3 */
+        /* WM3, note we have to correct the cursor latency */
         if (!ironlake_compute_srwm(dev, 3, enabled,
                                    SNB_READ_WM3_LATENCY() * 500,
                                    &sandybridge_display_srwm_info,
                                    &sandybridge_cursor_srwm_info,
-                                   &fbc_wm, &plane_wm, &cursor_wm))
+                                   &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
+            !ironlake_compute_srwm(dev, 3, enabled,
+                                   2 * SNB_READ_WM3_LATENCY() * 500,
+                                   &sandybridge_display_srwm_info,
+                                   &sandybridge_cursor_srwm_info,
+                                   &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
                 return;
 
         I915_WRITE(WM3_LP_ILK,
@@ -1929,7 +2051,7 @@ sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
         int entries, tlb_miss;
 
         crtc = intel_get_crtc_for_plane(dev, plane);
-        if (crtc->fb == NULL || !crtc->enabled) {
+        if (!intel_crtc_active(crtc)) {
                 *sprite_wm = display->guard_size;
                 return false;
         }
@@ -3471,6 +3593,15 @@ static void gen6_init_clock_gating(struct drm_device *dev)
                    I915_READ(ILK_DISPLAY_CHICKEN2) |
                    ILK_ELPIN_409_SELECT);
 
+        /* WaDisableHiZPlanesWhenMSAAEnabled */
+        I915_WRITE(_3D_CHICKEN,
+                   _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
+
+        /* WaSetupGtModeTdRowDispatch */
+        if (IS_SNB_GT1(dev))
+                I915_WRITE(GEN6_GT_MODE,
+                           _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
+
         I915_WRITE(WM3_LP_ILK, 0);
         I915_WRITE(WM2_LP_ILK, 0);
         I915_WRITE(WM1_LP_ILK, 0);
@@ -3999,7 +4130,7 @@ void intel_init_pm(struct drm_device *dev)
                 } else if (IS_IVYBRIDGE(dev)) {
                         /* FIXME: detect B0+ stepping and use auto training */
                         if (SNB_READ_WM0_LATENCY()) {
-                                dev_priv->display.update_wm = sandybridge_update_wm;
+                                dev_priv->display.update_wm = ivybridge_update_wm;
                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
                         } else {
                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
@@ -4119,7 +4250,8 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
 {
         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
-        POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
+        /* something from same cacheline, but !FORCEWAKE_MT */
+        POSTING_READ(ECOBUS);
 }
 
 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
@@ -4136,7 +4268,8 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
 
         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
-        POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
+        /* something from same cacheline, but !FORCEWAKE_MT */
+        POSTING_READ(ECOBUS);
 
         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
                             FORCEWAKE_ACK_TIMEOUT_MS))
@@ -4173,14 +4306,16 @@ void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 {
         I915_WRITE_NOTRACE(FORCEWAKE, 0);
-        /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
+        /* something from same cacheline, but !FORCEWAKE */
+        POSTING_READ(ECOBUS);
         gen6_gt_check_fifodbg(dev_priv);
 }
 
 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 {
         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
-        /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
+        /* something from same cacheline, but !FORCEWAKE_MT */
+        POSTING_READ(ECOBUS);
         gen6_gt_check_fifodbg(dev_priv);
 }
 
@@ -4220,6 +4355,8 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
 {
         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
+        /* something from same cacheline, but !FORCEWAKE_VLV */
+        POSTING_READ(FORCEWAKE_ACK_VLV);
 }
 
 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
@@ -4240,7 +4377,8 @@ static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
 {
         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
-        /* The below doubles as a POSTING_READ */
+        /* something from same cacheline, but !FORCEWAKE_VLV */
+        POSTING_READ(FORCEWAKE_ACK_VLV);
         gen6_gt_check_fifodbg(dev_priv);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2346b920bd86..ae253e04c391 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -547,9 +547,14 @@ static int init_render_ring(struct intel_ring_buffer *ring)
 
 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 {
+        struct drm_device *dev = ring->dev;
+
         if (!ring->private)
                 return;
 
+        if (HAS_BROKEN_CS_TLB(dev))
+                drm_gem_object_unreference(to_gem_object(ring->private));
+
         cleanup_pipe_control(ring);
 }
 
@@ -969,6 +974,8 @@ i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
         return 0;
 }
 
+/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
+#define I830_BATCH_LIMIT (256*1024)
 static int
 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
                                 u32 offset, u32 len,
@@ -976,15 +983,47 @@ i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
 {
         int ret;
 
-        ret = intel_ring_begin(ring, 4);
-        if (ret)
-                return ret;
+        if (flags & I915_DISPATCH_PINNED) {
+                ret = intel_ring_begin(ring, 4);
+                if (ret)
+                        return ret;
 
-        intel_ring_emit(ring, MI_BATCH_BUFFER);
-        intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
-        intel_ring_emit(ring, offset + len - 8);
-        intel_ring_emit(ring, 0);
-        intel_ring_advance(ring);
+                intel_ring_emit(ring, MI_BATCH_BUFFER);
+                intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
+                intel_ring_emit(ring, offset + len - 8);
+                intel_ring_emit(ring, MI_NOOP);
+                intel_ring_advance(ring);
+        } else {
+                struct drm_i915_gem_object *obj = ring->private;
+                u32 cs_offset = obj->gtt_offset;
+
+                if (len > I830_BATCH_LIMIT)
+                        return -ENOSPC;
+
+                ret = intel_ring_begin(ring, 9+3);
+                if (ret)
+                        return ret;
+                /* Blit the batch (which has now all relocs applied) to the stable batch
+                 * scratch bo area (so that the CS never stumbles over its tlb
+                 * invalidation bug) ... */
+                intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
+                                XY_SRC_COPY_BLT_WRITE_ALPHA |
+                                XY_SRC_COPY_BLT_WRITE_RGB);
+                intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
+                intel_ring_emit(ring, 0);
+                intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
+                intel_ring_emit(ring, cs_offset);
+                intel_ring_emit(ring, 0);
+                intel_ring_emit(ring, 4096);
+                intel_ring_emit(ring, offset);
+                intel_ring_emit(ring, MI_FLUSH);
+
+                /* ... and execute it. */
+                intel_ring_emit(ring, MI_BATCH_BUFFER);
+                intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
+                intel_ring_emit(ring, cs_offset + len - 8);
+                intel_ring_advance(ring);
+        }
 
         return 0;
 }
@@ -1596,6 +1635,27 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
         ring->init = init_render_ring;
         ring->cleanup = render_ring_cleanup;
 
+        /* Workaround batchbuffer to combat CS tlb bug. */
+        if (HAS_BROKEN_CS_TLB(dev)) {
+                struct drm_i915_gem_object *obj;
+                int ret;
+
+                obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
+                if (obj == NULL) {
+                        DRM_ERROR("Failed to allocate batch bo\n");
+                        return -ENOMEM;
+                }
+
+                ret = i915_gem_object_pin(obj, 0, true, false);
+                if (ret != 0) {
+                        drm_gem_object_unreference(&obj->base);
+                        DRM_ERROR("Failed to ping batch bo\n");
+                        return ret;
+                }
+
+                ring->private = obj;
+        }
+
         return intel_init_ring_buffer(dev, ring);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 526182ed0c6d..6af87cd05725 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -94,6 +94,7 @@ struct  intel_ring_buffer {
                                                u32 offset, u32 length,
                                                unsigned flags);
 #define I915_DISPATCH_SECURE 0x1
+#define I915_DISPATCH_PINNED 0x2
         void            (*cleanup)(struct intel_ring_buffer *ring);
         int             (*sync_to)(struct intel_ring_buffer *ring,
                                    struct intel_ring_buffer *to,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 827dcd4edf1c..d7b060e0a231 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -120,11 +120,10 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 
-        linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
+        linear_offset = y * fb->pitches[0] + x * pixel_size;
         sprsurf_offset =
                 intel_gen4_compute_offset_xtiled(&x, &y,
-                                                 fb->bits_per_pixel / 8,
-                                                 fb->pitches[0]);
+                                                 pixel_size, fb->pitches[0]);
         linear_offset -= sprsurf_offset;
 
         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
@@ -286,11 +285,10 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 
-        linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
+        linear_offset = y * fb->pitches[0] + x * pixel_size;
         dvssurf_offset =
                 intel_gen4_compute_offset_xtiled(&x, &y,
-                                                 fb->bits_per_pixel / 8,
-                                                 fb->pitches[0]);
+                                                 pixel_size, fb->pitches[0]);
         linear_offset -= dvssurf_offset;
 
         if (obj->tiling_mode != I915_TILING_NONE)
diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c b/drivers/gpu/drm/mgag200/mgag200_drv.c
index 1e910117b0a2..122b571ccc7c 100644
--- a/drivers/gpu/drm/mgag200/mgag200_drv.c
+++ b/drivers/gpu/drm/mgag200/mgag200_drv.c
@@ -60,8 +60,7 @@ static void mgag200_kick_out_firmware_fb(struct pci_dev *pdev)
 }
 
 
-static int __devinit
-mga_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+static int mga_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
         mgag200_kick_out_firmware_fb(pdev);
 
diff --git a/drivers/gpu/drm/nouveau/core/core/client.c b/drivers/gpu/drm/nouveau/core/core/client.c
index c617f0480071..8bbb58f94a19 100644
--- a/drivers/gpu/drm/nouveau/core/core/client.c
+++ b/drivers/gpu/drm/nouveau/core/core/client.c
@@ -66,10 +66,8 @@ nouveau_client_create_(const char *name, u64 devname, const char *cfg,
 
         ret = nouveau_handle_create(nv_object(client), ~0, ~0,
                                     nv_object(client), &client->root);
-        if (ret) {
-                nouveau_namedb_destroy(&client->base);
+        if (ret)
                 return ret;
-        }
 
         /* prevent init/fini being called, os in in charge of this */
         atomic_set(&nv_object(client)->usecount, 2);
diff --git a/drivers/gpu/drm/nouveau/core/core/handle.c b/drivers/gpu/drm/nouveau/core/core/handle.c
index b8d2cbf8a7a7..264c2b338ac3 100644
--- a/drivers/gpu/drm/nouveau/core/core/handle.c
+++ b/drivers/gpu/drm/nouveau/core/core/handle.c
@@ -109,7 +109,7 @@ nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle,
         while (!nv_iclass(namedb, NV_NAMEDB_CLASS))
                 namedb = namedb->parent;
 
-        handle = *phandle = kzalloc(sizeof(*handle), GFP_KERNEL);
+        handle = kzalloc(sizeof(*handle), GFP_KERNEL);
         if (!handle)
                 return -ENOMEM;
 
@@ -146,6 +146,9 @@ nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle,
         }
 
         hprintk(handle, TRACE, "created\n");
+
+        *phandle = handle;
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 0f09af135415..ca1a7d76a95b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -851,20 +851,23 @@ exec_script(struct nv50_disp_priv *priv, int head, int id)
         for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)
                 ctrl = nv_rd32(priv, 0x610b5c + (i * 8));
 
-        if (nv_device(priv)->chipset  < 0x90 ||
-            nv_device(priv)->chipset == 0x92 ||
-            nv_device(priv)->chipset == 0xa0) {
-                for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)
-                        ctrl = nv_rd32(priv, 0x610b74 + (i * 8));
-                i += 3;
-        } else {
-                for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)
-                        ctrl = nv_rd32(priv, 0x610798 + (i * 8));
-                i += 3;
+        if (!(ctrl & (1 << head))) {
+                if (nv_device(priv)->chipset  < 0x90 ||
+                    nv_device(priv)->chipset == 0x92 ||
+                    nv_device(priv)->chipset == 0xa0) {
+                        for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)
+                                ctrl = nv_rd32(priv, 0x610b74 + (i * 8));
+                        i += 4;
+                } else {
+                        for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)
+                                ctrl = nv_rd32(priv, 0x610798 + (i * 8));
+                        i += 4;
+                }
         }
 
         if (!(ctrl & (1 << head)))
                 return false;
+        i--;
 
         data = exec_lookup(priv, head, i, ctrl, &dcb, &ver, &hdr, &cnt, &len, &info);
         if (data) {
@@ -898,20 +901,23 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk,
         for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)
                 ctrl = nv_rd32(priv, 0x610b58 + (i * 8));
 
-        if (nv_device(priv)->chipset  < 0x90 ||
-            nv_device(priv)->chipset == 0x92 ||
-            nv_device(priv)->chipset == 0xa0) {
-                for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)
-                        ctrl = nv_rd32(priv, 0x610b70 + (i * 8));
-                i += 3;
-        } else {
-                for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)
-                        ctrl = nv_rd32(priv, 0x610794 + (i * 8));
-                i += 3;
+        if (!(ctrl & (1 << head))) {
+                if (nv_device(priv)->chipset  < 0x90 ||
+                    nv_device(priv)->chipset == 0x92 ||
+                    nv_device(priv)->chipset == 0xa0) {
+                        for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)
+                                ctrl = nv_rd32(priv, 0x610b70 + (i * 8));
+                        i += 4;
+                } else {
+                        for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)
+                                ctrl = nv_rd32(priv, 0x610794 + (i * 8));
+                        i += 4;
+                }
         }
 
         if (!(ctrl & (1 << head)))
                 return 0x0000;
+        i--;
 
         data = exec_lookup(priv, head, i, ctrl, outp, &ver, &hdr, &cnt, &len, &info1);
         if (!data)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
index 7b715fda2763..62ab231cd6b6 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
@@ -57,6 +57,11 @@ chipsets:
 .b16 #nve4_gpc_mmio_tail
 .b16 #nve4_tpc_mmio_head
 .b16 #nve4_tpc_mmio_tail
+.b8  0xe6 0 0 0
+.b16 #nve4_gpc_mmio_head
+.b16 #nve4_gpc_mmio_tail
+.b16 #nve4_tpc_mmio_head
+.b16 #nve4_tpc_mmio_tail
 .b8  0 0 0 0
 
 // GPC mmio lists
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
index 26c2165bad0f..09ee4702c8b2 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
@@ -34,13 +34,16 @@ uint32_t nve0_grgpc_data[] = {
         0x00000000,
 /* 0x0064: chipsets */
         0x000000e4,
-        0x01040080,
-        0x014c0104,
+        0x0110008c,
+        0x01580110,
         0x000000e7,
-        0x01040080,
-        0x014c0104,
+        0x0110008c,
+        0x01580110,
+        0x000000e6,
+        0x0110008c,
+        0x01580110,
         0x00000000,
-/* 0x0080: nve4_gpc_mmio_head */
+/* 0x008c: nve4_gpc_mmio_head */
         0x00000380,
         0x04000400,
         0x0800040c,
@@ -74,8 +77,8 @@ uint32_t nve0_grgpc_data[] = {
         0x14003100,
         0x000031d0,
         0x040031e0,
-/* 0x0104: nve4_gpc_mmio_tail */
-/* 0x0104: nve4_tpc_mmio_head */
+/* 0x0110: nve4_gpc_mmio_tail */
+/* 0x0110: nve4_tpc_mmio_head */
         0x00000048,
         0x00000064,
         0x00000088,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
index acfc457654bd..0bcfa4d447e5 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
@@ -754,6 +754,16 @@ ctx_mmio_exec:
 //              on load it means: "a save preceeded this load"
 //
 ctx_xfer:
+        // according to mwk, some kind of wait for idle
+        mov $r15 0xc00
+        shl b32 $r15 6
+        mov $r14 4
+        iowr I[$r15 + 0x200] $r14
+        ctx_xfer_idle:
+                iord $r14 I[$r15 + 0x000]
+                and $r14 0x2000
+                bra ne #ctx_xfer_idle
+
         bra not $p1 #ctx_xfer_pre
         bra $p2 #ctx_xfer_pre_load
         ctx_xfer_pre:
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
index 85a8d556f484..bb03d2a1d57b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
@@ -799,79 +799,80 @@ uint32_t nvc0_grhub_code[] = {
         0x01fa0613,
         0xf803f806,
 /* 0x0829: ctx_xfer */
-        0x0611f400,
-/* 0x082f: ctx_xfer_pre */
-        0xf01102f4,
-        0x21f510f7,
-        0x21f50698,
-        0x11f40631,
-/* 0x083d: ctx_xfer_pre_load */
-        0x02f7f01c,
-        0x065721f5,
-        0x066621f5,
-        0x067821f5,
-        0x21f5f4bd,
-        0x21f50657,
-/* 0x0856: ctx_xfer_exec */
-        0x019806b8,
-        0x1427f116,
-        0x0624b604,
-        0xf10020d0,
-        0xf0a500e7,
-        0x1fb941e3,
-        0x8d21f402,
-        0xf004e0b6,
-        0x2cf001fc,
-        0x0124b602,
-        0xf405f2fd,
-        0x17f18d21,
-        0x13f04afc,
-        0x0c27f002,
-        0xf50012d0,
-        0xf1020721,
-        0xf047fc27,
-        0x20d00223,
-        0x012cf000,
-        0xd00320b6,
-        0xacf00012,
-        0x06a5f001,
-        0x9800b7f0,
-        0x0d98140c,
-        0x00e7f015,
-        0x015c21f5,
-        0xf508a7f0,
-        0xf5010321,
-        0xf4020721,
-        0xa7f02201,
-        0xc921f40c,
-        0x0a1017f1,
-        0xf00614b6,
-        0x12d00527,
-/* 0x08dd: ctx_xfer_post_save_wait */
-        0x0012cf00,
-        0xf40522fd,
-        0x02f4fa1b,
-/* 0x08e9: ctx_xfer_post */
-        0x02f7f032,
-        0x065721f5,
-        0x21f5f4bd,
-        0x21f50698,
-        0x21f50226,
-        0xf4bd0666,
-        0x065721f5,
-        0x981011f4,
-        0x11fd8001,
-        0x070bf405,
-        0x07df21f5,
-/* 0x0914: ctx_xfer_no_post_mmio */
-        0x064921f5,
-/* 0x0918: ctx_xfer_done */
-        0x000000f8,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
+        0x00f7f100,
+        0x06f4b60c,
+        0xd004e7f0,
+/* 0x0836: ctx_xfer_idle */
+        0xfecf80fe,
+        0x00e4f100,
+        0xf91bf420,
+        0xf40611f4,
+/* 0x0846: ctx_xfer_pre */
+        0xf7f01102,
+        0x9821f510,
+        0x3121f506,
+        0x1c11f406,
+/* 0x0854: ctx_xfer_pre_load */
+        0xf502f7f0,
+        0xf5065721,
+        0xf5066621,
+        0xbd067821,
+        0x5721f5f4,
+        0xb821f506,
+/* 0x086d: ctx_xfer_exec */
+        0x16019806,
+        0x041427f1,
+        0xd00624b6,
+        0xe7f10020,
+        0xe3f0a500,
+        0x021fb941,
+        0xb68d21f4,
+        0xfcf004e0,
+        0x022cf001,
+        0xfd0124b6,
+        0x21f405f2,
+        0xfc17f18d,
+        0x0213f04a,
+        0xd00c27f0,
+        0x21f50012,
+        0x27f10207,
+        0x23f047fc,
+        0x0020d002,
+        0xb6012cf0,
+        0x12d00320,
+        0x01acf000,
+        0xf006a5f0,
+        0x0c9800b7,
+        0x150d9814,
+        0xf500e7f0,
+        0xf0015c21,
+        0x21f508a7,
+        0x21f50103,
+        0x01f40207,
+        0x0ca7f022,
+        0xf1c921f4,
+        0xb60a1017,
+        0x27f00614,
+        0x0012d005,
+/* 0x08f4: ctx_xfer_post_save_wait */
+        0xfd0012cf,
+        0x1bf40522,
+        0x3202f4fa,
+/* 0x0900: ctx_xfer_post */
+        0xf502f7f0,
+        0xbd065721,
+        0x9821f5f4,
+        0x2621f506,
+        0x6621f502,
+        0xf5f4bd06,
+        0xf4065721,
+        0x01981011,
+        0x0511fd80,
+        0xf5070bf4,
+/* 0x092b: ctx_xfer_no_post_mmio */
+        0xf507df21,
+/* 0x092f: ctx_xfer_done */
+        0xf8064921,
         0x00000000,
         0x00000000,
         0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
index 138eeaa28665..7fe9d7cf486b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
@@ -44,6 +44,9 @@ chipsets:
 .b8  0xe7 0 0 0
 .b16 #nve4_hub_mmio_head
 .b16 #nve4_hub_mmio_tail
+.b8  0xe6 0 0 0
+.b16 #nve4_hub_mmio_head
+.b16 #nve4_hub_mmio_tail
 .b8  0 0 0 0
 
 nve4_hub_mmio_head:
@@ -680,6 +683,16 @@ ctx_mmio_exec:
 //              on load it means: "a save preceeded this load"
 //
 ctx_xfer:
+        // according to mwk, some kind of wait for idle
+        mov $r15 0xc00
+        shl b32 $r15 6
+        mov $r14 4
+        iowr I[$r15 + 0x200] $r14
+        ctx_xfer_idle:
+                iord $r14 I[$r15 + 0x000]
+                and $r14 0x2000
+                bra ne #ctx_xfer_idle
+
         bra not $p1 #ctx_xfer_pre
         bra $p2 #ctx_xfer_pre_load
         ctx_xfer_pre:
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
index decf0c60ca3b..e3421af68ab9 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
@@ -30,11 +30,13 @@ uint32_t nve0_grhub_data[] = {
         0x00000000,
 /* 0x005c: chipsets */
         0x000000e4,
-        0x013c0070,
+        0x01440078,
         0x000000e7,
-        0x013c0070,
+        0x01440078,
+        0x000000e6,
+        0x01440078,
         0x00000000,
-/* 0x0070: nve4_hub_mmio_head */
+/* 0x0078: nve4_hub_mmio_head */
         0x0417e91c,
         0x04400204,
         0x18404010,
@@ -86,9 +88,7 @@ uint32_t nve0_grhub_data[] = {
         0x00408840,
         0x08408900,
         0x00408980,
-/* 0x013c: nve4_hub_mmio_tail */
-        0x00000000,
-        0x00000000,
+/* 0x0144: nve4_hub_mmio_tail */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -781,77 +781,78 @@ uint32_t nve0_grhub_code[] = {
         0x0613f002,
         0xf80601fa,
 /* 0x07fb: ctx_xfer */
-        0xf400f803,
-        0x02f40611,
-/* 0x0801: ctx_xfer_pre */
-        0x10f7f00d,
-        0x067221f5,
-/* 0x080b: ctx_xfer_pre_load */
-        0xf01c11f4,
-        0x21f502f7,
-        0x21f50631,
-        0x21f50640,
-        0xf4bd0652,
-        0x063121f5,
-        0x069221f5,
-/* 0x0824: ctx_xfer_exec */
-        0xf1160198,
-        0xb6041427,
-        0x20d00624,
-        0x00e7f100,
-        0x41e3f0a5,
-        0xf4021fb9,
-        0xe0b68d21,
-        0x01fcf004,
-        0xb6022cf0,
-        0xf2fd0124,
-        0x8d21f405,
-        0x4afc17f1,
-        0xf00213f0,
-        0x12d00c27,
-        0x0721f500,
-        0xfc27f102,
-        0x0223f047,
-        0xf00020d0,
-        0x20b6012c,
-        0x0012d003,
-        0xf001acf0,
-        0xb7f006a5,
-        0x140c9800,
-        0xf0150d98,
-        0x21f500e7,
-        0xa7f0015c,
-        0x0321f508,
-        0x0721f501,
-        0x2201f402,
-        0xf40ca7f0,
-        0x17f1c921,
-        0x14b60a10,
-        0x0527f006,
-/* 0x08ab: ctx_xfer_post_save_wait */
-        0xcf0012d0,
-        0x22fd0012,
-        0xfa1bf405,
-/* 0x08b7: ctx_xfer_post */
-        0xf02e02f4,
-        0x21f502f7,
-        0xf4bd0631,
-        0x067221f5,
-        0x022621f5,
-        0x064021f5,
-        0x21f5f4bd,
-        0x11f40631,
-        0x80019810,
-        0xf40511fd,
-        0x21f5070b,
-/* 0x08e2: ctx_xfer_no_post_mmio */
-/* 0x08e2: ctx_xfer_done */
-        0x00f807b1,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
+        0xf100f803,
+        0xb60c00f7,
+        0xe7f006f4,
+        0x80fed004,
+/* 0x0808: ctx_xfer_idle */
+        0xf100fecf,
+        0xf42000e4,
+        0x11f4f91b,
+        0x0d02f406,
+/* 0x0818: ctx_xfer_pre */
+        0xf510f7f0,
+        0xf4067221,
+/* 0x0822: ctx_xfer_pre_load */
+        0xf7f01c11,
+        0x3121f502,
+        0x4021f506,
+        0x5221f506,
+        0xf5f4bd06,
+        0xf5063121,
+/* 0x083b: ctx_xfer_exec */
+        0x98069221,
+        0x27f11601,
+        0x24b60414,
+        0x0020d006,
+        0xa500e7f1,
+        0xb941e3f0,
+        0x21f4021f,
+        0x04e0b68d,
+        0xf001fcf0,
+        0x24b6022c,
+        0x05f2fd01,
+        0xf18d21f4,
+        0xf04afc17,
+        0x27f00213,
+        0x0012d00c,
+        0x020721f5,
+        0x47fc27f1,
+        0xd00223f0,
+        0x2cf00020,
+        0x0320b601,
+        0xf00012d0,
+        0xa5f001ac,
+        0x00b7f006,
+        0x98140c98,
+        0xe7f0150d,
+        0x5c21f500,
+        0x08a7f001,
+        0x010321f5,
+        0x020721f5,
+        0xf02201f4,
+        0x21f40ca7,
+        0x1017f1c9,
+        0x0614b60a,
+        0xd00527f0,
+/* 0x08c2: ctx_xfer_post_save_wait */
+        0x12cf0012,
+        0x0522fd00,
+        0xf4fa1bf4,
+/* 0x08ce: ctx_xfer_post */
+        0xf7f02e02,
+        0x3121f502,
+        0xf5f4bd06,
+        0xf5067221,
+        0xf5022621,
+        0xbd064021,
+        0x3121f5f4,
+        0x1011f406,
+        0xfd800198,
+        0x0bf40511,
+        0xb121f507,
+/* 0x08f9: ctx_xfer_no_post_mmio */
+/* 0x08f9: ctx_xfer_done */
+        0x0000f807,
         0x00000000,
 };
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index 47a02081d708..45aff5f5085a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -516,18 +516,9 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 {
         struct nouveau_device *device = nv_device(parent);
         struct nvc0_graph_priv *priv;
-        bool enable = true;
         int ret, i;
 
-        switch (device->chipset) {
-        case 0xd9: /* known broken without binary driver firmware */
-                enable = false;
-                break;
-        default:
-                break;
-        }
-
-        ret = nouveau_graph_create(parent, engine, oclass, enable, &priv);
+        ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
index 18d2210e12eb..a1e78de46456 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
@@ -121,6 +121,7 @@ nvc0_graph_class(void *obj)
                 return 0x9297;
         case 0xe4:
         case 0xe7:
+        case 0xe6:
                 return 0xa097;
         default:
                 return 0;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
index 539d4c72f192..9f82e9702b46 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
@@ -203,7 +203,7 @@ nve0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nvc0_graph_priv *priv;
         int ret, i;
 
-        ret = nouveau_graph_create(parent, engine, oclass, false, &priv);
+        ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
@@ -252,6 +252,7 @@ nve0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                         priv->magic_not_rop_nr = 1;
                 break;
         case 0xe7:
+        case 0xe6:
                 priv->magic_not_rop_nr = 1;
                 break;
         default:
diff --git a/drivers/gpu/drm/nouveau/core/include/core/client.h b/drivers/gpu/drm/nouveau/core/include/core/client.h
index 0193532ceac9..63acc0346ff2 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/client.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/client.h
@@ -36,6 +36,9 @@ nouveau_client(void *obj)
 
 int  nouveau_client_create_(const char *name, u64 device, const char *cfg,
                             const char *dbg, int, void **);
+#define nouveau_client_destroy(p)                                              \
+        nouveau_namedb_destroy(&(p)->base)
+
 int  nouveau_client_init(struct nouveau_client *);
 int  nouveau_client_fini(struct nouveau_client *, bool suspend);
 
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios.h
index d145b25e6be4..5bd1ca8cd20d 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios.h
@@ -17,6 +17,7 @@ struct nouveau_bios {
                 u8 chip;
                 u8 minor;
                 u8 micro;
+                u8 patch;
         } version;
 };
 
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h
index 2bf178082a36..e6563b5cb08e 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h
@@ -25,9 +25,11 @@ struct dcb_gpio_func {
         u8 param;
 };
 
-u16 dcb_gpio_table(struct nouveau_bios *);
-u16 dcb_gpio_entry(struct nouveau_bios *, int idx, int ent, u8 *ver);
-int dcb_gpio_parse(struct nouveau_bios *, int idx, u8 func, u8 line,
+u16 dcb_gpio_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
+u16 dcb_gpio_entry(struct nouveau_bios *, int idx, int ent, u8 *ver, u8 *len);
+u16 dcb_gpio_parse(struct nouveau_bios *, int idx, int ent, u8 *ver, u8 *len,
                    struct dcb_gpio_func *);
+u16 dcb_gpio_match(struct nouveau_bios *, int idx, u8 func, u8 line,
+                   u8 *ver, u8 *len, struct dcb_gpio_func *);
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h
index e69a8bdc6e97..ca2f6bf37f46 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h
@@ -13,6 +13,7 @@ struct nvbios_init {
         u32 nested;
         u16 repeat;
         u16 repend;
+        u32 ramcfg;
 };
 
 int nvbios_exec(struct nvbios_init *);
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h
index c345097592f2..b2f3d4d0aa49 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h
@@ -38,6 +38,8 @@ enum nvbios_pll_type {
         PLL_UNK42  = 0x42,
         PLL_VPLL0  = 0x80,
         PLL_VPLL1  = 0x81,
+        PLL_VPLL2  = 0x82,
+        PLL_VPLL3  = 0x83,
         PLL_MAX    = 0xff
 };
 
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h b/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h
index 9ea2b12cc15d..b75e8f18e52c 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h
@@ -11,7 +11,7 @@ struct nouveau_gpio {
         struct nouveau_subdev base;
 
         /* hardware interfaces */
-        void (*reset)(struct nouveau_gpio *);
+        void (*reset)(struct nouveau_gpio *, u8 func);
         int  (*drive)(struct nouveau_gpio *, int line, int dir, int out);
         int  (*sense)(struct nouveau_gpio *, int line);
         void (*irq_enable)(struct nouveau_gpio *, int line, bool);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
index dd111947eb86..f621f69fa1a2 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
@@ -447,6 +447,7 @@ nouveau_bios_ctor(struct nouveau_object *parent,
                 bios->version.chip  = nv_ro08(bios, bit_i.offset + 2);
                 bios->version.minor = nv_ro08(bios, bit_i.offset + 1);
                 bios->version.micro = nv_ro08(bios, bit_i.offset + 0);
+                bios->version.patch = nv_ro08(bios, bit_i.offset + 4);
         } else
         if (bmp_version(bios)) {
                 bios->version.major = nv_ro08(bios, bios->bmp_offset + 13);
@@ -455,9 +456,9 @@ nouveau_bios_ctor(struct nouveau_object *parent,
                 bios->version.micro = nv_ro08(bios, bios->bmp_offset + 10);
         }
 
-        nv_info(bios, "version %02x.%02x.%02x.%02x\n",
+        nv_info(bios, "version %02x.%02x.%02x.%02x.%02x\n",
                 bios->version.major, bios->version.chip,
-                bios->version.minor, bios->version.micro);
+                bios->version.minor, bios->version.micro, bios->version.patch);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c b/drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c
index c90d4aa3ae4f..c84e93fa6d95 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c
@@ -27,84 +27,105 @@
 #include <subdev/bios/gpio.h>
 
 u16
-dcb_gpio_table(struct nouveau_bios *bios)
+dcb_gpio_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
 {
-        u8  ver, hdr, cnt, len;
-        u16 dcb = dcb_table(bios, &ver, &hdr, &cnt, &len);
+        u16 data = 0x0000;
+        u16 dcb = dcb_table(bios, ver, hdr, cnt, len);
         if (dcb) {
-                if (ver >= 0x30 && hdr >= 0x0c)
-                        return nv_ro16(bios, dcb + 0x0a);
-                if (ver >= 0x22 && nv_ro08(bios, dcb - 1) >= 0x13)
-                        return nv_ro16(bios, dcb - 0x0f);
+                if (*ver >= 0x30 && *hdr >= 0x0c)
+                        data = nv_ro16(bios, dcb + 0x0a);
+                else
+                if (*ver >= 0x22 && nv_ro08(bios, dcb - 1) >= 0x13)
+                        data = nv_ro16(bios, dcb - 0x0f);
+
+                if (data) {
+                        *ver = nv_ro08(bios, data + 0x00);
+                        if (*ver < 0x30) {
+                                *hdr = 3;
+                                *cnt = nv_ro08(bios, data + 0x02);
+                                *len = nv_ro08(bios, data + 0x01);
+                        } else
+                        if (*ver <= 0x41) {
+                                *hdr = nv_ro08(bios, data + 0x01);
+                                *cnt = nv_ro08(bios, data + 0x02);
+                                *len = nv_ro08(bios, data + 0x03);
+                        } else {
+                                data = 0x0000;
+                        }
+                }
         }
-        return 0x0000;
+        return data;
 }
 
 u16
-dcb_gpio_entry(struct nouveau_bios *bios, int idx, int ent, u8 *ver)
+dcb_gpio_entry(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len)
 {
-        u16 gpio = dcb_gpio_table(bios);
-        if (gpio) {
-                *ver = nv_ro08(bios, gpio);
-                if (*ver < 0x30 && ent < nv_ro08(bios, gpio + 2))
-                        return gpio + 3 + (ent * nv_ro08(bios, gpio + 1));
-                else if (ent < nv_ro08(bios, gpio + 2))
-                        return gpio + nv_ro08(bios, gpio + 1) +
-                               (ent * nv_ro08(bios, gpio + 3));
-        }
+        u8  hdr, cnt;
+        u16 gpio = !idx ? dcb_gpio_table(bios, ver, &hdr, &cnt, len) : 0x0000;
+        if (gpio && ent < cnt)
+                return gpio + hdr + (ent * *len);
         return 0x0000;
 }
 
-int
-dcb_gpio_parse(struct nouveau_bios *bios, int idx, u8 func, u8 line,
+u16
+dcb_gpio_parse(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len,
                struct dcb_gpio_func *gpio)
 {
-        u8  ver, hdr, cnt, len;
-        u16 entry;
-        int i = -1;
-
-        while ((entry = dcb_gpio_entry(bios, idx, ++i, &ver))) {
-                if (ver < 0x40) {
-                        u16 data = nv_ro16(bios, entry);
+        u16 data = dcb_gpio_entry(bios, idx, ent, ver, len);
+        if (data) {
+                if (*ver < 0x40) {
+                        u16 info = nv_ro16(bios, data);
                         *gpio = (struct dcb_gpio_func) {
-                                .line = (data & 0x001f) >> 0,
-                                .func = (data & 0x07e0) >> 5,
-                                .log[0] = (data & 0x1800) >> 11,
-                                .log[1] = (data & 0x6000) >> 13,
-                                .param = !!(data & 0x8000),
+                                .line = (info & 0x001f) >> 0,
+                                .func = (info & 0x07e0) >> 5,
+                                .log[0] = (info & 0x1800) >> 11,
+                                .log[1] = (info & 0x6000) >> 13,
+                                .param = !!(info & 0x8000),
                         };
                 } else
-                if (ver < 0x41) {
-                        u32 data = nv_ro32(bios, entry);
+                if (*ver < 0x41) {
+                        u32 info = nv_ro32(bios, data);
                         *gpio = (struct dcb_gpio_func) {
-                                .line = (data & 0x0000001f) >> 0,
-                                .func = (data & 0x0000ff00) >> 8,
-                                .log[0] = (data & 0x18000000) >> 27,
-                                .log[1] = (data & 0x60000000) >> 29,
-                                .param = !!(data & 0x80000000),
+                                .line = (info & 0x0000001f) >> 0,
+                                .func = (info & 0x0000ff00) >> 8,
+                                .log[0] = (info & 0x18000000) >> 27,
+                                .log[1] = (info & 0x60000000) >> 29,
+                                .param = !!(info & 0x80000000),
                         };
                 } else {
-                        u32 data = nv_ro32(bios, entry + 0);
-                        u8 data1 = nv_ro32(bios, entry + 4);
+                        u32 info = nv_ro32(bios, data + 0);
+                        u8 info1 = nv_ro32(bios, data + 4);
                         *gpio = (struct dcb_gpio_func) {
-                                .line = (data & 0x0000003f) >> 0,
-                                .func = (data & 0x0000ff00) >> 8,
-                                .log[0] = (data1 & 0x30) >> 4,
-                                .log[1] = (data1 & 0xc0) >> 6,
-                                .param = !!(data & 0x80000000),
+                                .line = (info & 0x0000003f) >> 0,
+                                .func = (info & 0x0000ff00) >> 8,
+                                .log[0] = (info1 & 0x30) >> 4,
+                                .log[1] = (info1 & 0xc0) >> 6,
+                                .param = !!(info & 0x80000000),
                         };
                 }
+        }
+
+        return data;
+}
 
+u16
+dcb_gpio_match(struct nouveau_bios *bios, int idx, u8 func, u8 line,
+               u8 *ver, u8 *len, struct dcb_gpio_func *gpio)
+{
+        u8  hdr, cnt, i = 0;
+        u16 data;
+
+        while ((data = dcb_gpio_parse(bios, idx, i++, ver, len, gpio))) {
                 if ((line == 0xff || line == gpio->line) &&
                     (func == 0xff || func == gpio->func))
-                        return 0;
+                        return data;
         }
 
         /* DCB 2.2, fixed TVDAC GPIO data */
-        if ((entry = dcb_table(bios, &ver, &hdr, &cnt, &len))) {
-                if (ver >= 0x22 && ver < 0x30 && func == DCB_GPIO_TVDAC0) {
-                        u8 conf = nv_ro08(bios, entry - 5);
-                        u8 addr = nv_ro08(bios, entry - 4);
+        if ((data = dcb_table(bios, ver, &hdr, &cnt, len))) {
+                if (*ver >= 0x22 && *ver < 0x30 && func == DCB_GPIO_TVDAC0) {
+                        u8 conf = nv_ro08(bios, data - 5);
+                        u8 addr = nv_ro08(bios, data - 4);
                         if (conf & 0x01) {
                                 *gpio = (struct dcb_gpio_func) {
                                         .func = DCB_GPIO_TVDAC0,
@@ -112,10 +133,11 @@ dcb_gpio_parse(struct nouveau_bios *bios, int idx, u8 func, u8 line,
                                         .log[0] = !!(conf & 0x02),
                                         .log[1] =  !(conf & 0x02),
                                 };
-                                return 0;
+                                *ver = 0x00;
+                                return data;
                         }
                 }
         }
 
-        return -EINVAL;
+        return 0x0000;
 }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c
index ae168bbb86d8..690ed438b2ad 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c
@@ -2,11 +2,12 @@
 #include <core/device.h>
 
 #include <subdev/bios.h>
-#include <subdev/bios/conn.h>
 #include <subdev/bios/bmp.h>
 #include <subdev/bios/bit.h>
+#include <subdev/bios/conn.h>
 #include <subdev/bios/dcb.h>
 #include <subdev/bios/dp.h>
+#include <subdev/bios/gpio.h>
 #include <subdev/bios/init.h>
 #include <subdev/devinit.h>
 #include <subdev/clock.h>
@@ -410,9 +411,25 @@ init_ram_restrict_group_count(struct nvbios_init *init)
 }
 
 static u8
+init_ram_restrict_strap(struct nvbios_init *init)
+{
+        /* This appears to be the behaviour of the VBIOS parser, and *is*
+         * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
+         * avoid fucking up the memory controller (somehow) by reading it
+         * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
+         *
+         * Preserving the non-caching behaviour on earlier chipsets just
+         * in case *not* re-reading the strap causes similar breakage.
+         */
+        if (!init->ramcfg || init->bios->version.major < 0x70)
+                init->ramcfg = init_rd32(init, 0x101000);
+        return (init->ramcfg & 0x00000003c) >> 2;
+}
+
+static u8
 init_ram_restrict(struct nvbios_init *init)
 {
-        u32 strap = (init_rd32(init, 0x101000) & 0x0000003c) >> 2;
+        u8  strap = init_ram_restrict_strap(init);
         u16 table = init_ram_restrict_table(init);
         if (table)
                 return nv_ro08(init->bios, table + strap);
@@ -1517,7 +1534,6 @@ init_io(struct nvbios_init *init)
                 mdelay(10);
                 init_wr32(init, 0x614100, 0x10000018);
                 init_wr32(init, 0x614900, 0x10000018);
-                return;
         }
 
         value = init_rdport(init, port) & mask;
@@ -1781,7 +1797,7 @@ init_gpio(struct nvbios_init *init)
         init->offset += 1;
 
         if (init_exec(init) && gpio && gpio->reset)
-                gpio->reset(gpio);
+                gpio->reset(gpio, DCB_GPIO_UNUSED);
 }
 
 /**
@@ -1995,6 +2011,47 @@ init_i2c_long_if(struct nvbios_init *init)
         init_exec_set(init, false);
 }
 
+/**
+ * INIT_GPIO_NE - opcode 0xa9
+ *
+ */
+static void
+init_gpio_ne(struct nvbios_init *init)
+{
+        struct nouveau_bios *bios = init->bios;
+        struct nouveau_gpio *gpio = nouveau_gpio(bios);
+        struct dcb_gpio_func func;
+        u8 count = nv_ro08(bios, init->offset + 1);
+        u8 idx = 0, ver, len;
+        u16 data, i;
+
+        trace("GPIO_NE\t");
+        init->offset += 2;
+
+        for (i = init->offset; i < init->offset + count; i++)
+                cont("0x%02x ", nv_ro08(bios, i));
+        cont("\n");
+
+        while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
+                if (func.func != DCB_GPIO_UNUSED) {
+                        for (i = init->offset; i < init->offset + count; i++) {
+                                if (func.func == nv_ro08(bios, i))
+                                        break;
+                        }
+
+                        trace("\tFUNC[0x%02x]", func.func);
+                        if (i == (init->offset + count)) {
+                                cont(" *");
+                                if (init_exec(init) && gpio && gpio->reset)
+                                        gpio->reset(gpio, func.func);
+                        }
+                        cont("\n");
+                }
+        }
+
+        init->offset += count;
+}
+
 static struct nvbios_init_opcode {
         void (*exec)(struct nvbios_init *);
 } init_opcode[] = {
@@ -2059,6 +2116,7 @@ static struct nvbios_init_opcode {
         [0x98] = { init_auxch },
         [0x99] = { init_zm_auxch },
         [0x9a] = { init_i2c_long_if },
+        [0xa9] = { init_gpio_ne },
 };
 
 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
index f6962c9b6c36..7c9626258a46 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
@@ -52,6 +52,8 @@ nvc0_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq)
         switch (info.type) {
         case PLL_VPLL0:
         case PLL_VPLL1:
+        case PLL_VPLL2:
+        case PLL_VPLL3:
                 nv_mask(priv, info.reg + 0x0c, 0x00000000, 0x00000100);
                 nv_wr32(priv, info.reg + 0x04, (P << 16) | (N << 8) | M);
                 nv_wr32(priv, info.reg + 0x10, fN << 16);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c
index 9b7881e76634..03a652876e73 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c
@@ -109,6 +109,34 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
                 break;
+        case 0xe6:
+                device->cname = "GK106";
+                device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] = &nvd0_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
+                device->oclass[NVDEV_SUBDEV_THERM  ] = &nv50_therm_oclass;
+                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
+                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
+                device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
+                device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
+                device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
+                device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
+                device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+                device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
+                device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
+                device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
+                device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
+                device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
+                device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
+                device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
+                device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
+                device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+                break;
         default:
                 nv_fatal(device, "unknown Kepler chipset\n");
                 return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c
index 306bdf121452..7606ed15b6fa 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c
@@ -145,14 +145,14 @@ nvc0_fb_vram_new(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
         mem->memtype = type;
         mem->size = size;
 
-        mutex_lock(&mm->mutex);
+        mutex_lock(&pfb->base.mutex);
         do {
                 if (back)
                         ret = nouveau_mm_tail(mm, 1, size, ncmin, align, &r);
                 else
                         ret = nouveau_mm_head(mm, 1, size, ncmin, align, &r);
                 if (ret) {
-                        mutex_unlock(&mm->mutex);
+                        mutex_unlock(&pfb->base.mutex);
                         pfb->ram.put(pfb, &mem);
                         return ret;
                 }
@@ -160,7 +160,7 @@ nvc0_fb_vram_new(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
                 list_add_tail(&r->rl_entry, &mem->regions);
                 size -= r->length;
         } while (size);
-        mutex_unlock(&mm->mutex);
+        mutex_unlock(&pfb->base.mutex);
 
         r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
         mem->offset = (u64)r->offset << 12;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c
index acf818c58bf0..9fb0f9b92d49 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c
@@ -43,10 +43,15 @@ static int
 nouveau_gpio_find(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line,
                   struct dcb_gpio_func *func)
 {
+        struct nouveau_bios *bios = nouveau_bios(gpio);
+        u8  ver, len;
+        u16 data;
+
         if (line == 0xff && tag == 0xff)
                 return -EINVAL;
 
-        if (!dcb_gpio_parse(nouveau_bios(gpio), idx, tag, line, func))
+        data = dcb_gpio_match(bios, idx, tag, line, &ver, &len, func);
+        if (data)
                 return 0;
 
         /* Apple iMac G4 NV18 */
@@ -265,7 +270,7 @@ nouveau_gpio_init(struct nouveau_gpio *gpio)
         int ret = nouveau_subdev_init(&gpio->base);
         if (ret == 0 && gpio->reset) {
                 if (dmi_check_system(gpio_reset_ids))
-                        gpio->reset(gpio);
+                        gpio->reset(gpio, DCB_GPIO_UNUSED);
         }
         return ret;
 }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c
index f3502c961cd9..bf13a1200f26 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c
@@ -29,15 +29,15 @@ struct nv50_gpio_priv {
 };
 
 static void
-nv50_gpio_reset(struct nouveau_gpio *gpio)
+nv50_gpio_reset(struct nouveau_gpio *gpio, u8 match)
 {
         struct nouveau_bios *bios = nouveau_bios(gpio);
         struct nv50_gpio_priv *priv = (void *)gpio;
+        u8 ver, len;
         u16 entry;
-        u8 ver;
         int ent = -1;
 
-        while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver))) {
+        while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
                 static const u32 regs[] = { 0xe100, 0xe28c };
                 u32 data = nv_ro32(bios, entry);
                 u8  line =   (data & 0x0000001f);
@@ -48,7 +48,8 @@ nv50_gpio_reset(struct nouveau_gpio *gpio)
                 u32 val = (unk1 << 16) | unk0;
                 u32 reg = regs[line >> 4]; line &= 0x0f;
 
-                if (func == 0xff)
+                if ( func  == DCB_GPIO_UNUSED ||
+                    (match != DCB_GPIO_UNUSED && match != func))
                         continue;
 
                 gpio->set(gpio, 0, func, line, defs);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c
index 8d18fcad26e0..83e8b8f16e6a 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c
@@ -29,15 +29,15 @@ struct nvd0_gpio_priv {
 };
 
 static void
-nvd0_gpio_reset(struct nouveau_gpio *gpio)
+nvd0_gpio_reset(struct nouveau_gpio *gpio, u8 match)
 {
         struct nouveau_bios *bios = nouveau_bios(gpio);
         struct nvd0_gpio_priv *priv = (void *)gpio;
+        u8 ver, len;
         u16 entry;
-        u8 ver;
         int ent = -1;
 
-        while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver))) {
+        while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
                 u32 data = nv_ro32(bios, entry);
                 u8  line =   (data & 0x0000003f);
                 u8  defs = !!(data & 0x00000080);
@@ -45,7 +45,8 @@ nvd0_gpio_reset(struct nouveau_gpio *gpio)
                 u8  unk0 =   (data & 0x00ff0000) >> 16;
                 u8  unk1 =   (data & 0x1f000000) >> 24;
 
-                if (func == 0xff)
+                if ( func  == DCB_GPIO_UNUSED ||
+                    (match != DCB_GPIO_UNUSED && match != func))
                         continue;
 
                 gpio->set(gpio, 0, func, line, defs);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c
index 1188227ca6aa..6565f3dbbe04 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c
@@ -40,15 +40,21 @@ nouveau_instobj_create_(struct nouveau_object *parent,
         if (ret)
                 return ret;
 
+        mutex_lock(&imem->base.mutex);
         list_add(&iobj->head, &imem->list);
+        mutex_unlock(&imem->base.mutex);
         return 0;
 }
 
 void
 nouveau_instobj_destroy(struct nouveau_instobj *iobj)
 {
-        if (iobj->head.prev)
-                list_del(&iobj->head);
+        struct nouveau_subdev *subdev = nv_subdev(iobj->base.engine);
+
+        mutex_lock(&subdev->mutex);
+        list_del(&iobj->head);
+        mutex_unlock(&subdev->mutex);
+
         return nouveau_object_destroy(&iobj->base);
 }
 
@@ -88,6 +94,8 @@ nouveau_instmem_init(struct nouveau_instmem *imem)
         if (ret)
                 return ret;
 
+        mutex_lock(&imem->base.mutex);
+
         list_for_each_entry(iobj, &imem->list, head) {
                 if (iobj->suspend) {
                         for (i = 0; i < iobj->size; i += 4)
@@ -97,6 +105,8 @@ nouveau_instmem_init(struct nouveau_instmem *imem)
                 }
         }
 
+        mutex_unlock(&imem->base.mutex);
+
         return 0;
 }
 
@@ -104,17 +114,26 @@ int
 nouveau_instmem_fini(struct nouveau_instmem *imem, bool suspend)
 {
         struct nouveau_instobj *iobj;
-        int i;
+        int i, ret = 0;
 
         if (suspend) {
+                mutex_lock(&imem->base.mutex);
+
                 list_for_each_entry(iobj, &imem->list, head) {
                         iobj->suspend = vmalloc(iobj->size);
-                        if (iobj->suspend) {
-                                for (i = 0; i < iobj->size; i += 4)
-                                        iobj->suspend[i / 4] = nv_ro32(iobj, i);
-                        } else
-                                return -ENOMEM;
+                        if (!iobj->suspend) {
+                                ret = -ENOMEM;
+                                break;
+                        }
+
+                        for (i = 0; i < iobj->size; i += 4)
+                                iobj->suspend[i / 4] = nv_ro32(iobj, i);
                 }
+
+                mutex_unlock(&imem->base.mutex);
+
+                if (ret)
+                        return ret;
         }
 
         return nouveau_subdev_fini(&imem->base, suspend);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c b/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c
index 93e3ddf7303a..e286e132c7e7 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c
@@ -260,7 +260,7 @@ nouveau_mxm_create_(struct nouveau_object *parent,
 
         data = mxm_table(bios, &ver, &len);
         if (!data || !(ver = nv_ro08(bios, data))) {
-                nv_info(mxm, "no VBIOS data, nothing to do\n");
+                nv_debug(mxm, "no VBIOS data, nothing to do\n");
                 return 0;
         }
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
index 082c11b75acb..77c67fc970e6 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
@@ -352,7 +352,7 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
         u64 mm_length = (offset + length) - mm_offset;
         int ret;
 
-        vm = *pvm = kzalloc(sizeof(*vm), GFP_KERNEL);
+        vm = kzalloc(sizeof(*vm), GFP_KERNEL);
         if (!vm)
                 return -ENOMEM;
 
@@ -376,6 +376,8 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
                 return ret;
         }
 
+        *pvm = vm;
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 5614c89148cb..69d7b1d0b9d6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -1276,7 +1276,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
                 if (drm->agp.stat == ENABLED) {
                         mem->bus.offset = mem->start << PAGE_SHIFT;
                         mem->bus.base = drm->agp.base;
-                        mem->bus.is_iomem = true;
+                        mem->bus.is_iomem = !dev->agp->cant_use_aperture;
                 }
 #endif
                 break;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index ac340ba32017..e620ba8271b4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -127,12 +127,26 @@ nouveau_connector_ddc_detect(struct drm_connector *connector,
                              struct nouveau_encoder **pnv_encoder)
 {
         struct drm_device *dev = connector->dev;
+        struct nouveau_connector *nv_connector = nouveau_connector(connector);
         struct nouveau_drm *drm = nouveau_drm(dev);
+        struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
         struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
-        int i;
+        struct nouveau_i2c_port *port = NULL;
+        int i, panel = -ENODEV;
+
+        /* eDP panels need powering on by us (if the VBIOS doesn't default it
+         * to on) before doing any AUX channel transactions.  LVDS panel power
+         * is handled by the SOR itself, and not required for LVDS DDC.
+         */
+        if (nv_connector->type == DCB_CONNECTOR_eDP) {
+                panel = gpio->get(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff);
+                if (panel == 0) {
+                        gpio->set(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff, 1);
+                        msleep(300);
+                }
+        }
 
         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
-                struct nouveau_i2c_port *port = NULL;
                 struct nouveau_encoder *nv_encoder;
                 struct drm_mode_object *obj;
                 int id;
@@ -150,11 +164,19 @@ nouveau_connector_ddc_detect(struct drm_connector *connector,
                         port = i2c->find(i2c, nv_encoder->dcb->i2c_index);
                 if (port && nv_probe_i2c(port, 0x50)) {
                         *pnv_encoder = nv_encoder;
-                        return port;
+                        break;
                 }
+
+                port = NULL;
         }
 
-        return NULL;
+        /* eDP panel not detected, restore panel power GPIO to previous
+         * state to avoid confusing the SOR for other output types.
+         */
+        if (!port && panel == 0)
+                gpio->set(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff, panel);
+
+        return port;
 }
 
 static struct nouveau_encoder *
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index e4188f24fc75..508b00a2ce0d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -225,15 +225,6 @@ nouveau_display_init(struct drm_device *dev)
         if (ret)
                 return ret;
 
-        /* power on internal panel if it's not already.  the init tables of
-         * some vbios default this to off for some reason, causing the
-         * panel to not work after resume
-         */
-        if (gpio && gpio->get(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff) == 0) {
-                gpio->set(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff, 1);
-                msleep(300);
-        }
-
         /* enable polling for external displays */
         drm_kms_helper_poll_enable(dev);
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 01c403ddb99b..8b090f1eb51d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -84,11 +84,16 @@ nouveau_cli_create(struct pci_dev *pdev, const char *name,
         struct nouveau_cli *cli;
         int ret;
 
+        *pcli = NULL;
         ret = nouveau_client_create_(name, nouveau_name(pdev), nouveau_config,
                                      nouveau_debug, size, pcli);
         cli = *pcli;
-        if (ret)
+        if (ret) {
+                if (cli)
+                        nouveau_client_destroy(&cli->base);
+                *pcli = NULL;
                 return ret;
+        }
 
         mutex_init(&cli->mutex);
         return 0;
@@ -189,8 +194,8 @@ nouveau_accel_init(struct nouveau_drm *drm)
         nouveau_bo_move_init(drm);
 }
 
-static int __devinit
-nouveau_drm_probe(struct pci_dev *pdev, const struct pci_device_id *pent)
+static int nouveau_drm_probe(struct pci_dev *pdev,
+                             const struct pci_device_id *pent)
 {
         struct nouveau_device *device;
         struct apertures_struct *aper;
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.h b/drivers/gpu/drm/nouveau/nouveau_fence.h
index bedafd1c9539..cdb83acdffe2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.h
@@ -60,6 +60,7 @@ u32  nv10_fence_read(struct nouveau_channel *);
 void nv10_fence_context_del(struct nouveau_channel *);
 void nv10_fence_destroy(struct nouveau_drm *);
 int  nv10_fence_create(struct nouveau_drm *);
+void nv17_fence_resume(struct nouveau_drm *drm);
 
 int nv50_fence_create(struct nouveau_drm *);
 int nv84_fence_create(struct nouveau_drm *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c b/drivers/gpu/drm/nouveau/nouveau_pm.c
index 5566172774df..a701ff5ffa5b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.c
@@ -698,10 +698,10 @@ static int
 nouveau_hwmon_init(struct drm_device *dev)
 {
         struct nouveau_pm *pm = nouveau_pm(dev);
-        struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_therm *therm = nouveau_therm(drm->device);
 
 #if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE))
+        struct nouveau_drm *drm = nouveau_drm(dev);
+        struct nouveau_therm *therm = nouveau_therm(drm->device);
         struct device *hwmon_dev;
         int ret = 0;
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c b/drivers/gpu/drm/nouveau/nouveau_prime.c
index 3543fec2355e..b8e05ae38212 100644
--- a/drivers/gpu/drm/nouveau/nouveau_prime.c
+++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
@@ -193,6 +193,7 @@ struct drm_gem_object *nouveau_gem_prime_import(struct drm_device *dev,
                 if (nvbo->gem) {
                         if (nvbo->gem->dev == dev) {
                                 drm_gem_object_reference(nvbo->gem);
+                                dma_buf_put(dma_buf);
                                 return nvbo->gem;
                         }
                 }
diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c
index 184cdf806761..39ffc07f906b 100644
--- a/drivers/gpu/drm/nouveau/nv04_dfp.c
+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c
@@ -505,7 +505,7 @@ static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
 
 static inline bool is_powersaving_dpms(int mode)
 {
-        return (mode != DRM_MODE_DPMS_ON);
+        return mode != DRM_MODE_DPMS_ON && mode != NV_DPMS_CLEARED;
 }
 
 static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
diff --git a/drivers/gpu/drm/nouveau/nv10_fence.c b/drivers/gpu/drm/nouveau/nv10_fence.c
index 7ae7f97a6d4d..03017f24d593 100644
--- a/drivers/gpu/drm/nouveau/nv10_fence.c
+++ b/drivers/gpu/drm/nouveau/nv10_fence.c
@@ -162,6 +162,13 @@ nv10_fence_destroy(struct nouveau_drm *drm)
         kfree(priv);
 }
 
+void nv17_fence_resume(struct nouveau_drm *drm)
+{
+        struct nv10_fence_priv *priv = drm->fence;
+
+        nouveau_bo_wr32(priv->bo, 0, priv->sequence);
+}
+
 int
 nv10_fence_create(struct nouveau_drm *drm)
 {
@@ -197,6 +204,7 @@ nv10_fence_create(struct nouveau_drm *drm)
                 if (ret == 0) {
                         nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
                         priv->base.sync = nv17_fence_sync;
+                        priv->base.resume = nv17_fence_resume;
                 }
         }
 
diff --git a/drivers/gpu/drm/nouveau/nv50_fence.c b/drivers/gpu/drm/nouveau/nv50_fence.c
index c20f2727ea0b..d889f3ac0d41 100644
--- a/drivers/gpu/drm/nouveau/nv50_fence.c
+++ b/drivers/gpu/drm/nouveau/nv50_fence.c
@@ -122,6 +122,7 @@ nv50_fence_create(struct nouveau_drm *drm)
         if (ret == 0) {
                 nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
                 priv->base.sync = nv17_fence_sync;
+                priv->base.resume = nv17_fence_resume;
         }
 
         if (ret)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index f95d7fc1f5e0..4d0e60adbc6d 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2306,22 +2306,20 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin
         return radeon_ring_test_lockup(rdev, ring);
 }
 
-static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
+static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev)
 {
-        struct evergreen_mc_save save;
         u32 grbm_reset = 0;
 
         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
-                return 0;
+                return;
 
-        dev_info(rdev->dev, "GPU softreset \n");
-        dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
                 RREG32(GRBM_STATUS));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE0));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE1));
-        dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
                 RREG32(SRBM_STATUS));
         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
                 RREG32(CP_STALLED_STAT1));
@@ -2331,10 +2329,7 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
                 RREG32(CP_BUSY_STAT));
         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
                 RREG32(CP_STAT));
-        evergreen_mc_stop(rdev, &save);
-        if (evergreen_mc_wait_for_idle(rdev)) {
-                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
-        }
+
         /* Disable CP parsing/prefetching */
         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
 
@@ -2358,15 +2353,14 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
         udelay(50);
         WREG32(GRBM_SOFT_RESET, 0);
         (void)RREG32(GRBM_SOFT_RESET);
-        /* Wait a little for things to settle down */
-        udelay(50);
-        dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
+
+        dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
                 RREG32(GRBM_STATUS));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE0));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE1));
-        dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
                 RREG32(SRBM_STATUS));
         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
                 RREG32(CP_STALLED_STAT1));
@@ -2376,13 +2370,71 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
                 RREG32(CP_BUSY_STAT));
         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
                 RREG32(CP_STAT));
+}
+
+static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
+                return;
+
+        dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
+                RREG32(DMA_STATUS_REG));
+
+        /* Disable DMA */
+        tmp = RREG32(DMA_RB_CNTL);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL, tmp);
+
+        /* Reset dma */
+        WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
+        RREG32(SRBM_SOFT_RESET);
+        udelay(50);
+        WREG32(SRBM_SOFT_RESET, 0);
+
+        dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
+                RREG32(DMA_STATUS_REG));
+}
+
+static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
+{
+        struct evergreen_mc_save save;
+
+        if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
+                reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
+
+        if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
+                reset_mask &= ~RADEON_RESET_DMA;
+
+        if (reset_mask == 0)
+                return 0;
+
+        dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
+
+        evergreen_mc_stop(rdev, &save);
+        if (evergreen_mc_wait_for_idle(rdev)) {
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+        }
+
+        if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
+                evergreen_gpu_soft_reset_gfx(rdev);
+
+        if (reset_mask & RADEON_RESET_DMA)
+                evergreen_gpu_soft_reset_dma(rdev);
+
+        /* Wait a little for things to settle down */
+        udelay(50);
+
         evergreen_mc_resume(rdev, &save);
         return 0;
 }
 
 int evergreen_asic_reset(struct radeon_device *rdev)
 {
-        return evergreen_gpu_soft_reset(rdev);
+        return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
+                                               RADEON_RESET_COMPUTE |
+                                               RADEON_RESET_DMA));
 }
 
 /* Interrupts */
@@ -3215,7 +3267,7 @@ void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
         /* flush HDP */
         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
-        radeon_ring_write(ring, (0xf << 16) | HDP_MEM_COHERENCY_FLUSH_CNTL);
+        radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
         radeon_ring_write(ring, 1);
 }
 
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 74c6b42d2597..7a445666e71f 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -2654,6 +2654,35 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                         ib[idx+4] = upper_32_bits(offset) & 0xff;
                 }
                 break;
+        case PACKET3_MEM_WRITE:
+        {
+                u64 offset;
+
+                if (pkt->count != 3) {
+                        DRM_ERROR("bad MEM_WRITE (invalid count)\n");
+                        return -EINVAL;
+                }
+                r = evergreen_cs_packet_next_reloc(p, &reloc);
+                if (r) {
+                        DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
+                        return -EINVAL;
+                }
+                offset = radeon_get_ib_value(p, idx+0);
+                offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
+                if (offset & 0x7) {
+                        DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
+                        return -EINVAL;
+                }
+                if ((offset + 8) > radeon_bo_size(reloc->robj)) {
+                        DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",
+                                  offset + 8, radeon_bo_size(reloc->robj));
+                        return -EINVAL;
+                }
+                offset += reloc->lobj.gpu_offset;
+                ib[idx+0] = offset;
+                ib[idx+1] = upper_32_bits(offset) & 0xff;
+                break;
+        }
         case PACKET3_COPY_DW:
                 if (pkt->count != 4) {
                         DRM_ERROR("bad COPY_DW (invalid count)\n");
@@ -3287,6 +3316,7 @@ static bool evergreen_vm_reg_valid(u32 reg)
 
         /* check config regs */
         switch (reg) {
+        case WAIT_UNTIL:
         case GRBM_GFX_INDEX:
         case CP_STRMOUT_CNTL:
         case CP_COHER_CNTL:
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index cb9baaac9e85..0bfd0e9e469b 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -742,8 +742,9 @@
 #define         SOFT_RESET_ROM                          (1 << 14)
 #define         SOFT_RESET_SEM                          (1 << 15)
 #define         SOFT_RESET_VMC                          (1 << 17)
+#define         SOFT_RESET_DMA                          (1 << 20)
 #define         SOFT_RESET_TST                          (1 << 21)
-#define         SOFT_RESET_REGBB                        (1 << 22)
+#define         SOFT_RESET_REGBB                        (1 << 22)
 #define         SOFT_RESET_ORB                          (1 << 23)
 
 /* display watermarks */
@@ -2027,4 +2028,15 @@
 /* cayman packet3 addition */
 #define CAYMAN_PACKET3_DEALLOC_STATE                    0x14
 
+/* DMA regs common on r6xx/r7xx/evergreen/ni */
+#define DMA_RB_CNTL                                       0xd000
+#       define DMA_RB_ENABLE                              (1 << 0)
+#       define DMA_RB_SIZE(x)                             ((x) << 1) /* log2 */
+#       define DMA_RB_SWAP_ENABLE                         (1 << 9) /* 8IN32 */
+#       define DMA_RPTR_WRITEBACK_ENABLE                  (1 << 12)
+#       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 << 13)  /* 8IN32 */
+#       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) << 16) /* log2 */
+#define DMA_STATUS_REG                                    0xd034
+#       define DMA_IDLE                                   (1 << 0)
+
 #endif
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 7bdbcb00aaf2..59acabb45c9b 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1306,22 +1306,20 @@ void cayman_dma_fini(struct radeon_device *rdev)
         radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
 }
 
-static int cayman_gpu_soft_reset(struct radeon_device *rdev)
+static void cayman_gpu_soft_reset_gfx(struct radeon_device *rdev)
 {
-        struct evergreen_mc_save save;
         u32 grbm_reset = 0;
 
         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
-                return 0;
+                return;
 
-        dev_info(rdev->dev, "GPU softreset \n");
-        dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
                 RREG32(GRBM_STATUS));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE0));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE1));
-        dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
                 RREG32(SRBM_STATUS));
         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
                 RREG32(CP_STALLED_STAT1));
@@ -1331,19 +1329,7 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
                 RREG32(CP_BUSY_STAT));
         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
                 RREG32(CP_STAT));
-        dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",
-                 RREG32(0x14F8));
-        dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
-                 RREG32(0x14D8));
-        dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
-                 RREG32(0x14FC));
-        dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
-                 RREG32(0x14DC));
 
-        evergreen_mc_stop(rdev, &save);
-        if (evergreen_mc_wait_for_idle(rdev)) {
-                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
-        }
         /* Disable CP parsing/prefetching */
         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
 
@@ -1368,16 +1354,14 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
         udelay(50);
         WREG32(GRBM_SOFT_RESET, 0);
         (void)RREG32(GRBM_SOFT_RESET);
-        /* Wait a little for things to settle down */
-        udelay(50);
 
-        dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
                 RREG32(GRBM_STATUS));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE0));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE1));
-        dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
                 RREG32(SRBM_STATUS));
         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
                 RREG32(CP_STALLED_STAT1));
@@ -1387,13 +1371,87 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
                 RREG32(CP_BUSY_STAT));
         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
                 RREG32(CP_STAT));
+
+}
+
+static void cayman_gpu_soft_reset_dma(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
+                return;
+
+        dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
+                RREG32(DMA_STATUS_REG));
+
+        /* dma0 */
+        tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
+
+        /* dma1 */
+        tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
+
+        /* Reset dma */
+        WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
+        RREG32(SRBM_SOFT_RESET);
+        udelay(50);
+        WREG32(SRBM_SOFT_RESET, 0);
+
+        dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
+                RREG32(DMA_STATUS_REG));
+
+}
+
+static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
+{
+        struct evergreen_mc_save save;
+
+        if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
+                reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
+
+        if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
+                reset_mask &= ~RADEON_RESET_DMA;
+
+        if (reset_mask == 0)
+                return 0;
+
+        dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
+
+        dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",
+                 RREG32(0x14F8));
+        dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
+                 RREG32(0x14D8));
+        dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
+                 RREG32(0x14FC));
+        dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
+                 RREG32(0x14DC));
+
+        evergreen_mc_stop(rdev, &save);
+        if (evergreen_mc_wait_for_idle(rdev)) {
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+        }
+
+        if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
+                cayman_gpu_soft_reset_gfx(rdev);
+
+        if (reset_mask & RADEON_RESET_DMA)
+                cayman_gpu_soft_reset_dma(rdev);
+
+        /* Wait a little for things to settle down */
+        udelay(50);
+
         evergreen_mc_resume(rdev, &save);
         return 0;
 }
 
 int cayman_asic_reset(struct radeon_device *rdev)
 {
-        return cayman_gpu_soft_reset(rdev);
+        return cayman_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
+                                            RADEON_RESET_COMPUTE |
+                                            RADEON_RESET_DMA));
 }
 
 /**
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index b93186b8ee4b..48e5022ee921 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -65,7 +65,7 @@
 #define         SOFT_RESET_VMC                          (1 << 17)
 #define         SOFT_RESET_DMA                          (1 << 20)
 #define         SOFT_RESET_TST                          (1 << 21)
-#define         SOFT_RESET_REGBB                        (1 << 22)
+#define         SOFT_RESET_REGBB                        (1 << 22)
 #define         SOFT_RESET_ORB                          (1 << 23)
 
 #define VM_CONTEXT0_REQUEST_RESPONSE                    0x1470
@@ -675,4 +675,3 @@
 #define DMA_PACKET_NOP                                    0xf
 
 #endif
-
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 2aaf147969bd..3cb9d6089373 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1258,9 +1258,8 @@ void r600_vram_scratch_fini(struct radeon_device *rdev)
  * reset, it's up to the caller to determine if the GPU needs one. We
  * might add an helper function to check that.
  */
-static int r600_gpu_soft_reset(struct radeon_device *rdev)
+static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev)
 {
-        struct rv515_mc_save save;
         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
@@ -1280,14 +1279,13 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev)
         u32 tmp;
 
         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
-                return 0;
+                return;
 
-        dev_info(rdev->dev, "GPU softreset \n");
-        dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
                 RREG32(R_008010_GRBM_STATUS));
-        dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
+        dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
                 RREG32(R_008014_GRBM_STATUS2));
-        dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
                 RREG32(R_000E50_SRBM_STATUS));
         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
                 RREG32(CP_STALLED_STAT1));
@@ -1297,12 +1295,10 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev)
                 RREG32(CP_BUSY_STAT));
         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
                 RREG32(CP_STAT));
-        rv515_mc_stop(rdev, &save);
-        if (r600_mc_wait_for_idle(rdev)) {
-                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
-        }
+
         /* Disable CP parsing/prefetching */
         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
+
         /* Check if any of the rendering block is busy and reset it */
         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
@@ -1332,13 +1328,12 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev)
         RREG32(R_008020_GRBM_SOFT_RESET);
         mdelay(15);
         WREG32(R_008020_GRBM_SOFT_RESET, 0);
-        /* Wait a little for things to settle down */
-        mdelay(1);
-        dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
+
+        dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
                 RREG32(R_008010_GRBM_STATUS));
-        dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
+        dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
                 RREG32(R_008014_GRBM_STATUS2));
-        dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
                 RREG32(R_000E50_SRBM_STATUS));
         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
                 RREG32(CP_STALLED_STAT1));
@@ -1348,6 +1343,66 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev)
                 RREG32(CP_BUSY_STAT));
         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
                 RREG32(CP_STAT));
+
+}
+
+static void r600_gpu_soft_reset_dma(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
+                return;
+
+        dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
+                RREG32(DMA_STATUS_REG));
+
+        /* Disable DMA */
+        tmp = RREG32(DMA_RB_CNTL);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL, tmp);
+
+        /* Reset dma */
+        if (rdev->family >= CHIP_RV770)
+                WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
+        else
+                WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
+        RREG32(SRBM_SOFT_RESET);
+        udelay(50);
+        WREG32(SRBM_SOFT_RESET, 0);
+
+        dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
+                RREG32(DMA_STATUS_REG));
+}
+
+static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
+{
+        struct rv515_mc_save save;
+
+        if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
+                reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
+
+        if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
+                reset_mask &= ~RADEON_RESET_DMA;
+
+        if (reset_mask == 0)
+                return 0;
+
+        dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
+
+        rv515_mc_stop(rdev, &save);
+        if (r600_mc_wait_for_idle(rdev)) {
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+        }
+
+        if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
+                r600_gpu_soft_reset_gfx(rdev);
+
+        if (reset_mask & RADEON_RESET_DMA)
+                r600_gpu_soft_reset_dma(rdev);
+
+        /* Wait a little for things to settle down */
+        mdelay(1);
+
         rv515_mc_resume(rdev, &save);
         return 0;
 }
@@ -1395,7 +1450,9 @@ bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
 
 int r600_asic_reset(struct radeon_device *rdev)
 {
-        return r600_gpu_soft_reset(rdev);
+        return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
+                                          RADEON_RESET_COMPUTE |
+                                          RADEON_RESET_DMA));
 }
 
 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
@@ -2595,7 +2652,7 @@ int r600_copy_blit(struct radeon_device *rdev,
  * @num_gpu_pages: number of GPU pages to xfer
  * @fence: radeon fence object
  *
- * Copy GPU paging using the DMA engine (r6xx-r7xx).
+ * Copy GPU paging using the DMA engine (r6xx).
  * Used by the radeon ttm implementation to move pages if
  * registered as the asic copy callback.
  */
@@ -2618,8 +2675,8 @@ int r600_copy_dma(struct radeon_device *rdev,
         }
 
         size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
-        num_loops = DIV_ROUND_UP(size_in_dw, 0xffff);
-        r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
+        num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
+        r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
         if (r) {
                 DRM_ERROR("radeon: moving bo (%d).\n", r);
                 radeon_semaphore_free(rdev, &sem, NULL);
@@ -2636,14 +2693,14 @@ int r600_copy_dma(struct radeon_device *rdev,
 
         for (i = 0; i < num_loops; i++) {
                 cur_size_in_dw = size_in_dw;
-                if (cur_size_in_dw > 0xFFFF)
-                        cur_size_in_dw = 0xFFFF;
+                if (cur_size_in_dw > 0xFFFE)
+                        cur_size_in_dw = 0xFFFE;
                 size_in_dw -= cur_size_in_dw;
                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
                 radeon_ring_write(ring, dst_offset & 0xfffffffc);
                 radeon_ring_write(ring, src_offset & 0xfffffffc);
-                radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
-                radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
+                radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
+                                         (upper_32_bits(src_offset) & 0xff)));
                 src_offset += cur_size_in_dw * 4;
                 dst_offset += cur_size_in_dw * 4;
         }
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 0be768be530c..69ec24ab8d63 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -2294,6 +2294,35 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                         ib[idx+4] = upper_32_bits(offset) & 0xff;
                 }
                 break;
+        case PACKET3_MEM_WRITE:
+        {
+                u64 offset;
+
+                if (pkt->count != 3) {
+                        DRM_ERROR("bad MEM_WRITE (invalid count)\n");
+                        return -EINVAL;
+                }
+                r = r600_cs_packet_next_reloc(p, &reloc);
+                if (r) {
+                        DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
+                        return -EINVAL;
+                }
+                offset = radeon_get_ib_value(p, idx+0);
+                offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
+                if (offset & 0x7) {
+                        DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
+                        return -EINVAL;
+                }
+                if ((offset + 8) > radeon_bo_size(reloc->robj)) {
+                        DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",
+                                  offset + 8, radeon_bo_size(reloc->robj));
+                        return -EINVAL;
+                }
+                offset += reloc->lobj.gpu_offset;
+                ib[idx+0] = offset;
+                ib[idx+1] = upper_32_bits(offset) & 0xff;
+                break;
+        }
         case PACKET3_COPY_DW:
                 if (pkt->count != 4) {
                         DRM_ERROR("bad COPY_DW (invalid count)\n");
@@ -2447,8 +2476,10 @@ static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
         kfree(parser->relocs);
         for (i = 0; i < parser->nchunks; i++) {
                 kfree(parser->chunks[i].kdata);
-                kfree(parser->chunks[i].kpage[0]);
-                kfree(parser->chunks[i].kpage[1]);
+                if (parser->rdev && (parser->rdev->flags & RADEON_IS_AGP)) {
+                        kfree(parser->chunks[i].kpage[0]);
+                        kfree(parser->chunks[i].kpage[1]);
+                }
         }
         kfree(parser->chunks);
         kfree(parser->chunks_array);
@@ -2532,16 +2563,16 @@ int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
         struct radeon_cs_chunk *relocs_chunk;
         unsigned idx;
 
+        *cs_reloc = NULL;
         if (p->chunk_relocs_idx == -1) {
                 DRM_ERROR("No relocation chunk !\n");
                 return -EINVAL;
         }
-        *cs_reloc = NULL;
         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
         idx = p->dma_reloc_idx;
-        if (idx >= relocs_chunk->length_dw) {
+        if (idx >= p->nrelocs) {
                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
-                          idx, relocs_chunk->length_dw);
+                          idx, p->nrelocs);
                 return -EINVAL;
         }
         *cs_reloc = p->relocs_ptr[idx];
@@ -2648,16 +2679,29 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
                                 }
                                 p->idx += 7;
                         } else {
-                                src_offset = ib[idx+2];
-                                src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
-                                dst_offset = ib[idx+1];
-                                dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
+                                if (p->family >= CHIP_RV770) {
+                                        src_offset = ib[idx+2];
+                                        src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
+                                        dst_offset = ib[idx+1];
+                                        dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
 
-                                ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                                ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
-                                ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
-                                ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
-                                p->idx += 5;
+                                        ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
+                                        ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
+                                        ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
+                                        ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                                        p->idx += 5;
+                                } else {
+                                        src_offset = ib[idx+2];
+                                        src_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
+                                        dst_offset = ib[idx+1];
+                                        dst_offset |= ((u64)(ib[idx+3] & 0xff0000)) << 16;
+
+                                        ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
+                                        ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
+                                        ib[idx+3] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                                        ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff) << 16;
+                                        p->idx += 4;
+                                }
                         }
                         if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
                                 dev_warn(p->dev, "DMA copy src buffer too small (%llu %lu)\n",
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5dc744d43d12..a08f657329a0 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -132,6 +132,11 @@ extern int radeon_lockup_timeout;
 #define RADEON_VA_RESERVED_SIZE                 (8 << 20)
 #define RADEON_IB_VM_MAX_SIZE                   (64 << 10)
 
+/* reset flags */
+#define RADEON_RESET_GFX                        (1 << 0)
+#define RADEON_RESET_COMPUTE                    (1 << 1)
+#define RADEON_RESET_DMA                        (1 << 2)
+
 /*
  * Errata workarounds.
  */
@@ -225,12 +230,13 @@ struct radeon_fence {
 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
 int radeon_fence_driver_init(struct radeon_device *rdev);
 void radeon_fence_driver_fini(struct radeon_device *rdev);
+void radeon_fence_driver_force_completion(struct radeon_device *rdev);
 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
 void radeon_fence_process(struct radeon_device *rdev, int ring);
 bool radeon_fence_signaled(struct radeon_fence *fence);
 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
-void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
+int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
 int radeon_fence_wait_any(struct radeon_device *rdev,
                           struct radeon_fence **fences,
                           bool intr);
@@ -318,7 +324,6 @@ struct radeon_bo {
         struct list_head                list;
         /* Protected by tbo.reserved */
         u32                             placements[3];
-        u32                             busy_placements[3];
         struct ttm_placement            placement;
         struct ttm_buffer_object        tbo;
         struct ttm_bo_kmap_obj          kmap;
@@ -648,6 +653,8 @@ struct radeon_ring {
         u32                     ptr_reg_mask;
         u32                     nop;
         u32                     idx;
+        u64                     last_semaphore_signal_addr;
+        u64                     last_semaphore_wait_addr;
 };
 
 /*
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 596bcbe80ed0..9056fafb00ea 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1140,9 +1140,9 @@ static struct radeon_asic rv770_asic = {
         .copy = {
                 .blit = &r600_copy_blit,
                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
-                .dma = &r600_copy_dma,
+                .dma = &rv770_copy_dma,
                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
-                .copy = &r600_copy_dma,
+                .copy = &rv770_copy_dma,
                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
         },
         .surface = {
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 5f4882cc2152..15d70e613076 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -403,6 +403,10 @@ u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
 void r700_cp_stop(struct radeon_device *rdev);
 void r700_cp_fini(struct radeon_device *rdev);
+int rv770_copy_dma(struct radeon_device *rdev,
+                  uint64_t src_offset, uint64_t dst_offset,
+                  unsigned num_gpu_pages,
+                   struct radeon_fence **fence);
 
 /*
  * evergreen
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 4af89126e223..33a56a09ff10 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -1548,6 +1548,9 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                            of_machine_is_compatible("PowerBook6,7")) {
                         /* ibook */
                         rdev->mode_info.connector_table = CT_IBOOK;
+                } else if (of_machine_is_compatible("PowerMac3,5")) {
+                        /* PowerMac G4 Silver radeon 7500 */
+                        rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
                 } else if (of_machine_is_compatible("PowerMac4,4")) {
                         /* emac */
                         rdev->mode_info.connector_table = CT_EMAC;
@@ -2212,6 +2215,54 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                             CONNECTOR_OBJECT_ID_SVIDEO,
                                             &hpd);
                 break;
+        case CT_MAC_G4_SILVER:
+                DRM_INFO("Connector Table: %d (mac g4 silver)\n",
+                         rdev->mode_info.connector_table);
+                /* DVI-I - tv dac, int tmds */
+                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
+                hpd.hpd = RADEON_HPD_1; /* ??? */
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_enum(dev,
+                                                                ATOM_DEVICE_DFP1_SUPPORT,
+                                                                0),
+                                          ATOM_DEVICE_DFP1_SUPPORT);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_enum(dev,
+                                                                ATOM_DEVICE_CRT2_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_CRT2_SUPPORT);
+                radeon_add_legacy_connector(dev, 0,
+                                            ATOM_DEVICE_DFP1_SUPPORT |
+                                            ATOM_DEVICE_CRT2_SUPPORT,
+                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
+                                            &hpd);
+                /* VGA - primary dac */
+                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
+                hpd.hpd = RADEON_HPD_NONE;
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_enum(dev,
+                                                                ATOM_DEVICE_CRT1_SUPPORT,
+                                                                1),
+                                          ATOM_DEVICE_CRT1_SUPPORT);
+                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_VGA,
+                                            &hpd);
+                /* TV - TV DAC */
+                ddc_i2c.valid = false;
+                hpd.hpd = RADEON_HPD_NONE;
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_enum(dev,
+                                                                ATOM_DEVICE_TV1_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_TV1_SUPPORT);
+                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_SVIDEO,
+                                            &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SVIDEO,
+                                            &hpd);
+                break;
         default:
                 DRM_INFO("Connector table: %d (invalid)\n",
                          rdev->mode_info.connector_table);
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 47bf162ab9c6..2399f25ec037 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -741,7 +741,7 @@ radeon_vga_detect(struct drm_connector *connector, bool force)
                 ret = connector_status_disconnected;
 
         if (radeon_connector->ddc_bus)
-                dret = radeon_ddc_probe(radeon_connector);
+                dret = radeon_ddc_probe(radeon_connector, false);
         if (dret) {
                 radeon_connector->detected_by_load = false;
                 if (radeon_connector->edid) {
@@ -947,7 +947,7 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
                 return connector->status;
 
         if (radeon_connector->ddc_bus)
-                dret = radeon_ddc_probe(radeon_connector);
+                dret = radeon_ddc_probe(radeon_connector, false);
         if (dret) {
                 radeon_connector->detected_by_load = false;
                 if (radeon_connector->edid) {
@@ -1401,7 +1401,8 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
                 if (encoder) {
                         /* setup ddc on the bridge */
                         radeon_atom_ext_encoder_setup_ddc(encoder);
-                        if (radeon_ddc_probe(radeon_connector)) /* try DDC */
+                        /* bridge chips are always aux */
+                        if (radeon_ddc_probe(radeon_connector, true)) /* try DDC */
                                 ret = connector_status_connected;
                         else if (radeon_connector->dac_load_detect) { /* try load detection */
                                 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
@@ -1419,7 +1420,8 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
                                 if (radeon_dp_getdpcd(radeon_connector))
                                         ret = connector_status_connected;
                         } else {
-                                if (radeon_ddc_probe(radeon_connector))
+                                /* try non-aux ddc (DP to DVI/HMDI/etc. adapter) */
+                                if (radeon_ddc_probe(radeon_connector, false))
                                         ret = connector_status_connected;
                         }
                 }
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 396baba0141a..469661fd1903 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -279,13 +279,13 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
                                   p->chunks[p->chunk_ib_idx].length_dw);
                         return -EINVAL;
                 }
-                if ((p->rdev->flags & RADEON_IS_AGP)) {
+                if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) {
                         p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
                         p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
                         if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
                             p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
-                                kfree(p->chunks[i].kpage[0]);
-                                kfree(p->chunks[i].kpage[1]);
+                                kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
+                                kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
                                 return -ENOMEM;
                         }
                 }
@@ -583,7 +583,8 @@ static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
         int i;
         int size = PAGE_SIZE;
-        bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;
+        bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ?
+                false : true;
 
         for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
                 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 49b06590001e..edfc54e41842 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -897,6 +897,25 @@ static void radeon_check_arguments(struct radeon_device *rdev)
 }
 
 /**
+ * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
+ * needed for waking up.
+ *
+ * @pdev: pci dev pointer
+ */
+static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
+{
+
+        /* 6600m in a macbook pro */
+        if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
+            pdev->subsystem_device == 0x00e2) {
+                printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
+                return true;
+        }
+
+        return false;
+}
+
+/**
  * radeon_switcheroo_set_state - set switcheroo state
  *
  * @pdev: pci dev pointer
@@ -910,10 +929,19 @@ static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switchero
         struct drm_device *dev = pci_get_drvdata(pdev);
         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
         if (state == VGA_SWITCHEROO_ON) {
+                unsigned d3_delay = dev->pdev->d3_delay;
+
                 printk(KERN_INFO "radeon: switched on\n");
                 /* don't suspend or resume card normally */
                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+
+                if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
+                        dev->pdev->d3_delay = 20;
+
                 radeon_resume_kms(dev);
+
+                dev->pdev->d3_delay = d3_delay;
+
                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
                 drm_kms_helper_poll_enable(dev);
         } else {
@@ -1164,6 +1192,7 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
         struct drm_crtc *crtc;
         struct drm_connector *connector;
         int i, r;
+        bool force_completion = false;
 
         if (dev == NULL || dev->dev_private == NULL) {
                 return -ENODEV;
@@ -1206,8 +1235,16 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 
         mutex_lock(&rdev->ring_lock);
         /* wait for gpu to finish processing current batch */
-        for (i = 0; i < RADEON_NUM_RINGS; i++)
-                radeon_fence_wait_empty_locked(rdev, i);
+        for (i = 0; i < RADEON_NUM_RINGS; i++) {
+                r = radeon_fence_wait_empty_locked(rdev, i);
+                if (r) {
+                        /* delay GPU reset to resume */
+                        force_completion = true;
+                }
+        }
+        if (force_completion) {
+                radeon_fence_driver_force_completion(rdev);
+        }
         mutex_unlock(&rdev->ring_lock);
 
         radeon_save_bios_scratch_regs(rdev);
@@ -1338,7 +1375,6 @@ retry:
         }
 
         radeon_restore_bios_scratch_regs(rdev);
-        drm_helper_resume_force_mode(rdev->ddev);
 
         if (!r) {
                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
@@ -1358,11 +1394,14 @@ retry:
                         }
                 }
         } else {
+                radeon_fence_driver_force_completion(rdev);
                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
                         kfree(ring_data[i]);
                 }
         }
 
+        drm_helper_resume_force_mode(rdev->ddev);
+
         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
         if (r) {
                 /* bad news, how to tell it to userspace ? */
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 310c0e5254ba..1da2386d7cf7 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -699,10 +699,15 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
         if (radeon_connector->router.ddc_valid)
                 radeon_router_select_ddc_port(radeon_connector);
 
-        if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
-            (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) ||
-            (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
-             ENCODER_OBJECT_ID_NONE)) {
+        if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
+            ENCODER_OBJECT_ID_NONE) {
+                struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
+
+                if (dig->dp_i2c_bus)
+                        radeon_connector->edid = drm_get_edid(&radeon_connector->base,
+                                                              &dig->dp_i2c_bus->adapter);
+        } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
+                   (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 
                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 9b1a727d3c9e..d9bf96ee299a 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -68,9 +68,11 @@
  *   2.25.0 - eg+: new info request for num SE and num SH
  *   2.26.0 - r600-eg: fix htile size computation
  *   2.27.0 - r600-SI: Add CS ioctl support for async DMA
+ *   2.28.0 - r600-eg: Add MEM_WRITE packet support
+ *   2.29.0 - R500 FP16 color clear registers
  */
 #define KMS_DRIVER_MAJOR        2
-#define KMS_DRIVER_MINOR        27
+#define KMS_DRIVER_MINOR        29
 #define KMS_DRIVER_PATCHLEVEL   0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);
@@ -305,8 +307,8 @@ static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
         return 0;
 }
 
-static int __devinit
-radeon_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+static int radeon_pci_probe(struct pci_dev *pdev,
+                            const struct pci_device_id *ent)
 {
         int ret;
 
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 410a975a8eec..34356252567a 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -609,26 +609,20 @@ int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring)
  * Returns 0 if the fences have passed, error for all other cases.
  * Caller must hold ring lock.
  */
-void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring)
+int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring)
 {
         uint64_t seq = rdev->fence_drv[ring].sync_seq[ring];
+        int r;
 
-        while(1) {
-                int r;
-                r = radeon_fence_wait_seq(rdev, seq, ring, false, false);
+        r = radeon_fence_wait_seq(rdev, seq, ring, false, false);
+        if (r) {
                 if (r == -EDEADLK) {
-                        mutex_unlock(&rdev->ring_lock);
-                        r = radeon_gpu_reset(rdev);
-                        mutex_lock(&rdev->ring_lock);
-                        if (!r)
-                                continue;
-                }
-                if (r) {
-                        dev_err(rdev->dev, "error waiting for ring to become"
-                                " idle (%d)\n", r);
+                        return -EDEADLK;
                 }
-                return;
+                dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%d)\n",
+                        ring, r);
         }
+        return 0;
 }
 
 /**
@@ -854,13 +848,17 @@ int radeon_fence_driver_init(struct radeon_device *rdev)
  */
 void radeon_fence_driver_fini(struct radeon_device *rdev)
 {
-        int ring;
+        int ring, r;
 
         mutex_lock(&rdev->ring_lock);
         for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
                 if (!rdev->fence_drv[ring].initialized)
                         continue;
-                radeon_fence_wait_empty_locked(rdev, ring);
+                r = radeon_fence_wait_empty_locked(rdev, ring);
+                if (r) {
+                        /* no need to trigger GPU reset as we are unloading */
+                        radeon_fence_driver_force_completion(rdev);
+                }
                 wake_up_all(&rdev->fence_queue);
                 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
                 rdev->fence_drv[ring].initialized = false;
@@ -868,6 +866,25 @@ void radeon_fence_driver_fini(struct radeon_device *rdev)
         mutex_unlock(&rdev->ring_lock);
 }
 
+/**
+ * radeon_fence_driver_force_completion - force all fence waiter to complete
+ *
+ * @rdev: radeon device pointer
+ *
+ * In case of GPU reset failure make sure no process keep waiting on fence
+ * that will never complete.
+ */
+void radeon_fence_driver_force_completion(struct radeon_device *rdev)
+{
+        int ring;
+
+        for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
+                if (!rdev->fence_drv[ring].initialized)
+                        continue;
+                radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
+        }
+}
+
 
 /*
  * Fence debugfs
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index c5bddd630eb9..fc60b74ee304 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -39,7 +39,7 @@ extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap);
  * radeon_ddc_probe
  *
  */
-bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
+bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
 {
         u8 out = 0x0;
         u8 buf[8];
@@ -63,7 +63,13 @@ bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
         if (radeon_connector->router.ddc_valid)
                 radeon_router_select_ddc_port(radeon_connector);
 
-        ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
+        if (use_aux) {
+                struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
+                ret = i2c_transfer(&dig->dp_i2c_bus->adapter, msgs, 2);
+        } else {
+                ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
+        }
+
         if (ret != 2)
                 /* Couldn't find an accessible DDC on this connector */
                 return false;
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index f5ba2241dacc..62cd512f5c8d 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -640,6 +640,14 @@ static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_enc
         enum drm_connector_status found = connector_status_disconnected;
         bool color = true;
 
+        /* just don't bother on RN50 those chip are often connected to remoting
+         * console hw and often we get failure to load detect those. So to make
+         * everyone happy report the encoder as always connected.
+         */
+        if (ASIC_IS_RN50(rdev)) {
+                return connector_status_connected;
+        }
+
         /* save the regs we need */
         vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index d818b503b42f..4003f5a68c09 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -209,7 +209,8 @@ enum radeon_connector_table {
         CT_RN50_POWER,
         CT_MAC_X800,
         CT_MAC_G5_9600,
-        CT_SAM440EP
+        CT_SAM440EP,
+        CT_MAC_G4_SILVER
 };
 
 enum radeon_dvo_chip {
@@ -558,7 +559,7 @@ extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
                                 u8 val);
 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
-extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
+extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
 
 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 883c95d8d90f..d3aface2d12d 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -84,6 +84,7 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
         rbo->placement.fpfn = 0;
         rbo->placement.lpfn = 0;
         rbo->placement.placement = rbo->placements;
+        rbo->placement.busy_placement = rbo->placements;
         if (domain & RADEON_GEM_DOMAIN_VRAM)
                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
                                         TTM_PL_FLAG_VRAM;
@@ -104,14 +105,6 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
         if (!c)
                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
         rbo->placement.num_placement = c;
-
-        c = 0;
-        rbo->placement.busy_placement = rbo->busy_placements;
-        if (rbo->rdev->flags & RADEON_IS_AGP) {
-                rbo->busy_placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
-        } else {
-                rbo->busy_placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
-        }
         rbo->placement.num_busy_placement = c;
 }
 
@@ -357,6 +350,7 @@ int radeon_bo_list_validate(struct list_head *head)
 {
         struct radeon_bo_list *lobj;
         struct radeon_bo *bo;
+        u32 domain;
         int r;
 
         r = ttm_eu_reserve_buffers(head);
@@ -366,9 +360,17 @@ int radeon_bo_list_validate(struct list_head *head)
         list_for_each_entry(lobj, head, tv.head) {
                 bo = lobj->bo;
                 if (!bo->pin_count) {
+                        domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
+                        
+                retry:
+                        radeon_ttm_placement_from_domain(bo, domain);
                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
                                                 true, false);
                         if (unlikely(r)) {
+                                if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
+                                        domain |= RADEON_GEM_DOMAIN_GTT;
+                                        goto retry;
+                                }
                                 return r;
                         }
                 }
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index aa14dbb7e4fb..0bfa656aa87d 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -234,7 +234,7 @@ static void radeon_set_power_state(struct radeon_device *rdev)
 
 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 {
-        int i;
+        int i, r;
 
         /* no need to take locks, etc. if nothing's going to change */
         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
@@ -248,8 +248,17 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev)
         /* wait for the rings to drain */
         for (i = 0; i < RADEON_NUM_RINGS; i++) {
                 struct radeon_ring *ring = &rdev->ring[i];
-                if (ring->ready)
-                        radeon_fence_wait_empty_locked(rdev, i);
+                if (!ring->ready) {
+                        continue;
+                }
+                r = radeon_fence_wait_empty_locked(rdev, i);
+                if (r) {
+                        /* needs a GPU reset dont reset here */
+                        mutex_unlock(&rdev->ring_lock);
+                        up_write(&rdev->pm.mclk_lock);
+                        mutex_unlock(&rdev->ddev->struct_mutex);
+                        return;
+                }
         }
 
         radeon_unmap_vram_bos(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_prime.c b/drivers/gpu/drm/radeon/radeon_prime.c
index e09521858f64..26c23bb651c6 100644
--- a/drivers/gpu/drm/radeon/radeon_prime.c
+++ b/drivers/gpu/drm/radeon/radeon_prime.c
@@ -194,6 +194,7 @@ struct drm_gem_object *radeon_gem_prime_import(struct drm_device *dev,
                 bo = dma_buf->priv;
                 if (bo->gem_base.dev == dev) {
                         drm_gem_object_reference(&bo->gem_base);
+                        dma_buf_put(dma_buf);
                         return &bo->gem_base;
                 }
         }
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index ebd69562ef6c..2430d80b1871 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -770,22 +770,30 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
         int ridx = *(int*)node->info_ent->data;
         struct radeon_ring *ring = &rdev->ring[ridx];
         unsigned count, i, j;
+        u32 tmp;
 
         radeon_ring_free_size(rdev, ring);
         count = (ring->ring_size / 4) - ring->ring_free_dw;
-        seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg));
-        seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg));
+        tmp = RREG32(ring->wptr_reg) >> ring->ptr_reg_shift;
+        seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp);
+        tmp = RREG32(ring->rptr_reg) >> ring->ptr_reg_shift;
+        seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp);
         if (ring->rptr_save_reg) {
                 seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg,
                            RREG32(ring->rptr_save_reg));
         }
-        seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr);
-        seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr);
+        seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr);
+        seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr);
+        seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr);
+        seq_printf(m, "last semaphore wait addr   : 0x%016llx\n", ring->last_semaphore_wait_addr);
         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
         seq_printf(m, "%u dwords in ring\n", count);
-        i = ring->rptr;
-        for (j = 0; j <= count; j++) {
-                seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
+        /* print 8 dw before current rptr as often it's the last executed
+         * packet that is the root issue
+         */
+        i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
+        for (j = 0; j <= (count + 32); j++) {
+                seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]);
                 i = (i + 1) & ring->ptr_mask;
         }
         return 0;
@@ -794,11 +802,15 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
 static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
 static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
 static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
+static int radeon_ring_type_dma1_index = R600_RING_TYPE_DMA_INDEX;
+static int radeon_ring_type_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
 
 static struct drm_info_list radeon_debugfs_ring_info_list[] = {
         {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
         {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
         {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
+        {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma1_index},
+        {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma2_index},
 };
 
 static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
diff --git a/drivers/gpu/drm/radeon/radeon_semaphore.c b/drivers/gpu/drm/radeon/radeon_semaphore.c
index 97f3ece81cd2..8dcc20f53d73 100644
--- a/drivers/gpu/drm/radeon/radeon_semaphore.c
+++ b/drivers/gpu/drm/radeon/radeon_semaphore.c
@@ -95,6 +95,10 @@ int radeon_semaphore_sync_rings(struct radeon_device *rdev,
         /* we assume caller has already allocated space on waiters ring */
         radeon_semaphore_emit_wait(rdev, waiter, semaphore);
 
+        /* for debugging lockup only, used by sysfs debug files */
+        rdev->ring[signaler].last_semaphore_signal_addr = semaphore->gpu_addr;
+        rdev->ring[waiter].last_semaphore_wait_addr = semaphore->gpu_addr;
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index 911a8fbd32bb..78d5e99d759d 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -324,6 +324,8 @@ rv515 0x6d40
 0x46AC US_OUT_FMT_2
 0x46B0 US_OUT_FMT_3
 0x46B4 US_W_FMT
+0x46C0 RB3D_COLOR_CLEAR_VALUE_AR
+0x46C4 RB3D_COLOR_CLEAR_VALUE_GB
 0x4BC0 FG_FOG_BLEND
 0x4BC4 FG_FOG_FACTOR
 0x4BC8 FG_FOG_COLOR_R
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 87c979c4f721..1b2444f4d8f4 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -887,6 +887,80 @@ static int rv770_mc_init(struct radeon_device *rdev)
         return 0;
 }
 
+/**
+ * rv770_copy_dma - copy pages using the DMA engine
+ *
+ * @rdev: radeon_device pointer
+ * @src_offset: src GPU address
+ * @dst_offset: dst GPU address
+ * @num_gpu_pages: number of GPU pages to xfer
+ * @fence: radeon fence object
+ *
+ * Copy GPU paging using the DMA engine (r7xx).
+ * Used by the radeon ttm implementation to move pages if
+ * registered as the asic copy callback.
+ */
+int rv770_copy_dma(struct radeon_device *rdev,
+                  uint64_t src_offset, uint64_t dst_offset,
+                  unsigned num_gpu_pages,
+                  struct radeon_fence **fence)
+{
+        struct radeon_semaphore *sem = NULL;
+        int ring_index = rdev->asic->copy.dma_ring_index;
+        struct radeon_ring *ring = &rdev->ring[ring_index];
+        u32 size_in_dw, cur_size_in_dw;
+        int i, num_loops;
+        int r = 0;
+
+        r = radeon_semaphore_create(rdev, &sem);
+        if (r) {
+                DRM_ERROR("radeon: moving bo (%d).\n", r);
+                return r;
+        }
+
+        size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
+        num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF);
+        r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
+        if (r) {
+                DRM_ERROR("radeon: moving bo (%d).\n", r);
+                radeon_semaphore_free(rdev, &sem, NULL);
+                return r;
+        }
+
+        if (radeon_fence_need_sync(*fence, ring->idx)) {
+                radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
+                                            ring->idx);
+                radeon_fence_note_sync(*fence, ring->idx);
+        } else {
+                radeon_semaphore_free(rdev, &sem, NULL);
+        }
+
+        for (i = 0; i < num_loops; i++) {
+                cur_size_in_dw = size_in_dw;
+                if (cur_size_in_dw > 0xFFFF)
+                        cur_size_in_dw = 0xFFFF;
+                size_in_dw -= cur_size_in_dw;
+                radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
+                radeon_ring_write(ring, dst_offset & 0xfffffffc);
+                radeon_ring_write(ring, src_offset & 0xfffffffc);
+                radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
+                radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
+                src_offset += cur_size_in_dw * 4;
+                dst_offset += cur_size_in_dw * 4;
+        }
+
+        r = radeon_fence_emit(rdev, fence, ring->idx);
+        if (r) {
+                radeon_ring_unlock_undo(rdev, ring);
+                return r;
+        }
+
+        radeon_ring_unlock_commit(rdev, ring);
+        radeon_semaphore_free(rdev, &sem, *fence);
+
+        return r;
+}
+
 static int rv770_startup(struct radeon_device *rdev)
 {
         struct radeon_ring *ring;
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index ef683653f0b7..ae8b48205a6c 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2126,15 +2126,13 @@ bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
         return radeon_ring_test_lockup(rdev, ring);
 }
 
-static int si_gpu_soft_reset(struct radeon_device *rdev)
+static void si_gpu_soft_reset_gfx(struct radeon_device *rdev)
 {
-        struct evergreen_mc_save save;
         u32 grbm_reset = 0;
 
         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
-                return 0;
+                return;
 
-        dev_info(rdev->dev, "GPU softreset \n");
         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
                 RREG32(GRBM_STATUS));
         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
@@ -2145,10 +2143,7 @@ static int si_gpu_soft_reset(struct radeon_device *rdev)
                 RREG32(GRBM_STATUS_SE1));
         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
                 RREG32(SRBM_STATUS));
-        evergreen_mc_stop(rdev, &save);
-        if (radeon_mc_wait_for_idle(rdev)) {
-                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
-        }
+
         /* Disable CP parsing/prefetching */
         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
 
@@ -2173,8 +2168,7 @@ static int si_gpu_soft_reset(struct radeon_device *rdev)
         udelay(50);
         WREG32(GRBM_SOFT_RESET, 0);
         (void)RREG32(GRBM_SOFT_RESET);
-        /* Wait a little for things to settle down */
-        udelay(50);
+
         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
                 RREG32(GRBM_STATUS));
         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
@@ -2185,13 +2179,81 @@ static int si_gpu_soft_reset(struct radeon_device *rdev)
                 RREG32(GRBM_STATUS_SE1));
         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
                 RREG32(SRBM_STATUS));
+}
+
+static void si_gpu_soft_reset_dma(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
+                return;
+
+        dev_info(rdev->dev, "  DMA_STATUS_REG   = 0x%08X\n",
+                RREG32(DMA_STATUS_REG));
+
+        /* dma0 */
+        tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
+
+        /* dma1 */
+        tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
+
+        /* Reset dma */
+        WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
+        RREG32(SRBM_SOFT_RESET);
+        udelay(50);
+        WREG32(SRBM_SOFT_RESET, 0);
+
+        dev_info(rdev->dev, "  DMA_STATUS_REG   = 0x%08X\n",
+                RREG32(DMA_STATUS_REG));
+}
+
+static int si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
+{
+        struct evergreen_mc_save save;
+
+        if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
+                reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
+
+        if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
+                reset_mask &= ~RADEON_RESET_DMA;
+
+        if (reset_mask == 0)
+                return 0;
+
+        dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
+
+        dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
+                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
+        dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
+                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
+
+        evergreen_mc_stop(rdev, &save);
+        if (radeon_mc_wait_for_idle(rdev)) {
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+        }
+
+        if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
+                si_gpu_soft_reset_gfx(rdev);
+
+        if (reset_mask & RADEON_RESET_DMA)
+                si_gpu_soft_reset_dma(rdev);
+
+        /* Wait a little for things to settle down */
+        udelay(50);
+
         evergreen_mc_resume(rdev, &save);
         return 0;
 }
 
 int si_asic_reset(struct radeon_device *rdev)
 {
-        return si_gpu_soft_reset(rdev);
+        return si_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
+                                        RADEON_RESET_COMPUTE |
+                                        RADEON_RESET_DMA));
 }
 
 /* MC */
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 62b46215d423..c056aae814f0 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -62,6 +62,22 @@
 
 #define SRBM_STATUS                                     0xE50
 
+#define SRBM_SOFT_RESET                                 0x0E60
+#define         SOFT_RESET_BIF                          (1 << 1)
+#define         SOFT_RESET_DC                           (1 << 5)
+#define         SOFT_RESET_DMA1                         (1 << 6)
+#define         SOFT_RESET_GRBM                         (1 << 8)
+#define         SOFT_RESET_HDP                          (1 << 9)
+#define         SOFT_RESET_IH                           (1 << 10)
+#define         SOFT_RESET_MC                           (1 << 11)
+#define         SOFT_RESET_ROM                          (1 << 14)
+#define         SOFT_RESET_SEM                          (1 << 15)
+#define         SOFT_RESET_VMC                          (1 << 17)
+#define         SOFT_RESET_DMA                          (1 << 20)
+#define         SOFT_RESET_TST                          (1 << 21)
+#define         SOFT_RESET_REGBB                        (1 << 22)
+#define         SOFT_RESET_ORB                          (1 << 23)
+
 #define CC_SYS_RB_BACKEND_DISABLE                       0xe80
 #define GC_USER_SYS_RB_BACKEND_DISABLE                  0xe84
 
@@ -1013,6 +1029,8 @@
 #       define DATA_SWAP_ENABLE                           (1 << 3)
 #       define FENCE_SWAP_ENABLE                          (1 << 4)
 #       define CTXEMPTY_INT_ENABLE                        (1 << 28)
+#define DMA_STATUS_REG                                    0xd034
+#       define DMA_IDLE                                   (1 << 0)
 #define DMA_TILING_CONFIG                                 0xd0b8
 
 #define DMA_PACKET(cmd, b, t, s, n)     ((((cmd) & 0xF) << 28) |        \
diff --git a/drivers/gpu/drm/shmobile/shmob_drm_drv.c b/drivers/gpu/drm/shmobile/shmob_drm_drv.c
index 1c350fc4e449..d1d5306ebf24 100644
--- a/drivers/gpu/drm/shmobile/shmob_drm_drv.c
+++ b/drivers/gpu/drm/shmobile/shmob_drm_drv.c
@@ -33,7 +33,7 @@
  * Hardware initialization
  */
 
-static int __devinit shmob_drm_init_interface(struct shmob_drm_device *sdev)
+static int shmob_drm_init_interface(struct shmob_drm_device *sdev)
 {
         static const u32 ldmt1r[] = {
                 [SHMOB_DRM_IFACE_RGB8] = LDMT1R_MIFTYP_RGB8,
@@ -67,7 +67,7 @@ static int __devinit shmob_drm_init_interface(struct shmob_drm_device *sdev)
         return 0;
 }
 
-static int __devinit shmob_drm_setup_clocks(struct shmob_drm_device *sdev,
+static int shmob_drm_setup_clocks(struct shmob_drm_device *sdev,
                                             enum shmob_drm_clk_source clksrc)
 {
         struct clk *clk;
@@ -330,12 +330,12 @@ static const struct dev_pm_ops shmob_drm_pm_ops = {
  * Platform driver
  */
 
-static int __devinit shmob_drm_probe(struct platform_device *pdev)
+static int shmob_drm_probe(struct platform_device *pdev)
 {
         return drm_platform_init(&shmob_drm_driver, pdev);
 }
 
-static int __devexit shmob_drm_remove(struct platform_device *pdev)
+static int shmob_drm_remove(struct platform_device *pdev)
 {
         drm_platform_exit(&shmob_drm_driver, pdev);
 
@@ -344,7 +344,7 @@ static int __devexit shmob_drm_remove(struct platform_device *pdev)
 
 static struct platform_driver shmob_drm_platform_driver = {
         .probe          = shmob_drm_probe,
-        .remove         = __devexit_p(shmob_drm_remove),
+        .remove         = shmob_drm_remove,
         .driver         = {
                 .owner  = THIS_MODULE,
                 .name   = "shmob-drm",
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 074410371e2a..656b2e3334a6 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -102,12 +102,12 @@ static int tegra_dc_set_timings(struct tegra_dc *dc,
                 ((mode->hsync_end - mode->hsync_start) <<  0);
         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
 
-        value = ((mode->vsync_start - mode->vdisplay) << 16) |
-                ((mode->hsync_start - mode->hdisplay) <<  0);
-        tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
-
         value = ((mode->vtotal - mode->vsync_end) << 16) |
                 ((mode->htotal - mode->hsync_end) <<  0);
+        tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
+
+        value = ((mode->vsync_start - mode->vdisplay) << 16) |
+                ((mode->hsync_start - mode->hdisplay) <<  0);
         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
 
         value = (mode->vdisplay << 16) | mode->hdisplay;
@@ -221,8 +221,7 @@ static int tegra_crtc_mode_set(struct drm_crtc *crtc,
         win.stride = crtc->fb->pitches[0];
 
         /* program window registers */
-        value = tegra_dc_readl(dc, DC_CMD_DISPLAY_WINDOW_HEADER);
-        value |= WINDOW_A_SELECT;
+        value = WINDOW_A_SELECT;
         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 
         tegra_dc_writel(dc, win.fmt, DC_WIN_COLOR_DEPTH);
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index 3a843a77ddc7..741b5dc2742c 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -204,24 +204,6 @@ extern int tegra_output_parse_dt(struct tegra_output *output);
 extern int tegra_output_init(struct drm_device *drm, struct tegra_output *output);
 extern int tegra_output_exit(struct tegra_output *output);
 
-/* from gem.c */
-extern struct tegra_gem_object *tegra_gem_alloc(struct drm_device *drm,
-                                                size_t size);
-extern int tegra_gem_handle_create(struct drm_device *drm,
-                                   struct drm_file *file, size_t size,
-                                   unsigned long flags, uint32_t *handle);
-extern int tegra_gem_dumb_create(struct drm_file *file, struct drm_device *drm,
-                                 struct drm_mode_create_dumb *args);
-extern int tegra_gem_dumb_map_offset(struct drm_file *file,
-                                     struct drm_device *drm, uint32_t handle,
-                                     uint64_t *offset);
-extern int tegra_gem_dumb_destroy(struct drm_file *file,
-                                  struct drm_device *drm, uint32_t handle);
-extern int tegra_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
-extern int tegra_gem_init_object(struct drm_gem_object *obj);
-extern void tegra_gem_free_object(struct drm_gem_object *obj);
-extern struct vm_operations_struct tegra_gem_vm_ops;
-
 /* from fb.c */
 extern int tegra_drm_fb_init(struct drm_device *drm);
 extern void tegra_drm_fb_exit(struct drm_device *drm);
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index ab4016412bbf..e060c7e6434d 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -149,7 +149,7 @@ struct tmds_config {
 };
 
 static const struct tmds_config tegra2_tmds_config[] = {
-        { /* 480p modes */
+        { /* slow pixel clock modes */
                 .pclk = 27000000,
                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
@@ -163,21 +163,8 @@ static const struct tmds_config tegra2_tmds_config[] = {
                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
-        }, { /* 720p modes */
-                .pclk = 74250000,
-                .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
-                        SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
-                        SOR_PLL_TX_REG_LOAD(3),
-                .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
-                .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
-                        PE_CURRENT1(PE_CURRENT_6_0_mA) |
-                        PE_CURRENT2(PE_CURRENT_6_0_mA) |
-                        PE_CURRENT3(PE_CURRENT_6_0_mA),
-                .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
-                        DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
-                        DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
-                        DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
-        }, { /* 1080p modes */
+        },
+        { /* high pixel clock modes */
                 .pclk = UINT_MAX,
                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
@@ -479,7 +466,7 @@ static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
                 return;
         }
 
-        h_front_porch = mode->htotal - mode->hsync_end;
+        h_front_porch = mode->hsync_start - mode->hdisplay;
         memset(&frame, 0, sizeof(frame));
         frame.r = HDMI_AVI_R_SAME;
 
@@ -634,8 +621,8 @@ static int tegra_output_hdmi_enable(struct tegra_output *output)
 
         pclk = mode->clock * 1000;
         h_sync_width = mode->hsync_end - mode->hsync_start;
-        h_front_porch = mode->htotal - mode->hsync_end;
-        h_back_porch = mode->hsync_start - mode->hdisplay;
+        h_back_porch = mode->htotal - mode->hsync_end;
+        h_front_porch = mode->hsync_start - mode->hdisplay;
 
         err = regulator_enable(hdmi->vdd);
         if (err < 0) {
diff --git a/drivers/gpu/drm/tegra/host1x.c b/drivers/gpu/drm/tegra/host1x.c
index bdb97a564d82..5d17b113a6fc 100644
--- a/drivers/gpu/drm/tegra/host1x.c
+++ b/drivers/gpu/drm/tegra/host1x.c
@@ -239,6 +239,8 @@ int host1x_register_client(struct host1x *host1x, struct host1x_client *client)
                 }
         }
 
+        client->host1x = host1x;
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 33d20be87db5..52b20b12c83a 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -434,6 +434,7 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo,
                         bo->mem = tmp_mem;
                         bdev->driver->move_notify(bo, mem);
                         bo->mem = *mem;
+                        *mem = tmp_mem;
                 }
 
                 goto out_err;
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 9e9c5d2a5c74..44420fca7dfa 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -344,8 +344,12 @@ int ttm_bo_move_memcpy(struct ttm_buffer_object *bo,
 
         if (ttm->state == tt_unpopulated) {
                 ret = ttm->bdev->driver->ttm_tt_populate(ttm);
-                if (ret)
+                if (ret) {
+                        /* if we fail here don't nuke the mm node
+                         * as the bo still owns it */
+                        old_copy.mm_node = NULL;
                         goto out1;
+                }
         }
 
         add = 0;
@@ -371,8 +375,11 @@ int ttm_bo_move_memcpy(struct ttm_buffer_object *bo,
                                                    prot);
                 } else
                         ret = ttm_copy_io_page(new_iomap, old_iomap, page);
-                if (ret)
+                if (ret) {
+                        /* failing here, means keep old copy as-is */
+                        old_copy.mm_node = NULL;
                         goto out1;
+                }
         }
         mb();
 out2:
@@ -654,11 +661,13 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
                  */
 
                 set_bit(TTM_BO_PRIV_FLAG_MOVING, &bo->priv_flags);
+
+                /* ttm_buffer_object_transfer accesses bo->sync_obj */
+                ret = ttm_buffer_object_transfer(bo, &ghost_obj);
                 spin_unlock(&bdev->fence_lock);
                 if (tmp_obj)
                         driver->sync_obj_unref(&tmp_obj);
 
-                ret = ttm_buffer_object_transfer(bo, &ghost_obj);
                 if (ret)
                         return ret;
 
diff --git a/drivers/gpu/drm/udl/udl_connector.c b/drivers/gpu/drm/udl/udl_connector.c
index 512f44add89f..fe5cdbcf2636 100644
--- a/drivers/gpu/drm/udl/udl_connector.c
+++ b/drivers/gpu/drm/udl/udl_connector.c
@@ -22,13 +22,17 @@
 static u8 *udl_get_edid(struct udl_device *udl)
 {
         u8 *block;
-        char rbuf[3];
+        char *rbuf;
         int ret, i;
 
         block = kmalloc(EDID_LENGTH, GFP_KERNEL);
         if (block == NULL)
                 return NULL;
 
+        rbuf = kmalloc(2, GFP_KERNEL);
+        if (rbuf == NULL)
+                goto error;
+
         for (i = 0; i < EDID_LENGTH; i++) {
                 ret = usb_control_msg(udl->ddev->usbdev,
                                       usb_rcvctrlpipe(udl->ddev->usbdev, 0), (0x02),
@@ -36,16 +40,17 @@ static u8 *udl_get_edid(struct udl_device *udl)
                                       HZ);
                 if (ret < 1) {
                         DRM_ERROR("Read EDID byte %d failed err %x\n", i, ret);
-                        i--;
                         goto error;
                 }
                 block[i] = rbuf[1];
         }
 
+        kfree(rbuf);
         return block;
 
 error:
         kfree(block);
+        kfree(rbuf);
         return NULL;
 }
 
@@ -57,6 +62,14 @@ static int udl_get_modes(struct drm_connector *connector)
 
         edid = (struct edid *)udl_get_edid(udl);
 
+        /*
+         * We only read the main block, but if the monitor reports extension
+         * blocks then the drm edid code expects them to be present, so patch
+         * the extension count to 0.
+         */
+        edid->checksum += edid->extensions;
+        edid->extensions = 0;
+
         drm_mode_connector_update_edid_property(connector, edid);
         ret = drm_add_edid_modes(connector, edid);
         kfree(edid);