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-rw-r--r--drivers/gpu/drm/Kconfig2
-rw-r--r--drivers/gpu/drm/ati_pcigart.c2
-rw-r--r--drivers/gpu/drm/drm_crtc.c4
-rw-r--r--drivers/gpu/drm/drm_crtc_helper.c5
-rw-r--r--drivers/gpu/drm/drm_edid.c3
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c2
-rw-r--r--drivers/gpu/drm/drm_gem.c13
-rw-r--r--drivers/gpu/drm/drm_modes.c90
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c33
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c30
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c178
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h128
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c363
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c46
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c132
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h13
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c12
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c35
-rw-r--r--drivers/gpu/drm/i915/intel_bios.h40
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c5
-rw-r--r--drivers/gpu/drm/i915/intel_display.c531
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c81
-rw-r--r--drivers/gpu/drm/i915/intel_fb.c2
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c55
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c109
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c96
-rw-r--r--drivers/gpu/drm/radeon/Makefile5
-rw-r--r--drivers/gpu/drm/radeon/atom.c102
-rw-r--r--drivers/gpu/drm/radeon/atom.h1
-rw-r--r--drivers/gpu/drm/radeon/atombios.h16
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c259
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c27
-rw-r--r--drivers/gpu/drm/radeon/r100.c19
-rw-r--r--drivers/gpu/drm/radeon/r200.c7
-rw-r--r--drivers/gpu/drm/radeon/r300.c16
-rw-r--r--drivers/gpu/drm/radeon/r420.c16
-rw-r--r--drivers/gpu/drm/radeon/r520.c3
-rw-r--r--drivers/gpu/drm/radeon/r600.c184
-rw-r--r--drivers/gpu/drm/radeon/r600_audio.c2
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c21
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c83
-rw-r--r--drivers/gpu/drm/radeon/r600d.h25
-rw-r--r--drivers/gpu/drm/radeon/radeon.h20
-rw-r--r--drivers/gpu/drm/radeon/radeon_agp.c11
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h11
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c45
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c165
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c77
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c21
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h30
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_state.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c7
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r2002
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r420795
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rs60068
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rv5156
-rw-r--r--drivers/gpu/drm/radeon/rs400.c28
-rw-r--r--drivers/gpu/drm/radeon/rs600.c2
-rw-r--r--drivers/gpu/drm/radeon/rs690.c2
-rw-r--r--drivers/gpu/drm/radeon/rv515.c4
-rw-r--r--drivers/gpu/drm/radeon/rv770.c80
-rw-r--r--drivers/gpu/drm/ttm/ttm_bo.c69
-rw-r--r--drivers/gpu/drm/ttm/ttm_bo_util.c11
-rw-r--r--drivers/gpu/drm/ttm/ttm_lock.c2
-rw-r--r--drivers/gpu/drm/ttm/ttm_object.c2
-rw-r--r--drivers/gpu/drm/ttm/ttm_tt.c23
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c25
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c76
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.h18
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c19
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_fb.c8
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c37
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c8
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_irq.c13
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_kms.c30
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c9
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_resource.c64
85 files changed, 3088 insertions, 1530 deletions
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 96eddd17e050..305c59003963 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -66,6 +66,8 @@ config DRM_RADEON
66 66
67 If M is selected, the module will be called radeon. 67 If M is selected, the module will be called radeon.
68 68
69source "drivers/gpu/drm/radeon/Kconfig"
70
69config DRM_I810 71config DRM_I810
70 tristate "Intel I810" 72 tristate "Intel I810"
71 depends on DRM && AGP && AGP_INTEL 73 depends on DRM && AGP && AGP_INTEL
diff --git a/drivers/gpu/drm/ati_pcigart.c b/drivers/gpu/drm/ati_pcigart.c
index a1fce68e3bbe..17be051b7aa3 100644
--- a/drivers/gpu/drm/ati_pcigart.c
+++ b/drivers/gpu/drm/ati_pcigart.c
@@ -113,7 +113,7 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
113 113
114 if (pci_set_dma_mask(dev->pdev, gart_info->table_mask)) { 114 if (pci_set_dma_mask(dev->pdev, gart_info->table_mask)) {
115 DRM_ERROR("fail to set dma mask to 0x%Lx\n", 115 DRM_ERROR("fail to set dma mask to 0x%Lx\n",
116 gart_info->table_mask); 116 (unsigned long long)gart_info->table_mask);
117 ret = 1; 117 ret = 1;
118 goto done; 118 goto done;
119 } 119 }
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index fa19c2b9820f..d91fb8c0b7b3 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -283,7 +283,7 @@ EXPORT_SYMBOL(drm_mode_object_find);
283 * functions & device file and adds it to the master fd list. 283 * functions & device file and adds it to the master fd list.
284 * 284 *
285 * RETURNS: 285 * RETURNS:
286 * Zero on success, error code on falure. 286 * Zero on success, error code on failure.
287 */ 287 */
288int drm_framebuffer_init(struct drm_device *dev, struct drm_framebuffer *fb, 288int drm_framebuffer_init(struct drm_device *dev, struct drm_framebuffer *fb,
289 const struct drm_framebuffer_funcs *funcs) 289 const struct drm_framebuffer_funcs *funcs)
@@ -2434,7 +2434,7 @@ int drm_mode_connector_property_set_ioctl(struct drm_device *dev,
2434 } else if (connector->funcs->set_property) 2434 } else if (connector->funcs->set_property)
2435 ret = connector->funcs->set_property(connector, property, out_resp->value); 2435 ret = connector->funcs->set_property(connector, property, out_resp->value);
2436 2436
2437 /* store the property value if succesful */ 2437 /* store the property value if successful */
2438 if (!ret) 2438 if (!ret)
2439 drm_connector_property_set_value(connector, property, out_resp->value); 2439 drm_connector_property_set_value(connector, property, out_resp->value);
2440out: 2440out:
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index aba79c494587..7d0f00a935fa 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -702,7 +702,7 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
702 if (encoder->crtc != crtc) 702 if (encoder->crtc != crtc)
703 continue; 703 continue;
704 704
705 DRM_INFO("%s: set mode %s %x\n", drm_get_encoder_name(encoder), 705 DRM_DEBUG("%s: set mode %s %x\n", drm_get_encoder_name(encoder),
706 mode->name, mode->base.id); 706 mode->name, mode->base.id);
707 encoder_funcs = encoder->helper_private; 707 encoder_funcs = encoder->helper_private;
708 encoder_funcs->mode_set(encoder, mode, adjusted_mode); 708 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
@@ -1032,7 +1032,8 @@ bool drm_helper_initial_config(struct drm_device *dev)
1032 /* 1032 /*
1033 * we shouldn't end up with no modes here. 1033 * we shouldn't end up with no modes here.
1034 */ 1034 */
1035 WARN(!count, "No connectors reported connected with modes\n"); 1035 if (count == 0)
1036 printk(KERN_INFO "No connectors reported connected with modes\n");
1036 1037
1037 drm_setup_crtcs(dev); 1038 drm_setup_crtcs(dev);
1038 1039
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index defcaf108460..f665b05592f3 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -633,8 +633,7 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
633 return NULL; 633 return NULL;
634 } 634 }
635 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 635 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
636 printk(KERN_WARNING "integrated sync not supported\n"); 636 printk(KERN_WARNING "composite sync not supported\n");
637 return NULL;
638 } 637 }
639 638
640 /* it is incorrect if hsync/vsync width is zero */ 639 /* it is incorrect if hsync/vsync width is zero */
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 1c2b7d44ec05..0f9e90552dc4 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -389,7 +389,7 @@ int drm_fb_helper_blank(int blank, struct fb_info *info)
389 break; 389 break;
390 /* Display: Off; HSync: On, VSync: On */ 390 /* Display: Off; HSync: On, VSync: On */
391 case FB_BLANK_NORMAL: 391 case FB_BLANK_NORMAL:
392 drm_fb_helper_off(info, DRM_MODE_DPMS_ON); 392 drm_fb_helper_off(info, DRM_MODE_DPMS_STANDBY);
393 break; 393 break;
394 /* Display: Off; HSync: Off, VSync: On */ 394 /* Display: Off; HSync: Off, VSync: On */
395 case FB_BLANK_HSYNC_SUSPEND: 395 case FB_BLANK_HSYNC_SUSPEND:
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index e9dbb481c469..8bf3770f294e 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -142,19 +142,6 @@ drm_gem_object_alloc(struct drm_device *dev, size_t size)
142 if (IS_ERR(obj->filp)) 142 if (IS_ERR(obj->filp))
143 goto free; 143 goto free;
144 144
145 /* Basically we want to disable the OOM killer and handle ENOMEM
146 * ourselves by sacrificing pages from cached buffers.
147 * XXX shmem_file_[gs]et_gfp_mask()
148 */
149 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping,
150 GFP_HIGHUSER |
151 __GFP_COLD |
152 __GFP_FS |
153 __GFP_RECLAIMABLE |
154 __GFP_NORETRY |
155 __GFP_NOWARN |
156 __GFP_NOMEMALLOC);
157
158 kref_init(&obj->refcount); 145 kref_init(&obj->refcount);
159 kref_init(&obj->handlecount); 146 kref_init(&obj->handlecount);
160 obj->size = size; 147 obj->size = size;
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 6d81a02463a3..76d63394c776 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1,9 +1,4 @@
1/* 1/*
2 * The list_sort function is (presumably) licensed under the GPL (see the
3 * top level "COPYING" file for details).
4 *
5 * The remainder of this file is:
6 *
7 * Copyright © 1997-2003 by The XFree86 Project, Inc. 2 * Copyright © 1997-2003 by The XFree86 Project, Inc.
8 * Copyright © 2007 Dave Airlie 3 * Copyright © 2007 Dave Airlie
9 * Copyright © 2007-2008 Intel Corporation 4 * Copyright © 2007-2008 Intel Corporation
@@ -36,6 +31,7 @@
36 */ 31 */
37 32
38#include <linux/list.h> 33#include <linux/list.h>
34#include <linux/list_sort.h>
39#include "drmP.h" 35#include "drmP.h"
40#include "drm.h" 36#include "drm.h"
41#include "drm_crtc.h" 37#include "drm_crtc.h"
@@ -855,6 +851,7 @@ EXPORT_SYMBOL(drm_mode_prune_invalid);
855 851
856/** 852/**
857 * drm_mode_compare - compare modes for favorability 853 * drm_mode_compare - compare modes for favorability
854 * @priv: unused
858 * @lh_a: list_head for first mode 855 * @lh_a: list_head for first mode
859 * @lh_b: list_head for second mode 856 * @lh_b: list_head for second mode
860 * 857 *
@@ -868,7 +865,7 @@ EXPORT_SYMBOL(drm_mode_prune_invalid);
868 * Negative if @lh_a is better than @lh_b, zero if they're equivalent, or 865 * Negative if @lh_a is better than @lh_b, zero if they're equivalent, or
869 * positive if @lh_b is better than @lh_a. 866 * positive if @lh_b is better than @lh_a.
870 */ 867 */
871static int drm_mode_compare(struct list_head *lh_a, struct list_head *lh_b) 868static int drm_mode_compare(void *priv, struct list_head *lh_a, struct list_head *lh_b)
872{ 869{
873 struct drm_display_mode *a = list_entry(lh_a, struct drm_display_mode, head); 870 struct drm_display_mode *a = list_entry(lh_a, struct drm_display_mode, head);
874 struct drm_display_mode *b = list_entry(lh_b, struct drm_display_mode, head); 871 struct drm_display_mode *b = list_entry(lh_b, struct drm_display_mode, head);
@@ -885,85 +882,6 @@ static int drm_mode_compare(struct list_head *lh_a, struct list_head *lh_b)
885 return diff; 882 return diff;
886} 883}
887 884
888/* FIXME: what we don't have a list sort function? */
889/* list sort from Mark J Roberts (mjr@znex.org) */
890void list_sort(struct list_head *head,
891 int (*cmp)(struct list_head *a, struct list_head *b))
892{
893 struct list_head *p, *q, *e, *list, *tail, *oldhead;
894 int insize, nmerges, psize, qsize, i;
895
896 list = head->next;
897 list_del(head);
898 insize = 1;
899 for (;;) {
900 p = oldhead = list;
901 list = tail = NULL;
902 nmerges = 0;
903
904 while (p) {
905 nmerges++;
906 q = p;
907 psize = 0;
908 for (i = 0; i < insize; i++) {
909 psize++;
910 q = q->next == oldhead ? NULL : q->next;
911 if (!q)
912 break;
913 }
914
915 qsize = insize;
916 while (psize > 0 || (qsize > 0 && q)) {
917 if (!psize) {
918 e = q;
919 q = q->next;
920 qsize--;
921 if (q == oldhead)
922 q = NULL;
923 } else if (!qsize || !q) {
924 e = p;
925 p = p->next;
926 psize--;
927 if (p == oldhead)
928 p = NULL;
929 } else if (cmp(p, q) <= 0) {
930 e = p;
931 p = p->next;
932 psize--;
933 if (p == oldhead)
934 p = NULL;
935 } else {
936 e = q;
937 q = q->next;
938 qsize--;
939 if (q == oldhead)
940 q = NULL;
941 }
942 if (tail)
943 tail->next = e;
944 else
945 list = e;
946 e->prev = tail;
947 tail = e;
948 }
949 p = q;
950 }
951
952 tail->next = list;
953 list->prev = tail;
954
955 if (nmerges <= 1)
956 break;
957
958 insize *= 2;
959 }
960
961 head->next = list;
962 head->prev = list->prev;
963 list->prev->next = head;
964 list->prev = head;
965}
966
967/** 885/**
968 * drm_mode_sort - sort mode list 886 * drm_mode_sort - sort mode list
969 * @mode_list: list to sort 887 * @mode_list: list to sort
@@ -975,7 +893,7 @@ void list_sort(struct list_head *head,
975 */ 893 */
976void drm_mode_sort(struct list_head *mode_list) 894void drm_mode_sort(struct list_head *mode_list)
977{ 895{
978 list_sort(mode_list, drm_mode_compare); 896 list_sort(NULL, mode_list, drm_mode_compare);
979} 897}
980EXPORT_SYMBOL(drm_mode_sort); 898EXPORT_SYMBOL(drm_mode_sort);
981 899
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 18476bf0b580..a894ade03093 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -272,7 +272,7 @@ static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_co
272 mem = kmap_atomic(pages[page], KM_USER0); 272 mem = kmap_atomic(pages[page], KM_USER0);
273 for (i = 0; i < PAGE_SIZE; i += 4) 273 for (i = 0; i < PAGE_SIZE; i += 4)
274 seq_printf(m, "%08x : %08x\n", i, mem[i / 4]); 274 seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
275 kunmap_atomic(pages[page], KM_USER0); 275 kunmap_atomic(mem, KM_USER0);
276 } 276 }
277} 277}
278 278
@@ -290,7 +290,7 @@ static int i915_batchbuffer_info(struct seq_file *m, void *data)
290 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) { 290 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
291 obj = obj_priv->obj; 291 obj = obj_priv->obj;
292 if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) { 292 if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
293 ret = i915_gem_object_get_pages(obj); 293 ret = i915_gem_object_get_pages(obj, 0);
294 if (ret) { 294 if (ret) {
295 DRM_ERROR("Failed to get pages: %d\n", ret); 295 DRM_ERROR("Failed to get pages: %d\n", ret);
296 spin_unlock(&dev_priv->mm.active_list_lock); 296 spin_unlock(&dev_priv->mm.active_list_lock);
@@ -386,34 +386,6 @@ out:
386 return 0; 386 return 0;
387} 387}
388 388
389static int i915_registers_info(struct seq_file *m, void *data) {
390 struct drm_info_node *node = (struct drm_info_node *) m->private;
391 struct drm_device *dev = node->minor->dev;
392 drm_i915_private_t *dev_priv = dev->dev_private;
393 uint32_t reg;
394
395#define DUMP_RANGE(start, end) \
396 for (reg=start; reg < end; reg += 4) \
397 seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg));
398
399 DUMP_RANGE(0x00000, 0x00fff); /* VGA registers */
400 DUMP_RANGE(0x02000, 0x02fff); /* instruction, memory, interrupt control registers */
401 DUMP_RANGE(0x03000, 0x031ff); /* FENCE and PPGTT control registers */
402 DUMP_RANGE(0x03200, 0x03fff); /* frame buffer compression registers */
403 DUMP_RANGE(0x05000, 0x05fff); /* I/O control registers */
404 DUMP_RANGE(0x06000, 0x06fff); /* clock control registers */
405 DUMP_RANGE(0x07000, 0x07fff); /* 3D internal debug registers */
406 DUMP_RANGE(0x07400, 0x088ff); /* GPE debug registers */
407 DUMP_RANGE(0x0a000, 0x0afff); /* display palette registers */
408 DUMP_RANGE(0x10000, 0x13fff); /* MMIO MCHBAR */
409 DUMP_RANGE(0x30000, 0x3ffff); /* overlay registers */
410 DUMP_RANGE(0x60000, 0x6ffff); /* display engine pipeline registers */
411 DUMP_RANGE(0x70000, 0x72fff); /* display and cursor registers */
412 DUMP_RANGE(0x73000, 0x73fff); /* performance counters */
413
414 return 0;
415}
416
417static int 389static int
418i915_wedged_open(struct inode *inode, 390i915_wedged_open(struct inode *inode,
419 struct file *filp) 391 struct file *filp)
@@ -519,7 +491,6 @@ static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
519} 491}
520 492
521static struct drm_info_list i915_debugfs_list[] = { 493static struct drm_info_list i915_debugfs_list[] = {
522 {"i915_regs", i915_registers_info, 0},
523 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, 494 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
524 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, 495 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
525 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, 496 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 02607ed61399..e660ac07f3b2 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -134,6 +134,10 @@ static int i915_init_phys_hws(struct drm_device *dev)
134 134
135 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 135 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
136 136
137 if (IS_I965G(dev))
138 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
139 0xf0;
140
137 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); 141 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
138 DRM_DEBUG_DRIVER("Enabled hardware status page\n"); 142 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
139 return 0; 143 return 0;
@@ -813,9 +817,13 @@ static int i915_getparam(struct drm_device *dev, void *data,
813 case I915_PARAM_HAS_PAGEFLIPPING: 817 case I915_PARAM_HAS_PAGEFLIPPING:
814 value = 1; 818 value = 1;
815 break; 819 break;
820 case I915_PARAM_HAS_EXECBUF2:
821 /* depends on GEM */
822 value = dev_priv->has_gem;
823 break;
816 default: 824 default:
817 DRM_DEBUG_DRIVER("Unknown parameter %d\n", 825 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
818 param->param); 826 param->param);
819 return -EINVAL; 827 return -EINVAL;
820 } 828 }
821 829
@@ -1117,7 +1125,8 @@ static void i915_setup_compression(struct drm_device *dev, int size)
1117{ 1125{
1118 struct drm_i915_private *dev_priv = dev->dev_private; 1126 struct drm_i915_private *dev_priv = dev->dev_private;
1119 struct drm_mm_node *compressed_fb, *compressed_llb; 1127 struct drm_mm_node *compressed_fb, *compressed_llb;
1120 unsigned long cfb_base, ll_base; 1128 unsigned long cfb_base;
1129 unsigned long ll_base = 0;
1121 1130
1122 /* Leave 1M for line length buffer & misc. */ 1131 /* Leave 1M for line length buffer & misc. */
1123 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0); 1132 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
@@ -1200,14 +1209,6 @@ static int i915_load_modeset_init(struct drm_device *dev,
1200 dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) & 1209 dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1201 0xff000000; 1210 0xff000000;
1202 1211
1203 if (IS_MOBILE(dev) || IS_I9XX(dev))
1204 dev_priv->cursor_needs_physical = true;
1205 else
1206 dev_priv->cursor_needs_physical = false;
1207
1208 if (IS_I965G(dev) || IS_G33(dev))
1209 dev_priv->cursor_needs_physical = false;
1210
1211 /* Basic memrange allocator for stolen space (aka vram) */ 1212 /* Basic memrange allocator for stolen space (aka vram) */
1212 drm_mm_init(&dev_priv->vram, 0, prealloc_size); 1213 drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1213 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024)); 1214 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
@@ -1257,6 +1258,8 @@ static int i915_load_modeset_init(struct drm_device *dev,
1257 if (ret) 1258 if (ret)
1258 goto destroy_ringbuffer; 1259 goto destroy_ringbuffer;
1259 1260
1261 intel_modeset_init(dev);
1262
1260 ret = drm_irq_install(dev); 1263 ret = drm_irq_install(dev);
1261 if (ret) 1264 if (ret)
1262 goto destroy_ringbuffer; 1265 goto destroy_ringbuffer;
@@ -1271,8 +1274,6 @@ static int i915_load_modeset_init(struct drm_device *dev,
1271 1274
1272 I915_WRITE(INSTPM, (1 << 5) | (1 << 21)); 1275 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1273 1276
1274 intel_modeset_init(dev);
1275
1276 drm_helper_initial_config(dev); 1277 drm_helper_initial_config(dev);
1277 1278
1278 return 0; 1279 return 0;
@@ -1360,7 +1361,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1360{ 1361{
1361 struct drm_i915_private *dev_priv = dev->dev_private; 1362 struct drm_i915_private *dev_priv = dev->dev_private;
1362 resource_size_t base, size; 1363 resource_size_t base, size;
1363 int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1; 1364 int ret = 0, mmio_bar;
1364 uint32_t agp_size, prealloc_size, prealloc_start; 1365 uint32_t agp_size, prealloc_size, prealloc_start;
1365 1366
1366 /* i915 has 4 more counters */ 1367 /* i915 has 4 more counters */
@@ -1376,8 +1377,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1376 1377
1377 dev->dev_private = (void *)dev_priv; 1378 dev->dev_private = (void *)dev_priv;
1378 dev_priv->dev = dev; 1379 dev_priv->dev = dev;
1380 dev_priv->info = (struct intel_device_info *) flags;
1379 1381
1380 /* Add register map (needed for suspend/resume) */ 1382 /* Add register map (needed for suspend/resume) */
1383 mmio_bar = IS_I9XX(dev) ? 0 : 1;
1381 base = drm_get_resource_start(dev, mmio_bar); 1384 base = drm_get_resource_start(dev, mmio_bar);
1382 size = drm_get_resource_len(dev, mmio_bar); 1385 size = drm_get_resource_len(dev, mmio_bar);
1383 1386
@@ -1652,6 +1655,7 @@ struct drm_ioctl_desc i915_ioctls[] = {
1652 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1655 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1653 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1656 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1654 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), 1657 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1658 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH),
1655 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1659 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1656 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1660 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1657 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH), 1661 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 24286ca168fc..ecac882e1d54 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -33,7 +33,6 @@
33#include "i915_drm.h" 33#include "i915_drm.h"
34#include "i915_drv.h" 34#include "i915_drv.h"
35 35
36#include "drm_pciids.h"
37#include <linux/console.h> 36#include <linux/console.h>
38#include "drm_crtc_helper.h" 37#include "drm_crtc_helper.h"
39 38
@@ -46,10 +45,129 @@ module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
46unsigned int i915_powersave = 1; 45unsigned int i915_powersave = 1;
47module_param_named(powersave, i915_powersave, int, 0400); 46module_param_named(powersave, i915_powersave, int, 0400);
48 47
48unsigned int i915_lvds_downclock = 0;
49module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
50
49static struct drm_driver driver; 51static struct drm_driver driver;
50 52
51static struct pci_device_id pciidlist[] = { 53#define INTEL_VGA_DEVICE(id, info) { \
52 i915_PCI_IDS 54 .class = PCI_CLASS_DISPLAY_VGA << 8, \
55 .class_mask = 0xffff00, \
56 .vendor = 0x8086, \
57 .device = id, \
58 .subvendor = PCI_ANY_ID, \
59 .subdevice = PCI_ANY_ID, \
60 .driver_data = (unsigned long) info }
61
62const static struct intel_device_info intel_i830_info = {
63 .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
64};
65
66const static struct intel_device_info intel_845g_info = {
67 .is_i8xx = 1,
68};
69
70const static struct intel_device_info intel_i85x_info = {
71 .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
72};
73
74const static struct intel_device_info intel_i865g_info = {
75 .is_i8xx = 1,
76};
77
78const static struct intel_device_info intel_i915g_info = {
79 .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
80};
81const static struct intel_device_info intel_i915gm_info = {
82 .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
83 .cursor_needs_physical = 1,
84};
85const static struct intel_device_info intel_i945g_info = {
86 .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
87};
88const static struct intel_device_info intel_i945gm_info = {
89 .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
90 .has_hotplug = 1, .cursor_needs_physical = 1,
91};
92
93const static struct intel_device_info intel_i965g_info = {
94 .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
95};
96
97const static struct intel_device_info intel_i965gm_info = {
98 .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
99 .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
100 .has_hotplug = 1,
101};
102
103const static struct intel_device_info intel_g33_info = {
104 .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
105 .has_hotplug = 1,
106};
107
108const static struct intel_device_info intel_g45_info = {
109 .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
110 .has_pipe_cxsr = 1,
111 .has_hotplug = 1,
112};
113
114const static struct intel_device_info intel_gm45_info = {
115 .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
116 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
117 .has_pipe_cxsr = 1,
118 .has_hotplug = 1,
119};
120
121const static struct intel_device_info intel_pineview_info = {
122 .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
123 .need_gfx_hws = 1,
124 .has_hotplug = 1,
125};
126
127const static struct intel_device_info intel_ironlake_d_info = {
128 .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
129 .has_pipe_cxsr = 1,
130 .has_hotplug = 1,
131};
132
133const static struct intel_device_info intel_ironlake_m_info = {
134 .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
135 .need_gfx_hws = 1, .has_rc6 = 1,
136 .has_hotplug = 1,
137};
138
139const static struct pci_device_id pciidlist[] = {
140 INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
141 INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
142 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
143 INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info),
144 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
145 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
146 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
147 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
148 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
149 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
150 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
151 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
152 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
153 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
154 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
155 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
156 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
157 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
158 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
159 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
160 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
161 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
162 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
163 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
164 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
165 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
166 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
167 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
168 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
169 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
170 {0, 0, 0}
53}; 171};
54 172
55#if defined(CONFIG_DRM_I915_KMS) 173#if defined(CONFIG_DRM_I915_KMS)
@@ -284,6 +402,52 @@ i915_pci_resume(struct pci_dev *pdev)
284 return i915_resume(dev); 402 return i915_resume(dev);
285} 403}
286 404
405static int
406i915_pm_suspend(struct device *dev)
407{
408 return i915_pci_suspend(to_pci_dev(dev), PMSG_SUSPEND);
409}
410
411static int
412i915_pm_resume(struct device *dev)
413{
414 return i915_pci_resume(to_pci_dev(dev));
415}
416
417static int
418i915_pm_freeze(struct device *dev)
419{
420 return i915_pci_suspend(to_pci_dev(dev), PMSG_FREEZE);
421}
422
423static int
424i915_pm_thaw(struct device *dev)
425{
426 /* thaw during hibernate, do nothing! */
427 return 0;
428}
429
430static int
431i915_pm_poweroff(struct device *dev)
432{
433 return i915_pci_suspend(to_pci_dev(dev), PMSG_HIBERNATE);
434}
435
436static int
437i915_pm_restore(struct device *dev)
438{
439 return i915_pci_resume(to_pci_dev(dev));
440}
441
442const struct dev_pm_ops i915_pm_ops = {
443 .suspend = i915_pm_suspend,
444 .resume = i915_pm_resume,
445 .freeze = i915_pm_freeze,
446 .thaw = i915_pm_thaw,
447 .poweroff = i915_pm_poweroff,
448 .restore = i915_pm_restore,
449};
450
287static struct vm_operations_struct i915_gem_vm_ops = { 451static struct vm_operations_struct i915_gem_vm_ops = {
288 .fault = i915_gem_fault, 452 .fault = i915_gem_fault,
289 .open = drm_gem_vm_open, 453 .open = drm_gem_vm_open,
@@ -303,8 +467,11 @@ static struct drm_driver driver = {
303 .lastclose = i915_driver_lastclose, 467 .lastclose = i915_driver_lastclose,
304 .preclose = i915_driver_preclose, 468 .preclose = i915_driver_preclose,
305 .postclose = i915_driver_postclose, 469 .postclose = i915_driver_postclose,
470
471 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
306 .suspend = i915_suspend, 472 .suspend = i915_suspend,
307 .resume = i915_resume, 473 .resume = i915_resume,
474
308 .device_is_agp = i915_driver_device_is_agp, 475 .device_is_agp = i915_driver_device_is_agp,
309 .enable_vblank = i915_enable_vblank, 476 .enable_vblank = i915_enable_vblank,
310 .disable_vblank = i915_disable_vblank, 477 .disable_vblank = i915_disable_vblank,
@@ -344,10 +511,7 @@ static struct drm_driver driver = {
344 .id_table = pciidlist, 511 .id_table = pciidlist,
345 .probe = i915_pci_probe, 512 .probe = i915_pci_probe,
346 .remove = i915_pci_remove, 513 .remove = i915_pci_remove,
347#ifdef CONFIG_PM 514 .driver.pm = &i915_pm_ops,
348 .resume = i915_pci_resume,
349 .suspend = i915_pci_suspend,
350#endif
351 }, 515 },
352 516
353 .name = DRIVER_NAME, 517 .name = DRIVER_NAME,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fbecac72f5bb..aaf934d96f21 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -172,9 +172,31 @@ struct drm_i915_display_funcs {
172 172
173struct intel_overlay; 173struct intel_overlay;
174 174
175struct intel_device_info {
176 u8 is_mobile : 1;
177 u8 is_i8xx : 1;
178 u8 is_i915g : 1;
179 u8 is_i9xx : 1;
180 u8 is_i945gm : 1;
181 u8 is_i965g : 1;
182 u8 is_i965gm : 1;
183 u8 is_g33 : 1;
184 u8 need_gfx_hws : 1;
185 u8 is_g4x : 1;
186 u8 is_pineview : 1;
187 u8 is_ironlake : 1;
188 u8 has_fbc : 1;
189 u8 has_rc6 : 1;
190 u8 has_pipe_cxsr : 1;
191 u8 has_hotplug : 1;
192 u8 cursor_needs_physical : 1;
193};
194
175typedef struct drm_i915_private { 195typedef struct drm_i915_private {
176 struct drm_device *dev; 196 struct drm_device *dev;
177 197
198 const struct intel_device_info *info;
199
178 int has_gem; 200 int has_gem;
179 201
180 void __iomem *regs; 202 void __iomem *regs;
@@ -232,8 +254,6 @@ typedef struct drm_i915_private {
232 int hangcheck_count; 254 int hangcheck_count;
233 uint32_t last_acthd; 255 uint32_t last_acthd;
234 256
235 bool cursor_needs_physical;
236
237 struct drm_mm vram; 257 struct drm_mm vram;
238 258
239 unsigned long cfb_size; 259 unsigned long cfb_size;
@@ -263,6 +283,7 @@ typedef struct drm_i915_private {
263 unsigned int lvds_use_ssc:1; 283 unsigned int lvds_use_ssc:1;
264 unsigned int edp_support:1; 284 unsigned int edp_support:1;
265 int lvds_ssc_freq; 285 int lvds_ssc_freq;
286 int edp_bpp;
266 287
267 struct notifier_block lid_notifier; 288 struct notifier_block lid_notifier;
268 289
@@ -287,8 +308,6 @@ typedef struct drm_i915_private {
287 u32 saveDSPACNTR; 308 u32 saveDSPACNTR;
288 u32 saveDSPBCNTR; 309 u32 saveDSPBCNTR;
289 u32 saveDSPARB; 310 u32 saveDSPARB;
290 u32 saveRENDERSTANDBY;
291 u32 savePWRCTXA;
292 u32 saveHWS; 311 u32 saveHWS;
293 u32 savePIPEACONF; 312 u32 savePIPEACONF;
294 u32 savePIPEBCONF; 313 u32 savePIPEBCONF;
@@ -561,6 +580,7 @@ typedef struct drm_i915_private {
561 u16 orig_clock; 580 u16 orig_clock;
562 int child_dev_num; 581 int child_dev_num;
563 struct child_device_config *child_dev; 582 struct child_device_config *child_dev;
583 struct drm_connector *int_lvds_connector;
564} drm_i915_private_t; 584} drm_i915_private_t;
565 585
566/** driver private structure attached to each drm_gem_object */ 586/** driver private structure attached to each drm_gem_object */
@@ -703,6 +723,7 @@ extern struct drm_ioctl_desc i915_ioctls[];
703extern int i915_max_ioctl; 723extern int i915_max_ioctl;
704extern unsigned int i915_fbpercrtc; 724extern unsigned int i915_fbpercrtc;
705extern unsigned int i915_powersave; 725extern unsigned int i915_powersave;
726extern unsigned int i915_lvds_downclock;
706 727
707extern void i915_save_display(struct drm_device *dev); 728extern void i915_save_display(struct drm_device *dev);
708extern void i915_restore_display(struct drm_device *dev); 729extern void i915_restore_display(struct drm_device *dev);
@@ -794,6 +815,8 @@ int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
794 struct drm_file *file_priv); 815 struct drm_file *file_priv);
795int i915_gem_execbuffer(struct drm_device *dev, void *data, 816int i915_gem_execbuffer(struct drm_device *dev, void *data,
796 struct drm_file *file_priv); 817 struct drm_file *file_priv);
818int i915_gem_execbuffer2(struct drm_device *dev, void *data,
819 struct drm_file *file_priv);
797int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 820int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
798 struct drm_file *file_priv); 821 struct drm_file *file_priv);
799int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 822int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
@@ -843,12 +866,13 @@ int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptib
843int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 866int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
844int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, 867int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
845 int write); 868 int write);
869int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
846int i915_gem_attach_phys_object(struct drm_device *dev, 870int i915_gem_attach_phys_object(struct drm_device *dev,
847 struct drm_gem_object *obj, int id); 871 struct drm_gem_object *obj, int id);
848void i915_gem_detach_phys_object(struct drm_device *dev, 872void i915_gem_detach_phys_object(struct drm_device *dev,
849 struct drm_gem_object *obj); 873 struct drm_gem_object *obj);
850void i915_gem_free_all_phys_object(struct drm_device *dev); 874void i915_gem_free_all_phys_object(struct drm_device *dev);
851int i915_gem_object_get_pages(struct drm_gem_object *obj); 875int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
852void i915_gem_object_put_pages(struct drm_gem_object *obj); 876void i915_gem_object_put_pages(struct drm_gem_object *obj);
853void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); 877void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
854void i915_gem_object_flush_write_domain(struct drm_gem_object *obj); 878void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
@@ -860,6 +884,9 @@ void i915_gem_shrinker_exit(void);
860void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 884void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
861void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); 885void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
862void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); 886void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
887bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
888 int tiling_mode);
889bool i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj);
863 890
864/* i915_gem_debug.c */ 891/* i915_gem_debug.c */
865void i915_gem_dump_object(struct drm_gem_object *obj, int len, 892void i915_gem_dump_object(struct drm_gem_object *obj, int len,
@@ -982,67 +1009,33 @@ extern void g4x_disable_fbc(struct drm_device *dev);
982extern int i915_wrap_ring(struct drm_device * dev); 1009extern int i915_wrap_ring(struct drm_device * dev);
983extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 1010extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
984 1011
985#define IS_I830(dev) ((dev)->pci_device == 0x3577) 1012#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
986#define IS_845G(dev) ((dev)->pci_device == 0x2562) 1013
987#define IS_I85X(dev) ((dev)->pci_device == 0x3582) 1014#define IS_I830(dev) ((dev)->pci_device == 0x3577)
988#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1015#define IS_845G(dev) ((dev)->pci_device == 0x2562)
989#define IS_I8XX(dev) (IS_I830(dev) || IS_845G(dev) || IS_I85X(dev) || IS_I865G(dev)) 1016#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
990 1017#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
991#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) 1018#define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx)
992#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1019#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
993#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1020#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
994#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ 1021#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
995 (dev)->pci_device == 0x27AE) 1022#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
996#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 1023#define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
997 (dev)->pci_device == 0x2982 || \ 1024#define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
998 (dev)->pci_device == 0x2992 || \ 1025#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
999 (dev)->pci_device == 0x29A2 || \ 1026#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1000 (dev)->pci_device == 0x2A02 || \ 1027#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1001 (dev)->pci_device == 0x2A12 || \ 1028#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1002 (dev)->pci_device == 0x2A42 || \ 1029#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1003 (dev)->pci_device == 0x2E02 || \ 1030#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1004 (dev)->pci_device == 0x2E12 || \
1005 (dev)->pci_device == 0x2E22 || \
1006 (dev)->pci_device == 0x2E32 || \
1007 (dev)->pci_device == 0x2E42 || \
1008 (dev)->pci_device == 0x0042 || \
1009 (dev)->pci_device == 0x0046)
1010
1011#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
1012 (dev)->pci_device == 0x2A12)
1013
1014#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1015
1016#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
1017 (dev)->pci_device == 0x2E12 || \
1018 (dev)->pci_device == 0x2E22 || \
1019 (dev)->pci_device == 0x2E32 || \
1020 (dev)->pci_device == 0x2E42 || \
1021 IS_GM45(dev))
1022
1023#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1024#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1025#define IS_PINEVIEW(dev) (IS_PINEVIEW_G(dev) || IS_PINEVIEW_M(dev))
1026
1027#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1028 (dev)->pci_device == 0x29B2 || \
1029 (dev)->pci_device == 0x29D2 || \
1030 (IS_PINEVIEW(dev)))
1031
1032#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1031#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1033#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1032#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1034#define IS_IRONLAKE(dev) (IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev)) 1033#define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1035 1034#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1036#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1035#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1037 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
1038 IS_IRONLAKE(dev))
1039 1036
1040#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 1037#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1041 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
1042 IS_PINEVIEW(dev) || IS_IRONLAKE_M(dev))
1043 1038
1044#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
1045 IS_IRONLAKE(dev))
1046/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1039/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1047 * rows, which changed the alignment requirements and fence programming. 1040 * rows, which changed the alignment requirements and fence programming.
1048 */ 1041 */
@@ -1054,17 +1047,14 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1054#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1047#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1055#define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ 1048#define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1056 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev)) 1049 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev))
1057#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev)) 1050#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1058/* dsparb controlled by hw only */ 1051/* dsparb controlled by hw only */
1059#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1052#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1060 1053
1061#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev)) 1054#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1062#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1055#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1063#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \ 1056#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1064 (IS_I9XX(dev) || IS_GM45(dev)) && \ 1057#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1065 !IS_PINEVIEW(dev) && \
1066 !IS_IRONLAKE(dev))
1067#define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IRONLAKE_M(dev))
1068 1058
1069#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1059#define PRIMARY_RINGBUFFER_SIZE (128*1024)
1070 1060
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c7f0cbec4e84..b4c8c0230689 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -277,7 +277,7 @@ i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
277 277
278 mutex_lock(&dev->struct_mutex); 278 mutex_lock(&dev->struct_mutex);
279 279
280 ret = i915_gem_object_get_pages(obj); 280 ret = i915_gem_object_get_pages(obj, 0);
281 if (ret != 0) 281 if (ret != 0)
282 goto fail_unlock; 282 goto fail_unlock;
283 283
@@ -321,40 +321,24 @@ fail_unlock:
321 return ret; 321 return ret;
322} 322}
323 323
324static inline gfp_t
325i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
326{
327 return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
328}
329
330static inline void
331i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
332{
333 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
334}
335
336static int 324static int
337i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) 325i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
338{ 326{
339 int ret; 327 int ret;
340 328
341 ret = i915_gem_object_get_pages(obj); 329 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
342 330
343 /* If we've insufficient memory to map in the pages, attempt 331 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers. 332 * to make some space by throwing out some old buffers.
345 */ 333 */
346 if (ret == -ENOMEM) { 334 if (ret == -ENOMEM) {
347 struct drm_device *dev = obj->dev; 335 struct drm_device *dev = obj->dev;
348 gfp_t gfp;
349 336
350 ret = i915_gem_evict_something(dev, obj->size); 337 ret = i915_gem_evict_something(dev, obj->size);
351 if (ret) 338 if (ret)
352 return ret; 339 return ret;
353 340
354 gfp = i915_gem_object_get_page_gfp_mask(obj); 341 ret = i915_gem_object_get_pages(obj, 0);
355 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356 ret = i915_gem_object_get_pages(obj);
357 i915_gem_object_set_page_gfp_mask (obj, gfp);
358 } 342 }
359 343
360 return ret; 344 return ret;
@@ -790,7 +774,7 @@ i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
790 774
791 mutex_lock(&dev->struct_mutex); 775 mutex_lock(&dev->struct_mutex);
792 776
793 ret = i915_gem_object_get_pages(obj); 777 ret = i915_gem_object_get_pages(obj, 0);
794 if (ret != 0) 778 if (ret != 0)
795 goto fail_unlock; 779 goto fail_unlock;
796 780
@@ -1310,7 +1294,7 @@ out_free_list:
1310 * i915_gem_release_mmap - remove physical page mappings 1294 * i915_gem_release_mmap - remove physical page mappings
1311 * @obj: obj in question 1295 * @obj: obj in question
1312 * 1296 *
1313 * Preserve the reservation of the mmaping with the DRM core code, but 1297 * Preserve the reservation of the mmapping with the DRM core code, but
1314 * relinquish ownership of the pages back to the system. 1298 * relinquish ownership of the pages back to the system.
1315 * 1299 *
1316 * It is vital that we remove the page mapping if we have mapped a tiled 1300 * It is vital that we remove the page mapping if we have mapped a tiled
@@ -2021,9 +2005,6 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
2021 /* blow away mappings if mapped through GTT */ 2005 /* blow away mappings if mapped through GTT */
2022 i915_gem_release_mmap(obj); 2006 i915_gem_release_mmap(obj);
2023 2007
2024 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2025 i915_gem_clear_fence_reg(obj);
2026
2027 /* Move the object to the CPU domain to ensure that 2008 /* Move the object to the CPU domain to ensure that
2028 * any possible CPU writes while it's not in the GTT 2009 * any possible CPU writes while it's not in the GTT
2029 * are flushed when we go to remap it. This will 2010 * are flushed when we go to remap it. This will
@@ -2039,6 +2020,10 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
2039 2020
2040 BUG_ON(obj_priv->active); 2021 BUG_ON(obj_priv->active);
2041 2022
2023 /* release the fence reg _after_ flushing */
2024 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2025 i915_gem_clear_fence_reg(obj);
2026
2042 if (obj_priv->agp_mem != NULL) { 2027 if (obj_priv->agp_mem != NULL) {
2043 drm_unbind_agp(obj_priv->agp_mem); 2028 drm_unbind_agp(obj_priv->agp_mem);
2044 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); 2029 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
@@ -2229,7 +2214,8 @@ i915_gem_evict_something(struct drm_device *dev, int min_size)
2229} 2214}
2230 2215
2231int 2216int
2232i915_gem_object_get_pages(struct drm_gem_object *obj) 2217i915_gem_object_get_pages(struct drm_gem_object *obj,
2218 gfp_t gfpmask)
2233{ 2219{
2234 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2220 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2235 int page_count, i; 2221 int page_count, i;
@@ -2255,7 +2241,10 @@ i915_gem_object_get_pages(struct drm_gem_object *obj)
2255 inode = obj->filp->f_path.dentry->d_inode; 2241 inode = obj->filp->f_path.dentry->d_inode;
2256 mapping = inode->i_mapping; 2242 mapping = inode->i_mapping;
2257 for (i = 0; i < page_count; i++) { 2243 for (i = 0; i < page_count; i++) {
2258 page = read_mapping_page(mapping, i, NULL); 2244 page = read_cache_page_gfp(mapping, i,
2245 mapping_gfp_mask (mapping) |
2246 __GFP_COLD |
2247 gfpmask);
2259 if (IS_ERR(page)) { 2248 if (IS_ERR(page)) {
2260 ret = PTR_ERR(page); 2249 ret = PTR_ERR(page);
2261 i915_gem_object_put_pages(obj); 2250 i915_gem_object_put_pages(obj);
@@ -2578,12 +2567,9 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2578 drm_i915_private_t *dev_priv = dev->dev_private; 2567 drm_i915_private_t *dev_priv = dev->dev_private;
2579 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2568 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2580 struct drm_mm_node *free_space; 2569 struct drm_mm_node *free_space;
2581 bool retry_alloc = false; 2570 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2582 int ret; 2571 int ret;
2583 2572
2584 if (dev_priv->mm.suspended)
2585 return -EBUSY;
2586
2587 if (obj_priv->madv != I915_MADV_WILLNEED) { 2573 if (obj_priv->madv != I915_MADV_WILLNEED) {
2588 DRM_ERROR("Attempting to bind a purgeable object\n"); 2574 DRM_ERROR("Attempting to bind a purgeable object\n");
2589 return -EINVAL; 2575 return -EINVAL;
@@ -2625,15 +2611,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2625 DRM_INFO("Binding object of size %zd at 0x%08x\n", 2611 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2626 obj->size, obj_priv->gtt_offset); 2612 obj->size, obj_priv->gtt_offset);
2627#endif 2613#endif
2628 if (retry_alloc) { 2614 ret = i915_gem_object_get_pages(obj, gfpmask);
2629 i915_gem_object_set_page_gfp_mask (obj,
2630 i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2631 }
2632 ret = i915_gem_object_get_pages(obj);
2633 if (retry_alloc) {
2634 i915_gem_object_set_page_gfp_mask (obj,
2635 i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2636 }
2637 if (ret) { 2615 if (ret) {
2638 drm_mm_put_block(obj_priv->gtt_space); 2616 drm_mm_put_block(obj_priv->gtt_space);
2639 obj_priv->gtt_space = NULL; 2617 obj_priv->gtt_space = NULL;
@@ -2643,9 +2621,9 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2643 ret = i915_gem_evict_something(dev, obj->size); 2621 ret = i915_gem_evict_something(dev, obj->size);
2644 if (ret) { 2622 if (ret) {
2645 /* now try to shrink everyone else */ 2623 /* now try to shrink everyone else */
2646 if (! retry_alloc) { 2624 if (gfpmask) {
2647 retry_alloc = true; 2625 gfpmask = 0;
2648 goto search_free; 2626 goto search_free;
2649 } 2627 }
2650 2628
2651 return ret; 2629 return ret;
@@ -2839,6 +2817,57 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2839 return 0; 2817 return 0;
2840} 2818}
2841 2819
2820/*
2821 * Prepare buffer for display plane. Use uninterruptible for possible flush
2822 * wait, as in modesetting process we're not supposed to be interrupted.
2823 */
2824int
2825i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2826{
2827 struct drm_device *dev = obj->dev;
2828 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2829 uint32_t old_write_domain, old_read_domains;
2830 int ret;
2831
2832 /* Not valid to be called on unbound objects. */
2833 if (obj_priv->gtt_space == NULL)
2834 return -EINVAL;
2835
2836 i915_gem_object_flush_gpu_write_domain(obj);
2837
2838 /* Wait on any GPU rendering and flushing to occur. */
2839 if (obj_priv->active) {
2840#if WATCH_BUF
2841 DRM_INFO("%s: object %p wait for seqno %08x\n",
2842 __func__, obj, obj_priv->last_rendering_seqno);
2843#endif
2844 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2845 if (ret != 0)
2846 return ret;
2847 }
2848
2849 old_write_domain = obj->write_domain;
2850 old_read_domains = obj->read_domains;
2851
2852 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2853
2854 i915_gem_object_flush_cpu_write_domain(obj);
2855
2856 /* It should now be out of any other write domains, and we can update
2857 * the domain values for our changes.
2858 */
2859 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2860 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2861 obj->write_domain = I915_GEM_DOMAIN_GTT;
2862 obj_priv->dirty = 1;
2863
2864 trace_i915_gem_object_change_domain(obj,
2865 old_read_domains,
2866 old_write_domain);
2867
2868 return 0;
2869}
2870
2842/** 2871/**
2843 * Moves a single object to the CPU read, and possibly write domain. 2872 * Moves a single object to the CPU read, and possibly write domain.
2844 * 2873 *
@@ -3198,7 +3227,7 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3198static int 3227static int
3199i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, 3228i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3200 struct drm_file *file_priv, 3229 struct drm_file *file_priv,
3201 struct drm_i915_gem_exec_object *entry, 3230 struct drm_i915_gem_exec_object2 *entry,
3202 struct drm_i915_gem_relocation_entry *relocs) 3231 struct drm_i915_gem_relocation_entry *relocs)
3203{ 3232{
3204 struct drm_device *dev = obj->dev; 3233 struct drm_device *dev = obj->dev;
@@ -3206,12 +3235,35 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3206 struct drm_i915_gem_object *obj_priv = obj->driver_private; 3235 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3207 int i, ret; 3236 int i, ret;
3208 void __iomem *reloc_page; 3237 void __iomem *reloc_page;
3238 bool need_fence;
3239
3240 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3241 obj_priv->tiling_mode != I915_TILING_NONE;
3242
3243 /* Check fence reg constraints and rebind if necessary */
3244 if (need_fence && !i915_obj_fenceable(dev, obj))
3245 i915_gem_object_unbind(obj);
3209 3246
3210 /* Choose the GTT offset for our buffer and put it there. */ 3247 /* Choose the GTT offset for our buffer and put it there. */
3211 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); 3248 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3212 if (ret) 3249 if (ret)
3213 return ret; 3250 return ret;
3214 3251
3252 /*
3253 * Pre-965 chips need a fence register set up in order to
3254 * properly handle blits to/from tiled surfaces.
3255 */
3256 if (need_fence) {
3257 ret = i915_gem_object_get_fence_reg(obj);
3258 if (ret != 0) {
3259 if (ret != -EBUSY && ret != -ERESTARTSYS)
3260 DRM_ERROR("Failure to install fence: %d\n",
3261 ret);
3262 i915_gem_object_unpin(obj);
3263 return ret;
3264 }
3265 }
3266
3215 entry->offset = obj_priv->gtt_offset; 3267 entry->offset = obj_priv->gtt_offset;
3216 3268
3217 /* Apply the relocations, using the GTT aperture to avoid cache 3269 /* Apply the relocations, using the GTT aperture to avoid cache
@@ -3373,7 +3425,7 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3373 */ 3425 */
3374static int 3426static int
3375i915_dispatch_gem_execbuffer(struct drm_device *dev, 3427i915_dispatch_gem_execbuffer(struct drm_device *dev,
3376 struct drm_i915_gem_execbuffer *exec, 3428 struct drm_i915_gem_execbuffer2 *exec,
3377 struct drm_clip_rect *cliprects, 3429 struct drm_clip_rect *cliprects,
3378 uint64_t exec_offset) 3430 uint64_t exec_offset)
3379{ 3431{
@@ -3463,7 +3515,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3463} 3515}
3464 3516
3465static int 3517static int
3466i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list, 3518i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3467 uint32_t buffer_count, 3519 uint32_t buffer_count,
3468 struct drm_i915_gem_relocation_entry **relocs) 3520 struct drm_i915_gem_relocation_entry **relocs)
3469{ 3521{
@@ -3478,8 +3530,10 @@ i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3478 } 3530 }
3479 3531
3480 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); 3532 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3481 if (*relocs == NULL) 3533 if (*relocs == NULL) {
3534 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3482 return -ENOMEM; 3535 return -ENOMEM;
3536 }
3483 3537
3484 for (i = 0; i < buffer_count; i++) { 3538 for (i = 0; i < buffer_count; i++) {
3485 struct drm_i915_gem_relocation_entry __user *user_relocs; 3539 struct drm_i915_gem_relocation_entry __user *user_relocs;
@@ -3503,13 +3557,16 @@ i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3503} 3557}
3504 3558
3505static int 3559static int
3506i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list, 3560i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3507 uint32_t buffer_count, 3561 uint32_t buffer_count,
3508 struct drm_i915_gem_relocation_entry *relocs) 3562 struct drm_i915_gem_relocation_entry *relocs)
3509{ 3563{
3510 uint32_t reloc_count = 0, i; 3564 uint32_t reloc_count = 0, i;
3511 int ret = 0; 3565 int ret = 0;
3512 3566
3567 if (relocs == NULL)
3568 return 0;
3569
3513 for (i = 0; i < buffer_count; i++) { 3570 for (i = 0; i < buffer_count; i++) {
3514 struct drm_i915_gem_relocation_entry __user *user_relocs; 3571 struct drm_i915_gem_relocation_entry __user *user_relocs;
3515 int unwritten; 3572 int unwritten;
@@ -3536,7 +3593,7 @@ err:
3536} 3593}
3537 3594
3538static int 3595static int
3539i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec, 3596i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3540 uint64_t exec_offset) 3597 uint64_t exec_offset)
3541{ 3598{
3542 uint32_t exec_start, exec_len; 3599 uint32_t exec_start, exec_len;
@@ -3589,18 +3646,18 @@ i915_gem_wait_for_pending_flip(struct drm_device *dev,
3589} 3646}
3590 3647
3591int 3648int
3592i915_gem_execbuffer(struct drm_device *dev, void *data, 3649i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3593 struct drm_file *file_priv) 3650 struct drm_file *file_priv,
3651 struct drm_i915_gem_execbuffer2 *args,
3652 struct drm_i915_gem_exec_object2 *exec_list)
3594{ 3653{
3595 drm_i915_private_t *dev_priv = dev->dev_private; 3654 drm_i915_private_t *dev_priv = dev->dev_private;
3596 struct drm_i915_gem_execbuffer *args = data;
3597 struct drm_i915_gem_exec_object *exec_list = NULL;
3598 struct drm_gem_object **object_list = NULL; 3655 struct drm_gem_object **object_list = NULL;
3599 struct drm_gem_object *batch_obj; 3656 struct drm_gem_object *batch_obj;
3600 struct drm_i915_gem_object *obj_priv; 3657 struct drm_i915_gem_object *obj_priv;
3601 struct drm_clip_rect *cliprects = NULL; 3658 struct drm_clip_rect *cliprects = NULL;
3602 struct drm_i915_gem_relocation_entry *relocs; 3659 struct drm_i915_gem_relocation_entry *relocs = NULL;
3603 int ret, ret2, i, pinned = 0; 3660 int ret = 0, ret2, i, pinned = 0;
3604 uint64_t exec_offset; 3661 uint64_t exec_offset;
3605 uint32_t seqno, flush_domains, reloc_index; 3662 uint32_t seqno, flush_domains, reloc_index;
3606 int pin_tries, flips; 3663 int pin_tries, flips;
@@ -3614,25 +3671,13 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
3614 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); 3671 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3615 return -EINVAL; 3672 return -EINVAL;
3616 } 3673 }
3617 /* Copy in the exec list from userland */
3618 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3619 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); 3674 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3620 if (exec_list == NULL || object_list == NULL) { 3675 if (object_list == NULL) {
3621 DRM_ERROR("Failed to allocate exec or object list " 3676 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3622 "for %d buffers\n",
3623 args->buffer_count); 3677 args->buffer_count);
3624 ret = -ENOMEM; 3678 ret = -ENOMEM;
3625 goto pre_mutex_err; 3679 goto pre_mutex_err;
3626 } 3680 }
3627 ret = copy_from_user(exec_list,
3628 (struct drm_i915_relocation_entry __user *)
3629 (uintptr_t) args->buffers_ptr,
3630 sizeof(*exec_list) * args->buffer_count);
3631 if (ret != 0) {
3632 DRM_ERROR("copy %d exec entries failed %d\n",
3633 args->buffer_count, ret);
3634 goto pre_mutex_err;
3635 }
3636 3681
3637 if (args->num_cliprects != 0) { 3682 if (args->num_cliprects != 0) {
3638 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), 3683 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
@@ -3680,6 +3725,8 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
3680 if (object_list[i] == NULL) { 3725 if (object_list[i] == NULL) {
3681 DRM_ERROR("Invalid object handle %d at index %d\n", 3726 DRM_ERROR("Invalid object handle %d at index %d\n",
3682 exec_list[i].handle, i); 3727 exec_list[i].handle, i);
3728 /* prevent error path from reading uninitialized data */
3729 args->buffer_count = i + 1;
3683 ret = -EBADF; 3730 ret = -EBADF;
3684 goto err; 3731 goto err;
3685 } 3732 }
@@ -3688,6 +3735,8 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
3688 if (obj_priv->in_execbuffer) { 3735 if (obj_priv->in_execbuffer) {
3689 DRM_ERROR("Object %p appears more than once in object list\n", 3736 DRM_ERROR("Object %p appears more than once in object list\n",
3690 object_list[i]); 3737 object_list[i]);
3738 /* prevent error path from reading uninitialized data */
3739 args->buffer_count = i + 1;
3691 ret = -EBADF; 3740 ret = -EBADF;
3692 goto err; 3741 goto err;
3693 } 3742 }
@@ -3884,8 +3933,101 @@ err:
3884 3933
3885 mutex_unlock(&dev->struct_mutex); 3934 mutex_unlock(&dev->struct_mutex);
3886 3935
3936pre_mutex_err:
3937 /* Copy the updated relocations out regardless of current error
3938 * state. Failure to update the relocs would mean that the next
3939 * time userland calls execbuf, it would do so with presumed offset
3940 * state that didn't match the actual object state.
3941 */
3942 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3943 relocs);
3944 if (ret2 != 0) {
3945 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3946
3947 if (ret == 0)
3948 ret = ret2;
3949 }
3950
3951 drm_free_large(object_list);
3952 kfree(cliprects);
3953
3954 return ret;
3955}
3956
3957/*
3958 * Legacy execbuffer just creates an exec2 list from the original exec object
3959 * list array and passes it to the real function.
3960 */
3961int
3962i915_gem_execbuffer(struct drm_device *dev, void *data,
3963 struct drm_file *file_priv)
3964{
3965 struct drm_i915_gem_execbuffer *args = data;
3966 struct drm_i915_gem_execbuffer2 exec2;
3967 struct drm_i915_gem_exec_object *exec_list = NULL;
3968 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3969 int ret, i;
3970
3971#if WATCH_EXEC
3972 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3973 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3974#endif
3975
3976 if (args->buffer_count < 1) {
3977 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3978 return -EINVAL;
3979 }
3980
3981 /* Copy in the exec list from userland */
3982 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3983 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3984 if (exec_list == NULL || exec2_list == NULL) {
3985 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3986 args->buffer_count);
3987 drm_free_large(exec_list);
3988 drm_free_large(exec2_list);
3989 return -ENOMEM;
3990 }
3991 ret = copy_from_user(exec_list,
3992 (struct drm_i915_relocation_entry __user *)
3993 (uintptr_t) args->buffers_ptr,
3994 sizeof(*exec_list) * args->buffer_count);
3995 if (ret != 0) {
3996 DRM_ERROR("copy %d exec entries failed %d\n",
3997 args->buffer_count, ret);
3998 drm_free_large(exec_list);
3999 drm_free_large(exec2_list);
4000 return -EFAULT;
4001 }
4002
4003 for (i = 0; i < args->buffer_count; i++) {
4004 exec2_list[i].handle = exec_list[i].handle;
4005 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4006 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4007 exec2_list[i].alignment = exec_list[i].alignment;
4008 exec2_list[i].offset = exec_list[i].offset;
4009 if (!IS_I965G(dev))
4010 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4011 else
4012 exec2_list[i].flags = 0;
4013 }
4014
4015 exec2.buffers_ptr = args->buffers_ptr;
4016 exec2.buffer_count = args->buffer_count;
4017 exec2.batch_start_offset = args->batch_start_offset;
4018 exec2.batch_len = args->batch_len;
4019 exec2.DR1 = args->DR1;
4020 exec2.DR4 = args->DR4;
4021 exec2.num_cliprects = args->num_cliprects;
4022 exec2.cliprects_ptr = args->cliprects_ptr;
4023 exec2.flags = 0;
4024
4025 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3887 if (!ret) { 4026 if (!ret) {
3888 /* Copy the new buffer offsets back to the user's exec list. */ 4027 /* Copy the new buffer offsets back to the user's exec list. */
4028 for (i = 0; i < args->buffer_count; i++)
4029 exec_list[i].offset = exec2_list[i].offset;
4030 /* ... and back out to userspace */
3889 ret = copy_to_user((struct drm_i915_relocation_entry __user *) 4031 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3890 (uintptr_t) args->buffers_ptr, 4032 (uintptr_t) args->buffers_ptr,
3891 exec_list, 4033 exec_list,
@@ -3898,25 +4040,62 @@ err:
3898 } 4040 }
3899 } 4041 }
3900 4042
3901 /* Copy the updated relocations out regardless of current error 4043 drm_free_large(exec_list);
3902 * state. Failure to update the relocs would mean that the next 4044 drm_free_large(exec2_list);
3903 * time userland calls execbuf, it would do so with presumed offset 4045 return ret;
3904 * state that didn't match the actual object state. 4046}
3905 */
3906 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3907 relocs);
3908 if (ret2 != 0) {
3909 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3910 4047
3911 if (ret == 0) 4048int
3912 ret = ret2; 4049i915_gem_execbuffer2(struct drm_device *dev, void *data,
4050 struct drm_file *file_priv)
4051{
4052 struct drm_i915_gem_execbuffer2 *args = data;
4053 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4054 int ret;
4055
4056#if WATCH_EXEC
4057 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4058 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4059#endif
4060
4061 if (args->buffer_count < 1) {
4062 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4063 return -EINVAL;
3913 } 4064 }
3914 4065
3915pre_mutex_err: 4066 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3916 drm_free_large(object_list); 4067 if (exec2_list == NULL) {
3917 drm_free_large(exec_list); 4068 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3918 kfree(cliprects); 4069 args->buffer_count);
4070 return -ENOMEM;
4071 }
4072 ret = copy_from_user(exec2_list,
4073 (struct drm_i915_relocation_entry __user *)
4074 (uintptr_t) args->buffers_ptr,
4075 sizeof(*exec2_list) * args->buffer_count);
4076 if (ret != 0) {
4077 DRM_ERROR("copy %d exec entries failed %d\n",
4078 args->buffer_count, ret);
4079 drm_free_large(exec2_list);
4080 return -EFAULT;
4081 }
3919 4082
4083 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4084 if (!ret) {
4085 /* Copy the new buffer offsets back to the user's exec list. */
4086 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4087 (uintptr_t) args->buffers_ptr,
4088 exec2_list,
4089 sizeof(*exec2_list) * args->buffer_count);
4090 if (ret) {
4091 ret = -EFAULT;
4092 DRM_ERROR("failed to copy %d exec entries "
4093 "back to user (%d)\n",
4094 args->buffer_count, ret);
4095 }
4096 }
4097
4098 drm_free_large(exec2_list);
3920 return ret; 4099 return ret;
3921} 4100}
3922 4101
@@ -3933,19 +4112,7 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3933 if (ret) 4112 if (ret)
3934 return ret; 4113 return ret;
3935 } 4114 }
3936 /* 4115
3937 * Pre-965 chips need a fence register set up in order to
3938 * properly handle tiled surfaces.
3939 */
3940 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
3941 ret = i915_gem_object_get_fence_reg(obj);
3942 if (ret != 0) {
3943 if (ret != -EBUSY && ret != -ERESTARTSYS)
3944 DRM_ERROR("Failure to install fence: %d\n",
3945 ret);
3946 return ret;
3947 }
3948 }
3949 obj_priv->pin_count++; 4116 obj_priv->pin_count++;
3950 4117
3951 /* If the object is not active and not pending a flush, 4118 /* If the object is not active and not pending a flush,
@@ -4766,7 +4933,7 @@ void i915_gem_detach_phys_object(struct drm_device *dev,
4766 if (!obj_priv->phys_obj) 4933 if (!obj_priv->phys_obj)
4767 return; 4934 return;
4768 4935
4769 ret = i915_gem_object_get_pages(obj); 4936 ret = i915_gem_object_get_pages(obj, 0);
4770 if (ret) 4937 if (ret)
4771 goto out; 4938 goto out;
4772 4939
@@ -4824,7 +4991,7 @@ i915_gem_attach_phys_object(struct drm_device *dev,
4824 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; 4991 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4825 obj_priv->phys_obj->cur_obj = obj; 4992 obj_priv->phys_obj->cur_obj = obj;
4826 4993
4827 ret = i915_gem_object_get_pages(obj); 4994 ret = i915_gem_object_get_pages(obj, 0);
4828 if (ret) { 4995 if (ret) {
4829 DRM_ERROR("failed to get page list\n"); 4996 DRM_ERROR("failed to get page list\n");
4830 goto out; 4997 goto out;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 30d6af6c09bb..df278b2685bf 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -304,35 +304,39 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
304 304
305 305
306/** 306/**
307 * Returns the size of the fence for a tiled object of the given size. 307 * Returns whether an object is currently fenceable. If not, it may need
308 * to be unbound and have its pitch adjusted.
308 */ 309 */
309static int 310bool
310i915_get_fence_size(struct drm_device *dev, int size) 311i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj)
311{ 312{
312 int i; 313 struct drm_i915_gem_object *obj_priv = obj->driver_private;
313 int start;
314 314
315 if (IS_I965G(dev)) { 315 if (IS_I965G(dev)) {
316 /* The 965 can have fences at any page boundary. */ 316 /* The 965 can have fences at any page boundary. */
317 return ALIGN(size, 4096); 317 if (obj->size & 4095)
318 return false;
319 return true;
320 } else if (IS_I9XX(dev)) {
321 if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK)
322 return false;
318 } else { 323 } else {
319 /* Align the size to a power of two greater than the smallest 324 if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK)
320 * fence size. 325 return false;
321 */ 326 }
322 if (IS_I9XX(dev))
323 start = 1024 * 1024;
324 else
325 start = 512 * 1024;
326 327
327 for (i = start; i < size; i <<= 1) 328 /* Power of two sized... */
328 ; 329 if (obj->size & (obj->size - 1))
330 return false;
329 331
330 return i; 332 /* Objects must be size aligned as well */
331 } 333 if (obj_priv->gtt_offset & (obj->size - 1))
334 return false;
335 return true;
332} 336}
333 337
334/* Check pitch constriants for all chips & tiling formats */ 338/* Check pitch constriants for all chips & tiling formats */
335static bool 339bool
336i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) 340i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
337{ 341{
338 int tile_width; 342 int tile_width;
@@ -384,12 +388,6 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
384 if (stride & (stride - 1)) 388 if (stride & (stride - 1))
385 return false; 389 return false;
386 390
387 /* We don't 0handle the aperture area covered by the fence being bigger
388 * than the object size.
389 */
390 if (i915_get_fence_size(dev, size) != size)
391 return false;
392
393 return true; 391 return true;
394} 392}
395 393
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 85f4c5de97e2..50ddf4a95c5e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -274,7 +274,6 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev)
274 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 274 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
275 int ret = IRQ_NONE; 275 int ret = IRQ_NONE;
276 u32 de_iir, gt_iir, de_ier, pch_iir; 276 u32 de_iir, gt_iir, de_ier, pch_iir;
277 u32 new_de_iir, new_gt_iir, new_pch_iir;
278 struct drm_i915_master_private *master_priv; 277 struct drm_i915_master_private *master_priv;
279 278
280 /* disable master interrupt before clearing iir */ 279 /* disable master interrupt before clearing iir */
@@ -286,49 +285,58 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev)
286 gt_iir = I915_READ(GTIIR); 285 gt_iir = I915_READ(GTIIR);
287 pch_iir = I915_READ(SDEIIR); 286 pch_iir = I915_READ(SDEIIR);
288 287
289 for (;;) { 288 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
290 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) 289 goto done;
291 break;
292 290
293 ret = IRQ_HANDLED; 291 ret = IRQ_HANDLED;
294 292
295 /* should clear PCH hotplug event before clear CPU irq */ 293 if (dev->primary->master) {
296 I915_WRITE(SDEIIR, pch_iir); 294 master_priv = dev->primary->master->driver_priv;
297 new_pch_iir = I915_READ(SDEIIR); 295 if (master_priv->sarea_priv)
296 master_priv->sarea_priv->last_dispatch =
297 READ_BREADCRUMB(dev_priv);
298 }
298 299
299 I915_WRITE(DEIIR, de_iir); 300 if (gt_iir & GT_USER_INTERRUPT) {
300 new_de_iir = I915_READ(DEIIR); 301 u32 seqno = i915_get_gem_seqno(dev);
301 I915_WRITE(GTIIR, gt_iir); 302 dev_priv->mm.irq_gem_seqno = seqno;
302 new_gt_iir = I915_READ(GTIIR); 303 trace_i915_gem_request_complete(dev, seqno);
304 DRM_WAKEUP(&dev_priv->irq_queue);
305 dev_priv->hangcheck_count = 0;
306 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
307 }
303 308
304 if (dev->primary->master) { 309 if (de_iir & DE_GSE)
305 master_priv = dev->primary->master->driver_priv; 310 ironlake_opregion_gse_intr(dev);
306 if (master_priv->sarea_priv)
307 master_priv->sarea_priv->last_dispatch =
308 READ_BREADCRUMB(dev_priv);
309 }
310 311
311 if (gt_iir & GT_USER_INTERRUPT) { 312 if (de_iir & DE_PLANEA_FLIP_DONE)
312 u32 seqno = i915_get_gem_seqno(dev); 313 intel_prepare_page_flip(dev, 0);
313 dev_priv->mm.irq_gem_seqno = seqno;
314 trace_i915_gem_request_complete(dev, seqno);
315 DRM_WAKEUP(&dev_priv->irq_queue);
316 }
317 314
318 if (de_iir & DE_GSE) 315 if (de_iir & DE_PLANEB_FLIP_DONE)
319 ironlake_opregion_gse_intr(dev); 316 intel_prepare_page_flip(dev, 1);
320 317
321 /* check event from PCH */ 318 if (de_iir & DE_PIPEA_VBLANK) {
322 if ((de_iir & DE_PCH_EVENT) && 319 drm_handle_vblank(dev, 0);
323 (pch_iir & SDE_HOTPLUG_MASK)) { 320 intel_finish_page_flip(dev, 0);
324 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 321 }
325 }
326 322
327 de_iir = new_de_iir; 323 if (de_iir & DE_PIPEB_VBLANK) {
328 gt_iir = new_gt_iir; 324 drm_handle_vblank(dev, 1);
329 pch_iir = new_pch_iir; 325 intel_finish_page_flip(dev, 1);
330 } 326 }
331 327
328 /* check event from PCH */
329 if ((de_iir & DE_PCH_EVENT) &&
330 (pch_iir & SDE_HOTPLUG_MASK)) {
331 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
332 }
333
334 /* should clear PCH hotplug event before clear CPU irq */
335 I915_WRITE(SDEIIR, pch_iir);
336 I915_WRITE(GTIIR, gt_iir);
337 I915_WRITE(DEIIR, de_iir);
338
339done:
332 I915_WRITE(DEIER, de_ier); 340 I915_WRITE(DEIER, de_ier);
333 (void)I915_READ(DEIER); 341 (void)I915_READ(DEIER);
334 342
@@ -852,11 +860,11 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
852 if (!(pipeconf & PIPEACONF_ENABLE)) 860 if (!(pipeconf & PIPEACONF_ENABLE))
853 return -EINVAL; 861 return -EINVAL;
854 862
855 if (IS_IRONLAKE(dev))
856 return 0;
857
858 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 863 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
859 if (IS_I965G(dev)) 864 if (IS_IRONLAKE(dev))
865 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
866 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
867 else if (IS_I965G(dev))
860 i915_enable_pipestat(dev_priv, pipe, 868 i915_enable_pipestat(dev_priv, pipe,
861 PIPE_START_VBLANK_INTERRUPT_ENABLE); 869 PIPE_START_VBLANK_INTERRUPT_ENABLE);
862 else 870 else
@@ -874,13 +882,14 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
874 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 882 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
875 unsigned long irqflags; 883 unsigned long irqflags;
876 884
877 if (IS_IRONLAKE(dev))
878 return;
879
880 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 885 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
881 i915_disable_pipestat(dev_priv, pipe, 886 if (IS_IRONLAKE(dev))
882 PIPE_VBLANK_INTERRUPT_ENABLE | 887 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
883 PIPE_START_VBLANK_INTERRUPT_ENABLE); 888 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
889 else
890 i915_disable_pipestat(dev_priv, pipe,
891 PIPE_VBLANK_INTERRUPT_ENABLE |
892 PIPE_START_VBLANK_INTERRUPT_ENABLE);
884 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); 893 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
885} 894}
886 895
@@ -1023,13 +1032,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1023{ 1032{
1024 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1033 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1025 /* enable kind of interrupts always enabled */ 1034 /* enable kind of interrupts always enabled */
1026 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT; 1035 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1036 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1027 u32 render_mask = GT_USER_INTERRUPT; 1037 u32 render_mask = GT_USER_INTERRUPT;
1028 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | 1038 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1029 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; 1039 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1030 1040
1031 dev_priv->irq_mask_reg = ~display_mask; 1041 dev_priv->irq_mask_reg = ~display_mask;
1032 dev_priv->de_irq_enable_reg = display_mask; 1042 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1033 1043
1034 /* should always can generate irq */ 1044 /* should always can generate irq */
1035 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1045 I915_WRITE(DEIIR, I915_READ(DEIIR));
@@ -1084,6 +1094,10 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
1084 (void) I915_READ(IER); 1094 (void) I915_READ(IER);
1085} 1095}
1086 1096
1097/*
1098 * Must be called after intel_modeset_init or hotplug interrupts won't be
1099 * enabled correctly.
1100 */
1087int i915_driver_irq_postinstall(struct drm_device *dev) 1101int i915_driver_irq_postinstall(struct drm_device *dev)
1088{ 1102{
1089 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1103 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1106,19 +1120,23 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
1106 if (I915_HAS_HOTPLUG(dev)) { 1120 if (I915_HAS_HOTPLUG(dev)) {
1107 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 1121 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1108 1122
1109 /* Leave other bits alone */ 1123 /* Note HDMI and DP share bits */
1110 hotplug_en |= HOTPLUG_EN_MASK; 1124 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1125 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1126 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1127 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1128 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1129 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1130 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1131 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1132 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1133 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1134 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1135 hotplug_en |= CRT_HOTPLUG_INT_EN;
1136 /* Ignore TV since it's buggy */
1137
1111 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 1138 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1112 1139
1113 dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
1114 TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
1115 SDVOB_HOTPLUG_INT_STATUS;
1116 if (IS_G4X(dev)) {
1117 dev_priv->hotplug_supported_mask |=
1118 HDMIB_HOTPLUG_INT_STATUS |
1119 HDMIC_HOTPLUG_INT_STATUS |
1120 HDMID_HOTPLUG_INT_STATUS;
1121 }
1122 /* Enable in IER... */ 1140 /* Enable in IER... */
1123 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 1141 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1124 /* and unmask in IMR */ 1142 /* and unmask in IMR */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 974b3cf70618..847006c5218e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -879,13 +879,6 @@
879#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 879#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
880#define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */ 880#define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */
881#define CRT_FORCE_HOTPLUG_MASK 0xfffffe1f 881#define CRT_FORCE_HOTPLUG_MASK 0xfffffe1f
882#define HOTPLUG_EN_MASK (HDMIB_HOTPLUG_INT_EN | \
883 HDMIC_HOTPLUG_INT_EN | \
884 HDMID_HOTPLUG_INT_EN | \
885 SDVOB_HOTPLUG_INT_EN | \
886 SDVOC_HOTPLUG_INT_EN | \
887 CRT_HOTPLUG_INT_EN)
888
889 882
890#define PORT_HOTPLUG_STAT 0x61114 883#define PORT_HOTPLUG_STAT 0x61114
891#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) 884#define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
@@ -982,6 +975,8 @@
982#define LVDS_PORT_EN (1 << 31) 975#define LVDS_PORT_EN (1 << 31)
983/* Selects pipe B for LVDS data. Must be set on pre-965. */ 976/* Selects pipe B for LVDS data. Must be set on pre-965. */
984#define LVDS_PIPEB_SELECT (1 << 30) 977#define LVDS_PIPEB_SELECT (1 << 30)
978/* LVDS dithering flag on 965/g4x platform */
979#define LVDS_ENABLE_DITHER (1 << 25)
985/* Enable border for unscaled (or aspect-scaled) display */ 980/* Enable border for unscaled (or aspect-scaled) display */
986#define LVDS_BORDER_ENABLE (1 << 15) 981#define LVDS_BORDER_ENABLE (1 << 15)
987/* 982/*
@@ -1751,6 +1746,8 @@
1751 1746
1752/* Display & cursor control */ 1747/* Display & cursor control */
1753 1748
1749/* dithering flag on Ironlake */
1750#define PIPE_ENABLE_DITHER (1 << 4)
1754/* Pipe A */ 1751/* Pipe A */
1755#define PIPEADSL 0x70000 1752#define PIPEADSL 0x70000
1756#define PIPEACONF 0x70008 1753#define PIPEACONF 0x70008
@@ -1818,7 +1815,7 @@
1818#define DSPFW_PLANEB_SHIFT 8 1815#define DSPFW_PLANEB_SHIFT 8
1819#define DSPFW2 0x70038 1816#define DSPFW2 0x70038
1820#define DSPFW_CURSORA_MASK 0x00003f00 1817#define DSPFW_CURSORA_MASK 0x00003f00
1821#define DSPFW_CURSORA_SHIFT 16 1818#define DSPFW_CURSORA_SHIFT 8
1822#define DSPFW3 0x7003c 1819#define DSPFW3 0x7003c
1823#define DSPFW_HPLL_SR_EN (1<<31) 1820#define DSPFW_HPLL_SR_EN (1<<31)
1824#define DSPFW_CURSOR_SR_SHIFT 24 1821#define DSPFW_CURSOR_SR_SHIFT 24
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index d5ebb00a9d49..a3b90c9561dc 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -732,12 +732,6 @@ int i915_save_state(struct drm_device *dev)
732 732
733 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 733 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
734 734
735 /* Render Standby */
736 if (I915_HAS_RC6(dev)) {
737 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
738 dev_priv->savePWRCTXA = I915_READ(PWRCTXA);
739 }
740
741 /* Hardware status page */ 735 /* Hardware status page */
742 dev_priv->saveHWS = I915_READ(HWS_PGA); 736 dev_priv->saveHWS = I915_READ(HWS_PGA);
743 737
@@ -793,12 +787,6 @@ int i915_restore_state(struct drm_device *dev)
793 787
794 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 788 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
795 789
796 /* Render Standby */
797 if (I915_HAS_RC6(dev)) {
798 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
799 I915_WRITE(PWRCTXA, dev_priv->savePWRCTXA);
800 }
801
802 /* Hardware status page */ 790 /* Hardware status page */
803 I915_WRITE(HWS_PGA, dev_priv->saveHWS); 791 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
804 792
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index f27567747580..15fbc1b5a83e 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -33,6 +33,8 @@
33#define SLAVE_ADDR1 0x70 33#define SLAVE_ADDR1 0x70
34#define SLAVE_ADDR2 0x72 34#define SLAVE_ADDR2 0x72
35 35
36static int panel_type;
37
36static void * 38static void *
37find_section(struct bdb_header *bdb, int section_id) 39find_section(struct bdb_header *bdb, int section_id)
38{ 40{
@@ -128,6 +130,7 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
128 dev_priv->lvds_dither = lvds_options->pixel_dither; 130 dev_priv->lvds_dither = lvds_options->pixel_dither;
129 if (lvds_options->panel_type == 0xff) 131 if (lvds_options->panel_type == 0xff)
130 return; 132 return;
133 panel_type = lvds_options->panel_type;
131 134
132 lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA); 135 lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
133 if (!lvds_lfp_data) 136 if (!lvds_lfp_data)
@@ -197,7 +200,8 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
197 memset(temp_mode, 0, sizeof(*temp_mode)); 200 memset(temp_mode, 0, sizeof(*temp_mode));
198 } 201 }
199 kfree(temp_mode); 202 kfree(temp_mode);
200 if (temp_downclock < panel_fixed_mode->clock) { 203 if (temp_downclock < panel_fixed_mode->clock &&
204 i915_lvds_downclock) {
201 dev_priv->lvds_downclock_avail = 1; 205 dev_priv->lvds_downclock_avail = 1;
202 dev_priv->lvds_downclock = temp_downclock; 206 dev_priv->lvds_downclock = temp_downclock;
203 DRM_DEBUG_KMS("LVDS downclock is found in VBT. ", 207 DRM_DEBUG_KMS("LVDS downclock is found in VBT. ",
@@ -405,6 +409,34 @@ parse_driver_features(struct drm_i915_private *dev_priv,
405} 409}
406 410
407static void 411static void
412parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
413{
414 struct bdb_edp *edp;
415
416 edp = find_section(bdb, BDB_EDP);
417 if (!edp) {
418 if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->edp_support) {
419 DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported,\
420 assume 18bpp panel color depth.\n");
421 dev_priv->edp_bpp = 18;
422 }
423 return;
424 }
425
426 switch ((edp->color_depth >> (panel_type * 2)) & 3) {
427 case EDP_18BPP:
428 dev_priv->edp_bpp = 18;
429 break;
430 case EDP_24BPP:
431 dev_priv->edp_bpp = 24;
432 break;
433 case EDP_30BPP:
434 dev_priv->edp_bpp = 30;
435 break;
436 }
437}
438
439static void
408parse_device_mapping(struct drm_i915_private *dev_priv, 440parse_device_mapping(struct drm_i915_private *dev_priv,
409 struct bdb_header *bdb) 441 struct bdb_header *bdb)
410{ 442{
@@ -521,6 +553,7 @@ intel_init_bios(struct drm_device *dev)
521 parse_sdvo_device_mapping(dev_priv, bdb); 553 parse_sdvo_device_mapping(dev_priv, bdb);
522 parse_device_mapping(dev_priv, bdb); 554 parse_device_mapping(dev_priv, bdb);
523 parse_driver_features(dev_priv, bdb); 555 parse_driver_features(dev_priv, bdb);
556 parse_edp(dev_priv, bdb);
524 557
525 pci_unmap_rom(pdev, bios); 558 pci_unmap_rom(pdev, bios);
526 559
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 425ac9d7f724..4c18514f6f80 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -98,6 +98,7 @@ struct vbios_data {
98#define BDB_SDVO_LVDS_PNP_IDS 24 98#define BDB_SDVO_LVDS_PNP_IDS 24
99#define BDB_SDVO_LVDS_POWER_SEQ 25 99#define BDB_SDVO_LVDS_POWER_SEQ 25
100#define BDB_TV_OPTIONS 26 100#define BDB_TV_OPTIONS 26
101#define BDB_EDP 27
101#define BDB_LVDS_OPTIONS 40 102#define BDB_LVDS_OPTIONS 40
102#define BDB_LVDS_LFP_DATA_PTRS 41 103#define BDB_LVDS_LFP_DATA_PTRS 41
103#define BDB_LVDS_LFP_DATA 42 104#define BDB_LVDS_LFP_DATA 42
@@ -426,6 +427,45 @@ struct bdb_driver_features {
426 u8 custom_vbt_version; 427 u8 custom_vbt_version;
427} __attribute__((packed)); 428} __attribute__((packed));
428 429
430#define EDP_18BPP 0
431#define EDP_24BPP 1
432#define EDP_30BPP 2
433#define EDP_RATE_1_62 0
434#define EDP_RATE_2_7 1
435#define EDP_LANE_1 0
436#define EDP_LANE_2 1
437#define EDP_LANE_4 3
438#define EDP_PREEMPHASIS_NONE 0
439#define EDP_PREEMPHASIS_3_5dB 1
440#define EDP_PREEMPHASIS_6dB 2
441#define EDP_PREEMPHASIS_9_5dB 3
442#define EDP_VSWING_0_4V 0
443#define EDP_VSWING_0_6V 1
444#define EDP_VSWING_0_8V 2
445#define EDP_VSWING_1_2V 3
446
447struct edp_power_seq {
448 u16 t3;
449 u16 t7;
450 u16 t9;
451 u16 t10;
452 u16 t12;
453} __attribute__ ((packed));
454
455struct edp_link_params {
456 u8 rate:4;
457 u8 lanes:4;
458 u8 preemphasis:4;
459 u8 vswing:4;
460} __attribute__ ((packed));
461
462struct bdb_edp {
463 struct edp_power_seq power_seqs[16];
464 u32 color_depth;
465 u32 sdrrs_msa_timing_delay;
466 struct edp_link_params link_params[16];
467} __attribute__ ((packed));
468
429bool intel_init_bios(struct drm_device *dev); 469bool intel_init_bios(struct drm_device *dev);
430 470
431/* 471/*
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 9f3d3e563414..79dd4026586f 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -157,6 +157,9 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
157 adpa = I915_READ(PCH_ADPA); 157 adpa = I915_READ(PCH_ADPA);
158 158
159 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 159 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
160 /* disable HPD first */
161 I915_WRITE(PCH_ADPA, adpa);
162 (void)I915_READ(PCH_ADPA);
160 163
161 adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 | 164 adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
162 ADPA_CRT_HOTPLUG_WARMUP_10MS | 165 ADPA_CRT_HOTPLUG_WARMUP_10MS |
@@ -548,4 +551,6 @@ void intel_crt_init(struct drm_device *dev)
548 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 551 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
549 552
550 drm_sysfs_connector_add(connector); 553 drm_sysfs_connector_add(connector);
554
555 dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
551} 556}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 52cd9b006da2..12775df1bbfd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -70,8 +70,6 @@ struct intel_limit {
70 intel_p2_t p2; 70 intel_p2_t p2;
71 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, 71 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *); 72 int, int, intel_clock_t *);
73 bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
74 int, int, intel_clock_t *);
75}; 73};
76 74
77#define I8XX_DOT_MIN 25000 75#define I8XX_DOT_MIN 25000
@@ -243,11 +241,11 @@ struct intel_limit {
243#define IRONLAKE_VCO_MIN 1760000 241#define IRONLAKE_VCO_MIN 1760000
244#define IRONLAKE_VCO_MAX 3510000 242#define IRONLAKE_VCO_MAX 3510000
245#define IRONLAKE_N_MIN 1 243#define IRONLAKE_N_MIN 1
246#define IRONLAKE_N_MAX 5 244#define IRONLAKE_N_MAX 6
247#define IRONLAKE_M_MIN 79 245#define IRONLAKE_M_MIN 79
248#define IRONLAKE_M_MAX 118 246#define IRONLAKE_M_MAX 127
249#define IRONLAKE_M1_MIN 12 247#define IRONLAKE_M1_MIN 12
250#define IRONLAKE_M1_MAX 23 248#define IRONLAKE_M1_MAX 22
251#define IRONLAKE_M2_MIN 5 249#define IRONLAKE_M2_MIN 5
252#define IRONLAKE_M2_MAX 9 250#define IRONLAKE_M2_MAX 9
253#define IRONLAKE_P_SDVO_DAC_MIN 5 251#define IRONLAKE_P_SDVO_DAC_MIN 5
@@ -262,18 +260,20 @@ struct intel_limit {
262#define IRONLAKE_P2_LVDS_FAST 7 /* double channel */ 260#define IRONLAKE_P2_LVDS_FAST 7 /* double channel */
263#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */ 261#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
264 262
263#define IRONLAKE_P_DISPLAY_PORT_MIN 10
264#define IRONLAKE_P_DISPLAY_PORT_MAX 20
265#define IRONLAKE_P2_DISPLAY_PORT_FAST 10
266#define IRONLAKE_P2_DISPLAY_PORT_SLOW 10
267#define IRONLAKE_P2_DISPLAY_PORT_LIMIT 0
268#define IRONLAKE_P1_DISPLAY_PORT_MIN 1
269#define IRONLAKE_P1_DISPLAY_PORT_MAX 2
270
265static bool 271static bool
266intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 272intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
267 int target, int refclk, intel_clock_t *best_clock); 273 int target, int refclk, intel_clock_t *best_clock);
268static bool 274static bool
269intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
270 int target, int refclk, intel_clock_t *best_clock);
271static bool
272intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 275intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
273 int target, int refclk, intel_clock_t *best_clock); 276 int target, int refclk, intel_clock_t *best_clock);
274static bool
275intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
276 int target, int refclk, intel_clock_t *best_clock);
277 277
278static bool 278static bool
279intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, 279intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
@@ -294,7 +294,6 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
294 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, 294 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
295 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, 295 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
296 .find_pll = intel_find_best_PLL, 296 .find_pll = intel_find_best_PLL,
297 .find_reduced_pll = intel_find_best_reduced_PLL,
298}; 297};
299 298
300static const intel_limit_t intel_limits_i8xx_lvds = { 299static const intel_limit_t intel_limits_i8xx_lvds = {
@@ -309,7 +308,6 @@ static const intel_limit_t intel_limits_i8xx_lvds = {
309 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, 308 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
310 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, 309 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
311 .find_pll = intel_find_best_PLL, 310 .find_pll = intel_find_best_PLL,
312 .find_reduced_pll = intel_find_best_reduced_PLL,
313}; 311};
314 312
315static const intel_limit_t intel_limits_i9xx_sdvo = { 313static const intel_limit_t intel_limits_i9xx_sdvo = {
@@ -324,7 +322,6 @@ static const intel_limit_t intel_limits_i9xx_sdvo = {
324 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 322 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
325 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, 323 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
326 .find_pll = intel_find_best_PLL, 324 .find_pll = intel_find_best_PLL,
327 .find_reduced_pll = intel_find_best_reduced_PLL,
328}; 325};
329 326
330static const intel_limit_t intel_limits_i9xx_lvds = { 327static const intel_limit_t intel_limits_i9xx_lvds = {
@@ -342,7 +339,6 @@ static const intel_limit_t intel_limits_i9xx_lvds = {
342 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 339 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
343 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, 340 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
344 .find_pll = intel_find_best_PLL, 341 .find_pll = intel_find_best_PLL,
345 .find_reduced_pll = intel_find_best_reduced_PLL,
346}; 342};
347 343
348 /* below parameter and function is for G4X Chipset Family*/ 344 /* below parameter and function is for G4X Chipset Family*/
@@ -360,7 +356,6 @@ static const intel_limit_t intel_limits_g4x_sdvo = {
360 .p2_fast = G4X_P2_SDVO_FAST 356 .p2_fast = G4X_P2_SDVO_FAST
361 }, 357 },
362 .find_pll = intel_g4x_find_best_PLL, 358 .find_pll = intel_g4x_find_best_PLL,
363 .find_reduced_pll = intel_g4x_find_best_PLL,
364}; 359};
365 360
366static const intel_limit_t intel_limits_g4x_hdmi = { 361static const intel_limit_t intel_limits_g4x_hdmi = {
@@ -377,7 +372,6 @@ static const intel_limit_t intel_limits_g4x_hdmi = {
377 .p2_fast = G4X_P2_HDMI_DAC_FAST 372 .p2_fast = G4X_P2_HDMI_DAC_FAST
378 }, 373 },
379 .find_pll = intel_g4x_find_best_PLL, 374 .find_pll = intel_g4x_find_best_PLL,
380 .find_reduced_pll = intel_g4x_find_best_PLL,
381}; 375};
382 376
383static const intel_limit_t intel_limits_g4x_single_channel_lvds = { 377static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
@@ -402,7 +396,6 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
402 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST 396 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
403 }, 397 },
404 .find_pll = intel_g4x_find_best_PLL, 398 .find_pll = intel_g4x_find_best_PLL,
405 .find_reduced_pll = intel_g4x_find_best_PLL,
406}; 399};
407 400
408static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { 401static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
@@ -427,7 +420,6 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
427 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST 420 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
428 }, 421 },
429 .find_pll = intel_g4x_find_best_PLL, 422 .find_pll = intel_g4x_find_best_PLL,
430 .find_reduced_pll = intel_g4x_find_best_PLL,
431}; 423};
432 424
433static const intel_limit_t intel_limits_g4x_display_port = { 425static const intel_limit_t intel_limits_g4x_display_port = {
@@ -465,7 +457,6 @@ static const intel_limit_t intel_limits_pineview_sdvo = {
465 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 457 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
466 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, 458 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
467 .find_pll = intel_find_best_PLL, 459 .find_pll = intel_find_best_PLL,
468 .find_reduced_pll = intel_find_best_reduced_PLL,
469}; 460};
470 461
471static const intel_limit_t intel_limits_pineview_lvds = { 462static const intel_limit_t intel_limits_pineview_lvds = {
@@ -481,7 +472,6 @@ static const intel_limit_t intel_limits_pineview_lvds = {
481 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 472 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
482 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, 473 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
483 .find_pll = intel_find_best_PLL, 474 .find_pll = intel_find_best_PLL,
484 .find_reduced_pll = intel_find_best_reduced_PLL,
485}; 475};
486 476
487static const intel_limit_t intel_limits_ironlake_sdvo = { 477static const intel_limit_t intel_limits_ironlake_sdvo = {
@@ -496,7 +486,7 @@ static const intel_limit_t intel_limits_ironlake_sdvo = {
496 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, 486 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
497 .p2_slow = IRONLAKE_P2_SDVO_DAC_SLOW, 487 .p2_slow = IRONLAKE_P2_SDVO_DAC_SLOW,
498 .p2_fast = IRONLAKE_P2_SDVO_DAC_FAST }, 488 .p2_fast = IRONLAKE_P2_SDVO_DAC_FAST },
499 .find_pll = intel_ironlake_find_best_PLL, 489 .find_pll = intel_g4x_find_best_PLL,
500}; 490};
501 491
502static const intel_limit_t intel_limits_ironlake_lvds = { 492static const intel_limit_t intel_limits_ironlake_lvds = {
@@ -511,7 +501,30 @@ static const intel_limit_t intel_limits_ironlake_lvds = {
511 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, 501 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
512 .p2_slow = IRONLAKE_P2_LVDS_SLOW, 502 .p2_slow = IRONLAKE_P2_LVDS_SLOW,
513 .p2_fast = IRONLAKE_P2_LVDS_FAST }, 503 .p2_fast = IRONLAKE_P2_LVDS_FAST },
514 .find_pll = intel_ironlake_find_best_PLL, 504 .find_pll = intel_g4x_find_best_PLL,
505};
506
507static const intel_limit_t intel_limits_ironlake_display_port = {
508 .dot = { .min = IRONLAKE_DOT_MIN,
509 .max = IRONLAKE_DOT_MAX },
510 .vco = { .min = IRONLAKE_VCO_MIN,
511 .max = IRONLAKE_VCO_MAX},
512 .n = { .min = IRONLAKE_N_MIN,
513 .max = IRONLAKE_N_MAX },
514 .m = { .min = IRONLAKE_M_MIN,
515 .max = IRONLAKE_M_MAX },
516 .m1 = { .min = IRONLAKE_M1_MIN,
517 .max = IRONLAKE_M1_MAX },
518 .m2 = { .min = IRONLAKE_M2_MIN,
519 .max = IRONLAKE_M2_MAX },
520 .p = { .min = IRONLAKE_P_DISPLAY_PORT_MIN,
521 .max = IRONLAKE_P_DISPLAY_PORT_MAX },
522 .p1 = { .min = IRONLAKE_P1_DISPLAY_PORT_MIN,
523 .max = IRONLAKE_P1_DISPLAY_PORT_MAX},
524 .p2 = { .dot_limit = IRONLAKE_P2_DISPLAY_PORT_LIMIT,
525 .p2_slow = IRONLAKE_P2_DISPLAY_PORT_SLOW,
526 .p2_fast = IRONLAKE_P2_DISPLAY_PORT_FAST },
527 .find_pll = intel_find_pll_ironlake_dp,
515}; 528};
516 529
517static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc) 530static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
@@ -519,6 +532,9 @@ static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
519 const intel_limit_t *limit; 532 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 533 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
521 limit = &intel_limits_ironlake_lvds; 534 limit = &intel_limits_ironlake_lvds;
535 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
536 HAS_eDP)
537 limit = &intel_limits_ironlake_display_port;
522 else 538 else
523 limit = &intel_limits_ironlake_sdvo; 539 limit = &intel_limits_ironlake_sdvo;
524 540
@@ -737,46 +753,6 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
737 return (err != target); 753 return (err != target);
738} 754}
739 755
740
741static bool
742intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
743 int target, int refclk, intel_clock_t *best_clock)
744
745{
746 struct drm_device *dev = crtc->dev;
747 intel_clock_t clock;
748 int err = target;
749 bool found = false;
750
751 memcpy(&clock, best_clock, sizeof(intel_clock_t));
752
753 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
754 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
755 /* m1 is always 0 in Pineview */
756 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
757 break;
758 for (clock.n = limit->n.min; clock.n <= limit->n.max;
759 clock.n++) {
760 int this_err;
761
762 intel_clock(dev, refclk, &clock);
763
764 if (!intel_PLL_is_valid(crtc, &clock))
765 continue;
766
767 this_err = abs(clock.dot - target);
768 if (this_err < err) {
769 *best_clock = clock;
770 err = this_err;
771 found = true;
772 }
773 }
774 }
775 }
776
777 return found;
778}
779
780static bool 756static bool
781intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 757intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
782 int target, int refclk, intel_clock_t *best_clock) 758 int target, int refclk, intel_clock_t *best_clock)
@@ -791,7 +767,13 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
791 found = false; 767 found = false;
792 768
793 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 769 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
794 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 770 int lvds_reg;
771
772 if (IS_IRONLAKE(dev))
773 lvds_reg = PCH_LVDS;
774 else
775 lvds_reg = LVDS;
776 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
795 LVDS_CLKB_POWER_UP) 777 LVDS_CLKB_POWER_UP)
796 clock.p2 = limit->p2.p2_fast; 778 clock.p2 = limit->p2.p2_fast;
797 else 779 else
@@ -839,6 +821,11 @@ intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
839{ 821{
840 struct drm_device *dev = crtc->dev; 822 struct drm_device *dev = crtc->dev;
841 intel_clock_t clock; 823 intel_clock_t clock;
824
825 /* return directly when it is eDP */
826 if (HAS_eDP)
827 return true;
828
842 if (target < 200000) { 829 if (target < 200000) {
843 clock.n = 1; 830 clock.n = 1;
844 clock.p1 = 2; 831 clock.p1 = 2;
@@ -857,68 +844,6 @@ intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
857 return true; 844 return true;
858} 845}
859 846
860static bool
861intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
862 int target, int refclk, intel_clock_t *best_clock)
863{
864 struct drm_device *dev = crtc->dev;
865 struct drm_i915_private *dev_priv = dev->dev_private;
866 intel_clock_t clock;
867 int err_most = 47;
868 int err_min = 10000;
869
870 /* eDP has only 2 clock choice, no n/m/p setting */
871 if (HAS_eDP)
872 return true;
873
874 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
875 return intel_find_pll_ironlake_dp(limit, crtc, target,
876 refclk, best_clock);
877
878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
879 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
880 LVDS_CLKB_POWER_UP)
881 clock.p2 = limit->p2.p2_fast;
882 else
883 clock.p2 = limit->p2.p2_slow;
884 } else {
885 if (target < limit->p2.dot_limit)
886 clock.p2 = limit->p2.p2_slow;
887 else
888 clock.p2 = limit->p2.p2_fast;
889 }
890
891 memset(best_clock, 0, sizeof(*best_clock));
892 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
893 /* based on hardware requriment prefer smaller n to precision */
894 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
895 /* based on hardware requirment prefere larger m1,m2 */
896 for (clock.m1 = limit->m1.max;
897 clock.m1 >= limit->m1.min; clock.m1--) {
898 for (clock.m2 = limit->m2.max;
899 clock.m2 >= limit->m2.min; clock.m2--) {
900 int this_err;
901
902 intel_clock(dev, refclk, &clock);
903 if (!intel_PLL_is_valid(crtc, &clock))
904 continue;
905 this_err = abs((10000 - (target*10000/clock.dot)));
906 if (this_err < err_most) {
907 *best_clock = clock;
908 /* found on first matching */
909 goto out;
910 } else if (this_err < err_min) {
911 *best_clock = clock;
912 err_min = this_err;
913 }
914 }
915 }
916 }
917 }
918out:
919 return true;
920}
921
922/* DisplayPort has only two frequencies, 162MHz and 270MHz */ 847/* DisplayPort has only two frequencies, 162MHz and 270MHz */
923static bool 848static bool
924intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 849intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
@@ -1282,7 +1207,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1282 return ret; 1207 return ret;
1283 } 1208 }
1284 1209
1285 ret = i915_gem_object_set_to_gtt_domain(obj, 1); 1210 ret = i915_gem_object_set_to_display_plane(obj);
1286 if (ret != 0) { 1211 if (ret != 0) {
1287 i915_gem_object_unpin(obj); 1212 i915_gem_object_unpin(obj);
1288 mutex_unlock(&dev->struct_mutex); 1213 mutex_unlock(&dev->struct_mutex);
@@ -1493,6 +1418,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1493 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; 1418 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1494 u32 temp; 1419 u32 temp;
1495 int tries = 5, j, n; 1420 int tries = 5, j, n;
1421 u32 pipe_bpc;
1422
1423 temp = I915_READ(pipeconf_reg);
1424 pipe_bpc = temp & PIPE_BPC_MASK;
1496 1425
1497 /* XXX: When our outputs are all unaware of DPMS modes other than off 1426 /* XXX: When our outputs are all unaware of DPMS modes other than off
1498 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 1427 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
@@ -1524,6 +1453,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1524 1453
1525 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1454 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1526 temp = I915_READ(fdi_rx_reg); 1455 temp = I915_READ(fdi_rx_reg);
1456 /*
1457 * make the BPC in FDI Rx be consistent with that in
1458 * pipeconf reg.
1459 */
1460 temp &= ~(0x7 << 16);
1461 temp |= (pipe_bpc << 11);
1527 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE | 1462 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1528 FDI_SEL_PCDCLK | 1463 FDI_SEL_PCDCLK |
1529 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */ 1464 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
@@ -1666,6 +1601,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1666 1601
1667 /* enable PCH transcoder */ 1602 /* enable PCH transcoder */
1668 temp = I915_READ(transconf_reg); 1603 temp = I915_READ(transconf_reg);
1604 /*
1605 * make the BPC in transcoder be consistent with
1606 * that in pipeconf reg.
1607 */
1608 temp &= ~PIPE_BPC_MASK;
1609 temp |= pipe_bpc;
1669 I915_WRITE(transconf_reg, temp | TRANS_ENABLE); 1610 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1670 I915_READ(transconf_reg); 1611 I915_READ(transconf_reg);
1671 1612
@@ -1697,6 +1638,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1697 case DRM_MODE_DPMS_OFF: 1638 case DRM_MODE_DPMS_OFF:
1698 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe); 1639 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1699 1640
1641 drm_vblank_off(dev, pipe);
1700 /* Disable display plane */ 1642 /* Disable display plane */
1701 temp = I915_READ(dspcntr_reg); 1643 temp = I915_READ(dspcntr_reg);
1702 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 1644 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
@@ -1745,6 +1687,9 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1745 I915_READ(fdi_tx_reg); 1687 I915_READ(fdi_tx_reg);
1746 1688
1747 temp = I915_READ(fdi_rx_reg); 1689 temp = I915_READ(fdi_rx_reg);
1690 /* BPC in FDI rx is consistent with that in pipeconf */
1691 temp &= ~(0x07 << 16);
1692 temp |= (pipe_bpc << 11);
1748 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE); 1693 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1749 I915_READ(fdi_rx_reg); 1694 I915_READ(fdi_rx_reg);
1750 1695
@@ -1789,7 +1734,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1789 } 1734 }
1790 } 1735 }
1791 } 1736 }
1792 1737 temp = I915_READ(transconf_reg);
1738 /* BPC in transcoder is consistent with that in pipeconf */
1739 temp &= ~PIPE_BPC_MASK;
1740 temp |= pipe_bpc;
1741 I915_WRITE(transconf_reg, temp);
1742 I915_READ(transconf_reg);
1793 udelay(100); 1743 udelay(100);
1794 1744
1795 /* disable PCH DPLL */ 1745 /* disable PCH DPLL */
@@ -2448,7 +2398,7 @@ static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2448 * A value of 5us seems to be a good balance; safe for very low end 2398 * A value of 5us seems to be a good balance; safe for very low end
2449 * platforms but not overly aggressive on lower latency configs. 2399 * platforms but not overly aggressive on lower latency configs.
2450 */ 2400 */
2451const static int latency_ns = 5000; 2401static const int latency_ns = 5000;
2452 2402
2453static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 2403static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2454{ 2404{
@@ -2559,7 +2509,7 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2559 /* Calc sr entries for one plane configs */ 2509 /* Calc sr entries for one plane configs */
2560 if (sr_hdisplay && (!planea_clock || !planeb_clock)) { 2510 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2561 /* self-refresh has much higher latency */ 2511 /* self-refresh has much higher latency */
2562 const static int sr_latency_ns = 12000; 2512 static const int sr_latency_ns = 12000;
2563 2513
2564 sr_clock = planea_clock ? planea_clock : planeb_clock; 2514 sr_clock = planea_clock ? planea_clock : planeb_clock;
2565 line_time_us = ((sr_hdisplay * 1000) / sr_clock); 2515 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2570,6 +2520,10 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2570 sr_entries = roundup(sr_entries / cacheline_size, 1); 2520 sr_entries = roundup(sr_entries / cacheline_size, 1);
2571 DRM_DEBUG("self-refresh entries: %d\n", sr_entries); 2521 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2572 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 2522 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2523 } else {
2524 /* Turn off self refresh if both pipes are enabled */
2525 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2526 & ~FW_BLC_SELF_EN);
2573 } 2527 }
2574 2528
2575 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", 2529 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
@@ -2598,7 +2552,7 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
2598 /* Calc sr entries for one plane configs */ 2552 /* Calc sr entries for one plane configs */
2599 if (sr_hdisplay && (!planea_clock || !planeb_clock)) { 2553 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2600 /* self-refresh has much higher latency */ 2554 /* self-refresh has much higher latency */
2601 const static int sr_latency_ns = 12000; 2555 static const int sr_latency_ns = 12000;
2602 2556
2603 sr_clock = planea_clock ? planea_clock : planeb_clock; 2557 sr_clock = planea_clock ? planea_clock : planeb_clock;
2604 line_time_us = ((sr_hdisplay * 1000) / sr_clock); 2558 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2613,6 +2567,10 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
2613 srwm = 1; 2567 srwm = 1;
2614 srwm &= 0x3f; 2568 srwm &= 0x3f;
2615 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 2569 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2570 } else {
2571 /* Turn off self refresh if both pipes are enabled */
2572 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2573 & ~FW_BLC_SELF_EN);
2616 } 2574 }
2617 2575
2618 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 2576 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
@@ -2667,7 +2625,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2667 if (HAS_FW_BLC(dev) && sr_hdisplay && 2625 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2668 (!planea_clock || !planeb_clock)) { 2626 (!planea_clock || !planeb_clock)) {
2669 /* self-refresh has much higher latency */ 2627 /* self-refresh has much higher latency */
2670 const static int sr_latency_ns = 6000; 2628 static const int sr_latency_ns = 6000;
2671 2629
2672 sr_clock = planea_clock ? planea_clock : planeb_clock; 2630 sr_clock = planea_clock ? planea_clock : planeb_clock;
2673 line_time_us = ((sr_hdisplay * 1000) / sr_clock); 2631 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2681,6 +2639,10 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2681 if (srwm < 0) 2639 if (srwm < 0)
2682 srwm = 1; 2640 srwm = 1;
2683 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); 2641 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2642 } else {
2643 /* Turn off self refresh if both pipes are enabled */
2644 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2645 & ~FW_BLC_SELF_EN);
2684 } 2646 }
2685 2647
2686 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 2648 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
@@ -2906,10 +2868,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2906 return -EINVAL; 2868 return -EINVAL;
2907 } 2869 }
2908 2870
2909 if (is_lvds && limit->find_reduced_pll && 2871 if (is_lvds && dev_priv->lvds_downclock_avail) {
2910 dev_priv->lvds_downclock_avail) { 2872 has_reduced_clock = limit->find_pll(limit, crtc,
2911 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2912 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2913 dev_priv->lvds_downclock, 2873 dev_priv->lvds_downclock,
2914 refclk, 2874 refclk,
2915 &reduced_clock); 2875 &reduced_clock);
@@ -2969,6 +2929,33 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2969 2929
2970 /* determine panel color depth */ 2930 /* determine panel color depth */
2971 temp = I915_READ(pipeconf_reg); 2931 temp = I915_READ(pipeconf_reg);
2932 temp &= ~PIPE_BPC_MASK;
2933 if (is_lvds) {
2934 int lvds_reg = I915_READ(PCH_LVDS);
2935 /* the BPC will be 6 if it is 18-bit LVDS panel */
2936 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
2937 temp |= PIPE_8BPC;
2938 else
2939 temp |= PIPE_6BPC;
2940 } else if (is_edp) {
2941 switch (dev_priv->edp_bpp/3) {
2942 case 8:
2943 temp |= PIPE_8BPC;
2944 break;
2945 case 10:
2946 temp |= PIPE_10BPC;
2947 break;
2948 case 6:
2949 temp |= PIPE_6BPC;
2950 break;
2951 case 12:
2952 temp |= PIPE_12BPC;
2953 break;
2954 }
2955 } else
2956 temp |= PIPE_8BPC;
2957 I915_WRITE(pipeconf_reg, temp);
2958 I915_READ(pipeconf_reg);
2972 2959
2973 switch (temp & PIPE_BPC_MASK) { 2960 switch (temp & PIPE_BPC_MASK) {
2974 case PIPE_8BPC: 2961 case PIPE_8BPC:
@@ -3195,7 +3182,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3195 * appropriately here, but we need to look more thoroughly into how 3182 * appropriately here, but we need to look more thoroughly into how
3196 * panels behave in the two modes. 3183 * panels behave in the two modes.
3197 */ 3184 */
3198 3185 /* set the dithering flag */
3186 if (IS_I965G(dev)) {
3187 if (dev_priv->lvds_dither) {
3188 if (IS_IRONLAKE(dev))
3189 pipeconf |= PIPE_ENABLE_DITHER;
3190 else
3191 lvds |= LVDS_ENABLE_DITHER;
3192 } else {
3193 if (IS_IRONLAKE(dev))
3194 pipeconf &= ~PIPE_ENABLE_DITHER;
3195 else
3196 lvds &= ~LVDS_ENABLE_DITHER;
3197 }
3198 }
3199 I915_WRITE(lvds_reg, lvds); 3199 I915_WRITE(lvds_reg, lvds);
3200 I915_READ(lvds_reg); 3200 I915_READ(lvds_reg);
3201 } 3201 }
@@ -3385,7 +3385,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3385 3385
3386 /* we only need to pin inside GTT if cursor is non-phy */ 3386 /* we only need to pin inside GTT if cursor is non-phy */
3387 mutex_lock(&dev->struct_mutex); 3387 mutex_lock(&dev->struct_mutex);
3388 if (!dev_priv->cursor_needs_physical) { 3388 if (!dev_priv->info->cursor_needs_physical) {
3389 ret = i915_gem_object_pin(bo, PAGE_SIZE); 3389 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3390 if (ret) { 3390 if (ret) {
3391 DRM_ERROR("failed to pin cursor bo\n"); 3391 DRM_ERROR("failed to pin cursor bo\n");
@@ -3420,7 +3420,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3420 I915_WRITE(base, addr); 3420 I915_WRITE(base, addr);
3421 3421
3422 if (intel_crtc->cursor_bo) { 3422 if (intel_crtc->cursor_bo) {
3423 if (dev_priv->cursor_needs_physical) { 3423 if (dev_priv->info->cursor_needs_physical) {
3424 if (intel_crtc->cursor_bo != bo) 3424 if (intel_crtc->cursor_bo != bo)
3425 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); 3425 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3426 } else 3426 } else
@@ -3779,125 +3779,6 @@ static void intel_gpu_idle_timer(unsigned long arg)
3779 queue_work(dev_priv->wq, &dev_priv->idle_work); 3779 queue_work(dev_priv->wq, &dev_priv->idle_work);
3780} 3780}
3781 3781
3782void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3783{
3784 drm_i915_private_t *dev_priv = dev->dev_private;
3785
3786 if (IS_IRONLAKE(dev))
3787 return;
3788
3789 if (!dev_priv->render_reclock_avail) {
3790 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3791 return;
3792 }
3793
3794 /* Restore render clock frequency to original value */
3795 if (IS_G4X(dev) || IS_I9XX(dev))
3796 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3797 else if (IS_I85X(dev))
3798 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3799 DRM_DEBUG_DRIVER("increasing render clock frequency\n");
3800
3801 /* Schedule downclock */
3802 if (schedule)
3803 mod_timer(&dev_priv->idle_timer, jiffies +
3804 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3805}
3806
3807void intel_decrease_renderclock(struct drm_device *dev)
3808{
3809 drm_i915_private_t *dev_priv = dev->dev_private;
3810
3811 if (IS_IRONLAKE(dev))
3812 return;
3813
3814 if (!dev_priv->render_reclock_avail) {
3815 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3816 return;
3817 }
3818
3819 if (IS_G4X(dev)) {
3820 u16 gcfgc;
3821
3822 /* Adjust render clock... */
3823 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3824
3825 /* Down to minimum... */
3826 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3827 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3828
3829 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3830 } else if (IS_I965G(dev)) {
3831 u16 gcfgc;
3832
3833 /* Adjust render clock... */
3834 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3835
3836 /* Down to minimum... */
3837 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3838 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3839
3840 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3841 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3842 u16 gcfgc;
3843
3844 /* Adjust render clock... */
3845 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3846
3847 /* Down to minimum... */
3848 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3849 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3850
3851 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3852 } else if (IS_I915G(dev)) {
3853 u16 gcfgc;
3854
3855 /* Adjust render clock... */
3856 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3857
3858 /* Down to minimum... */
3859 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3860 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3861
3862 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3863 } else if (IS_I85X(dev)) {
3864 u16 hpllcc;
3865
3866 /* Adjust render clock... */
3867 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3868
3869 /* Up to maximum... */
3870 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3871 hpllcc |= GC_CLOCK_133_200;
3872
3873 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3874 }
3875 DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
3876}
3877
3878/* Note that no increase function is needed for this - increase_renderclock()
3879 * will also rewrite these bits
3880 */
3881void intel_decrease_displayclock(struct drm_device *dev)
3882{
3883 if (IS_IRONLAKE(dev))
3884 return;
3885
3886 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3887 IS_I915GM(dev)) {
3888 u16 gcfgc;
3889
3890 /* Adjust render clock... */
3891 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3892
3893 /* Down to minimum... */
3894 gcfgc &= ~0xf0;
3895 gcfgc |= 0x80;
3896
3897 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3898 }
3899}
3900
3901#define CRTC_IDLE_TIMEOUT 1000 /* ms */ 3782#define CRTC_IDLE_TIMEOUT 1000 /* ms */
3902 3783
3903static void intel_crtc_idle_timer(unsigned long arg) 3784static void intel_crtc_idle_timer(unsigned long arg)
@@ -4011,12 +3892,6 @@ static void intel_idle_update(struct work_struct *work)
4011 3892
4012 mutex_lock(&dev->struct_mutex); 3893 mutex_lock(&dev->struct_mutex);
4013 3894
4014 /* GPU isn't processing, downclock it. */
4015 if (!dev_priv->busy) {
4016 intel_decrease_renderclock(dev);
4017 intel_decrease_displayclock(dev);
4018 }
4019
4020 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3895 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4021 /* Skip inactive CRTCs */ 3896 /* Skip inactive CRTCs */
4022 if (!crtc->fb) 3897 if (!crtc->fb)
@@ -4050,13 +3925,11 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4050 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 3925 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4051 return; 3926 return;
4052 3927
4053 if (!dev_priv->busy) { 3928 if (!dev_priv->busy)
4054 dev_priv->busy = true; 3929 dev_priv->busy = true;
4055 intel_increase_renderclock(dev, true); 3930 else
4056 } else {
4057 mod_timer(&dev_priv->idle_timer, jiffies + 3931 mod_timer(&dev_priv->idle_timer, jiffies +
4058 msecs_to_jiffies(GPU_IDLE_TIMEOUT)); 3932 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4059 }
4060 3933
4061 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3934 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4062 if (!crtc->fb) 3935 if (!crtc->fb)
@@ -4124,6 +3997,12 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe)
4124 spin_lock_irqsave(&dev->event_lock, flags); 3997 spin_lock_irqsave(&dev->event_lock, flags);
4125 work = intel_crtc->unpin_work; 3998 work = intel_crtc->unpin_work;
4126 if (work == NULL || !work->pending) { 3999 if (work == NULL || !work->pending) {
4000 if (work && !work->pending) {
4001 obj_priv = work->obj->driver_private;
4002 DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4003 obj_priv,
4004 atomic_read(&obj_priv->pending_flip));
4005 }
4127 spin_unlock_irqrestore(&dev->event_lock, flags); 4006 spin_unlock_irqrestore(&dev->event_lock, flags);
4128 return; 4007 return;
4129 } 4008 }
@@ -4145,7 +4024,10 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe)
4145 spin_unlock_irqrestore(&dev->event_lock, flags); 4024 spin_unlock_irqrestore(&dev->event_lock, flags);
4146 4025
4147 obj_priv = work->obj->driver_private; 4026 obj_priv = work->obj->driver_private;
4148 if (atomic_dec_and_test(&obj_priv->pending_flip)) 4027
4028 /* Initial scanout buffer will have a 0 pending flip count */
4029 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4030 atomic_dec_and_test(&obj_priv->pending_flip))
4149 DRM_WAKEUP(&dev_priv->pending_flip_queue); 4031 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4150 schedule_work(&work->work); 4032 schedule_work(&work->work);
4151} 4033}
@@ -4158,8 +4040,11 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
4158 unsigned long flags; 4040 unsigned long flags;
4159 4041
4160 spin_lock_irqsave(&dev->event_lock, flags); 4042 spin_lock_irqsave(&dev->event_lock, flags);
4161 if (intel_crtc->unpin_work) 4043 if (intel_crtc->unpin_work) {
4162 intel_crtc->unpin_work->pending = 1; 4044 intel_crtc->unpin_work->pending = 1;
4045 } else {
4046 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4047 }
4163 spin_unlock_irqrestore(&dev->event_lock, flags); 4048 spin_unlock_irqrestore(&dev->event_lock, flags);
4164} 4049}
4165 4050
@@ -4193,6 +4078,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
4193 /* We borrow the event spin lock for protecting unpin_work */ 4078 /* We borrow the event spin lock for protecting unpin_work */
4194 spin_lock_irqsave(&dev->event_lock, flags); 4079 spin_lock_irqsave(&dev->event_lock, flags);
4195 if (intel_crtc->unpin_work) { 4080 if (intel_crtc->unpin_work) {
4081 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4196 spin_unlock_irqrestore(&dev->event_lock, flags); 4082 spin_unlock_irqrestore(&dev->event_lock, flags);
4197 kfree(work); 4083 kfree(work);
4198 mutex_unlock(&dev->struct_mutex); 4084 mutex_unlock(&dev->struct_mutex);
@@ -4206,7 +4092,10 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
4206 4092
4207 ret = intel_pin_and_fence_fb_obj(dev, obj); 4093 ret = intel_pin_and_fence_fb_obj(dev, obj);
4208 if (ret != 0) { 4094 if (ret != 0) {
4095 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4096 obj->driver_private);
4209 kfree(work); 4097 kfree(work);
4098 intel_crtc->unpin_work = NULL;
4210 mutex_unlock(&dev->struct_mutex); 4099 mutex_unlock(&dev->struct_mutex);
4211 return ret; 4100 return ret;
4212 } 4101 }
@@ -4400,29 +4289,43 @@ static void intel_setup_outputs(struct drm_device *dev)
4400 bool found = false; 4289 bool found = false;
4401 4290
4402 if (I915_READ(SDVOB) & SDVO_DETECTED) { 4291 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4292 DRM_DEBUG_KMS("probing SDVOB\n");
4403 found = intel_sdvo_init(dev, SDVOB); 4293 found = intel_sdvo_init(dev, SDVOB);
4404 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) 4294 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4295 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4405 intel_hdmi_init(dev, SDVOB); 4296 intel_hdmi_init(dev, SDVOB);
4297 }
4406 4298
4407 if (!found && SUPPORTS_INTEGRATED_DP(dev)) 4299 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4300 DRM_DEBUG_KMS("probing DP_B\n");
4408 intel_dp_init(dev, DP_B); 4301 intel_dp_init(dev, DP_B);
4302 }
4409 } 4303 }
4410 4304
4411 /* Before G4X SDVOC doesn't have its own detect register */ 4305 /* Before G4X SDVOC doesn't have its own detect register */
4412 4306
4413 if (I915_READ(SDVOB) & SDVO_DETECTED) 4307 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4308 DRM_DEBUG_KMS("probing SDVOC\n");
4414 found = intel_sdvo_init(dev, SDVOC); 4309 found = intel_sdvo_init(dev, SDVOC);
4310 }
4415 4311
4416 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { 4312 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4417 4313
4418 if (SUPPORTS_INTEGRATED_HDMI(dev)) 4314 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4315 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4419 intel_hdmi_init(dev, SDVOC); 4316 intel_hdmi_init(dev, SDVOC);
4420 if (SUPPORTS_INTEGRATED_DP(dev)) 4317 }
4318 if (SUPPORTS_INTEGRATED_DP(dev)) {
4319 DRM_DEBUG_KMS("probing DP_C\n");
4421 intel_dp_init(dev, DP_C); 4320 intel_dp_init(dev, DP_C);
4321 }
4422 } 4322 }
4423 4323
4424 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED)) 4324 if (SUPPORTS_INTEGRATED_DP(dev) &&
4325 (I915_READ(DP_D) & DP_DETECTED)) {
4326 DRM_DEBUG_KMS("probing DP_D\n");
4425 intel_dp_init(dev, DP_D); 4327 intel_dp_init(dev, DP_D);
4328 }
4426 } else if (IS_I8XX(dev)) 4329 } else if (IS_I8XX(dev))
4427 intel_dvo_init(dev); 4330 intel_dvo_init(dev);
4428 4331
@@ -4527,6 +4430,42 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
4527 .fb_changed = intelfb_probe, 4430 .fb_changed = intelfb_probe,
4528}; 4431};
4529 4432
4433static struct drm_gem_object *
4434intel_alloc_power_context(struct drm_device *dev)
4435{
4436 struct drm_gem_object *pwrctx;
4437 int ret;
4438
4439 pwrctx = drm_gem_object_alloc(dev, 4096);
4440 if (!pwrctx) {
4441 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4442 return NULL;
4443 }
4444
4445 mutex_lock(&dev->struct_mutex);
4446 ret = i915_gem_object_pin(pwrctx, 4096);
4447 if (ret) {
4448 DRM_ERROR("failed to pin power context: %d\n", ret);
4449 goto err_unref;
4450 }
4451
4452 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4453 if (ret) {
4454 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4455 goto err_unpin;
4456 }
4457 mutex_unlock(&dev->struct_mutex);
4458
4459 return pwrctx;
4460
4461err_unpin:
4462 i915_gem_object_unpin(pwrctx);
4463err_unref:
4464 drm_gem_object_unreference(pwrctx);
4465 mutex_unlock(&dev->struct_mutex);
4466 return NULL;
4467}
4468
4530void intel_init_clock_gating(struct drm_device *dev) 4469void intel_init_clock_gating(struct drm_device *dev)
4531{ 4470{
4532 struct drm_i915_private *dev_priv = dev->dev_private; 4471 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4579,42 +4518,27 @@ void intel_init_clock_gating(struct drm_device *dev)
4579 * GPU can automatically power down the render unit if given a page 4518 * GPU can automatically power down the render unit if given a page
4580 * to save state. 4519 * to save state.
4581 */ 4520 */
4582 if (I915_HAS_RC6(dev)) { 4521 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4583 struct drm_gem_object *pwrctx; 4522 struct drm_i915_gem_object *obj_priv = NULL;
4584 struct drm_i915_gem_object *obj_priv;
4585 int ret;
4586 4523
4587 if (dev_priv->pwrctx) { 4524 if (dev_priv->pwrctx) {
4588 obj_priv = dev_priv->pwrctx->driver_private; 4525 obj_priv = dev_priv->pwrctx->driver_private;
4589 } else { 4526 } else {
4590 pwrctx = drm_gem_object_alloc(dev, 4096); 4527 struct drm_gem_object *pwrctx;
4591 if (!pwrctx) {
4592 DRM_DEBUG("failed to alloc power context, "
4593 "RC6 disabled\n");
4594 goto out;
4595 }
4596 4528
4597 ret = i915_gem_object_pin(pwrctx, 4096); 4529 pwrctx = intel_alloc_power_context(dev);
4598 if (ret) { 4530 if (pwrctx) {
4599 DRM_ERROR("failed to pin power context: %d\n", 4531 dev_priv->pwrctx = pwrctx;
4600 ret); 4532 obj_priv = pwrctx->driver_private;
4601 drm_gem_object_unreference(pwrctx);
4602 goto out;
4603 } 4533 }
4604
4605 i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4606
4607 dev_priv->pwrctx = pwrctx;
4608 obj_priv = pwrctx->driver_private;
4609 } 4534 }
4610 4535
4611 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); 4536 if (obj_priv) {
4612 I915_WRITE(MCHBAR_RENDER_STANDBY, 4537 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4613 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); 4538 I915_WRITE(MCHBAR_RENDER_STANDBY,
4539 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4540 }
4614 } 4541 }
4615
4616out:
4617 return;
4618} 4542}
4619 4543
4620/* Set up chip specific display functions */ 4544/* Set up chip specific display functions */
@@ -4770,7 +4694,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
4770 del_timer_sync(&intel_crtc->idle_timer); 4694 del_timer_sync(&intel_crtc->idle_timer);
4771 } 4695 }
4772 4696
4773 intel_increase_renderclock(dev, false);
4774 del_timer_sync(&dev_priv->idle_timer); 4697 del_timer_sync(&dev_priv->idle_timer);
4775 4698
4776 if (dev_priv->display.disable_fbc) 4699 if (dev_priv->display.disable_fbc)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4e7aa8b7b938..439506cefc14 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -125,9 +125,15 @@ intel_dp_link_clock(uint8_t link_bw)
125 125
126/* I think this is a fiction */ 126/* I think this is a fiction */
127static int 127static int
128intel_dp_link_required(int pixel_clock) 128intel_dp_link_required(struct drm_device *dev,
129 struct intel_output *intel_output, int pixel_clock)
129{ 130{
130 return pixel_clock * 3; 131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 if (IS_eDP(intel_output))
134 return (pixel_clock * dev_priv->edp_bpp) / 8;
135 else
136 return pixel_clock * 3;
131} 137}
132 138
133static int 139static int
@@ -138,7 +144,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
138 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output)); 144 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
139 int max_lanes = intel_dp_max_lane_count(intel_output); 145 int max_lanes = intel_dp_max_lane_count(intel_output);
140 146
141 if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes) 147 if (intel_dp_link_required(connector->dev, intel_output, mode->clock)
148 > max_link_clock * max_lanes)
142 return MODE_CLOCK_HIGH; 149 return MODE_CLOCK_HIGH;
143 150
144 if (mode->clock < 10000) 151 if (mode->clock < 10000)
@@ -492,7 +499,8 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
492 for (clock = 0; clock <= max_clock; clock++) { 499 for (clock = 0; clock <= max_clock; clock++) {
493 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count; 500 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
494 501
495 if (intel_dp_link_required(mode->clock) <= link_avail) { 502 if (intel_dp_link_required(encoder->dev, intel_output, mode->clock)
503 <= link_avail) {
496 dp_priv->link_bw = bws[clock]; 504 dp_priv->link_bw = bws[clock];
497 dp_priv->lane_count = lane_count; 505 dp_priv->lane_count = lane_count;
498 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw); 506 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
@@ -1289,53 +1297,7 @@ intel_dp_hot_plug(struct intel_output *intel_output)
1289 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON) 1297 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1290 intel_dp_check_link_status(intel_output); 1298 intel_dp_check_link_status(intel_output);
1291} 1299}
1292/* 1300
1293 * Enumerate the child dev array parsed from VBT to check whether
1294 * the given DP is present.
1295 * If it is present, return 1.
1296 * If it is not present, return false.
1297 * If no child dev is parsed from VBT, it is assumed that the given
1298 * DP is present.
1299 */
1300static int dp_is_present_in_vbt(struct drm_device *dev, int dp_reg)
1301{
1302 struct drm_i915_private *dev_priv = dev->dev_private;
1303 struct child_device_config *p_child;
1304 int i, dp_port, ret;
1305
1306 if (!dev_priv->child_dev_num)
1307 return 1;
1308
1309 dp_port = 0;
1310 if (dp_reg == DP_B || dp_reg == PCH_DP_B)
1311 dp_port = PORT_IDPB;
1312 else if (dp_reg == DP_C || dp_reg == PCH_DP_C)
1313 dp_port = PORT_IDPC;
1314 else if (dp_reg == DP_D || dp_reg == PCH_DP_D)
1315 dp_port = PORT_IDPD;
1316
1317 ret = 0;
1318 for (i = 0; i < dev_priv->child_dev_num; i++) {
1319 p_child = dev_priv->child_dev + i;
1320 /*
1321 * If the device type is not DP, continue.
1322 */
1323 if (p_child->device_type != DEVICE_TYPE_DP &&
1324 p_child->device_type != DEVICE_TYPE_eDP)
1325 continue;
1326 /* Find the eDP port */
1327 if (dp_reg == DP_A && p_child->device_type == DEVICE_TYPE_eDP) {
1328 ret = 1;
1329 break;
1330 }
1331 /* Find the DP port */
1332 if (p_child->dvo_port == dp_port) {
1333 ret = 1;
1334 break;
1335 }
1336 }
1337 return ret;
1338}
1339void 1301void
1340intel_dp_init(struct drm_device *dev, int output_reg) 1302intel_dp_init(struct drm_device *dev, int output_reg)
1341{ 1303{
@@ -1345,10 +1307,6 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1345 struct intel_dp_priv *dp_priv; 1307 struct intel_dp_priv *dp_priv;
1346 const char *name = NULL; 1308 const char *name = NULL;
1347 1309
1348 if (!dp_is_present_in_vbt(dev, output_reg)) {
1349 DRM_DEBUG_KMS("DP is not present. Ignore it\n");
1350 return;
1351 }
1352 intel_output = kcalloc(sizeof(struct intel_output) + 1310 intel_output = kcalloc(sizeof(struct intel_output) +
1353 sizeof(struct intel_dp_priv), 1, GFP_KERNEL); 1311 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1354 if (!intel_output) 1312 if (!intel_output)
@@ -1373,11 +1331,10 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1373 else if (output_reg == DP_D || output_reg == PCH_DP_D) 1331 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1374 intel_output->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 1332 intel_output->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1375 1333
1376 if (IS_eDP(intel_output)) { 1334 if (IS_eDP(intel_output))
1377 intel_output->crtc_mask = (1 << 1);
1378 intel_output->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 1335 intel_output->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1379 } else 1336
1380 intel_output->crtc_mask = (1 << 0) | (1 << 1); 1337 intel_output->crtc_mask = (1 << 0) | (1 << 1);
1381 connector->interlace_allowed = true; 1338 connector->interlace_allowed = true;
1382 connector->doublescan_allowed = 0; 1339 connector->doublescan_allowed = 0;
1383 1340
@@ -1402,14 +1359,20 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1402 break; 1359 break;
1403 case DP_B: 1360 case DP_B:
1404 case PCH_DP_B: 1361 case PCH_DP_B:
1362 dev_priv->hotplug_supported_mask |=
1363 HDMIB_HOTPLUG_INT_STATUS;
1405 name = "DPDDC-B"; 1364 name = "DPDDC-B";
1406 break; 1365 break;
1407 case DP_C: 1366 case DP_C:
1408 case PCH_DP_C: 1367 case PCH_DP_C:
1368 dev_priv->hotplug_supported_mask |=
1369 HDMIC_HOTPLUG_INT_STATUS;
1409 name = "DPDDC-C"; 1370 name = "DPDDC-C";
1410 break; 1371 break;
1411 case DP_D: 1372 case DP_D:
1412 case PCH_DP_D: 1373 case PCH_DP_D:
1374 dev_priv->hotplug_supported_mask |=
1375 HDMID_HOTPLUG_INT_STATUS;
1413 name = "DPDDC-D"; 1376 name = "DPDDC-D";
1414 break; 1377 break;
1415 } 1378 }
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index d4823cc87895..371d753e362b 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -70,7 +70,7 @@ static struct drm_fb_helper_funcs intel_fb_helper_funcs = {
70 70
71 71
72/** 72/**
73 * Curretly it is assumed that the old framebuffer is reused. 73 * Currently it is assumed that the old framebuffer is reused.
74 * 74 *
75 * LOCKING 75 * LOCKING
76 * caller should hold the mode config lock. 76 * caller should hold the mode config lock.
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f04dbbe7d400..0e268deed761 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -225,52 +225,6 @@ static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
225 .destroy = intel_hdmi_enc_destroy, 225 .destroy = intel_hdmi_enc_destroy,
226}; 226};
227 227
228/*
229 * Enumerate the child dev array parsed from VBT to check whether
230 * the given HDMI is present.
231 * If it is present, return 1.
232 * If it is not present, return false.
233 * If no child dev is parsed from VBT, it assumes that the given
234 * HDMI is present.
235 */
236static int hdmi_is_present_in_vbt(struct drm_device *dev, int hdmi_reg)
237{
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 struct child_device_config *p_child;
240 int i, hdmi_port, ret;
241
242 if (!dev_priv->child_dev_num)
243 return 1;
244
245 if (hdmi_reg == SDVOB)
246 hdmi_port = DVO_B;
247 else if (hdmi_reg == SDVOC)
248 hdmi_port = DVO_C;
249 else if (hdmi_reg == HDMIB)
250 hdmi_port = DVO_B;
251 else if (hdmi_reg == HDMIC)
252 hdmi_port = DVO_C;
253 else if (hdmi_reg == HDMID)
254 hdmi_port = DVO_D;
255 else
256 return 0;
257
258 ret = 0;
259 for (i = 0; i < dev_priv->child_dev_num; i++) {
260 p_child = dev_priv->child_dev + i;
261 /*
262 * If the device type is not HDMI, continue.
263 */
264 if (p_child->device_type != DEVICE_TYPE_HDMI)
265 continue;
266 /* Find the HDMI port */
267 if (p_child->dvo_port == hdmi_port) {
268 ret = 1;
269 break;
270 }
271 }
272 return ret;
273}
274void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) 228void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
275{ 229{
276 struct drm_i915_private *dev_priv = dev->dev_private; 230 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -278,10 +232,6 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
278 struct intel_output *intel_output; 232 struct intel_output *intel_output;
279 struct intel_hdmi_priv *hdmi_priv; 233 struct intel_hdmi_priv *hdmi_priv;
280 234
281 if (!hdmi_is_present_in_vbt(dev, sdvox_reg)) {
282 DRM_DEBUG_KMS("HDMI is not present. Ignored it \n");
283 return;
284 }
285 intel_output = kcalloc(sizeof(struct intel_output) + 235 intel_output = kcalloc(sizeof(struct intel_output) +
286 sizeof(struct intel_hdmi_priv), 1, GFP_KERNEL); 236 sizeof(struct intel_hdmi_priv), 1, GFP_KERNEL);
287 if (!intel_output) 237 if (!intel_output)
@@ -303,21 +253,26 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
303 if (sdvox_reg == SDVOB) { 253 if (sdvox_reg == SDVOB) {
304 intel_output->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); 254 intel_output->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
305 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "HDMIB"); 255 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "HDMIB");
256 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
306 } else if (sdvox_reg == SDVOC) { 257 } else if (sdvox_reg == SDVOC) {
307 intel_output->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); 258 intel_output->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
308 intel_output->ddc_bus = intel_i2c_create(dev, GPIOD, "HDMIC"); 259 intel_output->ddc_bus = intel_i2c_create(dev, GPIOD, "HDMIC");
260 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
309 } else if (sdvox_reg == HDMIB) { 261 } else if (sdvox_reg == HDMIB) {
310 intel_output->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); 262 intel_output->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
311 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOE, 263 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOE,
312 "HDMIB"); 264 "HDMIB");
265 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
313 } else if (sdvox_reg == HDMIC) { 266 } else if (sdvox_reg == HDMIC) {
314 intel_output->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); 267 intel_output->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
315 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOD, 268 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOD,
316 "HDMIC"); 269 "HDMIC");
270 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
317 } else if (sdvox_reg == HDMID) { 271 } else if (sdvox_reg == HDMID) {
318 intel_output->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); 272 intel_output->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
319 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOF, 273 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOF,
320 "HDMID"); 274 "HDMID");
275 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
321 } 276 }
322 if (!intel_output->ddc_bus) 277 if (!intel_output->ddc_bus)
323 goto err_connector; 278 goto err_connector;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index b04d1e63d439..b1d0acbae4e4 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -602,12 +602,40 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
602/* Some lid devices report incorrect lid status, assume they're connected */ 602/* Some lid devices report incorrect lid status, assume they're connected */
603static const struct dmi_system_id bad_lid_status[] = { 603static const struct dmi_system_id bad_lid_status[] = {
604 { 604 {
605 .ident = "Compaq nx9020",
606 .matches = {
607 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
608 DMI_MATCH(DMI_BOARD_NAME, "3084"),
609 },
610 },
611 {
612 .ident = "Samsung SX20S",
613 .matches = {
614 DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
615 DMI_MATCH(DMI_BOARD_NAME, "SX20S"),
616 },
617 },
618 {
605 .ident = "Aspire One", 619 .ident = "Aspire One",
606 .matches = { 620 .matches = {
607 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 621 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
608 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire one"), 622 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire one"),
609 }, 623 },
610 }, 624 },
625 {
626 .ident = "Aspire 1810T",
627 .matches = {
628 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
629 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 1810T"),
630 },
631 },
632 {
633 .ident = "PC-81005",
634 .matches = {
635 DMI_MATCH(DMI_SYS_VENDOR, "MALATA"),
636 DMI_MATCH(DMI_PRODUCT_NAME, "PC-81005"),
637 },
638 },
611 { } 639 { }
612}; 640};
613 641
@@ -622,7 +650,7 @@ static enum drm_connector_status intel_lvds_detect(struct drm_connector *connect
622{ 650{
623 enum drm_connector_status status = connector_status_connected; 651 enum drm_connector_status status = connector_status_connected;
624 652
625 if (!acpi_lid_open() && !dmi_check_system(bad_lid_status)) 653 if (!dmi_check_system(bad_lid_status) && !acpi_lid_open())
626 status = connector_status_disconnected; 654 status = connector_status_disconnected;
627 655
628 return status; 656 return status;
@@ -679,7 +707,14 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
679 struct drm_i915_private *dev_priv = 707 struct drm_i915_private *dev_priv =
680 container_of(nb, struct drm_i915_private, lid_notifier); 708 container_of(nb, struct drm_i915_private, lid_notifier);
681 struct drm_device *dev = dev_priv->dev; 709 struct drm_device *dev = dev_priv->dev;
710 struct drm_connector *connector = dev_priv->int_lvds_connector;
682 711
712 /*
713 * check and update the status of LVDS connector after receiving
714 * the LID nofication event.
715 */
716 if (connector)
717 connector->status = connector->funcs->detect(connector);
683 if (!acpi_lid_open()) { 718 if (!acpi_lid_open()) {
684 dev_priv->modeset_on_lid = 1; 719 dev_priv->modeset_on_lid = 1;
685 return NOTIFY_OK; 720 return NOTIFY_OK;
@@ -854,65 +889,6 @@ static const struct dmi_system_id intel_no_lvds[] = {
854 { } /* terminating entry */ 889 { } /* terminating entry */
855}; 890};
856 891
857#ifdef CONFIG_ACPI
858/*
859 * check_lid_device -- check whether @handle is an ACPI LID device.
860 * @handle: ACPI device handle
861 * @level : depth in the ACPI namespace tree
862 * @context: the number of LID device when we find the device
863 * @rv: a return value to fill if desired (Not use)
864 */
865static acpi_status
866check_lid_device(acpi_handle handle, u32 level, void *context,
867 void **return_value)
868{
869 struct acpi_device *acpi_dev;
870 int *lid_present = context;
871
872 acpi_dev = NULL;
873 /* Get the acpi device for device handle */
874 if (acpi_bus_get_device(handle, &acpi_dev) || !acpi_dev) {
875 /* If there is no ACPI device for handle, return */
876 return AE_OK;
877 }
878
879 if (!strncmp(acpi_device_hid(acpi_dev), "PNP0C0D", 7))
880 *lid_present = 1;
881
882 return AE_OK;
883}
884
885/**
886 * check whether there exists the ACPI LID device by enumerating the ACPI
887 * device tree.
888 */
889static int intel_lid_present(void)
890{
891 int lid_present = 0;
892
893 if (acpi_disabled) {
894 /* If ACPI is disabled, there is no ACPI device tree to
895 * check, so assume the LID device would have been present.
896 */
897 return 1;
898 }
899
900 acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
901 ACPI_UINT32_MAX,
902 check_lid_device, &lid_present, NULL);
903
904 return lid_present;
905}
906#else
907static int intel_lid_present(void)
908{
909 /* In the absence of ACPI built in, assume that the LID device would
910 * have been present.
911 */
912 return 1;
913}
914#endif
915
916/** 892/**
917 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID 893 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
918 * @dev: drm device 894 * @dev: drm device
@@ -957,7 +933,8 @@ static void intel_find_lvds_downclock(struct drm_device *dev,
957 } 933 }
958 } 934 }
959 mutex_unlock(&dev->mode_config.mutex); 935 mutex_unlock(&dev->mode_config.mutex);
960 if (temp_downclock < panel_fixed_mode->clock) { 936 if (temp_downclock < panel_fixed_mode->clock &&
937 i915_lvds_downclock) {
961 /* We found the downclock for LVDS. */ 938 /* We found the downclock for LVDS. */
962 dev_priv->lvds_downclock_avail = 1; 939 dev_priv->lvds_downclock_avail = 1;
963 dev_priv->lvds_downclock = temp_downclock; 940 dev_priv->lvds_downclock = temp_downclock;
@@ -1031,12 +1008,8 @@ void intel_lvds_init(struct drm_device *dev)
1031 if (dmi_check_system(intel_no_lvds)) 1008 if (dmi_check_system(intel_no_lvds))
1032 return; 1009 return;
1033 1010
1034 /* 1011 if (!lvds_is_present_in_vbt(dev)) {
1035 * Assume LVDS is present if there's an ACPI lid device or if the 1012 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
1036 * device is present in the VBT.
1037 */
1038 if (!lvds_is_present_in_vbt(dev) && !intel_lid_present()) {
1039 DRM_DEBUG_KMS("LVDS is not present in VBT and no lid detected\n");
1040 return; 1013 return;
1041 } 1014 }
1042 1015
@@ -1180,6 +1153,8 @@ out:
1180 DRM_DEBUG_KMS("lid notifier registration failed\n"); 1153 DRM_DEBUG_KMS("lid notifier registration failed\n");
1181 dev_priv->lid_notifier.notifier_call = NULL; 1154 dev_priv->lid_notifier.notifier_call = NULL;
1182 } 1155 }
1156 /* keep the LVDS connector */
1157 dev_priv->int_lvds_connector = connector;
1183 drm_sysfs_connector_add(connector); 1158 drm_sysfs_connector_add(connector);
1184 return; 1159 return;
1185 1160
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index dba5147f4064..82678d30ab06 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -462,14 +462,63 @@ static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
462} 462}
463 463
464/** 464/**
465 * Don't check status code from this as it switches the bus back to the 465 * Try to read the response after issuie the DDC switch command. But it
466 * SDVO chips which defeats the purpose of doing a bus switch in the first 466 * is noted that we must do the action of reading response and issuing DDC
467 * place. 467 * switch command in one I2C transaction. Otherwise when we try to start
468 * another I2C transaction after issuing the DDC bus switch, it will be
469 * switched to the internal SDVO register.
468 */ 470 */
469static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output, 471static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
470 u8 target) 472 u8 target)
471{ 473{
472 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1); 474 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
475 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
476 struct i2c_msg msgs[] = {
477 {
478 .addr = sdvo_priv->slave_addr >> 1,
479 .flags = 0,
480 .len = 2,
481 .buf = out_buf,
482 },
483 /* the following two are to read the response */
484 {
485 .addr = sdvo_priv->slave_addr >> 1,
486 .flags = 0,
487 .len = 1,
488 .buf = cmd_buf,
489 },
490 {
491 .addr = sdvo_priv->slave_addr >> 1,
492 .flags = I2C_M_RD,
493 .len = 1,
494 .buf = ret_value,
495 },
496 };
497
498 intel_sdvo_debug_write(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
499 &target, 1);
500 /* write the DDC switch command argument */
501 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0, target);
502
503 out_buf[0] = SDVO_I2C_OPCODE;
504 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
505 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
506 cmd_buf[1] = 0;
507 ret_value[0] = 0;
508 ret_value[1] = 0;
509
510 ret = i2c_transfer(intel_output->i2c_bus, msgs, 3);
511 if (ret != 3) {
512 /* failure in I2C transfer */
513 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
514 return;
515 }
516 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
517 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
518 ret_value[0]);
519 return;
520 }
521 return;
473} 522}
474 523
475static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1) 524static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
@@ -1579,6 +1628,32 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1579 edid = drm_get_edid(&intel_output->base, 1628 edid = drm_get_edid(&intel_output->base,
1580 intel_output->ddc_bus); 1629 intel_output->ddc_bus);
1581 1630
1631 /* This is only applied to SDVO cards with multiple outputs */
1632 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_output)) {
1633 uint8_t saved_ddc, temp_ddc;
1634 saved_ddc = sdvo_priv->ddc_bus;
1635 temp_ddc = sdvo_priv->ddc_bus >> 1;
1636 /*
1637 * Don't use the 1 as the argument of DDC bus switch to get
1638 * the EDID. It is used for SDVO SPD ROM.
1639 */
1640 while(temp_ddc > 1) {
1641 sdvo_priv->ddc_bus = temp_ddc;
1642 edid = drm_get_edid(&intel_output->base,
1643 intel_output->ddc_bus);
1644 if (edid) {
1645 /*
1646 * When we can get the EDID, maybe it is the
1647 * correct DDC bus. Update it.
1648 */
1649 sdvo_priv->ddc_bus = temp_ddc;
1650 break;
1651 }
1652 temp_ddc >>= 1;
1653 }
1654 if (edid == NULL)
1655 sdvo_priv->ddc_bus = saved_ddc;
1656 }
1582 /* when there is no edid and no monitor is connected with VGA 1657 /* when there is no edid and no monitor is connected with VGA
1583 * port, try to use the CRT ddc to read the EDID for DVI-connector 1658 * port, try to use the CRT ddc to read the EDID for DVI-connector
1584 */ 1659 */
@@ -2270,6 +2345,14 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2270 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2345 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2271 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2346 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2272 (1 << INTEL_ANALOG_CLONE_BIT); 2347 (1 << INTEL_ANALOG_CLONE_BIT);
2348 } else if (flags & SDVO_OUTPUT_CVBS0) {
2349
2350 sdvo_priv->controlled_output = SDVO_OUTPUT_CVBS0;
2351 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2352 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2353 sdvo_priv->is_tv = true;
2354 intel_output->needs_tv_clock = true;
2355 intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2273 } else if (flags & SDVO_OUTPUT_LVDS0) { 2356 } else if (flags & SDVO_OUTPUT_LVDS0) {
2274 2357
2275 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0; 2358 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
@@ -2662,6 +2745,7 @@ static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2662 2745
2663bool intel_sdvo_init(struct drm_device *dev, int output_device) 2746bool intel_sdvo_init(struct drm_device *dev, int output_device)
2664{ 2747{
2748 struct drm_i915_private *dev_priv = dev->dev_private;
2665 struct drm_connector *connector; 2749 struct drm_connector *connector;
2666 struct intel_output *intel_output; 2750 struct intel_output *intel_output;
2667 struct intel_sdvo_priv *sdvo_priv; 2751 struct intel_sdvo_priv *sdvo_priv;
@@ -2708,10 +2792,12 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
2708 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS"); 2792 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
2709 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, 2793 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2710 "SDVOB/VGA DDC BUS"); 2794 "SDVOB/VGA DDC BUS");
2795 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
2711 } else { 2796 } else {
2712 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS"); 2797 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
2713 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, 2798 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2714 "SDVOC/VGA DDC BUS"); 2799 "SDVOC/VGA DDC BUS");
2800 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
2715 } 2801 }
2716 2802
2717 if (intel_output->ddc_bus == NULL) 2803 if (intel_output->ddc_bus == NULL)
@@ -2720,7 +2806,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
2720 /* Wrap with our custom algo which switches to DDC mode */ 2806 /* Wrap with our custom algo which switches to DDC mode */
2721 intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo; 2807 intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
2722 2808
2723 /* In defaut case sdvo lvds is false */ 2809 /* In default case sdvo lvds is false */
2724 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps); 2810 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
2725 2811
2726 if (intel_sdvo_output_setup(intel_output, 2812 if (intel_sdvo_output_setup(intel_output,
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index b5f5fe75e6af..1cc7b937b1ea 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -24,6 +24,9 @@ $(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable
24$(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable 24$(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable
25 $(call if_changed,mkregtable) 25 $(call if_changed,mkregtable)
26 26
27$(obj)/r420_reg_safe.h: $(src)/reg_srcs/r420 $(obj)/mkregtable
28 $(call if_changed,mkregtable)
29
27$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable 30$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable
28 $(call if_changed,mkregtable) 31 $(call if_changed,mkregtable)
29 32
@@ -35,6 +38,8 @@ $(obj)/rv515.o: $(obj)/rv515_reg_safe.h
35 38
36$(obj)/r300.o: $(obj)/r300_reg_safe.h 39$(obj)/r300.o: $(obj)/r300_reg_safe.h
37 40
41$(obj)/r420.o: $(obj)/r420_reg_safe.h
42
38$(obj)/rs600.o: $(obj)/rs600_reg_safe.h 43$(obj)/rs600.o: $(obj)/rs600_reg_safe.h
39 44
40radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \ 45radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 388140a7e651..e3b44562d265 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -246,6 +246,9 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
246 case ATOM_WS_ATTRIBUTES: 246 case ATOM_WS_ATTRIBUTES:
247 val = gctx->io_attr; 247 val = gctx->io_attr;
248 break; 248 break;
249 case ATOM_WS_REGPTR:
250 val = gctx->reg_block;
251 break;
249 default: 252 default:
250 val = ctx->ws[idx]; 253 val = ctx->ws[idx];
251 } 254 }
@@ -385,6 +388,32 @@ static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
385 return atom_get_src_int(ctx, attr, ptr, NULL, 1); 388 return atom_get_src_int(ctx, attr, ptr, NULL, 1);
386} 389}
387 390
391static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
392{
393 uint32_t val = 0xCDCDCDCD;
394
395 switch (align) {
396 case ATOM_SRC_DWORD:
397 val = U32(*ptr);
398 (*ptr) += 4;
399 break;
400 case ATOM_SRC_WORD0:
401 case ATOM_SRC_WORD8:
402 case ATOM_SRC_WORD16:
403 val = U16(*ptr);
404 (*ptr) += 2;
405 break;
406 case ATOM_SRC_BYTE0:
407 case ATOM_SRC_BYTE8:
408 case ATOM_SRC_BYTE16:
409 case ATOM_SRC_BYTE24:
410 val = U8(*ptr);
411 (*ptr)++;
412 break;
413 }
414 return val;
415}
416
388static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, 417static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
389 int *ptr, uint32_t *saved, int print) 418 int *ptr, uint32_t *saved, int print)
390{ 419{
@@ -482,6 +511,9 @@ static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
482 case ATOM_WS_ATTRIBUTES: 511 case ATOM_WS_ATTRIBUTES:
483 gctx->io_attr = val; 512 gctx->io_attr = val;
484 break; 513 break;
514 case ATOM_WS_REGPTR:
515 gctx->reg_block = val;
516 break;
485 default: 517 default:
486 ctx->ws[idx] = val; 518 ctx->ws[idx] = val;
487 } 519 }
@@ -677,7 +709,7 @@ static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
677 SDEBUG(" dst: "); 709 SDEBUG(" dst: ");
678 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 710 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
679 SDEBUG(" src1: "); 711 SDEBUG(" src1: ");
680 src1 = atom_get_src(ctx, attr, ptr); 712 src1 = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
681 SDEBUG(" src2: "); 713 SDEBUG(" src2: ");
682 src2 = atom_get_src(ctx, attr, ptr); 714 src2 = atom_get_src(ctx, attr, ptr);
683 dst &= src1; 715 dst &= src1;
@@ -809,6 +841,38 @@ static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
809 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); 841 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block);
810} 842}
811 843
844static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
845{
846 uint8_t attr = U8((*ptr)++), shift;
847 uint32_t saved, dst;
848 int dptr = *ptr;
849 attr &= 0x38;
850 attr |= atom_def_dst[attr >> 3] << 6;
851 SDEBUG(" dst: ");
852 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
853 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
854 SDEBUG(" shift: %d\n", shift);
855 dst <<= shift;
856 SDEBUG(" dst: ");
857 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
858}
859
860static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
861{
862 uint8_t attr = U8((*ptr)++), shift;
863 uint32_t saved, dst;
864 int dptr = *ptr;
865 attr &= 0x38;
866 attr |= atom_def_dst[attr >> 3] << 6;
867 SDEBUG(" dst: ");
868 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
869 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
870 SDEBUG(" shift: %d\n", shift);
871 dst >>= shift;
872 SDEBUG(" dst: ");
873 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
874}
875
812static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg) 876static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
813{ 877{
814 uint8_t attr = U8((*ptr)++), shift; 878 uint8_t attr = U8((*ptr)++), shift;
@@ -818,7 +882,7 @@ static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
818 attr |= atom_def_dst[attr >> 3] << 6; 882 attr |= atom_def_dst[attr >> 3] << 6;
819 SDEBUG(" dst: "); 883 SDEBUG(" dst: ");
820 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 884 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
821 shift = U8((*ptr)++); 885 shift = atom_get_src(ctx, attr, ptr);
822 SDEBUG(" shift: %d\n", shift); 886 SDEBUG(" shift: %d\n", shift);
823 dst <<= shift; 887 dst <<= shift;
824 SDEBUG(" dst: "); 888 SDEBUG(" dst: ");
@@ -834,7 +898,7 @@ static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
834 attr |= atom_def_dst[attr >> 3] << 6; 898 attr |= atom_def_dst[attr >> 3] << 6;
835 SDEBUG(" dst: "); 899 SDEBUG(" dst: ");
836 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 900 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
837 shift = U8((*ptr)++); 901 shift = atom_get_src(ctx, attr, ptr);
838 SDEBUG(" shift: %d\n", shift); 902 SDEBUG(" shift: %d\n", shift);
839 dst >>= shift; 903 dst >>= shift;
840 SDEBUG(" dst: "); 904 SDEBUG(" dst: ");
@@ -937,18 +1001,18 @@ static struct {
937 atom_op_or, ATOM_ARG_FB}, { 1001 atom_op_or, ATOM_ARG_FB}, {
938 atom_op_or, ATOM_ARG_PLL}, { 1002 atom_op_or, ATOM_ARG_PLL}, {
939 atom_op_or, ATOM_ARG_MC}, { 1003 atom_op_or, ATOM_ARG_MC}, {
940 atom_op_shl, ATOM_ARG_REG}, { 1004 atom_op_shift_left, ATOM_ARG_REG}, {
941 atom_op_shl, ATOM_ARG_PS}, { 1005 atom_op_shift_left, ATOM_ARG_PS}, {
942 atom_op_shl, ATOM_ARG_WS}, { 1006 atom_op_shift_left, ATOM_ARG_WS}, {
943 atom_op_shl, ATOM_ARG_FB}, { 1007 atom_op_shift_left, ATOM_ARG_FB}, {
944 atom_op_shl, ATOM_ARG_PLL}, { 1008 atom_op_shift_left, ATOM_ARG_PLL}, {
945 atom_op_shl, ATOM_ARG_MC}, { 1009 atom_op_shift_left, ATOM_ARG_MC}, {
946 atom_op_shr, ATOM_ARG_REG}, { 1010 atom_op_shift_right, ATOM_ARG_REG}, {
947 atom_op_shr, ATOM_ARG_PS}, { 1011 atom_op_shift_right, ATOM_ARG_PS}, {
948 atom_op_shr, ATOM_ARG_WS}, { 1012 atom_op_shift_right, ATOM_ARG_WS}, {
949 atom_op_shr, ATOM_ARG_FB}, { 1013 atom_op_shift_right, ATOM_ARG_FB}, {
950 atom_op_shr, ATOM_ARG_PLL}, { 1014 atom_op_shift_right, ATOM_ARG_PLL}, {
951 atom_op_shr, ATOM_ARG_MC}, { 1015 atom_op_shift_right, ATOM_ARG_MC}, {
952 atom_op_mul, ATOM_ARG_REG}, { 1016 atom_op_mul, ATOM_ARG_REG}, {
953 atom_op_mul, ATOM_ARG_PS}, { 1017 atom_op_mul, ATOM_ARG_PS}, {
954 atom_op_mul, ATOM_ARG_WS}, { 1018 atom_op_mul, ATOM_ARG_WS}, {
@@ -1058,8 +1122,6 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3
1058 1122
1059 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); 1123 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
1060 1124
1061 /* reset reg block */
1062 ctx->reg_block = 0;
1063 ectx.ctx = ctx; 1125 ectx.ctx = ctx;
1064 ectx.ps_shift = ps / 4; 1126 ectx.ps_shift = ps / 4;
1065 ectx.start = base; 1127 ectx.start = base;
@@ -1096,6 +1158,12 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3
1096void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1158void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
1097{ 1159{
1098 mutex_lock(&ctx->mutex); 1160 mutex_lock(&ctx->mutex);
1161 /* reset reg block */
1162 ctx->reg_block = 0;
1163 /* reset fb window */
1164 ctx->fb_base = 0;
1165 /* reset io mode */
1166 ctx->io_mode = ATOM_IO_MM;
1099 atom_execute_table_locked(ctx, index, params); 1167 atom_execute_table_locked(ctx, index, params);
1100 mutex_unlock(&ctx->mutex); 1168 mutex_unlock(&ctx->mutex);
1101} 1169}
diff --git a/drivers/gpu/drm/radeon/atom.h b/drivers/gpu/drm/radeon/atom.h
index 47fd943f6d14..bc73781423a1 100644
--- a/drivers/gpu/drm/radeon/atom.h
+++ b/drivers/gpu/drm/radeon/atom.h
@@ -91,6 +91,7 @@
91#define ATOM_WS_AND_MASK 0x45 91#define ATOM_WS_AND_MASK 0x45
92#define ATOM_WS_FB_WINDOW 0x46 92#define ATOM_WS_FB_WINDOW 0x46
93#define ATOM_WS_ATTRIBUTES 0x47 93#define ATOM_WS_ATTRIBUTES 0x47
94#define ATOM_WS_REGPTR 0x48
94 95
95#define ATOM_IIO_NOP 0 96#define ATOM_IIO_NOP 0
96#define ATOM_IIO_START 1 97#define ATOM_IIO_START 1
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 8e28842080df..91ad0d1c1b17 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -1141,7 +1141,7 @@ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS {
1141/* ucTableFormatRevision=1,ucTableContentRevision=2 */ 1141/* ucTableFormatRevision=1,ucTableContentRevision=2 */
1142typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 { 1142typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 {
1143 USHORT usPixelClock; /* in 10KHz; for bios convenient */ 1143 USHORT usPixelClock; /* in 10KHz; for bios convenient */
1144 UCHAR ucMisc; /* see PANEL_ENCODER_MISC_xx defintions below */ 1144 UCHAR ucMisc; /* see PANEL_ENCODER_MISC_xx definitions below */
1145 UCHAR ucAction; /* 0: turn off encoder */ 1145 UCHAR ucAction; /* 0: turn off encoder */
1146 /* 1: setup and turn on encoder */ 1146 /* 1: setup and turn on encoder */
1147 UCHAR ucTruncate; /* bit0=0: Disable truncate */ 1147 UCHAR ucTruncate; /* bit0=0: Disable truncate */
@@ -1424,7 +1424,7 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO {
1424/* Structures used in FirmwareInfoTable */ 1424/* Structures used in FirmwareInfoTable */
1425/****************************************************************************/ 1425/****************************************************************************/
1426 1426
1427/* usBIOSCapability Defintion: */ 1427/* usBIOSCapability Definition: */
1428/* Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; */ 1428/* Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; */
1429/* Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; */ 1429/* Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; */
1430/* Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; */ 1430/* Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; */
@@ -2386,7 +2386,7 @@ typedef struct _ATOM_ANALOG_TV_INFO_V1_2 {
2386} ATOM_ANALOG_TV_INFO_V1_2; 2386} ATOM_ANALOG_TV_INFO_V1_2;
2387 2387
2388/**************************************************************************/ 2388/**************************************************************************/
2389/* VRAM usage and their defintions */ 2389/* VRAM usage and their definitions */
2390 2390
2391/* One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. */ 2391/* One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. */
2392/* Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. */ 2392/* Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. */
@@ -3046,7 +3046,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO {
3046#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 3046#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2
3047#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 3047#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
3048 3048
3049/* Byte aligned defintion for BIOS usage */ 3049/* Byte aligned definition for BIOS usage */
3050#define ATOM_S0_CRT1_MONOb0 0x01 3050#define ATOM_S0_CRT1_MONOb0 0x01
3051#define ATOM_S0_CRT1_COLORb0 0x02 3051#define ATOM_S0_CRT1_COLORb0 0x02
3052#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 3052#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
@@ -3131,7 +3131,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO {
3131#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 3131#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
3132#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 3132#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L
3133 3133
3134/* Byte aligned defintion for BIOS usage */ 3134/* Byte aligned definition for BIOS usage */
3135#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 3135#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F
3136#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 3136#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
3137#define ATOM_S2_CRT1_DPMS_STATEb2 0x01 3137#define ATOM_S2_CRT1_DPMS_STATEb2 0x01
@@ -3190,7 +3190,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO {
3190#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 3190#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L
3191#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 3191#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
3192 3192
3193/* Byte aligned defintion for BIOS usage */ 3193/* Byte aligned definition for BIOS usage */
3194#define ATOM_S3_CRT1_ACTIVEb0 0x01 3194#define ATOM_S3_CRT1_ACTIVEb0 0x01
3195#define ATOM_S3_LCD1_ACTIVEb0 0x02 3195#define ATOM_S3_LCD1_ACTIVEb0 0x02
3196#define ATOM_S3_TV1_ACTIVEb0 0x04 3196#define ATOM_S3_TV1_ACTIVEb0 0x04
@@ -3230,7 +3230,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO {
3230#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 3230#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L
3231#define ATOM_S4_LCD1_REFRESH_SHIFT 8 3231#define ATOM_S4_LCD1_REFRESH_SHIFT 8
3232 3232
3233/* Byte aligned defintion for BIOS usage */ 3233/* Byte aligned definition for BIOS usage */
3234#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 3234#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF
3235#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 3235#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0
3236#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 3236#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0
@@ -3310,7 +3310,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO {
3310#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 3310#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L
3311#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 3311#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L
3312 3312
3313/* Byte aligned defintion for BIOS usage */ 3313/* Byte aligned definition for BIOS usage */
3314#define ATOM_S6_DEVICE_CHANGEb0 0x01 3314#define ATOM_S6_DEVICE_CHANGEb0 0x01
3315#define ATOM_S6_SCALER_CHANGEb0 0x02 3315#define ATOM_S6_SCALER_CHANGEb0 0x02
3316#define ATOM_S6_LID_CHANGEb0 0x04 3316#define ATOM_S6_LID_CHANGEb0 0x04
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 260fcf59f00c..af464e351fbd 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -307,7 +307,6 @@ atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
308 args.ucCRTC = radeon_crtc->crtc_id; 308 args.ucCRTC = radeon_crtc->crtc_id;
309 309
310 printk("executing set crtc dtd timing\n");
311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
312} 311}
313 312
@@ -347,7 +346,6 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
347 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 346 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
348 args.ucCRTC = radeon_crtc->crtc_id; 347 args.ucCRTC = radeon_crtc->crtc_id;
349 348
350 printk("executing set crtc timing\n");
351 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
352} 350}
353 351
@@ -409,59 +407,57 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
409 } 407 }
410} 408}
411 409
412void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 410union adjust_pixel_clock {
411 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
412};
413
414static u32 atombios_adjust_pll(struct drm_crtc *crtc,
415 struct drm_display_mode *mode,
416 struct radeon_pll *pll)
413{ 417{
414 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
415 struct drm_device *dev = crtc->dev; 418 struct drm_device *dev = crtc->dev;
416 struct radeon_device *rdev = dev->dev_private; 419 struct radeon_device *rdev = dev->dev_private;
417 struct drm_encoder *encoder = NULL; 420 struct drm_encoder *encoder = NULL;
418 struct radeon_encoder *radeon_encoder = NULL; 421 struct radeon_encoder *radeon_encoder = NULL;
419 uint8_t frev, crev; 422 u32 adjusted_clock = mode->clock;
420 int index;
421 SET_PIXEL_CLOCK_PS_ALLOCATION args;
422 PIXEL_CLOCK_PARAMETERS *spc1_ptr;
423 PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
424 PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
425 uint32_t pll_clock = mode->clock;
426 uint32_t adjusted_clock;
427 uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
428 struct radeon_pll *pll;
429 int pll_flags = 0;
430 423
431 memset(&args, 0, sizeof(args)); 424 /* reset the pll flags */
425 pll->flags = 0;
432 426
433 if (ASIC_IS_AVIVO(rdev)) { 427 if (ASIC_IS_AVIVO(rdev)) {
434 if ((rdev->family == CHIP_RS600) || 428 if ((rdev->family == CHIP_RS600) ||
435 (rdev->family == CHIP_RS690) || 429 (rdev->family == CHIP_RS690) ||
436 (rdev->family == CHIP_RS740)) 430 (rdev->family == CHIP_RS740))
437 pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV | 431 pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
438 RADEON_PLL_PREFER_CLOSEST_LOWER); 432 RADEON_PLL_PREFER_CLOSEST_LOWER);
439 433
440 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 434 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
441 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 435 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
442 else 436 else
443 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 437 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
444 } else { 438 } else {
445 pll_flags |= RADEON_PLL_LEGACY; 439 pll->flags |= RADEON_PLL_LEGACY;
446 440
447 if (mode->clock > 200000) /* range limits??? */ 441 if (mode->clock > 200000) /* range limits??? */
448 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 442 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
449 else 443 else
450 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 444 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
451 445
452 } 446 }
453 447
454 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 448 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
455 if (encoder->crtc == crtc) { 449 if (encoder->crtc == crtc) {
456 if (!ASIC_IS_AVIVO(rdev)) {
457 if (encoder->encoder_type !=
458 DRM_MODE_ENCODER_DAC)
459 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
460 if (encoder->encoder_type ==
461 DRM_MODE_ENCODER_LVDS)
462 pll_flags |= RADEON_PLL_USE_REF_DIV;
463 }
464 radeon_encoder = to_radeon_encoder(encoder); 450 radeon_encoder = to_radeon_encoder(encoder);
451 if (ASIC_IS_AVIVO(rdev)) {
452 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
453 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
454 adjusted_clock = mode->clock * 2;
455 } else {
456 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
457 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
458 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
459 pll->flags |= RADEON_PLL_USE_REF_DIV;
460 }
465 break; 461 break;
466 } 462 }
467 } 463 }
@@ -471,46 +467,101 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
471 * special hw requirements. 467 * special hw requirements.
472 */ 468 */
473 if (ASIC_IS_DCE3(rdev)) { 469 if (ASIC_IS_DCE3(rdev)) {
474 ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_args; 470 union adjust_pixel_clock args;
471 struct radeon_encoder_atom_dig *dig;
472 u8 frev, crev;
473 int index;
475 474
476 if (!encoder) 475 if (!radeon_encoder->enc_priv)
477 return; 476 return adjusted_clock;
478 477 dig = radeon_encoder->enc_priv;
479 memset(&adjust_pll_args, 0, sizeof(adjust_pll_args));
480 adjust_pll_args.usPixelClock = cpu_to_le16(mode->clock / 10);
481 adjust_pll_args.ucTransmitterID = radeon_encoder->encoder_id;
482 adjust_pll_args.ucEncodeMode = atombios_get_encoder_mode(encoder);
483 478
484 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 479 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
485 atom_execute_table(rdev->mode_info.atom_context, 480 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
486 index, (uint32_t *)&adjust_pll_args); 481 &crev);
487 adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10; 482
488 } else { 483 memset(&args, 0, sizeof(args));
489 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 484
490 if (ASIC_IS_AVIVO(rdev) && 485 switch (frev) {
491 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 486 case 1:
492 adjusted_clock = mode->clock * 2; 487 switch (crev) {
493 else 488 case 1:
494 adjusted_clock = mode->clock; 489 case 2:
490 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
491 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
492 args.v1.ucEncodeMode = atombios_get_encoder_mode(encoder);
493
494 atom_execute_table(rdev->mode_info.atom_context,
495 index, (uint32_t *)&args);
496 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
497 break;
498 default:
499 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
500 return adjusted_clock;
501 }
502 break;
503 default:
504 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
505 return adjusted_clock;
506 }
495 } 507 }
508 return adjusted_clock;
509}
510
511union set_pixel_clock {
512 SET_PIXEL_CLOCK_PS_ALLOCATION base;
513 PIXEL_CLOCK_PARAMETERS v1;
514 PIXEL_CLOCK_PARAMETERS_V2 v2;
515 PIXEL_CLOCK_PARAMETERS_V3 v3;
516};
517
518void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
519{
520 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
521 struct drm_device *dev = crtc->dev;
522 struct radeon_device *rdev = dev->dev_private;
523 struct drm_encoder *encoder = NULL;
524 struct radeon_encoder *radeon_encoder = NULL;
525 u8 frev, crev;
526 int index;
527 union set_pixel_clock args;
528 u32 pll_clock = mode->clock;
529 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
530 struct radeon_pll *pll;
531 u32 adjusted_clock;
532
533 memset(&args, 0, sizeof(args));
534
535 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
536 if (encoder->crtc == crtc) {
537 radeon_encoder = to_radeon_encoder(encoder);
538 break;
539 }
540 }
541
542 if (!radeon_encoder)
543 return;
496 544
497 if (radeon_crtc->crtc_id == 0) 545 if (radeon_crtc->crtc_id == 0)
498 pll = &rdev->clock.p1pll; 546 pll = &rdev->clock.p1pll;
499 else 547 else
500 pll = &rdev->clock.p2pll; 548 pll = &rdev->clock.p2pll;
501 549
550 /* adjust pixel clock as needed */
551 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
552
502 if (ASIC_IS_AVIVO(rdev)) { 553 if (ASIC_IS_AVIVO(rdev)) {
503 if (radeon_new_pll) 554 if (radeon_new_pll)
504 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, 555 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock,
505 &fb_div, &frac_fb_div, 556 &fb_div, &frac_fb_div,
506 &ref_div, &post_div, pll_flags); 557 &ref_div, &post_div);
507 else 558 else
508 radeon_compute_pll(pll, adjusted_clock, &pll_clock, 559 radeon_compute_pll(pll, adjusted_clock, &pll_clock,
509 &fb_div, &frac_fb_div, 560 &fb_div, &frac_fb_div,
510 &ref_div, &post_div, pll_flags); 561 &ref_div, &post_div);
511 } else 562 } else
512 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 563 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
513 &ref_div, &post_div, pll_flags); 564 &ref_div, &post_div);
514 565
515 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 566 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
516 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 567 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
@@ -520,45 +571,38 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
520 case 1: 571 case 1:
521 switch (crev) { 572 switch (crev) {
522 case 1: 573 case 1:
523 spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput; 574 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
524 spc1_ptr->usPixelClock = cpu_to_le16(mode->clock / 10); 575 args.v1.usRefDiv = cpu_to_le16(ref_div);
525 spc1_ptr->usRefDiv = cpu_to_le16(ref_div); 576 args.v1.usFbDiv = cpu_to_le16(fb_div);
526 spc1_ptr->usFbDiv = cpu_to_le16(fb_div); 577 args.v1.ucFracFbDiv = frac_fb_div;
527 spc1_ptr->ucFracFbDiv = frac_fb_div; 578 args.v1.ucPostDiv = post_div;
528 spc1_ptr->ucPostDiv = post_div; 579 args.v1.ucPpll =
529 spc1_ptr->ucPpll =
530 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 580 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
531 spc1_ptr->ucCRTC = radeon_crtc->crtc_id; 581 args.v1.ucCRTC = radeon_crtc->crtc_id;
532 spc1_ptr->ucRefDivSrc = 1; 582 args.v1.ucRefDivSrc = 1;
533 break; 583 break;
534 case 2: 584 case 2:
535 spc2_ptr = 585 args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
536 (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput; 586 args.v2.usRefDiv = cpu_to_le16(ref_div);
537 spc2_ptr->usPixelClock = cpu_to_le16(mode->clock / 10); 587 args.v2.usFbDiv = cpu_to_le16(fb_div);
538 spc2_ptr->usRefDiv = cpu_to_le16(ref_div); 588 args.v2.ucFracFbDiv = frac_fb_div;
539 spc2_ptr->usFbDiv = cpu_to_le16(fb_div); 589 args.v2.ucPostDiv = post_div;
540 spc2_ptr->ucFracFbDiv = frac_fb_div; 590 args.v2.ucPpll =
541 spc2_ptr->ucPostDiv = post_div;
542 spc2_ptr->ucPpll =
543 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 591 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
544 spc2_ptr->ucCRTC = radeon_crtc->crtc_id; 592 args.v2.ucCRTC = radeon_crtc->crtc_id;
545 spc2_ptr->ucRefDivSrc = 1; 593 args.v2.ucRefDivSrc = 1;
546 break; 594 break;
547 case 3: 595 case 3:
548 if (!encoder) 596 args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
549 return; 597 args.v3.usRefDiv = cpu_to_le16(ref_div);
550 spc3_ptr = 598 args.v3.usFbDiv = cpu_to_le16(fb_div);
551 (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput; 599 args.v3.ucFracFbDiv = frac_fb_div;
552 spc3_ptr->usPixelClock = cpu_to_le16(mode->clock / 10); 600 args.v3.ucPostDiv = post_div;
553 spc3_ptr->usRefDiv = cpu_to_le16(ref_div); 601 args.v3.ucPpll =
554 spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
555 spc3_ptr->ucFracFbDiv = frac_fb_div;
556 spc3_ptr->ucPostDiv = post_div;
557 spc3_ptr->ucPpll =
558 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 602 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
559 spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2); 603 args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2);
560 spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id; 604 args.v3.ucTransmitterId = radeon_encoder->encoder_id;
561 spc3_ptr->ucEncoderMode = 605 args.v3.ucEncoderMode =
562 atombios_get_encoder_mode(encoder); 606 atombios_get_encoder_mode(encoder);
563 break; 607 break;
564 default: 608 default:
@@ -571,12 +615,11 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
571 return; 615 return;
572 } 616 }
573 617
574 printk("executing set pll\n");
575 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 618 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
576} 619}
577 620
578int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 621static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
579 struct drm_framebuffer *old_fb) 622 struct drm_framebuffer *old_fb)
580{ 623{
581 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 624 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
582 struct drm_device *dev = crtc->dev; 625 struct drm_device *dev = crtc->dev;
@@ -706,6 +749,42 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
706 return 0; 749 return 0;
707} 750}
708 751
752int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
753 struct drm_framebuffer *old_fb)
754{
755 struct drm_device *dev = crtc->dev;
756 struct radeon_device *rdev = dev->dev_private;
757
758 if (ASIC_IS_AVIVO(rdev))
759 return avivo_crtc_set_base(crtc, x, y, old_fb);
760 else
761 return radeon_crtc_set_base(crtc, x, y, old_fb);
762}
763
764/* properly set additional regs when using atombios */
765static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
766{
767 struct drm_device *dev = crtc->dev;
768 struct radeon_device *rdev = dev->dev_private;
769 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
770 u32 disp_merge_cntl;
771
772 switch (radeon_crtc->crtc_id) {
773 case 0:
774 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
775 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
776 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
777 break;
778 case 1:
779 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
780 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
781 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
782 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
783 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
784 break;
785 }
786}
787
709int atombios_crtc_mode_set(struct drm_crtc *crtc, 788int atombios_crtc_mode_set(struct drm_crtc *crtc,
710 struct drm_display_mode *mode, 789 struct drm_display_mode *mode,
711 struct drm_display_mode *adjusted_mode, 790 struct drm_display_mode *adjusted_mode,
@@ -727,8 +806,8 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
727 else { 806 else {
728 if (radeon_crtc->crtc_id == 0) 807 if (radeon_crtc->crtc_id == 0)
729 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 808 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
730 radeon_crtc_set_base(crtc, x, y, old_fb); 809 atombios_crtc_set_base(crtc, x, y, old_fb);
731 radeon_legacy_atom_set_surface(crtc); 810 radeon_legacy_atom_fixup(crtc);
732 } 811 }
733 atombios_overscan_setup(crtc, mode, adjusted_mode); 812 atombios_overscan_setup(crtc, mode, adjusted_mode);
734 atombios_scaler_setup(crtc); 813 atombios_scaler_setup(crtc);
@@ -746,8 +825,8 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
746 825
747static void atombios_crtc_prepare(struct drm_crtc *crtc) 826static void atombios_crtc_prepare(struct drm_crtc *crtc)
748{ 827{
749 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
750 atombios_lock_crtc(crtc, 1); 828 atombios_lock_crtc(crtc, 1);
829 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
751} 830}
752 831
753static void atombios_crtc_commit(struct drm_crtc *crtc) 832static void atombios_crtc_commit(struct drm_crtc *crtc)
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 3eb0ca5b3d73..71060114d5de 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -468,7 +468,7 @@ void radeon_dp_set_link_config(struct drm_connector *connector,
468 struct radeon_connector *radeon_connector; 468 struct radeon_connector *radeon_connector;
469 struct radeon_connector_atom_dig *dig_connector; 469 struct radeon_connector_atom_dig *dig_connector;
470 470
471 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) || 471 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
472 (connector->connector_type != DRM_MODE_CONNECTOR_eDP)) 472 (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
473 return; 473 return;
474 474
@@ -583,7 +583,7 @@ void dp_link_train(struct drm_encoder *encoder,
583 u8 train_set[4]; 583 u8 train_set[4];
584 int i; 584 int i;
585 585
586 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) || 586 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
587 (connector->connector_type != DRM_MODE_CONNECTOR_eDP)) 587 (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
588 return; 588 return;
589 589
@@ -596,21 +596,14 @@ void dp_link_train(struct drm_encoder *encoder,
596 return; 596 return;
597 dig_connector = radeon_connector->con_priv; 597 dig_connector = radeon_connector->con_priv;
598 598
599 if (ASIC_IS_DCE32(rdev)) { 599 if (dig->dig_encoder)
600 if (dig->dig_block) 600 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
601 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 601 else
602 else 602 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
603 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 603 if (dig_connector->linkb)
604 if (dig_connector->linkb) 604 enc_id |= ATOM_DP_CONFIG_LINK_B;
605 enc_id |= ATOM_DP_CONFIG_LINK_B; 605 else
606 else 606 enc_id |= ATOM_DP_CONFIG_LINK_A;
607 enc_id |= ATOM_DP_CONFIG_LINK_A;
608 } else {
609 if (dig_connector->linkb)
610 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER | ATOM_DP_CONFIG_LINK_B;
611 else
612 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER | ATOM_DP_CONFIG_LINK_A;
613 }
614 607
615 memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 608 memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
616 if (dig_connector->dp_clock == 270000) 609 if (dig_connector->dp_clock == 270000)
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 8760d66e058a..c0d4650cdb79 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -354,11 +354,17 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
354 return RREG32(RADEON_CRTC2_CRNT_FRAME); 354 return RREG32(RADEON_CRTC2_CRNT_FRAME);
355} 355}
356 356
357/* Who ever call radeon_fence_emit should call ring_lock and ask
358 * for enough space (today caller are ib schedule and buffer move) */
357void r100_fence_ring_emit(struct radeon_device *rdev, 359void r100_fence_ring_emit(struct radeon_device *rdev,
358 struct radeon_fence *fence) 360 struct radeon_fence *fence)
359{ 361{
360 /* Who ever call radeon_fence_emit should call ring_lock and ask 362 /* We have to make sure that caches are flushed before
361 * for enough space (today caller are ib schedule and buffer move) */ 363 * CPU might read something from VRAM. */
364 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
365 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
366 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
367 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
362 /* Wait until IDLE & CLEAN */ 368 /* Wait until IDLE & CLEAN */
363 radeon_ring_write(rdev, PACKET0(0x1720, 0)); 369 radeon_ring_write(rdev, PACKET0(0x1720, 0));
364 radeon_ring_write(rdev, (1 << 16) | (1 << 17)); 370 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
@@ -1504,6 +1510,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1504 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1510 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1505 return -EINVAL; 1511 return -EINVAL;
1506 } 1512 }
1513 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1507 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1514 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1508 track->immd_dwords = pkt->count - 1; 1515 track->immd_dwords = pkt->count - 1;
1509 r = r100_cs_track_check(p->rdev, track); 1516 r = r100_cs_track_check(p->rdev, track);
@@ -3368,7 +3375,6 @@ int r100_suspend(struct radeon_device *rdev)
3368 3375
3369void r100_fini(struct radeon_device *rdev) 3376void r100_fini(struct radeon_device *rdev)
3370{ 3377{
3371 r100_suspend(rdev);
3372 r100_cp_fini(rdev); 3378 r100_cp_fini(rdev);
3373 r100_wb_fini(rdev); 3379 r100_wb_fini(rdev);
3374 r100_ib_fini(rdev); 3380 r100_ib_fini(rdev);
@@ -3399,9 +3405,7 @@ int r100_mc_init(struct radeon_device *rdev)
3399 if (rdev->flags & RADEON_IS_AGP) { 3405 if (rdev->flags & RADEON_IS_AGP) {
3400 r = radeon_agp_init(rdev); 3406 r = radeon_agp_init(rdev);
3401 if (r) { 3407 if (r) {
3402 printk(KERN_WARNING "[drm] Disabling AGP\n"); 3408 radeon_agp_disable(rdev);
3403 rdev->flags &= ~RADEON_IS_AGP;
3404 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
3405 } else { 3409 } else {
3406 rdev->mc.gtt_location = rdev->mc.agp_base; 3410 rdev->mc.gtt_location = rdev->mc.agp_base;
3407 } 3411 }
@@ -3482,13 +3486,12 @@ int r100_init(struct radeon_device *rdev)
3482 if (r) { 3486 if (r) {
3483 /* Somethings want wront with the accel init stop accel */ 3487 /* Somethings want wront with the accel init stop accel */
3484 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 3488 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3485 r100_suspend(rdev);
3486 r100_cp_fini(rdev); 3489 r100_cp_fini(rdev);
3487 r100_wb_fini(rdev); 3490 r100_wb_fini(rdev);
3488 r100_ib_fini(rdev); 3491 r100_ib_fini(rdev);
3492 radeon_irq_kms_fini(rdev);
3489 if (rdev->flags & RADEON_IS_PCI) 3493 if (rdev->flags & RADEON_IS_PCI)
3490 r100_pci_gart_fini(rdev); 3494 r100_pci_gart_fini(rdev);
3491 radeon_irq_kms_fini(rdev);
3492 rdev->accel_working = false; 3495 rdev->accel_working = false;
3493 } 3496 }
3494 return 0; 3497 return 0;
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index 20942127c46b..ff1e0cd608bf 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -371,13 +371,16 @@ int r200_packet0_check(struct radeon_cs_parser *p,
371 case 5: 371 case 5:
372 case 6: 372 case 6:
373 case 7: 373 case 7:
374 /* 1D/2D */
374 track->textures[i].tex_coord_type = 0; 375 track->textures[i].tex_coord_type = 0;
375 break; 376 break;
376 case 1: 377 case 1:
377 track->textures[i].tex_coord_type = 1; 378 /* CUBE */
379 track->textures[i].tex_coord_type = 2;
378 break; 380 break;
379 case 2: 381 case 2:
380 track->textures[i].tex_coord_type = 2; 382 /* 3D */
383 track->textures[i].tex_coord_type = 1;
381 break; 384 break;
382 } 385 }
383 break; 386 break;
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 0051d11b907c..43b55a030b4d 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -506,11 +506,14 @@ void r300_vram_info(struct radeon_device *rdev)
506 506
507 /* DDR for all card after R300 & IGP */ 507 /* DDR for all card after R300 & IGP */
508 rdev->mc.vram_is_ddr = true; 508 rdev->mc.vram_is_ddr = true;
509
509 tmp = RREG32(RADEON_MEM_CNTL); 510 tmp = RREG32(RADEON_MEM_CNTL);
510 if (tmp & R300_MEM_NUM_CHANNELS_MASK) { 511 tmp &= R300_MEM_NUM_CHANNELS_MASK;
511 rdev->mc.vram_width = 128; 512 switch (tmp) {
512 } else { 513 case 0: rdev->mc.vram_width = 64; break;
513 rdev->mc.vram_width = 64; 514 case 1: rdev->mc.vram_width = 128; break;
515 case 2: rdev->mc.vram_width = 256; break;
516 default: rdev->mc.vram_width = 128; break;
514 } 517 }
515 518
516 r100_vram_init_sizes(rdev); 519 r100_vram_init_sizes(rdev);
@@ -1327,7 +1330,6 @@ int r300_suspend(struct radeon_device *rdev)
1327 1330
1328void r300_fini(struct radeon_device *rdev) 1331void r300_fini(struct radeon_device *rdev)
1329{ 1332{
1330 r300_suspend(rdev);
1331 r100_cp_fini(rdev); 1333 r100_cp_fini(rdev);
1332 r100_wb_fini(rdev); 1334 r100_wb_fini(rdev);
1333 r100_ib_fini(rdev); 1335 r100_ib_fini(rdev);
@@ -1418,15 +1420,15 @@ int r300_init(struct radeon_device *rdev)
1418 if (r) { 1420 if (r) {
1419 /* Somethings want wront with the accel init stop accel */ 1421 /* Somethings want wront with the accel init stop accel */
1420 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1422 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1421 r300_suspend(rdev);
1422 r100_cp_fini(rdev); 1423 r100_cp_fini(rdev);
1423 r100_wb_fini(rdev); 1424 r100_wb_fini(rdev);
1424 r100_ib_fini(rdev); 1425 r100_ib_fini(rdev);
1426 radeon_irq_kms_fini(rdev);
1425 if (rdev->flags & RADEON_IS_PCIE) 1427 if (rdev->flags & RADEON_IS_PCIE)
1426 rv370_pcie_gart_fini(rdev); 1428 rv370_pcie_gart_fini(rdev);
1427 if (rdev->flags & RADEON_IS_PCI) 1429 if (rdev->flags & RADEON_IS_PCI)
1428 r100_pci_gart_fini(rdev); 1430 r100_pci_gart_fini(rdev);
1429 radeon_irq_kms_fini(rdev); 1431 radeon_agp_fini(rdev);
1430 rdev->accel_working = false; 1432 rdev->accel_working = false;
1431 } 1433 }
1432 return 0; 1434 return 0;
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 1d4d16ed7db1..d9373246c97f 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -32,6 +32,13 @@
32#include "atom.h" 32#include "atom.h"
33#include "r100d.h" 33#include "r100d.h"
34#include "r420d.h" 34#include "r420d.h"
35#include "r420_reg_safe.h"
36
37static void r420_set_reg_safe(struct radeon_device *rdev)
38{
39 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
40 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
41}
35 42
36int r420_mc_init(struct radeon_device *rdev) 43int r420_mc_init(struct radeon_device *rdev)
37{ 44{
@@ -43,9 +50,7 @@ int r420_mc_init(struct radeon_device *rdev)
43 if (rdev->flags & RADEON_IS_AGP) { 50 if (rdev->flags & RADEON_IS_AGP) {
44 r = radeon_agp_init(rdev); 51 r = radeon_agp_init(rdev);
45 if (r) { 52 if (r) {
46 printk(KERN_WARNING "[drm] Disabling AGP\n"); 53 radeon_agp_disable(rdev);
47 rdev->flags &= ~RADEON_IS_AGP;
48 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
49 } else { 54 } else {
50 rdev->mc.gtt_location = rdev->mc.agp_base; 55 rdev->mc.gtt_location = rdev->mc.agp_base;
51 } 56 }
@@ -378,22 +383,21 @@ int r420_init(struct radeon_device *rdev)
378 if (r) 383 if (r)
379 return r; 384 return r;
380 } 385 }
381 r300_set_reg_safe(rdev); 386 r420_set_reg_safe(rdev);
382 rdev->accel_working = true; 387 rdev->accel_working = true;
383 r = r420_startup(rdev); 388 r = r420_startup(rdev);
384 if (r) { 389 if (r) {
385 /* Somethings want wront with the accel init stop accel */ 390 /* Somethings want wront with the accel init stop accel */
386 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 391 dev_err(rdev->dev, "Disabling GPU acceleration\n");
387 r420_suspend(rdev);
388 r100_cp_fini(rdev); 392 r100_cp_fini(rdev);
389 r100_wb_fini(rdev); 393 r100_wb_fini(rdev);
390 r100_ib_fini(rdev); 394 r100_ib_fini(rdev);
395 radeon_irq_kms_fini(rdev);
391 if (rdev->flags & RADEON_IS_PCIE) 396 if (rdev->flags & RADEON_IS_PCIE)
392 rv370_pcie_gart_fini(rdev); 397 rv370_pcie_gart_fini(rdev);
393 if (rdev->flags & RADEON_IS_PCI) 398 if (rdev->flags & RADEON_IS_PCI)
394 r100_pci_gart_fini(rdev); 399 r100_pci_gart_fini(rdev);
395 radeon_agp_fini(rdev); 400 radeon_agp_fini(rdev);
396 radeon_irq_kms_fini(rdev);
397 rdev->accel_working = false; 401 rdev->accel_working = false;
398 } 402 }
399 return 0; 403 return 0;
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 9a189072f2b9..ddf5731eba0d 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -294,13 +294,12 @@ int r520_init(struct radeon_device *rdev)
294 if (r) { 294 if (r) {
295 /* Somethings want wront with the accel init stop accel */ 295 /* Somethings want wront with the accel init stop accel */
296 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 296 dev_err(rdev->dev, "Disabling GPU acceleration\n");
297 rv515_suspend(rdev);
298 r100_cp_fini(rdev); 297 r100_cp_fini(rdev);
299 r100_wb_fini(rdev); 298 r100_wb_fini(rdev);
300 r100_ib_fini(rdev); 299 r100_ib_fini(rdev);
300 radeon_irq_kms_fini(rdev);
301 rv370_pcie_gart_fini(rdev); 301 rv370_pcie_gart_fini(rdev);
302 radeon_agp_fini(rdev); 302 radeon_agp_fini(rdev);
303 radeon_irq_kms_fini(rdev);
304 rdev->accel_working = false; 303 rdev->accel_working = false;
305 } 304 }
306 return 0; 305 return 0;
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 1f4f83d6fbe6..a1198d99cdf9 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -624,7 +624,6 @@ int r600_mc_init(struct radeon_device *rdev)
624 fixed20_12 a; 624 fixed20_12 a;
625 u32 tmp; 625 u32 tmp;
626 int chansize, numchan; 626 int chansize, numchan;
627 int r;
628 627
629 /* Get VRAM informations */ 628 /* Get VRAM informations */
630 rdev->mc.vram_is_ddr = true; 629 rdev->mc.vram_is_ddr = true;
@@ -667,9 +666,6 @@ int r600_mc_init(struct radeon_device *rdev)
667 rdev->mc.real_vram_size = rdev->mc.aper_size; 666 rdev->mc.real_vram_size = rdev->mc.aper_size;
668 667
669 if (rdev->flags & RADEON_IS_AGP) { 668 if (rdev->flags & RADEON_IS_AGP) {
670 r = radeon_agp_init(rdev);
671 if (r)
672 return r;
673 /* gtt_size is setup by radeon_agp_init */ 669 /* gtt_size is setup by radeon_agp_init */
674 rdev->mc.gtt_location = rdev->mc.agp_base; 670 rdev->mc.gtt_location = rdev->mc.agp_base;
675 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; 671 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
@@ -678,11 +674,11 @@ int r600_mc_init(struct radeon_device *rdev)
678 * AGP so that GPU can catch out of VRAM/AGP access 674 * AGP so that GPU can catch out of VRAM/AGP access
679 */ 675 */
680 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { 676 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
681 /* Enought place before */ 677 /* Enough place before */
682 rdev->mc.vram_location = rdev->mc.gtt_location - 678 rdev->mc.vram_location = rdev->mc.gtt_location -
683 rdev->mc.mc_vram_size; 679 rdev->mc.mc_vram_size;
684 } else if (tmp > rdev->mc.mc_vram_size) { 680 } else if (tmp > rdev->mc.mc_vram_size) {
685 /* Enought place after */ 681 /* Enough place after */
686 rdev->mc.vram_location = rdev->mc.gtt_location + 682 rdev->mc.vram_location = rdev->mc.gtt_location +
687 rdev->mc.gtt_size; 683 rdev->mc.gtt_size;
688 } else { 684 } else {
@@ -1658,6 +1654,12 @@ void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1658 rdev->cp.align_mask = 16 - 1; 1654 rdev->cp.align_mask = 16 - 1;
1659} 1655}
1660 1656
1657void r600_cp_fini(struct radeon_device *rdev)
1658{
1659 r600_cp_stop(rdev);
1660 radeon_ring_fini(rdev);
1661}
1662
1661 1663
1662/* 1664/*
1663 * GPU scratch registers helpers function. 1665 * GPU scratch registers helpers function.
@@ -1792,23 +1794,24 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
1792 radeon_ring_write(rdev, RB_INT_STAT); 1794 radeon_ring_write(rdev, RB_INT_STAT);
1793} 1795}
1794 1796
1795int r600_copy_dma(struct radeon_device *rdev,
1796 uint64_t src_offset,
1797 uint64_t dst_offset,
1798 unsigned num_pages,
1799 struct radeon_fence *fence)
1800{
1801 /* FIXME: implement */
1802 return 0;
1803}
1804
1805int r600_copy_blit(struct radeon_device *rdev, 1797int r600_copy_blit(struct radeon_device *rdev,
1806 uint64_t src_offset, uint64_t dst_offset, 1798 uint64_t src_offset, uint64_t dst_offset,
1807 unsigned num_pages, struct radeon_fence *fence) 1799 unsigned num_pages, struct radeon_fence *fence)
1808{ 1800{
1809 r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); 1801 int r;
1802
1803 mutex_lock(&rdev->r600_blit.mutex);
1804 rdev->r600_blit.vb_ib = NULL;
1805 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1806 if (r) {
1807 if (rdev->r600_blit.vb_ib)
1808 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1809 mutex_unlock(&rdev->r600_blit.mutex);
1810 return r;
1811 }
1810 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); 1812 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1811 r600_blit_done_copy(rdev, fence); 1813 r600_blit_done_copy(rdev, fence);
1814 mutex_unlock(&rdev->r600_blit.mutex);
1812 return 0; 1815 return 0;
1813} 1816}
1814 1817
@@ -1864,26 +1867,25 @@ int r600_startup(struct radeon_device *rdev)
1864 return r; 1867 return r;
1865 } 1868 }
1866 r600_gpu_init(rdev); 1869 r600_gpu_init(rdev);
1867 1870 r = r600_blit_init(rdev);
1868 if (!rdev->r600_blit.shader_obj) { 1871 if (r) {
1869 r = r600_blit_init(rdev); 1872 r600_blit_fini(rdev);
1873 rdev->asic->copy = NULL;
1874 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1875 }
1876 /* pin copy shader into vram */
1877 if (rdev->r600_blit.shader_obj) {
1878 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1879 if (unlikely(r != 0))
1880 return r;
1881 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1882 &rdev->r600_blit.shader_gpu_addr);
1883 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1870 if (r) { 1884 if (r) {
1871 DRM_ERROR("radeon: failed blitter (%d).\n", r); 1885 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1872 return r; 1886 return r;
1873 } 1887 }
1874 } 1888 }
1875
1876 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1877 if (unlikely(r != 0))
1878 return r;
1879 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1880 &rdev->r600_blit.shader_gpu_addr);
1881 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1882 if (r) {
1883 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1884 return r;
1885 }
1886
1887 /* Enable IRQ */ 1889 /* Enable IRQ */
1888 r = r600_irq_init(rdev); 1890 r = r600_irq_init(rdev);
1889 if (r) { 1891 if (r) {
@@ -1958,14 +1960,17 @@ int r600_suspend(struct radeon_device *rdev)
1958 /* FIXME: we should wait for ring to be empty */ 1960 /* FIXME: we should wait for ring to be empty */
1959 r600_cp_stop(rdev); 1961 r600_cp_stop(rdev);
1960 rdev->cp.ready = false; 1962 rdev->cp.ready = false;
1963 r600_irq_suspend(rdev);
1961 r600_wb_disable(rdev); 1964 r600_wb_disable(rdev);
1962 r600_pcie_gart_disable(rdev); 1965 r600_pcie_gart_disable(rdev);
1963 /* unpin shaders bo */ 1966 /* unpin shaders bo */
1964 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 1967 if (rdev->r600_blit.shader_obj) {
1965 if (unlikely(r != 0)) 1968 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1966 return r; 1969 if (!r) {
1967 radeon_bo_unpin(rdev->r600_blit.shader_obj); 1970 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1968 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 1971 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1972 }
1973 }
1969 return 0; 1974 return 0;
1970} 1975}
1971 1976
@@ -2026,6 +2031,11 @@ int r600_init(struct radeon_device *rdev)
2026 r = radeon_fence_driver_init(rdev); 2031 r = radeon_fence_driver_init(rdev);
2027 if (r) 2032 if (r)
2028 return r; 2033 return r;
2034 if (rdev->flags & RADEON_IS_AGP) {
2035 r = radeon_agp_init(rdev);
2036 if (r)
2037 radeon_agp_disable(rdev);
2038 }
2029 r = r600_mc_init(rdev); 2039 r = r600_mc_init(rdev);
2030 if (r) 2040 if (r)
2031 return r; 2041 return r;
@@ -2051,22 +2061,25 @@ int r600_init(struct radeon_device *rdev)
2051 rdev->accel_working = true; 2061 rdev->accel_working = true;
2052 r = r600_startup(rdev); 2062 r = r600_startup(rdev);
2053 if (r) { 2063 if (r) {
2054 r600_suspend(rdev); 2064 dev_err(rdev->dev, "disabling GPU acceleration\n");
2065 r600_cp_fini(rdev);
2055 r600_wb_fini(rdev); 2066 r600_wb_fini(rdev);
2056 radeon_ring_fini(rdev); 2067 r600_irq_fini(rdev);
2068 radeon_irq_kms_fini(rdev);
2057 r600_pcie_gart_fini(rdev); 2069 r600_pcie_gart_fini(rdev);
2058 rdev->accel_working = false; 2070 rdev->accel_working = false;
2059 } 2071 }
2060 if (rdev->accel_working) { 2072 if (rdev->accel_working) {
2061 r = radeon_ib_pool_init(rdev); 2073 r = radeon_ib_pool_init(rdev);
2062 if (r) { 2074 if (r) {
2063 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); 2075 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2064 rdev->accel_working = false;
2065 }
2066 r = r600_ib_test(rdev);
2067 if (r) {
2068 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2069 rdev->accel_working = false; 2076 rdev->accel_working = false;
2077 } else {
2078 r = r600_ib_test(rdev);
2079 if (r) {
2080 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2081 rdev->accel_working = false;
2082 }
2070 } 2083 }
2071 } 2084 }
2072 2085
@@ -2078,20 +2091,17 @@ int r600_init(struct radeon_device *rdev)
2078 2091
2079void r600_fini(struct radeon_device *rdev) 2092void r600_fini(struct radeon_device *rdev)
2080{ 2093{
2081 /* Suspend operations */
2082 r600_suspend(rdev);
2083
2084 r600_audio_fini(rdev); 2094 r600_audio_fini(rdev);
2085 r600_blit_fini(rdev); 2095 r600_blit_fini(rdev);
2096 r600_cp_fini(rdev);
2097 r600_wb_fini(rdev);
2086 r600_irq_fini(rdev); 2098 r600_irq_fini(rdev);
2087 radeon_irq_kms_fini(rdev); 2099 radeon_irq_kms_fini(rdev);
2088 radeon_ring_fini(rdev);
2089 r600_wb_fini(rdev);
2090 r600_pcie_gart_fini(rdev); 2100 r600_pcie_gart_fini(rdev);
2101 radeon_agp_fini(rdev);
2091 radeon_gem_fini(rdev); 2102 radeon_gem_fini(rdev);
2092 radeon_fence_driver_fini(rdev); 2103 radeon_fence_driver_fini(rdev);
2093 radeon_clocks_fini(rdev); 2104 radeon_clocks_fini(rdev);
2094 radeon_agp_fini(rdev);
2095 radeon_bo_fini(rdev); 2105 radeon_bo_fini(rdev);
2096 radeon_atombios_fini(rdev); 2106 radeon_atombios_fini(rdev);
2097 kfree(rdev->bios); 2107 kfree(rdev->bios);
@@ -2197,14 +2207,14 @@ void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2197 rb_bufsz = drm_order(ring_size / 4); 2207 rb_bufsz = drm_order(ring_size / 4);
2198 ring_size = (1 << rb_bufsz) * 4; 2208 ring_size = (1 << rb_bufsz) * 4;
2199 rdev->ih.ring_size = ring_size; 2209 rdev->ih.ring_size = ring_size;
2200 rdev->ih.align_mask = 4 - 1; 2210 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2211 rdev->ih.rptr = 0;
2201} 2212}
2202 2213
2203static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size) 2214static int r600_ih_ring_alloc(struct radeon_device *rdev)
2204{ 2215{
2205 int r; 2216 int r;
2206 2217
2207 rdev->ih.ring_size = ring_size;
2208 /* Allocate ring buffer */ 2218 /* Allocate ring buffer */
2209 if (rdev->ih.ring_obj == NULL) { 2219 if (rdev->ih.ring_obj == NULL) {
2210 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size, 2220 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
@@ -2234,9 +2244,6 @@ static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size)
2234 return r; 2244 return r;
2235 } 2245 }
2236 } 2246 }
2237 rdev->ih.ptr_mask = (rdev->cp.ring_size / 4) - 1;
2238 rdev->ih.rptr = 0;
2239
2240 return 0; 2247 return 0;
2241} 2248}
2242 2249
@@ -2386,7 +2393,7 @@ int r600_irq_init(struct radeon_device *rdev)
2386 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 2393 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2387 2394
2388 /* allocate ring */ 2395 /* allocate ring */
2389 ret = r600_ih_ring_alloc(rdev, rdev->ih.ring_size); 2396 ret = r600_ih_ring_alloc(rdev);
2390 if (ret) 2397 if (ret)
2391 return ret; 2398 return ret;
2392 2399
@@ -2449,10 +2456,15 @@ int r600_irq_init(struct radeon_device *rdev)
2449 return ret; 2456 return ret;
2450} 2457}
2451 2458
2452void r600_irq_fini(struct radeon_device *rdev) 2459void r600_irq_suspend(struct radeon_device *rdev)
2453{ 2460{
2454 r600_disable_interrupts(rdev); 2461 r600_disable_interrupts(rdev);
2455 r600_rlc_stop(rdev); 2462 r600_rlc_stop(rdev);
2463}
2464
2465void r600_irq_fini(struct radeon_device *rdev)
2466{
2467 r600_irq_suspend(rdev);
2456 r600_ih_ring_fini(rdev); 2468 r600_ih_ring_fini(rdev);
2457} 2469}
2458 2470
@@ -2467,8 +2479,12 @@ int r600_irq_set(struct radeon_device *rdev)
2467 return -EINVAL; 2479 return -EINVAL;
2468 } 2480 }
2469 /* don't enable anything if the ih is disabled */ 2481 /* don't enable anything if the ih is disabled */
2470 if (!rdev->ih.enabled) 2482 if (!rdev->ih.enabled) {
2483 r600_disable_interrupts(rdev);
2484 /* force the active interrupt state to all disabled */
2485 r600_disable_interrupt_state(rdev);
2471 return 0; 2486 return 0;
2487 }
2472 2488
2473 if (ASIC_IS_DCE3(rdev)) { 2489 if (ASIC_IS_DCE3(rdev)) {
2474 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 2490 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
@@ -2638,16 +2654,18 @@ static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2638 wptr = RREG32(IH_RB_WPTR); 2654 wptr = RREG32(IH_RB_WPTR);
2639 2655
2640 if (wptr & RB_OVERFLOW) { 2656 if (wptr & RB_OVERFLOW) {
2641 WARN_ON(1); 2657 /* When a ring buffer overflow happen start parsing interrupt
2642 /* XXX deal with overflow */ 2658 * from the last not overwritten vector (wptr + 16). Hopefully
2643 DRM_ERROR("IH RB overflow\n"); 2659 * this should allow us to catchup.
2660 */
2661 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2662 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2663 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2644 tmp = RREG32(IH_RB_CNTL); 2664 tmp = RREG32(IH_RB_CNTL);
2645 tmp |= IH_WPTR_OVERFLOW_CLEAR; 2665 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2646 WREG32(IH_RB_CNTL, tmp); 2666 WREG32(IH_RB_CNTL, tmp);
2647 } 2667 }
2648 wptr = wptr & WPTR_OFFSET_MASK; 2668 return (wptr & rdev->ih.ptr_mask);
2649
2650 return wptr;
2651} 2669}
2652 2670
2653/* r600 IV Ring 2671/* r600 IV Ring
@@ -2683,12 +2701,13 @@ int r600_irq_process(struct radeon_device *rdev)
2683 u32 wptr = r600_get_ih_wptr(rdev); 2701 u32 wptr = r600_get_ih_wptr(rdev);
2684 u32 rptr = rdev->ih.rptr; 2702 u32 rptr = rdev->ih.rptr;
2685 u32 src_id, src_data; 2703 u32 src_id, src_data;
2686 u32 last_entry = rdev->ih.ring_size - 16;
2687 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2; 2704 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2688 unsigned long flags; 2705 unsigned long flags;
2689 bool queue_hotplug = false; 2706 bool queue_hotplug = false;
2690 2707
2691 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 2708 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2709 if (!rdev->ih.enabled)
2710 return IRQ_NONE;
2692 2711
2693 spin_lock_irqsave(&rdev->ih.lock, flags); 2712 spin_lock_irqsave(&rdev->ih.lock, flags);
2694 2713
@@ -2729,7 +2748,7 @@ restart_ih:
2729 } 2748 }
2730 break; 2749 break;
2731 default: 2750 default:
2732 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2751 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2733 break; 2752 break;
2734 } 2753 }
2735 break; 2754 break;
@@ -2749,7 +2768,7 @@ restart_ih:
2749 } 2768 }
2750 break; 2769 break;
2751 default: 2770 default:
2752 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2771 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2753 break; 2772 break;
2754 } 2773 }
2755 break; 2774 break;
@@ -2798,7 +2817,7 @@ restart_ih:
2798 } 2817 }
2799 break; 2818 break;
2800 default: 2819 default:
2801 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2820 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2802 break; 2821 break;
2803 } 2822 }
2804 break; 2823 break;
@@ -2812,15 +2831,13 @@ restart_ih:
2812 DRM_DEBUG("IH: CP EOP\n"); 2831 DRM_DEBUG("IH: CP EOP\n");
2813 break; 2832 break;
2814 default: 2833 default:
2815 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2834 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2816 break; 2835 break;
2817 } 2836 }
2818 2837
2819 /* wptr/rptr are in bytes! */ 2838 /* wptr/rptr are in bytes! */
2820 if (rptr == last_entry) 2839 rptr += 16;
2821 rptr = 0; 2840 rptr &= rdev->ih.ptr_mask;
2822 else
2823 rptr += 16;
2824 } 2841 }
2825 /* make sure wptr hasn't changed while processing */ 2842 /* make sure wptr hasn't changed while processing */
2826 wptr = r600_get_ih_wptr(rdev); 2843 wptr = r600_get_ih_wptr(rdev);
@@ -2888,3 +2905,18 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2888 return 0; 2905 return 0;
2889#endif 2906#endif
2890} 2907}
2908
2909/**
2910 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2911 * rdev: radeon device structure
2912 * bo: buffer object struct which userspace is waiting for idle
2913 *
2914 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2915 * through ring buffer, this leads to corruption in rendering, see
2916 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2917 * directly perform HDP flush by writing register through MMIO.
2918 */
2919void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2920{
2921 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2922}
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index 99e2c3891a7d..b1c1d3433454 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -35,7 +35,7 @@
35 */ 35 */
36static int r600_audio_chipset_supported(struct radeon_device *rdev) 36static int r600_audio_chipset_supported(struct radeon_device *rdev)
37{ 37{
38 return rdev->family >= CHIP_R600 38 return (rdev->family >= CHIP_R600 && rdev->family < CHIP_RV710)
39 || rdev->family == CHIP_RS600 39 || rdev->family == CHIP_RS600
40 || rdev->family == CHIP_RS690 40 || rdev->family == CHIP_RS690
41 || rdev->family == CHIP_RS740; 41 || rdev->family == CHIP_RS740;
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 8787ea89dc6e..af1c3ca8a4cb 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -449,6 +449,7 @@ int r600_blit_init(struct radeon_device *rdev)
449 u32 packet2s[16]; 449 u32 packet2s[16];
450 int num_packet2s = 0; 450 int num_packet2s = 0;
451 451
452 mutex_init(&rdev->r600_blit.mutex);
452 rdev->r600_blit.state_offset = 0; 453 rdev->r600_blit.state_offset = 0;
453 454
454 if (rdev->family >= CHIP_RV770) 455 if (rdev->family >= CHIP_RV770)
@@ -512,14 +513,16 @@ void r600_blit_fini(struct radeon_device *rdev)
512{ 513{
513 int r; 514 int r;
514 515
516 if (rdev->r600_blit.shader_obj == NULL)
517 return;
518 /* If we can't reserve the bo, unref should be enough to destroy
519 * it when it becomes idle.
520 */
515 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 521 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
516 if (unlikely(r != 0)) { 522 if (!r) {
517 dev_err(rdev->dev, "(%d) can't finish r600 blit\n", r); 523 radeon_bo_unpin(rdev->r600_blit.shader_obj);
518 goto out_unref; 524 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
519 } 525 }
520 radeon_bo_unpin(rdev->r600_blit.shader_obj);
521 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
522out_unref:
523 radeon_bo_unref(&rdev->r600_blit.shader_obj); 526 radeon_bo_unref(&rdev->r600_blit.shader_obj);
524} 527}
525 528
@@ -555,7 +558,8 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
555 int dwords_per_loop = 76, num_loops; 558 int dwords_per_loop = 76, num_loops;
556 559
557 r = r600_vb_ib_get(rdev); 560 r = r600_vb_ib_get(rdev);
558 WARN_ON(r); 561 if (r)
562 return r;
559 563
560 /* set_render_target emits 2 extra dwords on rv6xx */ 564 /* set_render_target emits 2 extra dwords on rv6xx */
561 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) 565 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
@@ -581,7 +585,8 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
581 ring_size += 5; /* done copy */ 585 ring_size += 5; /* done copy */
582 ring_size += 7; /* fence emit for done copy */ 586 ring_size += 7; /* fence emit for done copy */
583 r = radeon_ring_lock(rdev, ring_size); 587 r = radeon_ring_lock(rdev, ring_size);
584 WARN_ON(r); 588 if (r)
589 return r;
585 590
586 set_default_state(rdev); /* 14 */ 591 set_default_state(rdev); /* 14 */
587 set_shaders(rdev); /* 26 */ 592 set_shaders(rdev); /* 26 */
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 44060b92d9e6..e4c45ec16507 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -36,6 +36,10 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
36typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**); 36typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
37static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm; 37static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
38 38
39struct r600_cs_track {
40 u32 cb_color0_base_last;
41};
42
39/** 43/**
40 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet 44 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
41 * @parser: parser structure holding parsing context. 45 * @parser: parser structure holding parsing context.
@@ -177,6 +181,28 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
177} 181}
178 182
179/** 183/**
184 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
185 * @parser: parser structure holding parsing context.
186 *
187 * Check next packet is relocation packet3, do bo validation and compute
188 * GPU offset using the provided start.
189 **/
190static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
191{
192 struct radeon_cs_packet p3reloc;
193 int r;
194
195 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
196 if (r) {
197 return 0;
198 }
199 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
200 return 0;
201 }
202 return 1;
203}
204
205/**
180 * r600_cs_packet_next_vline() - parse userspace VLINE packet 206 * r600_cs_packet_next_vline() - parse userspace VLINE packet
181 * @parser: parser structure holding parsing context. 207 * @parser: parser structure holding parsing context.
182 * 208 *
@@ -337,6 +363,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
337 struct radeon_cs_packet *pkt) 363 struct radeon_cs_packet *pkt)
338{ 364{
339 struct radeon_cs_reloc *reloc; 365 struct radeon_cs_reloc *reloc;
366 struct r600_cs_track *track;
340 volatile u32 *ib; 367 volatile u32 *ib;
341 unsigned idx; 368 unsigned idx;
342 unsigned i; 369 unsigned i;
@@ -344,6 +371,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
344 int r; 371 int r;
345 u32 idx_value; 372 u32 idx_value;
346 373
374 track = (struct r600_cs_track *)p->track;
347 ib = p->ib->ptr; 375 ib = p->ib->ptr;
348 idx = pkt->idx + 1; 376 idx = pkt->idx + 1;
349 idx_value = radeon_get_ib_value(p, idx); 377 idx_value = radeon_get_ib_value(p, idx);
@@ -503,9 +531,60 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
503 for (i = 0; i < pkt->count; i++) { 531 for (i = 0; i < pkt->count; i++) {
504 reg = start_reg + (4 * i); 532 reg = start_reg + (4 * i);
505 switch (reg) { 533 switch (reg) {
534 /* This register were added late, there is userspace
535 * which does provide relocation for those but set
536 * 0 offset. In order to avoid breaking old userspace
537 * we detect this and set address to point to last
538 * CB_COLOR0_BASE, note that if userspace doesn't set
539 * CB_COLOR0_BASE before this register we will report
540 * error. Old userspace always set CB_COLOR0_BASE
541 * before any of this.
542 */
543 case R_0280E0_CB_COLOR0_FRAG:
544 case R_0280E4_CB_COLOR1_FRAG:
545 case R_0280E8_CB_COLOR2_FRAG:
546 case R_0280EC_CB_COLOR3_FRAG:
547 case R_0280F0_CB_COLOR4_FRAG:
548 case R_0280F4_CB_COLOR5_FRAG:
549 case R_0280F8_CB_COLOR6_FRAG:
550 case R_0280FC_CB_COLOR7_FRAG:
551 case R_0280C0_CB_COLOR0_TILE:
552 case R_0280C4_CB_COLOR1_TILE:
553 case R_0280C8_CB_COLOR2_TILE:
554 case R_0280CC_CB_COLOR3_TILE:
555 case R_0280D0_CB_COLOR4_TILE:
556 case R_0280D4_CB_COLOR5_TILE:
557 case R_0280D8_CB_COLOR6_TILE:
558 case R_0280DC_CB_COLOR7_TILE:
559 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
560 if (!track->cb_color0_base_last) {
561 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
562 return -EINVAL;
563 }
564 ib[idx+1+i] = track->cb_color0_base_last;
565 printk_once(KERN_WARNING "radeon: You have old & broken userspace "
566 "please consider updating mesa & xf86-video-ati\n");
567 } else {
568 r = r600_cs_packet_next_reloc(p, &reloc);
569 if (r) {
570 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
571 return -EINVAL;
572 }
573 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
574 }
575 break;
506 case DB_DEPTH_BASE: 576 case DB_DEPTH_BASE:
507 case DB_HTILE_DATA_BASE: 577 case DB_HTILE_DATA_BASE:
508 case CB_COLOR0_BASE: 578 case CB_COLOR0_BASE:
579 r = r600_cs_packet_next_reloc(p, &reloc);
580 if (r) {
581 DRM_ERROR("bad SET_CONTEXT_REG "
582 "0x%04X\n", reg);
583 return -EINVAL;
584 }
585 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
586 track->cb_color0_base_last = ib[idx+1+i];
587 break;
509 case CB_COLOR1_BASE: 588 case CB_COLOR1_BASE:
510 case CB_COLOR2_BASE: 589 case CB_COLOR2_BASE:
511 case CB_COLOR3_BASE: 590 case CB_COLOR3_BASE:
@@ -678,8 +757,11 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
678int r600_cs_parse(struct radeon_cs_parser *p) 757int r600_cs_parse(struct radeon_cs_parser *p)
679{ 758{
680 struct radeon_cs_packet pkt; 759 struct radeon_cs_packet pkt;
760 struct r600_cs_track *track;
681 int r; 761 int r;
682 762
763 track = kzalloc(sizeof(*track), GFP_KERNEL);
764 p->track = track;
683 do { 765 do {
684 r = r600_cs_packet_parse(p, &pkt, p->idx); 766 r = r600_cs_packet_parse(p, &pkt, p->idx);
685 if (r) { 767 if (r) {
@@ -757,6 +839,7 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
757 /* initialize parser */ 839 /* initialize parser */
758 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 840 memset(&parser, 0, sizeof(struct radeon_cs_parser));
759 parser.filp = filp; 841 parser.filp = filp;
842 parser.dev = &dev->pdev->dev;
760 parser.rdev = NULL; 843 parser.rdev = NULL;
761 parser.family = family; 844 parser.family = family;
762 parser.ib = &fake_ib; 845 parser.ib = &fake_ib;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 05894edadab4..30480881aed1 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -882,4 +882,29 @@
882#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 882#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)
883 883
884#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 884#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
885
886#define R_0280E0_CB_COLOR0_FRAG 0x0280E0
887#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
888#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
889#define C_0280E0_BASE_256B 0x00000000
890#define R_0280E4_CB_COLOR1_FRAG 0x0280E4
891#define R_0280E8_CB_COLOR2_FRAG 0x0280E8
892#define R_0280EC_CB_COLOR3_FRAG 0x0280EC
893#define R_0280F0_CB_COLOR4_FRAG 0x0280F0
894#define R_0280F4_CB_COLOR5_FRAG 0x0280F4
895#define R_0280F8_CB_COLOR6_FRAG 0x0280F8
896#define R_0280FC_CB_COLOR7_FRAG 0x0280FC
897#define R_0280C0_CB_COLOR0_TILE 0x0280C0
898#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
899#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
900#define C_0280C0_BASE_256B 0x00000000
901#define R_0280C4_CB_COLOR1_TILE 0x0280C4
902#define R_0280C8_CB_COLOR2_TILE 0x0280C8
903#define R_0280CC_CB_COLOR3_TILE 0x0280CC
904#define R_0280D0_CB_COLOR4_TILE 0x0280D0
905#define R_0280D4_CB_COLOR5_TILE 0x0280D4
906#define R_0280D8_CB_COLOR6_TILE 0x0280D8
907#define R_0280DC_CB_COLOR7_TILE 0x0280DC
908
909
885#endif 910#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index eb5f99b9469d..f57480ba1355 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -410,13 +410,13 @@ struct r600_ih {
410 unsigned wptr_old; 410 unsigned wptr_old;
411 unsigned ring_size; 411 unsigned ring_size;
412 uint64_t gpu_addr; 412 uint64_t gpu_addr;
413 uint32_t align_mask;
414 uint32_t ptr_mask; 413 uint32_t ptr_mask;
415 spinlock_t lock; 414 spinlock_t lock;
416 bool enabled; 415 bool enabled;
417}; 416};
418 417
419struct r600_blit { 418struct r600_blit {
419 struct mutex mutex;
420 struct radeon_bo *shader_obj; 420 struct radeon_bo *shader_obj;
421 u64 shader_gpu_addr; 421 u64 shader_gpu_addr;
422 u32 vs_offset, ps_offset; 422 u32 vs_offset, ps_offset;
@@ -465,6 +465,7 @@ struct radeon_cs_chunk {
465}; 465};
466 466
467struct radeon_cs_parser { 467struct radeon_cs_parser {
468 struct device *dev;
468 struct radeon_device *rdev; 469 struct radeon_device *rdev;
469 struct drm_file *filp; 470 struct drm_file *filp;
470 /* chunks */ 471 /* chunks */
@@ -660,6 +661,13 @@ struct radeon_asic {
660 void (*hpd_fini)(struct radeon_device *rdev); 661 void (*hpd_fini)(struct radeon_device *rdev);
661 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 662 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
662 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 663 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
664 /* ioctl hw specific callback. Some hw might want to perform special
665 * operation on specific ioctl. For instance on wait idle some hw
666 * might want to perform and HDP flush through MMIO as it seems that
667 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
668 * through ring.
669 */
670 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
663}; 671};
664 672
665/* 673/*
@@ -847,7 +855,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
847 855
848static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 856static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
849{ 857{
850 if (reg < 0x10000) 858 if (reg < rdev->rmmio_size)
851 return readl(((void __iomem *)rdev->rmmio) + reg); 859 return readl(((void __iomem *)rdev->rmmio) + reg);
852 else { 860 else {
853 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 861 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
@@ -857,7 +865,7 @@ static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
857 865
858static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 866static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
859{ 867{
860 if (reg < 0x10000) 868 if (reg < rdev->rmmio_size)
861 writel(v, ((void __iomem *)rdev->rmmio) + reg); 869 writel(v, ((void __iomem *)rdev->rmmio) + reg);
862 else { 870 else {
863 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 871 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
@@ -1017,6 +1025,8 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1017#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) 1025#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1018 1026
1019/* Common functions */ 1027/* Common functions */
1028/* AGP */
1029extern void radeon_agp_disable(struct radeon_device *rdev);
1020extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); 1030extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1021extern int radeon_modeset_init(struct radeon_device *rdev); 1031extern int radeon_modeset_init(struct radeon_device *rdev);
1022extern void radeon_modeset_fini(struct radeon_device *rdev); 1032extern void radeon_modeset_fini(struct radeon_device *rdev);
@@ -1140,6 +1150,7 @@ extern bool r600_card_posted(struct radeon_device *rdev);
1140extern void r600_cp_stop(struct radeon_device *rdev); 1150extern void r600_cp_stop(struct radeon_device *rdev);
1141extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); 1151extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1142extern int r600_cp_resume(struct radeon_device *rdev); 1152extern int r600_cp_resume(struct radeon_device *rdev);
1153extern void r600_cp_fini(struct radeon_device *rdev);
1143extern int r600_count_pipe_bits(uint32_t val); 1154extern int r600_count_pipe_bits(uint32_t val);
1144extern int r600_gart_clear_page(struct radeon_device *rdev, int i); 1155extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1145extern int r600_mc_wait_for_idle(struct radeon_device *rdev); 1156extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
@@ -1160,7 +1171,8 @@ extern int r600_irq_init(struct radeon_device *rdev);
1160extern void r600_irq_fini(struct radeon_device *rdev); 1171extern void r600_irq_fini(struct radeon_device *rdev);
1161extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 1172extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1162extern int r600_irq_set(struct radeon_device *rdev); 1173extern int r600_irq_set(struct radeon_device *rdev);
1163 1174extern void r600_irq_suspend(struct radeon_device *rdev);
1175/* r600 audio */
1164extern int r600_audio_init(struct radeon_device *rdev); 1176extern int r600_audio_init(struct radeon_device *rdev);
1165extern int r600_audio_tmds_index(struct drm_encoder *encoder); 1177extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1166extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 1178extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index 220f454ea9fa..c0681a5556dc 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -144,9 +144,19 @@ int radeon_agp_init(struct radeon_device *rdev)
144 144
145 ret = drm_agp_info(rdev->ddev, &info); 145 ret = drm_agp_info(rdev->ddev, &info);
146 if (ret) { 146 if (ret) {
147 drm_agp_release(rdev->ddev);
147 DRM_ERROR("Unable to get AGP info: %d\n", ret); 148 DRM_ERROR("Unable to get AGP info: %d\n", ret);
148 return ret; 149 return ret;
149 } 150 }
151
152 if (rdev->ddev->agp->agp_info.aper_size < 32) {
153 drm_agp_release(rdev->ddev);
154 dev_warn(rdev->dev, "AGP aperture too small (%zuM) "
155 "need at least 32M, disabling AGP\n",
156 rdev->ddev->agp->agp_info.aper_size);
157 return -EINVAL;
158 }
159
150 mode.mode = info.mode; 160 mode.mode = info.mode;
151 agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode; 161 agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
152 is_v3 = !!(agp_status & RADEON_AGPv3_MODE); 162 is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
@@ -221,6 +231,7 @@ int radeon_agp_init(struct radeon_device *rdev)
221 ret = drm_agp_enable(rdev->ddev, mode); 231 ret = drm_agp_enable(rdev->ddev, mode);
222 if (ret) { 232 if (ret) {
223 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode); 233 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
234 drm_agp_release(rdev->ddev);
224 return ret; 235 return ret;
225 } 236 }
226 237
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index f2fbd2e4e9df..05ee1aeac3fd 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -117,6 +117,7 @@ static struct radeon_asic r100_asic = {
117 .hpd_fini = &r100_hpd_fini, 117 .hpd_fini = &r100_hpd_fini,
118 .hpd_sense = &r100_hpd_sense, 118 .hpd_sense = &r100_hpd_sense,
119 .hpd_set_polarity = &r100_hpd_set_polarity, 119 .hpd_set_polarity = &r100_hpd_set_polarity,
120 .ioctl_wait_idle = NULL,
120}; 121};
121 122
122 123
@@ -176,6 +177,7 @@ static struct radeon_asic r300_asic = {
176 .hpd_fini = &r100_hpd_fini, 177 .hpd_fini = &r100_hpd_fini,
177 .hpd_sense = &r100_hpd_sense, 178 .hpd_sense = &r100_hpd_sense,
178 .hpd_set_polarity = &r100_hpd_set_polarity, 179 .hpd_set_polarity = &r100_hpd_set_polarity,
180 .ioctl_wait_idle = NULL,
179}; 181};
180 182
181/* 183/*
@@ -219,6 +221,7 @@ static struct radeon_asic r420_asic = {
219 .hpd_fini = &r100_hpd_fini, 221 .hpd_fini = &r100_hpd_fini,
220 .hpd_sense = &r100_hpd_sense, 222 .hpd_sense = &r100_hpd_sense,
221 .hpd_set_polarity = &r100_hpd_set_polarity, 223 .hpd_set_polarity = &r100_hpd_set_polarity,
224 .ioctl_wait_idle = NULL,
222}; 225};
223 226
224 227
@@ -267,6 +270,7 @@ static struct radeon_asic rs400_asic = {
267 .hpd_fini = &r100_hpd_fini, 270 .hpd_fini = &r100_hpd_fini,
268 .hpd_sense = &r100_hpd_sense, 271 .hpd_sense = &r100_hpd_sense,
269 .hpd_set_polarity = &r100_hpd_set_polarity, 272 .hpd_set_polarity = &r100_hpd_set_polarity,
273 .ioctl_wait_idle = NULL,
270}; 274};
271 275
272 276
@@ -323,6 +327,7 @@ static struct radeon_asic rs600_asic = {
323 .hpd_fini = &rs600_hpd_fini, 327 .hpd_fini = &rs600_hpd_fini,
324 .hpd_sense = &rs600_hpd_sense, 328 .hpd_sense = &rs600_hpd_sense,
325 .hpd_set_polarity = &rs600_hpd_set_polarity, 329 .hpd_set_polarity = &rs600_hpd_set_polarity,
330 .ioctl_wait_idle = NULL,
326}; 331};
327 332
328 333
@@ -370,6 +375,7 @@ static struct radeon_asic rs690_asic = {
370 .hpd_fini = &rs600_hpd_fini, 375 .hpd_fini = &rs600_hpd_fini,
371 .hpd_sense = &rs600_hpd_sense, 376 .hpd_sense = &rs600_hpd_sense,
372 .hpd_set_polarity = &rs600_hpd_set_polarity, 377 .hpd_set_polarity = &rs600_hpd_set_polarity,
378 .ioctl_wait_idle = NULL,
373}; 379};
374 380
375 381
@@ -421,6 +427,7 @@ static struct radeon_asic rv515_asic = {
421 .hpd_fini = &rs600_hpd_fini, 427 .hpd_fini = &rs600_hpd_fini,
422 .hpd_sense = &rs600_hpd_sense, 428 .hpd_sense = &rs600_hpd_sense,
423 .hpd_set_polarity = &rs600_hpd_set_polarity, 429 .hpd_set_polarity = &rs600_hpd_set_polarity,
430 .ioctl_wait_idle = NULL,
424}; 431};
425 432
426 433
@@ -463,6 +470,7 @@ static struct radeon_asic r520_asic = {
463 .hpd_fini = &rs600_hpd_fini, 470 .hpd_fini = &rs600_hpd_fini,
464 .hpd_sense = &rs600_hpd_sense, 471 .hpd_sense = &rs600_hpd_sense,
465 .hpd_set_polarity = &rs600_hpd_set_polarity, 472 .hpd_set_polarity = &rs600_hpd_set_polarity,
473 .ioctl_wait_idle = NULL,
466}; 474};
467 475
468/* 476/*
@@ -504,6 +512,7 @@ void r600_hpd_fini(struct radeon_device *rdev);
504bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 512bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
505void r600_hpd_set_polarity(struct radeon_device *rdev, 513void r600_hpd_set_polarity(struct radeon_device *rdev,
506 enum radeon_hpd_id hpd); 514 enum radeon_hpd_id hpd);
515extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
507 516
508static struct radeon_asic r600_asic = { 517static struct radeon_asic r600_asic = {
509 .init = &r600_init, 518 .init = &r600_init,
@@ -538,6 +547,7 @@ static struct radeon_asic r600_asic = {
538 .hpd_fini = &r600_hpd_fini, 547 .hpd_fini = &r600_hpd_fini,
539 .hpd_sense = &r600_hpd_sense, 548 .hpd_sense = &r600_hpd_sense,
540 .hpd_set_polarity = &r600_hpd_set_polarity, 549 .hpd_set_polarity = &r600_hpd_set_polarity,
550 .ioctl_wait_idle = r600_ioctl_wait_idle,
541}; 551};
542 552
543/* 553/*
@@ -582,6 +592,7 @@ static struct radeon_asic rv770_asic = {
582 .hpd_fini = &r600_hpd_fini, 592 .hpd_fini = &r600_hpd_fini,
583 .hpd_sense = &r600_hpd_sense, 593 .hpd_sense = &r600_hpd_sense,
584 .hpd_set_polarity = &r600_hpd_set_polarity, 594 .hpd_set_polarity = &r600_hpd_set_polarity,
595 .ioctl_wait_idle = r600_ioctl_wait_idle,
585}; 596};
586 597
587#endif 598#endif
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index 812f24dbc2a8..73c4405bf42f 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -56,7 +56,7 @@ uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
56 else if (post_div == 3) 56 else if (post_div == 3)
57 sclk >>= 2; 57 sclk >>= 2;
58 else if (post_div == 4) 58 else if (post_div == 4)
59 sclk >>= 4; 59 sclk >>= 3;
60 60
61 return sclk; 61 return sclk;
62} 62}
@@ -86,7 +86,7 @@ uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
86 else if (post_div == 3) 86 else if (post_div == 3)
87 mclk >>= 2; 87 mclk >>= 2;
88 else if (post_div == 4) 88 else if (post_div == 4)
89 mclk >>= 4; 89 mclk >>= 3;
90 90
91 return mclk; 91 return mclk;
92} 92}
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 7914455c96ca..e7b19440102e 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -687,6 +687,9 @@ radeon_combios_get_tv_info(struct radeon_device *rdev)
687 uint16_t tv_info; 687 uint16_t tv_info;
688 enum radeon_tv_std tv_std = TV_STD_NTSC; 688 enum radeon_tv_std tv_std = TV_STD_NTSC;
689 689
690 if (rdev->bios == NULL)
691 return tv_std;
692
690 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 693 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
691 if (tv_info) { 694 if (tv_info) {
692 if (RBIOS8(tv_info + 6) == 'T') { 695 if (RBIOS8(tv_info + 6) == 'T') {
@@ -968,8 +971,7 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
968 lvds->native_mode.vdisplay); 971 lvds->native_mode.vdisplay);
969 972
970 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 973 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
971 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0) 974 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
972 lvds->panel_vcc_delay = 2000;
973 975
974 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 976 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
975 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 977 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 9da10dd5df80..2d8e5a70f284 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -900,10 +900,18 @@ static void radeon_dvi_force(struct drm_connector *connector)
900static int radeon_dvi_mode_valid(struct drm_connector *connector, 900static int radeon_dvi_mode_valid(struct drm_connector *connector,
901 struct drm_display_mode *mode) 901 struct drm_display_mode *mode)
902{ 902{
903 struct drm_device *dev = connector->dev;
904 struct radeon_device *rdev = dev->dev_private;
903 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 905 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
904 906
905 /* XXX check mode bandwidth */ 907 /* XXX check mode bandwidth */
906 908
909 /* clocks over 135 MHz have heat issues with DVI on RV100 */
910 if (radeon_connector->use_digital &&
911 (rdev->family == CHIP_RV100) &&
912 (mode->clock > 135000))
913 return MODE_CLOCK_HIGH;
914
907 if (radeon_connector->use_digital && (mode->clock > 165000)) { 915 if (radeon_connector->use_digital && (mode->clock > 165000)) {
908 if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 916 if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
909 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 917 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
@@ -1335,7 +1343,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
1335 radeon_connector->dac_load_detect = false; 1343 radeon_connector->dac_load_detect = false;
1336 drm_connector_attach_property(&radeon_connector->base, 1344 drm_connector_attach_property(&radeon_connector->base,
1337 rdev->mode_info.load_detect_property, 1345 rdev->mode_info.load_detect_property,
1338 1); 1346 radeon_connector->dac_load_detect);
1339 drm_connector_attach_property(&radeon_connector->base, 1347 drm_connector_attach_property(&radeon_connector->base,
1340 rdev->mode_info.tv_std_property, 1348 rdev->mode_info.tv_std_property,
1341 radeon_combios_get_tv_info(rdev)); 1349 radeon_combios_get_tv_info(rdev));
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 65590a0f1d93..1190148cf5e6 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -189,7 +189,7 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
189{ 189{
190 unsigned i; 190 unsigned i;
191 191
192 if (error) { 192 if (error && parser->ib) {
193 radeon_bo_list_unvalidate(&parser->validated, 193 radeon_bo_list_unvalidate(&parser->validated,
194 parser->ib->fence); 194 parser->ib->fence);
195 } else { 195 } else {
@@ -231,6 +231,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
231 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 231 memset(&parser, 0, sizeof(struct radeon_cs_parser));
232 parser.filp = filp; 232 parser.filp = filp;
233 parser.rdev = rdev; 233 parser.rdev = rdev;
234 parser.dev = rdev->dev;
234 r = radeon_cs_parser_init(&parser, data); 235 r = radeon_cs_parser_init(&parser, data);
235 if (r) { 236 if (r) {
236 DRM_ERROR("Failed to initialize parser !\n"); 237 DRM_ERROR("Failed to initialize parser !\n");
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 0c51f8e46613..768b1509fa03 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -544,6 +544,7 @@ void radeon_agp_disable(struct radeon_device *rdev)
544 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 544 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
545 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 545 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
546 } 546 }
547 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
547} 548}
548 549
549void radeon_check_arguments(struct radeon_device *rdev) 550void radeon_check_arguments(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 0ec491ead2ff..6a92f994cc26 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -357,7 +357,8 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
357 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 357 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
358 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { 358 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
359 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 359 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
360 if (dig->dp_i2c_bus) 360 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
361 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
361 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); 362 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
362 } 363 }
363 if (!radeon_connector->ddc_bus) 364 if (!radeon_connector->ddc_bus)
@@ -410,11 +411,12 @@ void radeon_compute_pll(struct radeon_pll *pll,
410 uint32_t *fb_div_p, 411 uint32_t *fb_div_p,
411 uint32_t *frac_fb_div_p, 412 uint32_t *frac_fb_div_p,
412 uint32_t *ref_div_p, 413 uint32_t *ref_div_p,
413 uint32_t *post_div_p, 414 uint32_t *post_div_p)
414 int flags)
415{ 415{
416 uint32_t min_ref_div = pll->min_ref_div; 416 uint32_t min_ref_div = pll->min_ref_div;
417 uint32_t max_ref_div = pll->max_ref_div; 417 uint32_t max_ref_div = pll->max_ref_div;
418 uint32_t min_post_div = pll->min_post_div;
419 uint32_t max_post_div = pll->max_post_div;
418 uint32_t min_fractional_feed_div = 0; 420 uint32_t min_fractional_feed_div = 0;
419 uint32_t max_fractional_feed_div = 0; 421 uint32_t max_fractional_feed_div = 0;
420 uint32_t best_vco = pll->best_vco; 422 uint32_t best_vco = pll->best_vco;
@@ -430,7 +432,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
430 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 432 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
431 freq = freq * 1000; 433 freq = freq * 1000;
432 434
433 if (flags & RADEON_PLL_USE_REF_DIV) 435 if (pll->flags & RADEON_PLL_USE_REF_DIV)
434 min_ref_div = max_ref_div = pll->reference_div; 436 min_ref_div = max_ref_div = pll->reference_div;
435 else { 437 else {
436 while (min_ref_div < max_ref_div-1) { 438 while (min_ref_div < max_ref_div-1) {
@@ -445,19 +447,22 @@ void radeon_compute_pll(struct radeon_pll *pll,
445 } 447 }
446 } 448 }
447 449
448 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { 450 if (pll->flags & RADEON_PLL_USE_POST_DIV)
451 min_post_div = max_post_div = pll->post_div;
452
453 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
449 min_fractional_feed_div = pll->min_frac_feedback_div; 454 min_fractional_feed_div = pll->min_frac_feedback_div;
450 max_fractional_feed_div = pll->max_frac_feedback_div; 455 max_fractional_feed_div = pll->max_frac_feedback_div;
451 } 456 }
452 457
453 for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { 458 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
454 uint32_t ref_div; 459 uint32_t ref_div;
455 460
456 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 461 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
457 continue; 462 continue;
458 463
459 /* legacy radeons only have a few post_divs */ 464 /* legacy radeons only have a few post_divs */
460 if (flags & RADEON_PLL_LEGACY) { 465 if (pll->flags & RADEON_PLL_LEGACY) {
461 if ((post_div == 5) || 466 if ((post_div == 5) ||
462 (post_div == 7) || 467 (post_div == 7) ||
463 (post_div == 9) || 468 (post_div == 9) ||
@@ -504,7 +509,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
504 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 509 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
505 current_freq = radeon_div(tmp, ref_div * post_div); 510 current_freq = radeon_div(tmp, ref_div * post_div);
506 511
507 if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 512 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
508 error = freq - current_freq; 513 error = freq - current_freq;
509 error = error < 0 ? 0xffffffff : error; 514 error = error < 0 ? 0xffffffff : error;
510 } else 515 } else
@@ -531,12 +536,12 @@ void radeon_compute_pll(struct radeon_pll *pll,
531 best_freq = current_freq; 536 best_freq = current_freq;
532 best_error = error; 537 best_error = error;
533 best_vco_diff = vco_diff; 538 best_vco_diff = vco_diff;
534 } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 539 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
535 ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 540 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
536 ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 541 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
537 ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 542 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
538 ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 543 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
539 ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 544 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
540 best_post_div = post_div; 545 best_post_div = post_div;
541 best_ref_div = ref_div; 546 best_ref_div = ref_div;
542 best_feedback_div = feedback_div; 547 best_feedback_div = feedback_div;
@@ -572,8 +577,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
572 uint32_t *fb_div_p, 577 uint32_t *fb_div_p,
573 uint32_t *frac_fb_div_p, 578 uint32_t *frac_fb_div_p,
574 uint32_t *ref_div_p, 579 uint32_t *ref_div_p,
575 uint32_t *post_div_p, 580 uint32_t *post_div_p)
576 int flags)
577{ 581{
578 fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq; 582 fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq;
579 fixed20_12 pll_out_max, pll_out_min; 583 fixed20_12 pll_out_max, pll_out_min;
@@ -667,7 +671,6 @@ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
667 radeonfb_remove(dev, fb); 671 radeonfb_remove(dev, fb);
668 672
669 if (radeon_fb->obj) { 673 if (radeon_fb->obj) {
670 radeon_gem_object_unpin(radeon_fb->obj);
671 mutex_lock(&dev->struct_mutex); 674 mutex_lock(&dev->struct_mutex);
672 drm_gem_object_unreference(radeon_fb->obj); 675 drm_gem_object_unreference(radeon_fb->obj);
673 mutex_unlock(&dev->struct_mutex); 676 mutex_unlock(&dev->struct_mutex);
@@ -715,7 +718,11 @@ radeon_user_framebuffer_create(struct drm_device *dev,
715 struct drm_gem_object *obj; 718 struct drm_gem_object *obj;
716 719
717 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); 720 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
718 721 if (obj == NULL) {
722 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
723 "can't create framebuffer\n", mode_cmd->handle);
724 return NULL;
725 }
719 return radeon_framebuffer_create(dev, mode_cmd, obj); 726 return radeon_framebuffer_create(dev, mode_cmd, obj);
720} 727}
721 728
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 82eb551970b9..3c91724457ca 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -156,6 +156,26 @@ radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t
156 return ret; 156 return ret;
157} 157}
158 158
159static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160{
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178}
159void 179void
160radeon_link_encoder_connector(struct drm_device *dev) 180radeon_link_encoder_connector(struct drm_device *dev)
161{ 181{
@@ -202,7 +222,7 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder)
202 222
203 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
204 radeon_connector = to_radeon_connector(connector); 224 radeon_connector = to_radeon_connector(connector);
205 if (radeon_encoder->devices & radeon_connector->devices) 225 if (radeon_encoder->active_device & radeon_connector->devices)
206 return connector; 226 return connector;
207 } 227 }
208 return NULL; 228 return NULL;
@@ -676,31 +696,11 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
676 696
677 memset(&args, 0, sizeof(args)); 697 memset(&args, 0, sizeof(args));
678 698
679 if (ASIC_IS_DCE32(rdev)) { 699 if (dig->dig_encoder)
680 if (dig->dig_block) 700 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
681 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 701 else
682 else 702 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
683 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 703 num = dig->dig_encoder + 1;
684 num = dig->dig_block + 1;
685 } else {
686 switch (radeon_encoder->encoder_id) {
687 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
688 /* XXX doesn't really matter which dig encoder we pick as long as it's
689 * not already in use
690 */
691 if (dig_connector->linkb)
692 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
693 else
694 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
695 num = 1;
696 break;
697 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
698 /* Only dig2 encoder can drive LVTMA */
699 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
700 num = 2;
701 break;
702 }
703 }
704 704
705 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); 705 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
706 706
@@ -822,7 +822,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
822 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 822 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
823 } 823 }
824 if (ASIC_IS_DCE32(rdev)) { 824 if (ASIC_IS_DCE32(rdev)) {
825 if (dig->dig_block) 825 if (dig->dig_encoder == 1)
826 args.v2.acConfig.ucEncoderSel = 1; 826 args.v2.acConfig.ucEncoderSel = 1;
827 if (dig_connector->linkb) 827 if (dig_connector->linkb)
828 args.v2.acConfig.ucLinkSel = 1; 828 args.v2.acConfig.ucLinkSel = 1;
@@ -849,17 +849,16 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
849 args.v2.acConfig.fCoherentMode = 1; 849 args.v2.acConfig.fCoherentMode = 1;
850 } 850 }
851 } else { 851 } else {
852
852 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 853 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
853 854
855 if (dig->dig_encoder)
856 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
857 else
858 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
859
854 switch (radeon_encoder->encoder_id) { 860 switch (radeon_encoder->encoder_id) {
855 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 861 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
856 /* XXX doesn't really matter which dig encoder we pick as long as it's
857 * not already in use
858 */
859 if (dig_connector->linkb)
860 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
861 else
862 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
863 if (rdev->flags & RADEON_IS_IGP) { 862 if (rdev->flags & RADEON_IS_IGP) {
864 if (radeon_encoder->pixel_clock > 165000) { 863 if (radeon_encoder->pixel_clock > 165000) {
865 if (dig_connector->igp_lane_info & 0x3) 864 if (dig_connector->igp_lane_info & 0x3)
@@ -878,10 +877,6 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
878 } 877 }
879 } 878 }
880 break; 879 break;
881 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
882 /* Only dig2 encoder can drive LVTMA */
883 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
884 break;
885 } 880 }
886 881
887 if (radeon_encoder->pixel_clock > 165000) 882 if (radeon_encoder->pixel_clock > 165000)
@@ -1046,6 +1041,7 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1046 union crtc_sourc_param args; 1041 union crtc_sourc_param args;
1047 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1042 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1048 uint8_t frev, crev; 1043 uint8_t frev, crev;
1044 struct radeon_encoder_atom_dig *dig;
1049 1045
1050 memset(&args, 0, sizeof(args)); 1046 memset(&args, 0, sizeof(args));
1051 1047
@@ -1109,40 +1105,16 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1109 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1105 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1110 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1111 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1107 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1112 if (ASIC_IS_DCE32(rdev)) { 1108 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1113 if (radeon_crtc->crtc_id) 1109 dig = radeon_encoder->enc_priv;
1114 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1110 if (dig->dig_encoder)
1115 else 1111 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1116 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1112 else
1117 } else { 1113 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1118 struct drm_connector *connector;
1119 struct radeon_connector *radeon_connector;
1120 struct radeon_connector_atom_dig *dig_connector;
1121
1122 connector = radeon_get_connector_for_encoder(encoder);
1123 if (!connector)
1124 return;
1125 radeon_connector = to_radeon_connector(connector);
1126 if (!radeon_connector->con_priv)
1127 return;
1128 dig_connector = radeon_connector->con_priv;
1129
1130 /* XXX doesn't really matter which dig encoder we pick as long as it's
1131 * not already in use
1132 */
1133 if (dig_connector->linkb)
1134 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1135 else
1136 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1137 }
1138 break; 1114 break;
1139 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1115 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1140 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1116 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1141 break; 1117 break;
1142 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1143 /* Only dig2 encoder can drive LVTMA */
1144 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1145 break;
1146 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1118 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1147 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1119 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1148 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1120 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
@@ -1202,6 +1174,47 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1202 } 1174 }
1203} 1175}
1204 1176
1177static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1178{
1179 struct drm_device *dev = encoder->dev;
1180 struct radeon_device *rdev = dev->dev_private;
1181 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1182 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1183 struct drm_encoder *test_encoder;
1184 struct radeon_encoder_atom_dig *dig;
1185 uint32_t dig_enc_in_use = 0;
1186 /* on DCE32 and encoder can driver any block so just crtc id */
1187 if (ASIC_IS_DCE32(rdev)) {
1188 return radeon_crtc->crtc_id;
1189 }
1190
1191 /* on DCE3 - LVTMA can only be driven by DIGB */
1192 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1193 struct radeon_encoder *radeon_test_encoder;
1194
1195 if (encoder == test_encoder)
1196 continue;
1197
1198 if (!radeon_encoder_is_digital(test_encoder))
1199 continue;
1200
1201 radeon_test_encoder = to_radeon_encoder(test_encoder);
1202 dig = radeon_test_encoder->enc_priv;
1203
1204 if (dig->dig_encoder >= 0)
1205 dig_enc_in_use |= (1 << dig->dig_encoder);
1206 }
1207
1208 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1209 if (dig_enc_in_use & 0x2)
1210 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1211 return 1;
1212 }
1213 if (!(dig_enc_in_use & 1))
1214 return 0;
1215 return 1;
1216}
1217
1205static void 1218static void
1206radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 1219radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1207 struct drm_display_mode *mode, 1220 struct drm_display_mode *mode,
@@ -1214,12 +1227,9 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1214 1227
1215 if (radeon_encoder->active_device & 1228 if (radeon_encoder->active_device &
1216 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) { 1229 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1217 if (radeon_encoder->enc_priv) { 1230 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1218 struct radeon_encoder_atom_dig *dig; 1231 if (dig)
1219 1232 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1220 dig = radeon_encoder->enc_priv;
1221 dig->dig_block = radeon_crtc->crtc_id;
1222 }
1223 } 1233 }
1224 radeon_encoder->pixel_clock = adjusted_mode->clock; 1234 radeon_encoder->pixel_clock = adjusted_mode->clock;
1225 1235
@@ -1379,7 +1389,13 @@ static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1379static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 1389static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1380{ 1390{
1381 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1391 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1392 struct radeon_encoder_atom_dig *dig;
1382 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 1393 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1394
1395 if (radeon_encoder_is_digital(encoder)) {
1396 dig = radeon_encoder->enc_priv;
1397 dig->dig_encoder = -1;
1398 }
1383 radeon_encoder->active_device = 0; 1399 radeon_encoder->active_device = 0;
1384} 1400}
1385 1401
@@ -1436,6 +1452,7 @@ radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1436 1452
1437 /* coherent mode by default */ 1453 /* coherent mode by default */
1438 dig->coherent_mode = true; 1454 dig->coherent_mode = true;
1455 dig->dig_encoder = -1;
1439 1456
1440 return dig; 1457 return dig;
1441} 1458}
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 66055b3d8668..3ba213d1b06c 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -59,7 +59,7 @@ static struct fb_ops radeonfb_ops = {
59}; 59};
60 60
61/** 61/**
62 * Curretly it is assumed that the old framebuffer is reused. 62 * Currently it is assumed that the old framebuffer is reused.
63 * 63 *
64 * LOCKING 64 * LOCKING
65 * caller should hold the mode config lock. 65 * caller should hold the mode config lock.
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 0e1325e18534..db8e9a355a01 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -308,6 +308,9 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
308 } 308 }
309 robj = gobj->driver_private; 309 robj = gobj->driver_private;
310 r = radeon_bo_wait(robj, NULL, false); 310 r = radeon_bo_wait(robj, NULL, false);
311 /* callback hw specific functions if any */
312 if (robj->rdev->asic->ioctl_wait_idle)
313 robj->rdev->asic->ioctl_wait_idle(robj->rdev, robj);
311 mutex_lock(&dev->struct_mutex); 314 mutex_lock(&dev->struct_mutex);
312 drm_gem_object_unreference(gobj); 315 drm_gem_object_unreference(gobj);
313 mutex_unlock(&dev->struct_mutex); 316 mutex_unlock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index cc27485a07ad..b6d8081e1246 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -339,69 +339,6 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
339 } 339 }
340} 340}
341 341
342/* properly set crtc bpp when using atombios */
343void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
344{
345 struct drm_device *dev = crtc->dev;
346 struct radeon_device *rdev = dev->dev_private;
347 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
348 int format;
349 uint32_t crtc_gen_cntl;
350 uint32_t disp_merge_cntl;
351 uint32_t crtc_pitch;
352
353 switch (crtc->fb->bits_per_pixel) {
354 case 8:
355 format = 2;
356 break;
357 case 15: /* 555 */
358 format = 3;
359 break;
360 case 16: /* 565 */
361 format = 4;
362 break;
363 case 24: /* RGB */
364 format = 5;
365 break;
366 case 32: /* xRGB */
367 format = 6;
368 break;
369 default:
370 return;
371 }
372
373 crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
374 ((crtc->fb->bits_per_pixel * 8) - 1)) /
375 (crtc->fb->bits_per_pixel * 8));
376 crtc_pitch |= crtc_pitch << 16;
377
378 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
379
380 switch (radeon_crtc->crtc_id) {
381 case 0:
382 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
383 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
384 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
385
386 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
387 crtc_gen_cntl |= (format << 8);
388 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
389 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
390 break;
391 case 1:
392 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
393 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
394 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
395
396 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
397 crtc_gen_cntl |= (format << 8);
398 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
399 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
400 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
401 break;
402 }
403}
404
405int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 342int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
406 struct drm_framebuffer *old_fb) 343 struct drm_framebuffer *old_fb)
407{ 344{
@@ -755,7 +692,6 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
755 uint32_t post_divider = 0; 692 uint32_t post_divider = 0;
756 uint32_t freq = 0; 693 uint32_t freq = 0;
757 uint8_t pll_gain; 694 uint8_t pll_gain;
758 int pll_flags = RADEON_PLL_LEGACY;
759 bool use_bios_divs = false; 695 bool use_bios_divs = false;
760 /* PLL registers */ 696 /* PLL registers */
761 uint32_t pll_ref_div = 0; 697 uint32_t pll_ref_div = 0;
@@ -789,10 +725,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
789 else 725 else
790 pll = &rdev->clock.p1pll; 726 pll = &rdev->clock.p1pll;
791 727
728 pll->flags = RADEON_PLL_LEGACY;
729
792 if (mode->clock > 200000) /* range limits??? */ 730 if (mode->clock > 200000) /* range limits??? */
793 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 731 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
794 else 732 else
795 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 733 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
796 734
797 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 735 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
798 if (encoder->crtc == crtc) { 736 if (encoder->crtc == crtc) {
@@ -804,7 +742,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
804 } 742 }
805 743
806 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 744 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
807 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 745 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
808 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 746 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
809 if (!rdev->is_atom_bios) { 747 if (!rdev->is_atom_bios) {
810 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 748 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
@@ -819,7 +757,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
819 } 757 }
820 } 758 }
821 } 759 }
822 pll_flags |= RADEON_PLL_USE_REF_DIV; 760 pll->flags |= RADEON_PLL_USE_REF_DIV;
823 } 761 }
824 } 762 }
825 } 763 }
@@ -829,8 +767,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
829 if (!use_bios_divs) { 767 if (!use_bios_divs) {
830 radeon_compute_pll(pll, mode->clock, 768 radeon_compute_pll(pll, mode->clock,
831 &freq, &feedback_div, &frac_fb_div, 769 &freq, &feedback_div, &frac_fb_div,
832 &reference_div, &post_divider, 770 &reference_div, &post_divider);
833 pll_flags);
834 771
835 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 772 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
836 if (post_div->divider == post_divider) 773 if (post_div->divider == post_divider)
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 981508ff7037..38e45e231ef5 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -46,6 +46,7 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
46 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 46 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
47 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; 47 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
48 int panel_pwr_delay = 2000; 48 int panel_pwr_delay = 2000;
49 bool is_mac = false;
49 DRM_DEBUG("\n"); 50 DRM_DEBUG("\n");
50 51
51 if (radeon_encoder->enc_priv) { 52 if (radeon_encoder->enc_priv) {
@@ -58,6 +59,15 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
58 } 59 }
59 } 60 }
60 61
62 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
63 * Taken from radeonfb.
64 */
65 if ((rdev->mode_info.connector_table == CT_IBOOK) ||
66 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
67 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
68 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
69 is_mac = true;
70
61 switch (mode) { 71 switch (mode) {
62 case DRM_MODE_DPMS_ON: 72 case DRM_MODE_DPMS_ON:
63 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); 73 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
@@ -74,6 +84,8 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
74 84
75 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 85 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
76 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON); 86 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
87 if (is_mac)
88 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
77 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS); 89 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
78 udelay(panel_pwr_delay * 1000); 90 udelay(panel_pwr_delay * 1000);
79 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 91 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
@@ -85,7 +97,14 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
85 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); 97 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
86 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 98 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
87 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 99 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
88 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); 100 if (is_mac) {
101 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
102 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
103 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
104 } else {
105 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
106 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
107 }
89 udelay(panel_pwr_delay * 1000); 108 udelay(panel_pwr_delay * 1000);
90 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 109 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
91 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 110 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 91cb041cb40d..e81b2aeb6a8f 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -125,16 +125,24 @@ struct radeon_tmds_pll {
125#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 125#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
126#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 126#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
127#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 127#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
128#define RADEON_PLL_USE_POST_DIV (1 << 12)
128 129
129struct radeon_pll { 130struct radeon_pll {
130 uint16_t reference_freq; 131 /* reference frequency */
131 uint16_t reference_div; 132 uint32_t reference_freq;
133
134 /* fixed dividers */
135 uint32_t reference_div;
136 uint32_t post_div;
137
138 /* pll in/out limits */
132 uint32_t pll_in_min; 139 uint32_t pll_in_min;
133 uint32_t pll_in_max; 140 uint32_t pll_in_max;
134 uint32_t pll_out_min; 141 uint32_t pll_out_min;
135 uint32_t pll_out_max; 142 uint32_t pll_out_max;
136 uint16_t xclk; 143 uint32_t best_vco;
137 144
145 /* divider limits */
138 uint32_t min_ref_div; 146 uint32_t min_ref_div;
139 uint32_t max_ref_div; 147 uint32_t max_ref_div;
140 uint32_t min_post_div; 148 uint32_t min_post_div;
@@ -143,7 +151,12 @@ struct radeon_pll {
143 uint32_t max_feedback_div; 151 uint32_t max_feedback_div;
144 uint32_t min_frac_feedback_div; 152 uint32_t min_frac_feedback_div;
145 uint32_t max_frac_feedback_div; 153 uint32_t max_frac_feedback_div;
146 uint32_t best_vco; 154
155 /* flags for the current clock */
156 uint32_t flags;
157
158 /* pll id */
159 uint32_t id;
147}; 160};
148 161
149struct radeon_i2c_chan { 162struct radeon_i2c_chan {
@@ -286,7 +299,7 @@ struct radeon_atom_ss {
286struct radeon_encoder_atom_dig { 299struct radeon_encoder_atom_dig {
287 /* atom dig */ 300 /* atom dig */
288 bool coherent_mode; 301 bool coherent_mode;
289 int dig_block; 302 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
290 /* atom lvds */ 303 /* atom lvds */
291 uint32_t lvds_misc; 304 uint32_t lvds_misc;
292 uint16_t panel_pwr_delay; 305 uint16_t panel_pwr_delay;
@@ -417,8 +430,7 @@ extern void radeon_compute_pll(struct radeon_pll *pll,
417 uint32_t *fb_div_p, 430 uint32_t *fb_div_p,
418 uint32_t *frac_fb_div_p, 431 uint32_t *frac_fb_div_p,
419 uint32_t *ref_div_p, 432 uint32_t *ref_div_p,
420 uint32_t *post_div_p, 433 uint32_t *post_div_p);
421 int flags);
422 434
423extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 435extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
424 uint64_t freq, 436 uint64_t freq,
@@ -426,8 +438,7 @@ extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
426 uint32_t *fb_div_p, 438 uint32_t *fb_div_p,
427 uint32_t *frac_fb_div_p, 439 uint32_t *frac_fb_div_p,
428 uint32_t *ref_div_p, 440 uint32_t *ref_div_p,
429 uint32_t *post_div_p, 441 uint32_t *post_div_p);
430 int flags);
431 442
432extern void radeon_setup_encoder_clones(struct drm_device *dev); 443extern void radeon_setup_encoder_clones(struct drm_device *dev);
433 444
@@ -453,7 +464,6 @@ extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
453 464
454extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 465extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
455 struct drm_framebuffer *old_fb); 466 struct drm_framebuffer *old_fb);
456extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);
457 467
458extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 468extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
459 struct drm_file *file_priv, 469 struct drm_file *file_priv,
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 4e636de877b2..d72a71bff218 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -220,7 +220,8 @@ int radeon_bo_unpin(struct radeon_bo *bo)
220 220
221int radeon_bo_evict_vram(struct radeon_device *rdev) 221int radeon_bo_evict_vram(struct radeon_device *rdev)
222{ 222{
223 if (rdev->flags & RADEON_IS_IGP) { 223 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
224 if (0 && (rdev->flags & RADEON_IS_IGP)) {
224 if (rdev->mc.igp_sideport_enabled == false) 225 if (rdev->mc.igp_sideport_enabled == false)
225 /* Useless to evict on IGP chips */ 226 /* Useless to evict on IGP chips */
226 return 0; 227 return 0;
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index 38537d971a3e..067167cb39ca 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -1950,7 +1950,7 @@ static void radeon_apply_surface_regs(int surf_index,
1950 * Note that refcount can be at most 2, since during a free refcount=3 1950 * Note that refcount can be at most 2, since during a free refcount=3
1951 * might mean we have to allocate a new surface which might not always 1951 * might mean we have to allocate a new surface which might not always
1952 * be available. 1952 * be available.
1953 * For example : we allocate three contigous surfaces ABC. If B is 1953 * For example : we allocate three contiguous surfaces ABC. If B is
1954 * freed, we suddenly need two surfaces to store A and C, which might 1954 * freed, we suddenly need two surfaces to store A and C, which might
1955 * not always be available. 1955 * not always be available.
1956 */ 1956 */
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index a00450743d60..58b5adf974ca 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -215,7 +215,10 @@ static void radeon_evict_flags(struct ttm_buffer_object *bo,
215 rbo = container_of(bo, struct radeon_bo, tbo); 215 rbo = container_of(bo, struct radeon_bo, tbo);
216 switch (bo->mem.mem_type) { 216 switch (bo->mem.mem_type) {
217 case TTM_PL_VRAM: 217 case TTM_PL_VRAM:
218 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 218 if (rbo->rdev->cp.ready == false)
219 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
220 else
221 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
219 break; 222 break;
220 case TTM_PL_TT: 223 case TTM_PL_TT:
221 default: 224 default:
@@ -406,7 +409,7 @@ static int radeon_bo_move(struct ttm_buffer_object *bo,
406 new_mem->mem_type == TTM_PL_SYSTEM) || 409 new_mem->mem_type == TTM_PL_SYSTEM) ||
407 (old_mem->mem_type == TTM_PL_SYSTEM && 410 (old_mem->mem_type == TTM_PL_SYSTEM &&
408 new_mem->mem_type == TTM_PL_TT)) { 411 new_mem->mem_type == TTM_PL_TT)) {
409 /* bind is enought */ 412 /* bind is enough */
410 radeon_move_null(bo, new_mem); 413 radeon_move_null(bo, new_mem);
411 return 0; 414 return 0;
412 } 415 }
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r200 b/drivers/gpu/drm/radeon/reg_srcs/r200
index 6021c8849a16..c29ac434ac9c 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r200
+++ b/drivers/gpu/drm/radeon/reg_srcs/r200
@@ -91,6 +91,8 @@ r200 0x3294
910x22b8 SE_TCL_TEX_CYL_WRAP_CTL 910x22b8 SE_TCL_TEX_CYL_WRAP_CTL
920x22c0 SE_TCL_UCP_VERT_BLEND_CNTL 920x22c0 SE_TCL_UCP_VERT_BLEND_CNTL
930x22c4 SE_TCL_POINT_SPRITE_CNTL 930x22c4 SE_TCL_POINT_SPRITE_CNTL
940x22d0 SE_PVS_CNTL
950x22d4 SE_PVS_CONST_CNTL
940x2648 RE_POINTSIZE 960x2648 RE_POINTSIZE
950x26c0 RE_TOP_LEFT 970x26c0 RE_TOP_LEFT
960x26c4 RE_MISC 980x26c4 RE_MISC
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r420 b/drivers/gpu/drm/radeon/reg_srcs/r420
new file mode 100644
index 000000000000..989f7a020832
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r420
@@ -0,0 +1,795 @@
1r420 0x4f60
20x1434 SRC_Y_X
30x1438 DST_Y_X
40x143C DST_HEIGHT_WIDTH
50x146C DP_GUI_MASTER_CNTL
60x1474 BRUSH_Y_X
70x1478 DP_BRUSH_BKGD_CLR
80x147C DP_BRUSH_FRGD_CLR
90x1480 BRUSH_DATA0
100x1484 BRUSH_DATA1
110x1598 DST_WIDTH_HEIGHT
120x15C0 CLR_CMP_CNTL
130x15C4 CLR_CMP_CLR_SRC
140x15C8 CLR_CMP_CLR_DST
150x15CC CLR_CMP_MSK
160x15D8 DP_SRC_FRGD_CLR
170x15DC DP_SRC_BKGD_CLR
180x1600 DST_LINE_START
190x1604 DST_LINE_END
200x1608 DST_LINE_PATCOUNT
210x16C0 DP_CNTL
220x16CC DP_WRITE_MSK
230x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
240x16E8 DEFAULT_SC_BOTTOM_RIGHT
250x16EC SC_TOP_LEFT
260x16F0 SC_BOTTOM_RIGHT
270x16F4 SRC_SC_BOTTOM_RIGHT
280x1714 DSTCACHE_CTLSTAT
290x1720 WAIT_UNTIL
300x172C RBBM_GUICNTL
310x1D98 VAP_VPORT_XSCALE
320x1D9C VAP_VPORT_XOFFSET
330x1DA0 VAP_VPORT_YSCALE
340x1DA4 VAP_VPORT_YOFFSET
350x1DA8 VAP_VPORT_ZSCALE
360x1DAC VAP_VPORT_ZOFFSET
370x2080 VAP_CNTL
380x2090 VAP_OUT_VTX_FMT_0
390x2094 VAP_OUT_VTX_FMT_1
400x20B0 VAP_VTE_CNTL
410x2138 VAP_VF_MIN_VTX_INDX
420x2140 VAP_CNTL_STATUS
430x2150 VAP_PROG_STREAM_CNTL_0
440x2154 VAP_PROG_STREAM_CNTL_1
450x2158 VAP_PROG_STREAM_CNTL_2
460x215C VAP_PROG_STREAM_CNTL_3
470x2160 VAP_PROG_STREAM_CNTL_4
480x2164 VAP_PROG_STREAM_CNTL_5
490x2168 VAP_PROG_STREAM_CNTL_6
500x216C VAP_PROG_STREAM_CNTL_7
510x2180 VAP_VTX_STATE_CNTL
520x2184 VAP_VSM_VTX_ASSM
530x2188 VAP_VTX_STATE_IND_REG_0
540x218C VAP_VTX_STATE_IND_REG_1
550x2190 VAP_VTX_STATE_IND_REG_2
560x2194 VAP_VTX_STATE_IND_REG_3
570x2198 VAP_VTX_STATE_IND_REG_4
580x219C VAP_VTX_STATE_IND_REG_5
590x21A0 VAP_VTX_STATE_IND_REG_6
600x21A4 VAP_VTX_STATE_IND_REG_7
610x21A8 VAP_VTX_STATE_IND_REG_8
620x21AC VAP_VTX_STATE_IND_REG_9
630x21B0 VAP_VTX_STATE_IND_REG_10
640x21B4 VAP_VTX_STATE_IND_REG_11
650x21B8 VAP_VTX_STATE_IND_REG_12
660x21BC VAP_VTX_STATE_IND_REG_13
670x21C0 VAP_VTX_STATE_IND_REG_14
680x21C4 VAP_VTX_STATE_IND_REG_15
690x21DC VAP_PSC_SGN_NORM_CNTL
700x21E0 VAP_PROG_STREAM_CNTL_EXT_0
710x21E4 VAP_PROG_STREAM_CNTL_EXT_1
720x21E8 VAP_PROG_STREAM_CNTL_EXT_2
730x21EC VAP_PROG_STREAM_CNTL_EXT_3
740x21F0 VAP_PROG_STREAM_CNTL_EXT_4
750x21F4 VAP_PROG_STREAM_CNTL_EXT_5
760x21F8 VAP_PROG_STREAM_CNTL_EXT_6
770x21FC VAP_PROG_STREAM_CNTL_EXT_7
780x2200 VAP_PVS_VECTOR_INDX_REG
790x2204 VAP_PVS_VECTOR_DATA_REG
800x2208 VAP_PVS_VECTOR_DATA_REG_128
810x221C VAP_CLIP_CNTL
820x2220 VAP_GB_VERT_CLIP_ADJ
830x2224 VAP_GB_VERT_DISC_ADJ
840x2228 VAP_GB_HORZ_CLIP_ADJ
850x222C VAP_GB_HORZ_DISC_ADJ
860x2230 VAP_PVS_FLOW_CNTL_ADDRS_0
870x2234 VAP_PVS_FLOW_CNTL_ADDRS_1
880x2238 VAP_PVS_FLOW_CNTL_ADDRS_2
890x223C VAP_PVS_FLOW_CNTL_ADDRS_3
900x2240 VAP_PVS_FLOW_CNTL_ADDRS_4
910x2244 VAP_PVS_FLOW_CNTL_ADDRS_5
920x2248 VAP_PVS_FLOW_CNTL_ADDRS_6
930x224C VAP_PVS_FLOW_CNTL_ADDRS_7
940x2250 VAP_PVS_FLOW_CNTL_ADDRS_8
950x2254 VAP_PVS_FLOW_CNTL_ADDRS_9
960x2258 VAP_PVS_FLOW_CNTL_ADDRS_10
970x225C VAP_PVS_FLOW_CNTL_ADDRS_11
980x2260 VAP_PVS_FLOW_CNTL_ADDRS_12
990x2264 VAP_PVS_FLOW_CNTL_ADDRS_13
1000x2268 VAP_PVS_FLOW_CNTL_ADDRS_14
1010x226C VAP_PVS_FLOW_CNTL_ADDRS_15
1020x2284 VAP_PVS_STATE_FLUSH_REG
1030x2288 VAP_PVS_VTX_TIMEOUT_REG
1040x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
1050x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1
1060x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2
1070x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3
1080x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4
1090x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5
1100x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6
1110x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7
1120x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8
1130x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9
1140x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10
1150x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11
1160x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12
1170x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13
1180x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14
1190x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15
1200x22D0 VAP_PVS_CODE_CNTL_0
1210x22D4 VAP_PVS_CONST_CNTL
1220x22D8 VAP_PVS_CODE_CNTL_1
1230x22DC VAP_PVS_FLOW_CNTL_OPC
1240x342C RB2D_DSTCACHE_CTLSTAT
1250x4000 GB_VAP_RASTER_VTX_FMT_0
1260x4004 GB_VAP_RASTER_VTX_FMT_1
1270x4008 GB_ENABLE
1280x401C GB_SELECT
1290x4020 GB_AA_CONFIG
1300x4024 GB_FIFO_SIZE
1310x4100 TX_INVALTAGS
1320x4200 GA_POINT_S0
1330x4204 GA_POINT_T0
1340x4208 GA_POINT_S1
1350x420C GA_POINT_T1
1360x4214 GA_TRIANGLE_STIPPLE
1370x421C GA_POINT_SIZE
1380x4230 GA_POINT_MINMAX
1390x4234 GA_LINE_CNTL
1400x4238 GA_LINE_STIPPLE_CONFIG
1410x4260 GA_LINE_STIPPLE_VALUE
1420x4264 GA_LINE_S0
1430x4268 GA_LINE_S1
1440x4278 GA_COLOR_CONTROL
1450x427C GA_SOLID_RG
1460x4280 GA_SOLID_BA
1470x4288 GA_POLY_MODE
1480x428C GA_ROUND_MODE
1490x4290 GA_OFFSET
1500x4294 GA_FOG_SCALE
1510x4298 GA_FOG_OFFSET
1520x42A0 SU_TEX_WRAP
1530x42A4 SU_POLY_OFFSET_FRONT_SCALE
1540x42A8 SU_POLY_OFFSET_FRONT_OFFSET
1550x42AC SU_POLY_OFFSET_BACK_SCALE
1560x42B0 SU_POLY_OFFSET_BACK_OFFSET
1570x42B4 SU_POLY_OFFSET_ENABLE
1580x42B8 SU_CULL_MODE
1590x42C0 SU_DEPTH_SCALE
1600x42C4 SU_DEPTH_OFFSET
1610x42C8 SU_REG_DEST
1620x4300 RS_COUNT
1630x4304 RS_INST_COUNT
1640x4310 RS_IP_0
1650x4314 RS_IP_1
1660x4318 RS_IP_2
1670x431C RS_IP_3
1680x4320 RS_IP_4
1690x4324 RS_IP_5
1700x4328 RS_IP_6
1710x432C RS_IP_7
1720x4330 RS_INST_0
1730x4334 RS_INST_1
1740x4338 RS_INST_2
1750x433C RS_INST_3
1760x4340 RS_INST_4
1770x4344 RS_INST_5
1780x4348 RS_INST_6
1790x434C RS_INST_7
1800x4350 RS_INST_8
1810x4354 RS_INST_9
1820x4358 RS_INST_10
1830x435C RS_INST_11
1840x4360 RS_INST_12
1850x4364 RS_INST_13
1860x4368 RS_INST_14
1870x436C RS_INST_15
1880x43A4 SC_HYPERZ_EN
1890x43A8 SC_EDGERULE
1900x43B0 SC_CLIP_0_A
1910x43B4 SC_CLIP_0_B
1920x43B8 SC_CLIP_1_A
1930x43BC SC_CLIP_1_B
1940x43C0 SC_CLIP_2_A
1950x43C4 SC_CLIP_2_B
1960x43C8 SC_CLIP_3_A
1970x43CC SC_CLIP_3_B
1980x43D0 SC_CLIP_RULE
1990x43E0 SC_SCISSOR0
2000x43E8 SC_SCREENDOOR
2010x4440 TX_FILTER1_0
2020x4444 TX_FILTER1_1
2030x4448 TX_FILTER1_2
2040x444C TX_FILTER1_3
2050x4450 TX_FILTER1_4
2060x4454 TX_FILTER1_5
2070x4458 TX_FILTER1_6
2080x445C TX_FILTER1_7
2090x4460 TX_FILTER1_8
2100x4464 TX_FILTER1_9
2110x4468 TX_FILTER1_10
2120x446C TX_FILTER1_11
2130x4470 TX_FILTER1_12
2140x4474 TX_FILTER1_13
2150x4478 TX_FILTER1_14
2160x447C TX_FILTER1_15
2170x4580 TX_CHROMA_KEY_0
2180x4584 TX_CHROMA_KEY_1
2190x4588 TX_CHROMA_KEY_2
2200x458C TX_CHROMA_KEY_3
2210x4590 TX_CHROMA_KEY_4
2220x4594 TX_CHROMA_KEY_5
2230x4598 TX_CHROMA_KEY_6
2240x459C TX_CHROMA_KEY_7
2250x45A0 TX_CHROMA_KEY_8
2260x45A4 TX_CHROMA_KEY_9
2270x45A8 TX_CHROMA_KEY_10
2280x45AC TX_CHROMA_KEY_11
2290x45B0 TX_CHROMA_KEY_12
2300x45B4 TX_CHROMA_KEY_13
2310x45B8 TX_CHROMA_KEY_14
2320x45BC TX_CHROMA_KEY_15
2330x45C0 TX_BORDER_COLOR_0
2340x45C4 TX_BORDER_COLOR_1
2350x45C8 TX_BORDER_COLOR_2
2360x45CC TX_BORDER_COLOR_3
2370x45D0 TX_BORDER_COLOR_4
2380x45D4 TX_BORDER_COLOR_5
2390x45D8 TX_BORDER_COLOR_6
2400x45DC TX_BORDER_COLOR_7
2410x45E0 TX_BORDER_COLOR_8
2420x45E4 TX_BORDER_COLOR_9
2430x45E8 TX_BORDER_COLOR_10
2440x45EC TX_BORDER_COLOR_11
2450x45F0 TX_BORDER_COLOR_12
2460x45F4 TX_BORDER_COLOR_13
2470x45F8 TX_BORDER_COLOR_14
2480x45FC TX_BORDER_COLOR_15
2490x4600 US_CONFIG
2500x4604 US_PIXSIZE
2510x4608 US_CODE_OFFSET
2520x460C US_RESET
2530x4610 US_CODE_ADDR_0
2540x4614 US_CODE_ADDR_1
2550x4618 US_CODE_ADDR_2
2560x461C US_CODE_ADDR_3
2570x4620 US_TEX_INST_0
2580x4624 US_TEX_INST_1
2590x4628 US_TEX_INST_2
2600x462C US_TEX_INST_3
2610x4630 US_TEX_INST_4
2620x4634 US_TEX_INST_5
2630x4638 US_TEX_INST_6
2640x463C US_TEX_INST_7
2650x4640 US_TEX_INST_8
2660x4644 US_TEX_INST_9
2670x4648 US_TEX_INST_10
2680x464C US_TEX_INST_11
2690x4650 US_TEX_INST_12
2700x4654 US_TEX_INST_13
2710x4658 US_TEX_INST_14
2720x465C US_TEX_INST_15
2730x4660 US_TEX_INST_16
2740x4664 US_TEX_INST_17
2750x4668 US_TEX_INST_18
2760x466C US_TEX_INST_19
2770x4670 US_TEX_INST_20
2780x4674 US_TEX_INST_21
2790x4678 US_TEX_INST_22
2800x467C US_TEX_INST_23
2810x4680 US_TEX_INST_24
2820x4684 US_TEX_INST_25
2830x4688 US_TEX_INST_26
2840x468C US_TEX_INST_27
2850x4690 US_TEX_INST_28
2860x4694 US_TEX_INST_29
2870x4698 US_TEX_INST_30
2880x469C US_TEX_INST_31
2890x46A4 US_OUT_FMT_0
2900x46A8 US_OUT_FMT_1
2910x46AC US_OUT_FMT_2
2920x46B0 US_OUT_FMT_3
2930x46B4 US_W_FMT
2940x46B8 US_CODE_BANK
2950x46BC US_CODE_EXT
2960x46C0 US_ALU_RGB_ADDR_0
2970x46C4 US_ALU_RGB_ADDR_1
2980x46C8 US_ALU_RGB_ADDR_2
2990x46CC US_ALU_RGB_ADDR_3
3000x46D0 US_ALU_RGB_ADDR_4
3010x46D4 US_ALU_RGB_ADDR_5
3020x46D8 US_ALU_RGB_ADDR_6
3030x46DC US_ALU_RGB_ADDR_7
3040x46E0 US_ALU_RGB_ADDR_8
3050x46E4 US_ALU_RGB_ADDR_9
3060x46E8 US_ALU_RGB_ADDR_10
3070x46EC US_ALU_RGB_ADDR_11
3080x46F0 US_ALU_RGB_ADDR_12
3090x46F4 US_ALU_RGB_ADDR_13
3100x46F8 US_ALU_RGB_ADDR_14
3110x46FC US_ALU_RGB_ADDR_15
3120x4700 US_ALU_RGB_ADDR_16
3130x4704 US_ALU_RGB_ADDR_17
3140x4708 US_ALU_RGB_ADDR_18
3150x470C US_ALU_RGB_ADDR_19
3160x4710 US_ALU_RGB_ADDR_20
3170x4714 US_ALU_RGB_ADDR_21
3180x4718 US_ALU_RGB_ADDR_22
3190x471C US_ALU_RGB_ADDR_23
3200x4720 US_ALU_RGB_ADDR_24
3210x4724 US_ALU_RGB_ADDR_25
3220x4728 US_ALU_RGB_ADDR_26
3230x472C US_ALU_RGB_ADDR_27
3240x4730 US_ALU_RGB_ADDR_28
3250x4734 US_ALU_RGB_ADDR_29
3260x4738 US_ALU_RGB_ADDR_30
3270x473C US_ALU_RGB_ADDR_31
3280x4740 US_ALU_RGB_ADDR_32
3290x4744 US_ALU_RGB_ADDR_33
3300x4748 US_ALU_RGB_ADDR_34
3310x474C US_ALU_RGB_ADDR_35
3320x4750 US_ALU_RGB_ADDR_36
3330x4754 US_ALU_RGB_ADDR_37
3340x4758 US_ALU_RGB_ADDR_38
3350x475C US_ALU_RGB_ADDR_39
3360x4760 US_ALU_RGB_ADDR_40
3370x4764 US_ALU_RGB_ADDR_41
3380x4768 US_ALU_RGB_ADDR_42
3390x476C US_ALU_RGB_ADDR_43
3400x4770 US_ALU_RGB_ADDR_44
3410x4774 US_ALU_RGB_ADDR_45
3420x4778 US_ALU_RGB_ADDR_46
3430x477C US_ALU_RGB_ADDR_47
3440x4780 US_ALU_RGB_ADDR_48
3450x4784 US_ALU_RGB_ADDR_49
3460x4788 US_ALU_RGB_ADDR_50
3470x478C US_ALU_RGB_ADDR_51
3480x4790 US_ALU_RGB_ADDR_52
3490x4794 US_ALU_RGB_ADDR_53
3500x4798 US_ALU_RGB_ADDR_54
3510x479C US_ALU_RGB_ADDR_55
3520x47A0 US_ALU_RGB_ADDR_56
3530x47A4 US_ALU_RGB_ADDR_57
3540x47A8 US_ALU_RGB_ADDR_58
3550x47AC US_ALU_RGB_ADDR_59
3560x47B0 US_ALU_RGB_ADDR_60
3570x47B4 US_ALU_RGB_ADDR_61
3580x47B8 US_ALU_RGB_ADDR_62
3590x47BC US_ALU_RGB_ADDR_63
3600x47C0 US_ALU_ALPHA_ADDR_0
3610x47C4 US_ALU_ALPHA_ADDR_1
3620x47C8 US_ALU_ALPHA_ADDR_2
3630x47CC US_ALU_ALPHA_ADDR_3
3640x47D0 US_ALU_ALPHA_ADDR_4
3650x47D4 US_ALU_ALPHA_ADDR_5
3660x47D8 US_ALU_ALPHA_ADDR_6
3670x47DC US_ALU_ALPHA_ADDR_7
3680x47E0 US_ALU_ALPHA_ADDR_8
3690x47E4 US_ALU_ALPHA_ADDR_9
3700x47E8 US_ALU_ALPHA_ADDR_10
3710x47EC US_ALU_ALPHA_ADDR_11
3720x47F0 US_ALU_ALPHA_ADDR_12
3730x47F4 US_ALU_ALPHA_ADDR_13
3740x47F8 US_ALU_ALPHA_ADDR_14
3750x47FC US_ALU_ALPHA_ADDR_15
3760x4800 US_ALU_ALPHA_ADDR_16
3770x4804 US_ALU_ALPHA_ADDR_17
3780x4808 US_ALU_ALPHA_ADDR_18
3790x480C US_ALU_ALPHA_ADDR_19
3800x4810 US_ALU_ALPHA_ADDR_20
3810x4814 US_ALU_ALPHA_ADDR_21
3820x4818 US_ALU_ALPHA_ADDR_22
3830x481C US_ALU_ALPHA_ADDR_23
3840x4820 US_ALU_ALPHA_ADDR_24
3850x4824 US_ALU_ALPHA_ADDR_25
3860x4828 US_ALU_ALPHA_ADDR_26
3870x482C US_ALU_ALPHA_ADDR_27
3880x4830 US_ALU_ALPHA_ADDR_28
3890x4834 US_ALU_ALPHA_ADDR_29
3900x4838 US_ALU_ALPHA_ADDR_30
3910x483C US_ALU_ALPHA_ADDR_31
3920x4840 US_ALU_ALPHA_ADDR_32
3930x4844 US_ALU_ALPHA_ADDR_33
3940x4848 US_ALU_ALPHA_ADDR_34
3950x484C US_ALU_ALPHA_ADDR_35
3960x4850 US_ALU_ALPHA_ADDR_36
3970x4854 US_ALU_ALPHA_ADDR_37
3980x4858 US_ALU_ALPHA_ADDR_38
3990x485C US_ALU_ALPHA_ADDR_39
4000x4860 US_ALU_ALPHA_ADDR_40
4010x4864 US_ALU_ALPHA_ADDR_41
4020x4868 US_ALU_ALPHA_ADDR_42
4030x486C US_ALU_ALPHA_ADDR_43
4040x4870 US_ALU_ALPHA_ADDR_44
4050x4874 US_ALU_ALPHA_ADDR_45
4060x4878 US_ALU_ALPHA_ADDR_46
4070x487C US_ALU_ALPHA_ADDR_47
4080x4880 US_ALU_ALPHA_ADDR_48
4090x4884 US_ALU_ALPHA_ADDR_49
4100x4888 US_ALU_ALPHA_ADDR_50
4110x488C US_ALU_ALPHA_ADDR_51
4120x4890 US_ALU_ALPHA_ADDR_52
4130x4894 US_ALU_ALPHA_ADDR_53
4140x4898 US_ALU_ALPHA_ADDR_54
4150x489C US_ALU_ALPHA_ADDR_55
4160x48A0 US_ALU_ALPHA_ADDR_56
4170x48A4 US_ALU_ALPHA_ADDR_57
4180x48A8 US_ALU_ALPHA_ADDR_58
4190x48AC US_ALU_ALPHA_ADDR_59
4200x48B0 US_ALU_ALPHA_ADDR_60
4210x48B4 US_ALU_ALPHA_ADDR_61
4220x48B8 US_ALU_ALPHA_ADDR_62
4230x48BC US_ALU_ALPHA_ADDR_63
4240x48C0 US_ALU_RGB_INST_0
4250x48C4 US_ALU_RGB_INST_1
4260x48C8 US_ALU_RGB_INST_2
4270x48CC US_ALU_RGB_INST_3
4280x48D0 US_ALU_RGB_INST_4
4290x48D4 US_ALU_RGB_INST_5
4300x48D8 US_ALU_RGB_INST_6
4310x48DC US_ALU_RGB_INST_7
4320x48E0 US_ALU_RGB_INST_8
4330x48E4 US_ALU_RGB_INST_9
4340x48E8 US_ALU_RGB_INST_10
4350x48EC US_ALU_RGB_INST_11
4360x48F0 US_ALU_RGB_INST_12
4370x48F4 US_ALU_RGB_INST_13
4380x48F8 US_ALU_RGB_INST_14
4390x48FC US_ALU_RGB_INST_15
4400x4900 US_ALU_RGB_INST_16
4410x4904 US_ALU_RGB_INST_17
4420x4908 US_ALU_RGB_INST_18
4430x490C US_ALU_RGB_INST_19
4440x4910 US_ALU_RGB_INST_20
4450x4914 US_ALU_RGB_INST_21
4460x4918 US_ALU_RGB_INST_22
4470x491C US_ALU_RGB_INST_23
4480x4920 US_ALU_RGB_INST_24
4490x4924 US_ALU_RGB_INST_25
4500x4928 US_ALU_RGB_INST_26
4510x492C US_ALU_RGB_INST_27
4520x4930 US_ALU_RGB_INST_28
4530x4934 US_ALU_RGB_INST_29
4540x4938 US_ALU_RGB_INST_30
4550x493C US_ALU_RGB_INST_31
4560x4940 US_ALU_RGB_INST_32
4570x4944 US_ALU_RGB_INST_33
4580x4948 US_ALU_RGB_INST_34
4590x494C US_ALU_RGB_INST_35
4600x4950 US_ALU_RGB_INST_36
4610x4954 US_ALU_RGB_INST_37
4620x4958 US_ALU_RGB_INST_38
4630x495C US_ALU_RGB_INST_39
4640x4960 US_ALU_RGB_INST_40
4650x4964 US_ALU_RGB_INST_41
4660x4968 US_ALU_RGB_INST_42
4670x496C US_ALU_RGB_INST_43
4680x4970 US_ALU_RGB_INST_44
4690x4974 US_ALU_RGB_INST_45
4700x4978 US_ALU_RGB_INST_46
4710x497C US_ALU_RGB_INST_47
4720x4980 US_ALU_RGB_INST_48
4730x4984 US_ALU_RGB_INST_49
4740x4988 US_ALU_RGB_INST_50
4750x498C US_ALU_RGB_INST_51
4760x4990 US_ALU_RGB_INST_52
4770x4994 US_ALU_RGB_INST_53
4780x4998 US_ALU_RGB_INST_54
4790x499C US_ALU_RGB_INST_55
4800x49A0 US_ALU_RGB_INST_56
4810x49A4 US_ALU_RGB_INST_57
4820x49A8 US_ALU_RGB_INST_58
4830x49AC US_ALU_RGB_INST_59
4840x49B0 US_ALU_RGB_INST_60
4850x49B4 US_ALU_RGB_INST_61
4860x49B8 US_ALU_RGB_INST_62
4870x49BC US_ALU_RGB_INST_63
4880x49C0 US_ALU_ALPHA_INST_0
4890x49C4 US_ALU_ALPHA_INST_1
4900x49C8 US_ALU_ALPHA_INST_2
4910x49CC US_ALU_ALPHA_INST_3
4920x49D0 US_ALU_ALPHA_INST_4
4930x49D4 US_ALU_ALPHA_INST_5
4940x49D8 US_ALU_ALPHA_INST_6
4950x49DC US_ALU_ALPHA_INST_7
4960x49E0 US_ALU_ALPHA_INST_8
4970x49E4 US_ALU_ALPHA_INST_9
4980x49E8 US_ALU_ALPHA_INST_10
4990x49EC US_ALU_ALPHA_INST_11
5000x49F0 US_ALU_ALPHA_INST_12
5010x49F4 US_ALU_ALPHA_INST_13
5020x49F8 US_ALU_ALPHA_INST_14
5030x49FC US_ALU_ALPHA_INST_15
5040x4A00 US_ALU_ALPHA_INST_16
5050x4A04 US_ALU_ALPHA_INST_17
5060x4A08 US_ALU_ALPHA_INST_18
5070x4A0C US_ALU_ALPHA_INST_19
5080x4A10 US_ALU_ALPHA_INST_20
5090x4A14 US_ALU_ALPHA_INST_21
5100x4A18 US_ALU_ALPHA_INST_22
5110x4A1C US_ALU_ALPHA_INST_23
5120x4A20 US_ALU_ALPHA_INST_24
5130x4A24 US_ALU_ALPHA_INST_25
5140x4A28 US_ALU_ALPHA_INST_26
5150x4A2C US_ALU_ALPHA_INST_27
5160x4A30 US_ALU_ALPHA_INST_28
5170x4A34 US_ALU_ALPHA_INST_29
5180x4A38 US_ALU_ALPHA_INST_30
5190x4A3C US_ALU_ALPHA_INST_31
5200x4A40 US_ALU_ALPHA_INST_32
5210x4A44 US_ALU_ALPHA_INST_33
5220x4A48 US_ALU_ALPHA_INST_34
5230x4A4C US_ALU_ALPHA_INST_35
5240x4A50 US_ALU_ALPHA_INST_36
5250x4A54 US_ALU_ALPHA_INST_37
5260x4A58 US_ALU_ALPHA_INST_38
5270x4A5C US_ALU_ALPHA_INST_39
5280x4A60 US_ALU_ALPHA_INST_40
5290x4A64 US_ALU_ALPHA_INST_41
5300x4A68 US_ALU_ALPHA_INST_42
5310x4A6C US_ALU_ALPHA_INST_43
5320x4A70 US_ALU_ALPHA_INST_44
5330x4A74 US_ALU_ALPHA_INST_45
5340x4A78 US_ALU_ALPHA_INST_46
5350x4A7C US_ALU_ALPHA_INST_47
5360x4A80 US_ALU_ALPHA_INST_48
5370x4A84 US_ALU_ALPHA_INST_49
5380x4A88 US_ALU_ALPHA_INST_50
5390x4A8C US_ALU_ALPHA_INST_51
5400x4A90 US_ALU_ALPHA_INST_52
5410x4A94 US_ALU_ALPHA_INST_53
5420x4A98 US_ALU_ALPHA_INST_54
5430x4A9C US_ALU_ALPHA_INST_55
5440x4AA0 US_ALU_ALPHA_INST_56
5450x4AA4 US_ALU_ALPHA_INST_57
5460x4AA8 US_ALU_ALPHA_INST_58
5470x4AAC US_ALU_ALPHA_INST_59
5480x4AB0 US_ALU_ALPHA_INST_60
5490x4AB4 US_ALU_ALPHA_INST_61
5500x4AB8 US_ALU_ALPHA_INST_62
5510x4ABC US_ALU_ALPHA_INST_63
5520x4AC0 US_ALU_EXT_ADDR_0
5530x4AC4 US_ALU_EXT_ADDR_1
5540x4AC8 US_ALU_EXT_ADDR_2
5550x4ACC US_ALU_EXT_ADDR_3
5560x4AD0 US_ALU_EXT_ADDR_4
5570x4AD4 US_ALU_EXT_ADDR_5
5580x4AD8 US_ALU_EXT_ADDR_6
5590x4ADC US_ALU_EXT_ADDR_7
5600x4AE0 US_ALU_EXT_ADDR_8
5610x4AE4 US_ALU_EXT_ADDR_9
5620x4AE8 US_ALU_EXT_ADDR_10
5630x4AEC US_ALU_EXT_ADDR_11
5640x4AF0 US_ALU_EXT_ADDR_12
5650x4AF4 US_ALU_EXT_ADDR_13
5660x4AF8 US_ALU_EXT_ADDR_14
5670x4AFC US_ALU_EXT_ADDR_15
5680x4B00 US_ALU_EXT_ADDR_16
5690x4B04 US_ALU_EXT_ADDR_17
5700x4B08 US_ALU_EXT_ADDR_18
5710x4B0C US_ALU_EXT_ADDR_19
5720x4B10 US_ALU_EXT_ADDR_20
5730x4B14 US_ALU_EXT_ADDR_21
5740x4B18 US_ALU_EXT_ADDR_22
5750x4B1C US_ALU_EXT_ADDR_23
5760x4B20 US_ALU_EXT_ADDR_24
5770x4B24 US_ALU_EXT_ADDR_25
5780x4B28 US_ALU_EXT_ADDR_26
5790x4B2C US_ALU_EXT_ADDR_27
5800x4B30 US_ALU_EXT_ADDR_28
5810x4B34 US_ALU_EXT_ADDR_29
5820x4B38 US_ALU_EXT_ADDR_30
5830x4B3C US_ALU_EXT_ADDR_31
5840x4B40 US_ALU_EXT_ADDR_32
5850x4B44 US_ALU_EXT_ADDR_33
5860x4B48 US_ALU_EXT_ADDR_34
5870x4B4C US_ALU_EXT_ADDR_35
5880x4B50 US_ALU_EXT_ADDR_36
5890x4B54 US_ALU_EXT_ADDR_37
5900x4B58 US_ALU_EXT_ADDR_38
5910x4B5C US_ALU_EXT_ADDR_39
5920x4B60 US_ALU_EXT_ADDR_40
5930x4B64 US_ALU_EXT_ADDR_41
5940x4B68 US_ALU_EXT_ADDR_42
5950x4B6C US_ALU_EXT_ADDR_43
5960x4B70 US_ALU_EXT_ADDR_44
5970x4B74 US_ALU_EXT_ADDR_45
5980x4B78 US_ALU_EXT_ADDR_46
5990x4B7C US_ALU_EXT_ADDR_47
6000x4B80 US_ALU_EXT_ADDR_48
6010x4B84 US_ALU_EXT_ADDR_49
6020x4B88 US_ALU_EXT_ADDR_50
6030x4B8C US_ALU_EXT_ADDR_51
6040x4B90 US_ALU_EXT_ADDR_52
6050x4B94 US_ALU_EXT_ADDR_53
6060x4B98 US_ALU_EXT_ADDR_54
6070x4B9C US_ALU_EXT_ADDR_55
6080x4BA0 US_ALU_EXT_ADDR_56
6090x4BA4 US_ALU_EXT_ADDR_57
6100x4BA8 US_ALU_EXT_ADDR_58
6110x4BAC US_ALU_EXT_ADDR_59
6120x4BB0 US_ALU_EXT_ADDR_60
6130x4BB4 US_ALU_EXT_ADDR_61
6140x4BB8 US_ALU_EXT_ADDR_62
6150x4BBC US_ALU_EXT_ADDR_63
6160x4BC0 FG_FOG_BLEND
6170x4BC4 FG_FOG_FACTOR
6180x4BC8 FG_FOG_COLOR_R
6190x4BCC FG_FOG_COLOR_G
6200x4BD0 FG_FOG_COLOR_B
6210x4BD4 FG_ALPHA_FUNC
6220x4BD8 FG_DEPTH_SRC
6230x4C00 US_ALU_CONST_R_0
6240x4C04 US_ALU_CONST_G_0
6250x4C08 US_ALU_CONST_B_0
6260x4C0C US_ALU_CONST_A_0
6270x4C10 US_ALU_CONST_R_1
6280x4C14 US_ALU_CONST_G_1
6290x4C18 US_ALU_CONST_B_1
6300x4C1C US_ALU_CONST_A_1
6310x4C20 US_ALU_CONST_R_2
6320x4C24 US_ALU_CONST_G_2
6330x4C28 US_ALU_CONST_B_2
6340x4C2C US_ALU_CONST_A_2
6350x4C30 US_ALU_CONST_R_3
6360x4C34 US_ALU_CONST_G_3
6370x4C38 US_ALU_CONST_B_3
6380x4C3C US_ALU_CONST_A_3
6390x4C40 US_ALU_CONST_R_4
6400x4C44 US_ALU_CONST_G_4
6410x4C48 US_ALU_CONST_B_4
6420x4C4C US_ALU_CONST_A_4
6430x4C50 US_ALU_CONST_R_5
6440x4C54 US_ALU_CONST_G_5
6450x4C58 US_ALU_CONST_B_5
6460x4C5C US_ALU_CONST_A_5
6470x4C60 US_ALU_CONST_R_6
6480x4C64 US_ALU_CONST_G_6
6490x4C68 US_ALU_CONST_B_6
6500x4C6C US_ALU_CONST_A_6
6510x4C70 US_ALU_CONST_R_7
6520x4C74 US_ALU_CONST_G_7
6530x4C78 US_ALU_CONST_B_7
6540x4C7C US_ALU_CONST_A_7
6550x4C80 US_ALU_CONST_R_8
6560x4C84 US_ALU_CONST_G_8
6570x4C88 US_ALU_CONST_B_8
6580x4C8C US_ALU_CONST_A_8
6590x4C90 US_ALU_CONST_R_9
6600x4C94 US_ALU_CONST_G_9
6610x4C98 US_ALU_CONST_B_9
6620x4C9C US_ALU_CONST_A_9
6630x4CA0 US_ALU_CONST_R_10
6640x4CA4 US_ALU_CONST_G_10
6650x4CA8 US_ALU_CONST_B_10
6660x4CAC US_ALU_CONST_A_10
6670x4CB0 US_ALU_CONST_R_11
6680x4CB4 US_ALU_CONST_G_11
6690x4CB8 US_ALU_CONST_B_11
6700x4CBC US_ALU_CONST_A_11
6710x4CC0 US_ALU_CONST_R_12
6720x4CC4 US_ALU_CONST_G_12
6730x4CC8 US_ALU_CONST_B_12
6740x4CCC US_ALU_CONST_A_12
6750x4CD0 US_ALU_CONST_R_13
6760x4CD4 US_ALU_CONST_G_13
6770x4CD8 US_ALU_CONST_B_13
6780x4CDC US_ALU_CONST_A_13
6790x4CE0 US_ALU_CONST_R_14
6800x4CE4 US_ALU_CONST_G_14
6810x4CE8 US_ALU_CONST_B_14
6820x4CEC US_ALU_CONST_A_14
6830x4CF0 US_ALU_CONST_R_15
6840x4CF4 US_ALU_CONST_G_15
6850x4CF8 US_ALU_CONST_B_15
6860x4CFC US_ALU_CONST_A_15
6870x4D00 US_ALU_CONST_R_16
6880x4D04 US_ALU_CONST_G_16
6890x4D08 US_ALU_CONST_B_16
6900x4D0C US_ALU_CONST_A_16
6910x4D10 US_ALU_CONST_R_17
6920x4D14 US_ALU_CONST_G_17
6930x4D18 US_ALU_CONST_B_17
6940x4D1C US_ALU_CONST_A_17
6950x4D20 US_ALU_CONST_R_18
6960x4D24 US_ALU_CONST_G_18
6970x4D28 US_ALU_CONST_B_18
6980x4D2C US_ALU_CONST_A_18
6990x4D30 US_ALU_CONST_R_19
7000x4D34 US_ALU_CONST_G_19
7010x4D38 US_ALU_CONST_B_19
7020x4D3C US_ALU_CONST_A_19
7030x4D40 US_ALU_CONST_R_20
7040x4D44 US_ALU_CONST_G_20
7050x4D48 US_ALU_CONST_B_20
7060x4D4C US_ALU_CONST_A_20
7070x4D50 US_ALU_CONST_R_21
7080x4D54 US_ALU_CONST_G_21
7090x4D58 US_ALU_CONST_B_21
7100x4D5C US_ALU_CONST_A_21
7110x4D60 US_ALU_CONST_R_22
7120x4D64 US_ALU_CONST_G_22
7130x4D68 US_ALU_CONST_B_22
7140x4D6C US_ALU_CONST_A_22
7150x4D70 US_ALU_CONST_R_23
7160x4D74 US_ALU_CONST_G_23
7170x4D78 US_ALU_CONST_B_23
7180x4D7C US_ALU_CONST_A_23
7190x4D80 US_ALU_CONST_R_24
7200x4D84 US_ALU_CONST_G_24
7210x4D88 US_ALU_CONST_B_24
7220x4D8C US_ALU_CONST_A_24
7230x4D90 US_ALU_CONST_R_25
7240x4D94 US_ALU_CONST_G_25
7250x4D98 US_ALU_CONST_B_25
7260x4D9C US_ALU_CONST_A_25
7270x4DA0 US_ALU_CONST_R_26
7280x4DA4 US_ALU_CONST_G_26
7290x4DA8 US_ALU_CONST_B_26
7300x4DAC US_ALU_CONST_A_26
7310x4DB0 US_ALU_CONST_R_27
7320x4DB4 US_ALU_CONST_G_27
7330x4DB8 US_ALU_CONST_B_27
7340x4DBC US_ALU_CONST_A_27
7350x4DC0 US_ALU_CONST_R_28
7360x4DC4 US_ALU_CONST_G_28
7370x4DC8 US_ALU_CONST_B_28
7380x4DCC US_ALU_CONST_A_28
7390x4DD0 US_ALU_CONST_R_29
7400x4DD4 US_ALU_CONST_G_29
7410x4DD8 US_ALU_CONST_B_29
7420x4DDC US_ALU_CONST_A_29
7430x4DE0 US_ALU_CONST_R_30
7440x4DE4 US_ALU_CONST_G_30
7450x4DE8 US_ALU_CONST_B_30
7460x4DEC US_ALU_CONST_A_30
7470x4DF0 US_ALU_CONST_R_31
7480x4DF4 US_ALU_CONST_G_31
7490x4DF8 US_ALU_CONST_B_31
7500x4DFC US_ALU_CONST_A_31
7510x4E04 RB3D_BLENDCNTL_R3
7520x4E08 RB3D_ABLENDCNTL_R3
7530x4E0C RB3D_COLOR_CHANNEL_MASK
7540x4E10 RB3D_CONSTANT_COLOR
7550x4E14 RB3D_COLOR_CLEAR_VALUE
7560x4E18 RB3D_ROPCNTL_R3
7570x4E1C RB3D_CLRCMP_FLIPE_R3
7580x4E20 RB3D_CLRCMP_CLR_R3
7590x4E24 RB3D_CLRCMP_MSK_R3
7600x4E48 RB3D_DEBUG_CTL
7610x4E4C RB3D_DSTCACHE_CTLSTAT_R3
7620x4E50 RB3D_DITHER_CTL
7630x4E54 RB3D_CMASK_OFFSET0
7640x4E58 RB3D_CMASK_OFFSET1
7650x4E5C RB3D_CMASK_OFFSET2
7660x4E60 RB3D_CMASK_OFFSET3
7670x4E64 RB3D_CMASK_PITCH0
7680x4E68 RB3D_CMASK_PITCH1
7690x4E6C RB3D_CMASK_PITCH2
7700x4E70 RB3D_CMASK_PITCH3
7710x4E74 RB3D_CMASK_WRINDEX
7720x4E78 RB3D_CMASK_DWORD
7730x4E7C RB3D_CMASK_RDINDEX
7740x4E80 RB3D_AARESOLVE_OFFSET
7750x4E84 RB3D_AARESOLVE_PITCH
7760x4E88 RB3D_AARESOLVE_CTL
7770x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
7780x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
7790x4F04 ZB_ZSTENCILCNTL
7800x4F08 ZB_STENCILREFMASK
7810x4F14 ZB_ZTOP
7820x4F18 ZB_ZCACHE_CTLSTAT
7830x4F1C ZB_BW_CNTL
7840x4F28 ZB_DEPTHCLEARVALUE
7850x4F30 ZB_ZMASK_OFFSET
7860x4F34 ZB_ZMASK_PITCH
7870x4F38 ZB_ZMASK_WRINDEX
7880x4F3C ZB_ZMASK_DWORD
7890x4F40 ZB_ZMASK_RDINDEX
7900x4F44 ZB_HIZ_OFFSET
7910x4F48 ZB_HIZ_WRINDEX
7920x4F4C ZB_HIZ_DWORD
7930x4F50 ZB_HIZ_RDINDEX
7940x4F54 ZB_HIZ_PITCH
7950x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600
index 8e3c0b807add..6801b865d1c4 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rs600
+++ b/drivers/gpu/drm/radeon/reg_srcs/rs600
@@ -153,7 +153,7 @@ rs600 0x6d40
1530x42A4 SU_POLY_OFFSET_FRONT_SCALE 1530x42A4 SU_POLY_OFFSET_FRONT_SCALE
1540x42A8 SU_POLY_OFFSET_FRONT_OFFSET 1540x42A8 SU_POLY_OFFSET_FRONT_OFFSET
1550x42AC SU_POLY_OFFSET_BACK_SCALE 1550x42AC SU_POLY_OFFSET_BACK_SCALE
1560x42B0 SU_POLY_OFFSET_BACK_OFFSET 1560x42B0 SU_POLY_OFFSET_BACK_OFFSET
1570x42B4 SU_POLY_OFFSET_ENABLE 1570x42B4 SU_POLY_OFFSET_ENABLE
1580x42B8 SU_CULL_MODE 1580x42B8 SU_CULL_MODE
1590x42C0 SU_DEPTH_SCALE 1590x42C0 SU_DEPTH_SCALE
@@ -291,6 +291,8 @@ rs600 0x6d40
2910x46AC US_OUT_FMT_2 2910x46AC US_OUT_FMT_2
2920x46B0 US_OUT_FMT_3 2920x46B0 US_OUT_FMT_3
2930x46B4 US_W_FMT 2930x46B4 US_W_FMT
2940x46B8 US_CODE_BANK
2950x46BC US_CODE_EXT
2940x46C0 US_ALU_RGB_ADDR_0 2960x46C0 US_ALU_RGB_ADDR_0
2950x46C4 US_ALU_RGB_ADDR_1 2970x46C4 US_ALU_RGB_ADDR_1
2960x46C8 US_ALU_RGB_ADDR_2 2980x46C8 US_ALU_RGB_ADDR_2
@@ -547,6 +549,70 @@ rs600 0x6d40
5470x4AB4 US_ALU_ALPHA_INST_61 5490x4AB4 US_ALU_ALPHA_INST_61
5480x4AB8 US_ALU_ALPHA_INST_62 5500x4AB8 US_ALU_ALPHA_INST_62
5490x4ABC US_ALU_ALPHA_INST_63 5510x4ABC US_ALU_ALPHA_INST_63
5520x4AC0 US_ALU_EXT_ADDR_0
5530x4AC4 US_ALU_EXT_ADDR_1
5540x4AC8 US_ALU_EXT_ADDR_2
5550x4ACC US_ALU_EXT_ADDR_3
5560x4AD0 US_ALU_EXT_ADDR_4
5570x4AD4 US_ALU_EXT_ADDR_5
5580x4AD8 US_ALU_EXT_ADDR_6
5590x4ADC US_ALU_EXT_ADDR_7
5600x4AE0 US_ALU_EXT_ADDR_8
5610x4AE4 US_ALU_EXT_ADDR_9
5620x4AE8 US_ALU_EXT_ADDR_10
5630x4AEC US_ALU_EXT_ADDR_11
5640x4AF0 US_ALU_EXT_ADDR_12
5650x4AF4 US_ALU_EXT_ADDR_13
5660x4AF8 US_ALU_EXT_ADDR_14
5670x4AFC US_ALU_EXT_ADDR_15
5680x4B00 US_ALU_EXT_ADDR_16
5690x4B04 US_ALU_EXT_ADDR_17
5700x4B08 US_ALU_EXT_ADDR_18
5710x4B0C US_ALU_EXT_ADDR_19
5720x4B10 US_ALU_EXT_ADDR_20
5730x4B14 US_ALU_EXT_ADDR_21
5740x4B18 US_ALU_EXT_ADDR_22
5750x4B1C US_ALU_EXT_ADDR_23
5760x4B20 US_ALU_EXT_ADDR_24
5770x4B24 US_ALU_EXT_ADDR_25
5780x4B28 US_ALU_EXT_ADDR_26
5790x4B2C US_ALU_EXT_ADDR_27
5800x4B30 US_ALU_EXT_ADDR_28
5810x4B34 US_ALU_EXT_ADDR_29
5820x4B38 US_ALU_EXT_ADDR_30
5830x4B3C US_ALU_EXT_ADDR_31
5840x4B40 US_ALU_EXT_ADDR_32
5850x4B44 US_ALU_EXT_ADDR_33
5860x4B48 US_ALU_EXT_ADDR_34
5870x4B4C US_ALU_EXT_ADDR_35
5880x4B50 US_ALU_EXT_ADDR_36
5890x4B54 US_ALU_EXT_ADDR_37
5900x4B58 US_ALU_EXT_ADDR_38
5910x4B5C US_ALU_EXT_ADDR_39
5920x4B60 US_ALU_EXT_ADDR_40
5930x4B64 US_ALU_EXT_ADDR_41
5940x4B68 US_ALU_EXT_ADDR_42
5950x4B6C US_ALU_EXT_ADDR_43
5960x4B70 US_ALU_EXT_ADDR_44
5970x4B74 US_ALU_EXT_ADDR_45
5980x4B78 US_ALU_EXT_ADDR_46
5990x4B7C US_ALU_EXT_ADDR_47
6000x4B80 US_ALU_EXT_ADDR_48
6010x4B84 US_ALU_EXT_ADDR_49
6020x4B88 US_ALU_EXT_ADDR_50
6030x4B8C US_ALU_EXT_ADDR_51
6040x4B90 US_ALU_EXT_ADDR_52
6050x4B94 US_ALU_EXT_ADDR_53
6060x4B98 US_ALU_EXT_ADDR_54
6070x4B9C US_ALU_EXT_ADDR_55
6080x4BA0 US_ALU_EXT_ADDR_56
6090x4BA4 US_ALU_EXT_ADDR_57
6100x4BA8 US_ALU_EXT_ADDR_58
6110x4BAC US_ALU_EXT_ADDR_59
6120x4BB0 US_ALU_EXT_ADDR_60
6130x4BB4 US_ALU_EXT_ADDR_61
6140x4BB8 US_ALU_EXT_ADDR_62
6150x4BBC US_ALU_EXT_ADDR_63
5500x4BC0 FG_FOG_BLEND 6160x4BC0 FG_FOG_BLEND
5510x4BC4 FG_FOG_FACTOR 6170x4BC4 FG_FOG_FACTOR
5520x4BC8 FG_FOG_COLOR_R 6180x4BC8 FG_FOG_COLOR_R
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index 0102a0d5735c..38abf63bf2cd 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -161,7 +161,12 @@ rv515 0x6d40
1610x401C GB_SELECT 1610x401C GB_SELECT
1620x4020 GB_AA_CONFIG 1620x4020 GB_AA_CONFIG
1630x4024 GB_FIFO_SIZE 1630x4024 GB_FIFO_SIZE
1640x4028 GB_Z_PEQ_CONFIG
1640x4100 TX_INVALTAGS 1650x4100 TX_INVALTAGS
1660x4114 SU_TEX_WRAP_PS3
1670x4118 PS3_ENABLE
1680x411c PS3_VTX_FMT
1690x4120 PS3_TEX_SOURCE
1650x4200 GA_POINT_S0 1700x4200 GA_POINT_S0
1660x4204 GA_POINT_T0 1710x4204 GA_POINT_T0
1670x4208 GA_POINT_S1 1720x4208 GA_POINT_S1
@@ -171,6 +176,7 @@ rv515 0x6d40
1710x4230 GA_POINT_MINMAX 1760x4230 GA_POINT_MINMAX
1720x4234 GA_LINE_CNTL 1770x4234 GA_LINE_CNTL
1730x4238 GA_LINE_STIPPLE_CONFIG 1780x4238 GA_LINE_STIPPLE_CONFIG
1790x4258 GA_COLOR_CONTROL_PS3
1740x4260 GA_LINE_STIPPLE_VALUE 1800x4260 GA_LINE_STIPPLE_VALUE
1750x4264 GA_LINE_S0 1810x4264 GA_LINE_S0
1760x4268 GA_LINE_S1 1820x4268 GA_LINE_S1
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 9f5418983e2a..287fcebfb4e6 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -223,15 +223,31 @@ int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
223 return 0; 223 return 0;
224} 224}
225 225
226int rs400_mc_wait_for_idle(struct radeon_device *rdev)
227{
228 unsigned i;
229 uint32_t tmp;
230
231 for (i = 0; i < rdev->usec_timeout; i++) {
232 /* read MC_STATUS */
233 tmp = RREG32(0x0150);
234 if (tmp & (1 << 2)) {
235 return 0;
236 }
237 DRM_UDELAY(1);
238 }
239 return -1;
240}
241
226void rs400_gpu_init(struct radeon_device *rdev) 242void rs400_gpu_init(struct radeon_device *rdev)
227{ 243{
228 /* FIXME: HDP same place on rs400 ? */ 244 /* FIXME: HDP same place on rs400 ? */
229 r100_hdp_reset(rdev); 245 r100_hdp_reset(rdev);
230 /* FIXME: is this correct ? */ 246 /* FIXME: is this correct ? */
231 r420_pipes_init(rdev); 247 r420_pipes_init(rdev);
232 if (r300_mc_wait_for_idle(rdev)) { 248 if (rs400_mc_wait_for_idle(rdev)) {
233 printk(KERN_WARNING "Failed to wait MC idle while " 249 printk(KERN_WARNING "rs400: Failed to wait MC idle while "
234 "programming pipes. Bad things might happen.\n"); 250 "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
235 } 251 }
236} 252}
237 253
@@ -370,8 +386,8 @@ void rs400_mc_program(struct radeon_device *rdev)
370 r100_mc_stop(rdev, &save); 386 r100_mc_stop(rdev, &save);
371 387
372 /* Wait for mc idle */ 388 /* Wait for mc idle */
373 if (r300_mc_wait_for_idle(rdev)) 389 if (rs400_mc_wait_for_idle(rdev))
374 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 390 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
375 WREG32(R_000148_MC_FB_LOCATION, 391 WREG32(R_000148_MC_FB_LOCATION,
376 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 392 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
377 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 393 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
@@ -448,7 +464,6 @@ int rs400_suspend(struct radeon_device *rdev)
448 464
449void rs400_fini(struct radeon_device *rdev) 465void rs400_fini(struct radeon_device *rdev)
450{ 466{
451 rs400_suspend(rdev);
452 r100_cp_fini(rdev); 467 r100_cp_fini(rdev);
453 r100_wb_fini(rdev); 468 r100_wb_fini(rdev);
454 r100_ib_fini(rdev); 469 r100_ib_fini(rdev);
@@ -527,7 +542,6 @@ int rs400_init(struct radeon_device *rdev)
527 if (r) { 542 if (r) {
528 /* Somethings want wront with the accel init stop accel */ 543 /* Somethings want wront with the accel init stop accel */
529 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 544 dev_err(rdev->dev, "Disabling GPU acceleration\n");
530 rs400_suspend(rdev);
531 r100_cp_fini(rdev); 545 r100_cp_fini(rdev);
532 r100_wb_fini(rdev); 546 r100_wb_fini(rdev);
533 r100_ib_fini(rdev); 547 r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index d5255751e7b3..c3818562a13e 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -610,7 +610,6 @@ int rs600_suspend(struct radeon_device *rdev)
610 610
611void rs600_fini(struct radeon_device *rdev) 611void rs600_fini(struct radeon_device *rdev)
612{ 612{
613 rs600_suspend(rdev);
614 r100_cp_fini(rdev); 613 r100_cp_fini(rdev);
615 r100_wb_fini(rdev); 614 r100_wb_fini(rdev);
616 r100_ib_fini(rdev); 615 r100_ib_fini(rdev);
@@ -689,7 +688,6 @@ int rs600_init(struct radeon_device *rdev)
689 if (r) { 688 if (r) {
690 /* Somethings want wront with the accel init stop accel */ 689 /* Somethings want wront with the accel init stop accel */
691 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 690 dev_err(rdev->dev, "Disabling GPU acceleration\n");
692 rs600_suspend(rdev);
693 r100_cp_fini(rdev); 691 r100_cp_fini(rdev);
694 r100_wb_fini(rdev); 692 r100_wb_fini(rdev);
695 r100_ib_fini(rdev); 693 r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index cd31da913771..06e2771aee5a 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -676,7 +676,6 @@ int rs690_suspend(struct radeon_device *rdev)
676 676
677void rs690_fini(struct radeon_device *rdev) 677void rs690_fini(struct radeon_device *rdev)
678{ 678{
679 rs690_suspend(rdev);
680 r100_cp_fini(rdev); 679 r100_cp_fini(rdev);
681 r100_wb_fini(rdev); 680 r100_wb_fini(rdev);
682 r100_ib_fini(rdev); 681 r100_ib_fini(rdev);
@@ -756,7 +755,6 @@ int rs690_init(struct radeon_device *rdev)
756 if (r) { 755 if (r) {
757 /* Somethings want wront with the accel init stop accel */ 756 /* Somethings want wront with the accel init stop accel */
758 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 757 dev_err(rdev->dev, "Disabling GPU acceleration\n");
759 rs690_suspend(rdev);
760 r100_cp_fini(rdev); 758 r100_cp_fini(rdev);
761 r100_wb_fini(rdev); 759 r100_wb_fini(rdev);
762 r100_ib_fini(rdev); 760 r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 62756717b044..0e1e6b8632b8 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -537,7 +537,6 @@ void rv515_set_safe_registers(struct radeon_device *rdev)
537 537
538void rv515_fini(struct radeon_device *rdev) 538void rv515_fini(struct radeon_device *rdev)
539{ 539{
540 rv515_suspend(rdev);
541 r100_cp_fini(rdev); 540 r100_cp_fini(rdev);
542 r100_wb_fini(rdev); 541 r100_wb_fini(rdev);
543 r100_ib_fini(rdev); 542 r100_ib_fini(rdev);
@@ -615,13 +614,12 @@ int rv515_init(struct radeon_device *rdev)
615 if (r) { 614 if (r) {
616 /* Somethings want wront with the accel init stop accel */ 615 /* Somethings want wront with the accel init stop accel */
617 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 616 dev_err(rdev->dev, "Disabling GPU acceleration\n");
618 rv515_suspend(rdev);
619 r100_cp_fini(rdev); 617 r100_cp_fini(rdev);
620 r100_wb_fini(rdev); 618 r100_wb_fini(rdev);
621 r100_ib_fini(rdev); 619 r100_ib_fini(rdev);
620 radeon_irq_kms_fini(rdev);
622 rv370_pcie_gart_fini(rdev); 621 rv370_pcie_gart_fini(rdev);
623 radeon_agp_fini(rdev); 622 radeon_agp_fini(rdev);
624 radeon_irq_kms_fini(rdev);
625 rdev->accel_working = false; 623 rdev->accel_working = false;
626 } 624 }
627 return 0; 625 return 0;
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 16f7317fa1af..5943d561fd1e 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -779,7 +779,6 @@ int rv770_mc_init(struct radeon_device *rdev)
779 fixed20_12 a; 779 fixed20_12 a;
780 u32 tmp; 780 u32 tmp;
781 int chansize, numchan; 781 int chansize, numchan;
782 int r;
783 782
784 /* Get VRAM informations */ 783 /* Get VRAM informations */
785 rdev->mc.vram_is_ddr = true; 784 rdev->mc.vram_is_ddr = true;
@@ -822,9 +821,6 @@ int rv770_mc_init(struct radeon_device *rdev)
822 rdev->mc.real_vram_size = rdev->mc.aper_size; 821 rdev->mc.real_vram_size = rdev->mc.aper_size;
823 822
824 if (rdev->flags & RADEON_IS_AGP) { 823 if (rdev->flags & RADEON_IS_AGP) {
825 r = radeon_agp_init(rdev);
826 if (r)
827 return r;
828 /* gtt_size is setup by radeon_agp_init */ 824 /* gtt_size is setup by radeon_agp_init */
829 rdev->mc.gtt_location = rdev->mc.agp_base; 825 rdev->mc.gtt_location = rdev->mc.agp_base;
830 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; 826 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
@@ -833,11 +829,11 @@ int rv770_mc_init(struct radeon_device *rdev)
833 * AGP so that GPU can catch out of VRAM/AGP access 829 * AGP so that GPU can catch out of VRAM/AGP access
834 */ 830 */
835 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { 831 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
836 /* Enought place before */ 832 /* Enough place before */
837 rdev->mc.vram_location = rdev->mc.gtt_location - 833 rdev->mc.vram_location = rdev->mc.gtt_location -
838 rdev->mc.mc_vram_size; 834 rdev->mc.mc_vram_size;
839 } else if (tmp > rdev->mc.mc_vram_size) { 835 } else if (tmp > rdev->mc.mc_vram_size) {
840 /* Enought place after */ 836 /* Enough place after */
841 rdev->mc.vram_location = rdev->mc.gtt_location + 837 rdev->mc.vram_location = rdev->mc.gtt_location +
842 rdev->mc.gtt_size; 838 rdev->mc.gtt_size;
843 } else { 839 } else {
@@ -891,26 +887,25 @@ static int rv770_startup(struct radeon_device *rdev)
891 return r; 887 return r;
892 } 888 }
893 rv770_gpu_init(rdev); 889 rv770_gpu_init(rdev);
894 890 r = r600_blit_init(rdev);
895 if (!rdev->r600_blit.shader_obj) { 891 if (r) {
896 r = r600_blit_init(rdev); 892 r600_blit_fini(rdev);
893 rdev->asic->copy = NULL;
894 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
895 }
896 /* pin copy shader into vram */
897 if (rdev->r600_blit.shader_obj) {
898 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
899 if (unlikely(r != 0))
900 return r;
901 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
902 &rdev->r600_blit.shader_gpu_addr);
903 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
897 if (r) { 904 if (r) {
898 DRM_ERROR("radeon: failed blitter (%d).\n", r); 905 DRM_ERROR("failed to pin blit object %d\n", r);
899 return r; 906 return r;
900 } 907 }
901 } 908 }
902
903 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
904 if (unlikely(r != 0))
905 return r;
906 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
907 &rdev->r600_blit.shader_gpu_addr);
908 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
909 if (r) {
910 DRM_ERROR("failed to pin blit object %d\n", r);
911 return r;
912 }
913
914 /* Enable IRQ */ 909 /* Enable IRQ */
915 r = r600_irq_init(rdev); 910 r = r600_irq_init(rdev);
916 if (r) { 911 if (r) {
@@ -972,13 +967,16 @@ int rv770_suspend(struct radeon_device *rdev)
972 /* FIXME: we should wait for ring to be empty */ 967 /* FIXME: we should wait for ring to be empty */
973 r700_cp_stop(rdev); 968 r700_cp_stop(rdev);
974 rdev->cp.ready = false; 969 rdev->cp.ready = false;
970 r600_irq_suspend(rdev);
975 r600_wb_disable(rdev); 971 r600_wb_disable(rdev);
976 rv770_pcie_gart_disable(rdev); 972 rv770_pcie_gart_disable(rdev);
977 /* unpin shaders bo */ 973 /* unpin shaders bo */
978 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 974 if (rdev->r600_blit.shader_obj) {
979 if (likely(r == 0)) { 975 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
980 radeon_bo_unpin(rdev->r600_blit.shader_obj); 976 if (likely(r == 0)) {
981 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 977 radeon_bo_unpin(rdev->r600_blit.shader_obj);
978 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
979 }
982 } 980 }
983 return 0; 981 return 0;
984} 982}
@@ -1037,6 +1035,11 @@ int rv770_init(struct radeon_device *rdev)
1037 r = radeon_fence_driver_init(rdev); 1035 r = radeon_fence_driver_init(rdev);
1038 if (r) 1036 if (r)
1039 return r; 1037 return r;
1038 if (rdev->flags & RADEON_IS_AGP) {
1039 r = radeon_agp_init(rdev);
1040 if (r)
1041 radeon_agp_disable(rdev);
1042 }
1040 r = rv770_mc_init(rdev); 1043 r = rv770_mc_init(rdev);
1041 if (r) 1044 if (r)
1042 return r; 1045 return r;
@@ -1062,22 +1065,25 @@ int rv770_init(struct radeon_device *rdev)
1062 rdev->accel_working = true; 1065 rdev->accel_working = true;
1063 r = rv770_startup(rdev); 1066 r = rv770_startup(rdev);
1064 if (r) { 1067 if (r) {
1065 rv770_suspend(rdev); 1068 dev_err(rdev->dev, "disabling GPU acceleration\n");
1069 r600_cp_fini(rdev);
1066 r600_wb_fini(rdev); 1070 r600_wb_fini(rdev);
1067 radeon_ring_fini(rdev); 1071 r600_irq_fini(rdev);
1072 radeon_irq_kms_fini(rdev);
1068 rv770_pcie_gart_fini(rdev); 1073 rv770_pcie_gart_fini(rdev);
1069 rdev->accel_working = false; 1074 rdev->accel_working = false;
1070 } 1075 }
1071 if (rdev->accel_working) { 1076 if (rdev->accel_working) {
1072 r = radeon_ib_pool_init(rdev); 1077 r = radeon_ib_pool_init(rdev);
1073 if (r) { 1078 if (r) {
1074 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); 1079 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1075 rdev->accel_working = false;
1076 }
1077 r = r600_ib_test(rdev);
1078 if (r) {
1079 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1080 rdev->accel_working = false; 1080 rdev->accel_working = false;
1081 } else {
1082 r = r600_ib_test(rdev);
1083 if (r) {
1084 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1085 rdev->accel_working = false;
1086 }
1081 } 1087 }
1082 } 1088 }
1083 return 0; 1089 return 0;
@@ -1085,13 +1091,11 @@ int rv770_init(struct radeon_device *rdev)
1085 1091
1086void rv770_fini(struct radeon_device *rdev) 1092void rv770_fini(struct radeon_device *rdev)
1087{ 1093{
1088 rv770_suspend(rdev);
1089
1090 r600_blit_fini(rdev); 1094 r600_blit_fini(rdev);
1095 r600_cp_fini(rdev);
1096 r600_wb_fini(rdev);
1091 r600_irq_fini(rdev); 1097 r600_irq_fini(rdev);
1092 radeon_irq_kms_fini(rdev); 1098 radeon_irq_kms_fini(rdev);
1093 radeon_ring_fini(rdev);
1094 r600_wb_fini(rdev);
1095 rv770_pcie_gart_fini(rdev); 1099 rv770_pcie_gart_fini(rdev);
1096 radeon_gem_fini(rdev); 1100 radeon_gem_fini(rdev);
1097 radeon_fence_driver_fini(rdev); 1101 radeon_fence_driver_fini(rdev);
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 2920f9a279e1..1a3e909b7bba 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -426,7 +426,8 @@ moved:
426 bdev->man[bo->mem.mem_type].gpu_offset; 426 bdev->man[bo->mem.mem_type].gpu_offset;
427 bo->cur_placement = bo->mem.placement; 427 bo->cur_placement = bo->mem.placement;
428 spin_unlock(&bo->lock); 428 spin_unlock(&bo->lock);
429 } 429 } else
430 bo->offset = 0;
430 431
431 return 0; 432 return 0;
432 433
@@ -523,52 +524,44 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
523static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) 524static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all)
524{ 525{
525 struct ttm_bo_global *glob = bdev->glob; 526 struct ttm_bo_global *glob = bdev->glob;
526 struct ttm_buffer_object *entry, *nentry; 527 struct ttm_buffer_object *entry = NULL;
527 struct list_head *list, *next; 528 int ret = 0;
528 int ret;
529 529
530 spin_lock(&glob->lru_lock); 530 spin_lock(&glob->lru_lock);
531 list_for_each_safe(list, next, &bdev->ddestroy) { 531 if (list_empty(&bdev->ddestroy))
532 entry = list_entry(list, struct ttm_buffer_object, ddestroy); 532 goto out_unlock;
533 nentry = NULL;
534 533
535 /* 534 entry = list_first_entry(&bdev->ddestroy,
536 * Protect the next list entry from destruction while we 535 struct ttm_buffer_object, ddestroy);
537 * unlock the lru_lock. 536 kref_get(&entry->list_kref);
538 */
539 537
540 if (next != &bdev->ddestroy) { 538 for (;;) {
541 nentry = list_entry(next, struct ttm_buffer_object, 539 struct ttm_buffer_object *nentry = NULL;
542 ddestroy); 540
541 if (entry->ddestroy.next != &bdev->ddestroy) {
542 nentry = list_first_entry(&entry->ddestroy,
543 struct ttm_buffer_object, ddestroy);
543 kref_get(&nentry->list_kref); 544 kref_get(&nentry->list_kref);
544 } 545 }
545 kref_get(&entry->list_kref);
546 546
547 spin_unlock(&glob->lru_lock); 547 spin_unlock(&glob->lru_lock);
548 ret = ttm_bo_cleanup_refs(entry, remove_all); 548 ret = ttm_bo_cleanup_refs(entry, remove_all);
549 kref_put(&entry->list_kref, ttm_bo_release_list); 549 kref_put(&entry->list_kref, ttm_bo_release_list);
550 entry = nentry;
551
552 if (ret || !entry)
553 goto out;
550 554
551 spin_lock(&glob->lru_lock); 555 spin_lock(&glob->lru_lock);
552 if (nentry) { 556 if (list_empty(&entry->ddestroy))
553 bool next_onlist = !list_empty(next);
554 spin_unlock(&glob->lru_lock);
555 kref_put(&nentry->list_kref, ttm_bo_release_list);
556 spin_lock(&glob->lru_lock);
557 /*
558 * Someone might have raced us and removed the
559 * next entry from the list. We don't bother restarting
560 * list traversal.
561 */
562
563 if (!next_onlist)
564 break;
565 }
566 if (ret)
567 break; 557 break;
568 } 558 }
569 ret = !list_empty(&bdev->ddestroy);
570 spin_unlock(&glob->lru_lock);
571 559
560out_unlock:
561 spin_unlock(&glob->lru_lock);
562out:
563 if (entry)
564 kref_put(&entry->list_kref, ttm_bo_release_list);
572 return ret; 565 return ret;
573} 566}
574 567
@@ -950,6 +943,14 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
950 ttm_flag_masked(&cur_flags, placement->busy_placement[i], 943 ttm_flag_masked(&cur_flags, placement->busy_placement[i],
951 ~TTM_PL_MASK_MEMTYPE); 944 ~TTM_PL_MASK_MEMTYPE);
952 945
946
947 if (mem_type == TTM_PL_SYSTEM) {
948 mem->mem_type = mem_type;
949 mem->placement = cur_flags;
950 mem->mm_node = NULL;
951 return 0;
952 }
953
953 ret = ttm_bo_mem_force_space(bo, mem_type, placement, mem, 954 ret = ttm_bo_mem_force_space(bo, mem_type, placement, mem,
954 interruptible, no_wait); 955 interruptible, no_wait);
955 if (ret == 0 && mem->mm_node) { 956 if (ret == 0 && mem->mm_node) {
@@ -1844,6 +1845,9 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink)
1844 * anyone tries to access a ttm page. 1845 * anyone tries to access a ttm page.
1845 */ 1846 */
1846 1847
1848 if (bo->bdev->driver->swap_notify)
1849 bo->bdev->driver->swap_notify(bo);
1850
1847 ret = ttm_tt_swapout(bo->ttm, bo->persistant_swap_storage); 1851 ret = ttm_tt_swapout(bo->ttm, bo->persistant_swap_storage);
1848out: 1852out:
1849 1853
@@ -1864,3 +1868,4 @@ void ttm_bo_swapout_all(struct ttm_bo_device *bdev)
1864 while (ttm_bo_swapout(&bdev->glob->shrink) == 0) 1868 while (ttm_bo_swapout(&bdev->glob->shrink) == 0)
1865 ; 1869 ;
1866} 1870}
1871EXPORT_SYMBOL(ttm_bo_swapout_all);
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
index ceae52f45c39..5ca37a58a98c 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -53,7 +53,6 @@ int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
53{ 53{
54 struct ttm_tt *ttm = bo->ttm; 54 struct ttm_tt *ttm = bo->ttm;
55 struct ttm_mem_reg *old_mem = &bo->mem; 55 struct ttm_mem_reg *old_mem = &bo->mem;
56 uint32_t save_flags = old_mem->placement;
57 int ret; 56 int ret;
58 57
59 if (old_mem->mem_type != TTM_PL_SYSTEM) { 58 if (old_mem->mem_type != TTM_PL_SYSTEM) {
@@ -62,7 +61,6 @@ int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
62 ttm_flag_masked(&old_mem->placement, TTM_PL_FLAG_SYSTEM, 61 ttm_flag_masked(&old_mem->placement, TTM_PL_FLAG_SYSTEM,
63 TTM_PL_MASK_MEM); 62 TTM_PL_MASK_MEM);
64 old_mem->mem_type = TTM_PL_SYSTEM; 63 old_mem->mem_type = TTM_PL_SYSTEM;
65 save_flags = old_mem->placement;
66 } 64 }
67 65
68 ret = ttm_tt_set_placement_caching(ttm, new_mem->placement); 66 ret = ttm_tt_set_placement_caching(ttm, new_mem->placement);
@@ -77,7 +75,7 @@ int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
77 75
78 *old_mem = *new_mem; 76 *old_mem = *new_mem;
79 new_mem->mm_node = NULL; 77 new_mem->mm_node = NULL;
80 ttm_flag_masked(&save_flags, new_mem->placement, TTM_PL_MASK_MEMTYPE); 78
81 return 0; 79 return 0;
82} 80}
83EXPORT_SYMBOL(ttm_bo_move_ttm); 81EXPORT_SYMBOL(ttm_bo_move_ttm);
@@ -219,7 +217,6 @@ int ttm_bo_move_memcpy(struct ttm_buffer_object *bo,
219 void *old_iomap; 217 void *old_iomap;
220 void *new_iomap; 218 void *new_iomap;
221 int ret; 219 int ret;
222 uint32_t save_flags = old_mem->placement;
223 unsigned long i; 220 unsigned long i;
224 unsigned long page; 221 unsigned long page;
225 unsigned long add = 0; 222 unsigned long add = 0;
@@ -270,7 +267,6 @@ out2:
270 267
271 *old_mem = *new_mem; 268 *old_mem = *new_mem;
272 new_mem->mm_node = NULL; 269 new_mem->mm_node = NULL;
273 ttm_flag_masked(&save_flags, new_mem->placement, TTM_PL_MASK_MEMTYPE);
274 270
275 if ((man->flags & TTM_MEMTYPE_FLAG_FIXED) && (ttm != NULL)) { 271 if ((man->flags & TTM_MEMTYPE_FLAG_FIXED) && (ttm != NULL)) {
276 ttm_tt_unbind(ttm); 272 ttm_tt_unbind(ttm);
@@ -428,7 +424,7 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo,
428 424
429 /* 425 /*
430 * We need to use vmap to get the desired page protection 426 * We need to use vmap to get the desired page protection
431 * or to make the buffer object look contigous. 427 * or to make the buffer object look contiguous.
432 */ 428 */
433 prot = (mem->placement & TTM_PL_FLAG_CACHED) ? 429 prot = (mem->placement & TTM_PL_FLAG_CACHED) ?
434 PAGE_KERNEL : 430 PAGE_KERNEL :
@@ -537,7 +533,6 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
537 struct ttm_mem_type_manager *man = &bdev->man[new_mem->mem_type]; 533 struct ttm_mem_type_manager *man = &bdev->man[new_mem->mem_type];
538 struct ttm_mem_reg *old_mem = &bo->mem; 534 struct ttm_mem_reg *old_mem = &bo->mem;
539 int ret; 535 int ret;
540 uint32_t save_flags = old_mem->placement;
541 struct ttm_buffer_object *ghost_obj; 536 struct ttm_buffer_object *ghost_obj;
542 void *tmp_obj = NULL; 537 void *tmp_obj = NULL;
543 538
@@ -598,7 +593,7 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
598 593
599 *old_mem = *new_mem; 594 *old_mem = *new_mem;
600 new_mem->mm_node = NULL; 595 new_mem->mm_node = NULL;
601 ttm_flag_masked(&save_flags, new_mem->placement, TTM_PL_MASK_MEMTYPE); 596
602 return 0; 597 return 0;
603} 598}
604EXPORT_SYMBOL(ttm_bo_move_accel_cleanup); 599EXPORT_SYMBOL(ttm_bo_move_accel_cleanup);
diff --git a/drivers/gpu/drm/ttm/ttm_lock.c b/drivers/gpu/drm/ttm/ttm_lock.c
index f619ebcaa4ec..3d172ef04ee1 100644
--- a/drivers/gpu/drm/ttm/ttm_lock.c
+++ b/drivers/gpu/drm/ttm/ttm_lock.c
@@ -288,6 +288,7 @@ void ttm_suspend_unlock(struct ttm_lock *lock)
288 wake_up_all(&lock->queue); 288 wake_up_all(&lock->queue);
289 spin_unlock(&lock->lock); 289 spin_unlock(&lock->lock);
290} 290}
291EXPORT_SYMBOL(ttm_suspend_unlock);
291 292
292static bool __ttm_suspend_lock(struct ttm_lock *lock) 293static bool __ttm_suspend_lock(struct ttm_lock *lock)
293{ 294{
@@ -309,3 +310,4 @@ void ttm_suspend_lock(struct ttm_lock *lock)
309{ 310{
310 wait_event(lock->queue, __ttm_suspend_lock(lock)); 311 wait_event(lock->queue, __ttm_suspend_lock(lock));
311} 312}
313EXPORT_SYMBOL(ttm_suspend_lock);
diff --git a/drivers/gpu/drm/ttm/ttm_object.c b/drivers/gpu/drm/ttm/ttm_object.c
index 1099abac824b..75e9d6f86ba4 100644
--- a/drivers/gpu/drm/ttm/ttm_object.c
+++ b/drivers/gpu/drm/ttm/ttm_object.c
@@ -109,8 +109,8 @@ struct ttm_ref_object {
109 struct drm_hash_item hash; 109 struct drm_hash_item hash;
110 struct list_head head; 110 struct list_head head;
111 struct kref kref; 111 struct kref kref;
112 struct ttm_base_object *obj;
113 enum ttm_ref_type ref_type; 112 enum ttm_ref_type ref_type;
113 struct ttm_base_object *obj;
114 struct ttm_object_file *tfile; 114 struct ttm_object_file *tfile;
115}; 115};
116 116
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 9c2b1cc5dba5..e2123af7775a 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -198,17 +198,26 @@ EXPORT_SYMBOL(ttm_tt_populate);
198static inline int ttm_tt_set_page_caching(struct page *p, 198static inline int ttm_tt_set_page_caching(struct page *p,
199 enum ttm_caching_state c_state) 199 enum ttm_caching_state c_state)
200{ 200{
201 int ret = 0;
202
201 if (PageHighMem(p)) 203 if (PageHighMem(p))
202 return 0; 204 return 0;
203 205
204 switch (c_state) { 206 if (get_page_memtype(p) != -1) {
205 case tt_cached: 207 /* p isn't in the default caching state, set it to
206 return set_pages_wb(p, 1); 208 * writeback first to free its current memtype. */
207 case tt_wc: 209
208 return set_memory_wc((unsigned long) page_address(p), 1); 210 ret = set_pages_wb(p, 1);
209 default: 211 if (ret)
210 return set_pages_uc(p, 1); 212 return ret;
211 } 213 }
214
215 if (c_state == tt_wc)
216 ret = set_memory_wc((unsigned long) page_address(p), 1);
217 else if (c_state == tt_uncached)
218 ret = set_pages_uc(p, 1);
219
220 return ret;
212} 221}
213#else /* CONFIG_X86 */ 222#else /* CONFIG_X86 */
214static inline int ttm_tt_set_page_caching(struct page *p, 223static inline int ttm_tt_set_page_caching(struct page *p,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c
index d6f2d2b882e9..825ebe3d89d5 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c
@@ -48,6 +48,15 @@ struct ttm_placement vmw_vram_placement = {
48 .busy_placement = &vram_placement_flags 48 .busy_placement = &vram_placement_flags
49}; 49};
50 50
51struct ttm_placement vmw_vram_sys_placement = {
52 .fpfn = 0,
53 .lpfn = 0,
54 .num_placement = 1,
55 .placement = &vram_placement_flags,
56 .num_busy_placement = 1,
57 .busy_placement = &sys_placement_flags
58};
59
51struct ttm_placement vmw_vram_ne_placement = { 60struct ttm_placement vmw_vram_ne_placement = {
52 .fpfn = 0, 61 .fpfn = 0,
53 .lpfn = 0, 62 .lpfn = 0,
@@ -172,6 +181,18 @@ static int vmw_verify_access(struct ttm_buffer_object *bo, struct file *filp)
172 return 0; 181 return 0;
173} 182}
174 183
184static void vmw_move_notify(struct ttm_buffer_object *bo,
185 struct ttm_mem_reg *new_mem)
186{
187 if (new_mem->mem_type != TTM_PL_SYSTEM)
188 vmw_dmabuf_gmr_unbind(bo);
189}
190
191static void vmw_swap_notify(struct ttm_buffer_object *bo)
192{
193 vmw_dmabuf_gmr_unbind(bo);
194}
195
175/** 196/**
176 * FIXME: We're using the old vmware polling method to sync. 197 * FIXME: We're using the old vmware polling method to sync.
177 * Do this with fences instead. 198 * Do this with fences instead.
@@ -225,5 +246,7 @@ struct ttm_bo_driver vmw_bo_driver = {
225 .sync_obj_wait = vmw_sync_obj_wait, 246 .sync_obj_wait = vmw_sync_obj_wait,
226 .sync_obj_flush = vmw_sync_obj_flush, 247 .sync_obj_flush = vmw_sync_obj_flush,
227 .sync_obj_unref = vmw_sync_obj_unref, 248 .sync_obj_unref = vmw_sync_obj_unref,
228 .sync_obj_ref = vmw_sync_obj_ref 249 .sync_obj_ref = vmw_sync_obj_ref,
250 .move_notify = vmw_move_notify,
251 .swap_notify = vmw_swap_notify
229}; 252};
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 1db1ef30be2b..a6e8f687fa64 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -147,6 +147,8 @@ static char *vmw_devname = "vmwgfx";
147 147
148static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 148static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
149static void vmw_master_init(struct vmw_master *); 149static void vmw_master_init(struct vmw_master *);
150static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
151 void *ptr);
150 152
151static void vmw_print_capabilities(uint32_t capabilities) 153static void vmw_print_capabilities(uint32_t capabilities)
152{ 154{
@@ -207,6 +209,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
207{ 209{
208 struct vmw_private *dev_priv; 210 struct vmw_private *dev_priv;
209 int ret; 211 int ret;
212 uint32_t svga_id;
210 213
211 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 214 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
212 if (unlikely(dev_priv == NULL)) { 215 if (unlikely(dev_priv == NULL)) {
@@ -217,6 +220,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
217 220
218 dev_priv->dev = dev; 221 dev_priv->dev = dev;
219 dev_priv->vmw_chipset = chipset; 222 dev_priv->vmw_chipset = chipset;
223 dev_priv->last_read_sequence = (uint32_t) -100;
220 mutex_init(&dev_priv->hw_mutex); 224 mutex_init(&dev_priv->hw_mutex);
221 mutex_init(&dev_priv->cmdbuf_mutex); 225 mutex_init(&dev_priv->cmdbuf_mutex);
222 rwlock_init(&dev_priv->resource_lock); 226 rwlock_init(&dev_priv->resource_lock);
@@ -236,6 +240,16 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
236 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 240 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
237 241
238 mutex_lock(&dev_priv->hw_mutex); 242 mutex_lock(&dev_priv->hw_mutex);
243
244 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
245 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
246 if (svga_id != SVGA_ID_2) {
247 ret = -ENOSYS;
248 DRM_ERROR("Unsuported SVGA ID 0x%x\n", svga_id);
249 mutex_unlock(&dev_priv->hw_mutex);
250 goto out_err0;
251 }
252
239 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 253 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
240 254
241 if (dev_priv->capabilities & SVGA_CAP_GMR) { 255 if (dev_priv->capabilities & SVGA_CAP_GMR) {
@@ -351,6 +365,11 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
351 vmw_fb_init(dev_priv); 365 vmw_fb_init(dev_priv);
352 } 366 }
353 367
368 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
369 register_pm_notifier(&dev_priv->pm_nb);
370
371 DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ? "Have 3D\n" : "No 3D\n");
372
354 return 0; 373 return 0;
355 374
356out_no_device: 375out_no_device:
@@ -385,6 +404,8 @@ static int vmw_driver_unload(struct drm_device *dev)
385 404
386 DRM_INFO(VMWGFX_DRIVER_NAME " unload.\n"); 405 DRM_INFO(VMWGFX_DRIVER_NAME " unload.\n");
387 406
407 unregister_pm_notifier(&dev_priv->pm_nb);
408
388 if (!dev_priv->stealth) { 409 if (!dev_priv->stealth) {
389 vmw_fb_close(dev_priv); 410 vmw_fb_close(dev_priv);
390 vmw_kms_close(dev_priv); 411 vmw_kms_close(dev_priv);
@@ -650,6 +671,57 @@ static void vmw_remove(struct pci_dev *pdev)
650 drm_put_dev(dev); 671 drm_put_dev(dev);
651} 672}
652 673
674static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
675 void *ptr)
676{
677 struct vmw_private *dev_priv =
678 container_of(nb, struct vmw_private, pm_nb);
679 struct vmw_master *vmaster = dev_priv->active_master;
680
681 switch (val) {
682 case PM_HIBERNATION_PREPARE:
683 case PM_SUSPEND_PREPARE:
684 ttm_suspend_lock(&vmaster->lock);
685
686 /**
687 * This empties VRAM and unbinds all GMR bindings.
688 * Buffer contents is moved to swappable memory.
689 */
690 ttm_bo_swapout_all(&dev_priv->bdev);
691 break;
692 case PM_POST_HIBERNATION:
693 case PM_POST_SUSPEND:
694 ttm_suspend_unlock(&vmaster->lock);
695 break;
696 case PM_RESTORE_PREPARE:
697 break;
698 case PM_POST_RESTORE:
699 break;
700 default:
701 break;
702 }
703 return 0;
704}
705
706/**
707 * These might not be needed with the virtual SVGA device.
708 */
709
710int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
711{
712 pci_save_state(pdev);
713 pci_disable_device(pdev);
714 pci_set_power_state(pdev, PCI_D3hot);
715 return 0;
716}
717
718int vmw_pci_resume(struct pci_dev *pdev)
719{
720 pci_set_power_state(pdev, PCI_D0);
721 pci_restore_state(pdev);
722 return pci_enable_device(pdev);
723}
724
653static struct drm_driver driver = { 725static struct drm_driver driver = {
654 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | 726 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
655 DRIVER_MODESET, 727 DRIVER_MODESET,
@@ -689,7 +761,9 @@ static struct drm_driver driver = {
689 .name = VMWGFX_DRIVER_NAME, 761 .name = VMWGFX_DRIVER_NAME,
690 .id_table = vmw_pci_id_list, 762 .id_table = vmw_pci_id_list,
691 .probe = vmw_probe, 763 .probe = vmw_probe,
692 .remove = vmw_remove 764 .remove = vmw_remove,
765 .suspend = vmw_pci_suspend,
766 .resume = vmw_pci_resume
693 }, 767 },
694 .name = VMWGFX_DRIVER_NAME, 768 .name = VMWGFX_DRIVER_NAME,
695 .desc = VMWGFX_DRIVER_DESC, 769 .desc = VMWGFX_DRIVER_DESC,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index e61bd85b6975..356dc935ec13 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -32,16 +32,17 @@
32#include "drmP.h" 32#include "drmP.h"
33#include "vmwgfx_drm.h" 33#include "vmwgfx_drm.h"
34#include "drm_hashtab.h" 34#include "drm_hashtab.h"
35#include "linux/suspend.h"
35#include "ttm/ttm_bo_driver.h" 36#include "ttm/ttm_bo_driver.h"
36#include "ttm/ttm_object.h" 37#include "ttm/ttm_object.h"
37#include "ttm/ttm_lock.h" 38#include "ttm/ttm_lock.h"
38#include "ttm/ttm_execbuf_util.h" 39#include "ttm/ttm_execbuf_util.h"
39#include "ttm/ttm_module.h" 40#include "ttm/ttm_module.h"
40 41
41#define VMWGFX_DRIVER_DATE "20090724" 42#define VMWGFX_DRIVER_DATE "20100209"
42#define VMWGFX_DRIVER_MAJOR 0 43#define VMWGFX_DRIVER_MAJOR 1
43#define VMWGFX_DRIVER_MINOR 1 44#define VMWGFX_DRIVER_MINOR 0
44#define VMWGFX_DRIVER_PATCHLEVEL 2 45#define VMWGFX_DRIVER_PATCHLEVEL 0
45#define VMWGFX_FILE_PAGE_OFFSET 0x00100000 46#define VMWGFX_FILE_PAGE_OFFSET 0x00100000
46#define VMWGFX_FIFO_STATIC_SIZE (1024*1024) 47#define VMWGFX_FIFO_STATIC_SIZE (1024*1024)
47#define VMWGFX_MAX_RELOCATIONS 2048 48#define VMWGFX_MAX_RELOCATIONS 2048
@@ -95,6 +96,8 @@ struct vmw_surface {
95 struct drm_vmw_size *sizes; 96 struct drm_vmw_size *sizes;
96 uint32_t num_sizes; 97 uint32_t num_sizes;
97 98
99 bool scanout;
100
98 /* TODO so far just a extra pointer */ 101 /* TODO so far just a extra pointer */
99 struct vmw_cursor_snooper snooper; 102 struct vmw_cursor_snooper snooper;
100}; 103};
@@ -110,6 +113,7 @@ struct vmw_fifo_state {
110 unsigned long static_buffer_size; 113 unsigned long static_buffer_size;
111 bool using_bounce_buffer; 114 bool using_bounce_buffer;
112 uint32_t capabilities; 115 uint32_t capabilities;
116 struct mutex fifo_mutex;
113 struct rw_semaphore rwsem; 117 struct rw_semaphore rwsem;
114}; 118};
115 119
@@ -210,7 +214,7 @@ struct vmw_private {
210 * Fencing and IRQs. 214 * Fencing and IRQs.
211 */ 215 */
212 216
213 uint32_t fence_seq; 217 atomic_t fence_seq;
214 wait_queue_head_t fence_queue; 218 wait_queue_head_t fence_queue;
215 wait_queue_head_t fifo_queue; 219 wait_queue_head_t fifo_queue;
216 atomic_t fence_queue_waiters; 220 atomic_t fence_queue_waiters;
@@ -258,6 +262,7 @@ struct vmw_private {
258 262
259 struct vmw_master *active_master; 263 struct vmw_master *active_master;
260 struct vmw_master fbdev_master; 264 struct vmw_master fbdev_master;
265 struct notifier_block pm_nb;
261}; 266};
262 267
263static inline struct vmw_private *vmw_priv(struct drm_device *dev) 268static inline struct vmw_private *vmw_priv(struct drm_device *dev)
@@ -353,6 +358,7 @@ extern int vmw_dmabuf_to_start_of_vram(struct vmw_private *vmw_priv,
353 struct vmw_dma_buffer *bo); 358 struct vmw_dma_buffer *bo);
354extern int vmw_dmabuf_from_vram(struct vmw_private *vmw_priv, 359extern int vmw_dmabuf_from_vram(struct vmw_private *vmw_priv,
355 struct vmw_dma_buffer *bo); 360 struct vmw_dma_buffer *bo);
361extern void vmw_dmabuf_gmr_unbind(struct ttm_buffer_object *bo);
356extern int vmw_stream_claim_ioctl(struct drm_device *dev, void *data, 362extern int vmw_stream_claim_ioctl(struct drm_device *dev, void *data,
357 struct drm_file *file_priv); 363 struct drm_file *file_priv);
358extern int vmw_stream_unref_ioctl(struct drm_device *dev, void *data, 364extern int vmw_stream_unref_ioctl(struct drm_device *dev, void *data,
@@ -386,6 +392,7 @@ extern int vmw_fifo_send_fence(struct vmw_private *dev_priv,
386 uint32_t *sequence); 392 uint32_t *sequence);
387extern void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason); 393extern void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason);
388extern int vmw_fifo_mmap(struct file *filp, struct vm_area_struct *vma); 394extern int vmw_fifo_mmap(struct file *filp, struct vm_area_struct *vma);
395extern bool vmw_fifo_have_3d(struct vmw_private *dev_priv);
389 396
390/** 397/**
391 * TTM glue - vmwgfx_ttm_glue.c 398 * TTM glue - vmwgfx_ttm_glue.c
@@ -401,6 +408,7 @@ extern int vmw_mmap(struct file *filp, struct vm_area_struct *vma);
401 408
402extern struct ttm_placement vmw_vram_placement; 409extern struct ttm_placement vmw_vram_placement;
403extern struct ttm_placement vmw_vram_ne_placement; 410extern struct ttm_placement vmw_vram_ne_placement;
411extern struct ttm_placement vmw_vram_sys_placement;
404extern struct ttm_placement vmw_sys_placement; 412extern struct ttm_placement vmw_sys_placement;
405extern struct ttm_bo_driver vmw_bo_driver; 413extern struct ttm_bo_driver vmw_bo_driver;
406extern int vmw_dma_quiescent(struct drm_device *dev); 414extern int vmw_dma_quiescent(struct drm_device *dev);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index 2e92da567403..d69caf92ffe7 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -490,10 +490,29 @@ static int vmw_validate_single_buffer(struct vmw_private *dev_priv,
490 if (vmw_dmabuf_gmr(bo) != SVGA_GMR_NULL) 490 if (vmw_dmabuf_gmr(bo) != SVGA_GMR_NULL)
491 return 0; 491 return 0;
492 492
493 /**
494 * Put BO in VRAM, only if there is space.
495 */
496
497 ret = ttm_bo_validate(bo, &vmw_vram_sys_placement, true, false);
498 if (unlikely(ret == -ERESTARTSYS))
499 return ret;
500
501 /**
502 * Otherwise, set it up as GMR.
503 */
504
505 if (vmw_dmabuf_gmr(bo) != SVGA_GMR_NULL)
506 return 0;
507
493 ret = vmw_gmr_bind(dev_priv, bo); 508 ret = vmw_gmr_bind(dev_priv, bo);
494 if (likely(ret == 0 || ret == -ERESTARTSYS)) 509 if (likely(ret == 0 || ret == -ERESTARTSYS))
495 return ret; 510 return ret;
496 511
512 /**
513 * If that failed, try VRAM again, this time evicting
514 * previous contents.
515 */
497 516
498 ret = ttm_bo_validate(bo, &vmw_vram_placement, true, false); 517 ret = ttm_bo_validate(bo, &vmw_vram_placement, true, false);
499 return ret; 518 return ret;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
index 641dde76ada1..4f4f6432be8b 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
@@ -649,14 +649,6 @@ int vmw_dmabuf_to_start_of_vram(struct vmw_private *vmw_priv,
649 if (unlikely(ret != 0)) 649 if (unlikely(ret != 0))
650 goto err_unlock; 650 goto err_unlock;
651 651
652 if (vmw_bo->gmr_bound) {
653 vmw_gmr_unbind(vmw_priv, vmw_bo->gmr_id);
654 spin_lock(&bo->glob->lru_lock);
655 ida_remove(&vmw_priv->gmr_ida, vmw_bo->gmr_id);
656 spin_unlock(&bo->glob->lru_lock);
657 vmw_bo->gmr_bound = NULL;
658 }
659
660 ret = ttm_bo_validate(bo, &ne_placement, false, false); 652 ret = ttm_bo_validate(bo, &ne_placement, false, false);
661 ttm_bo_unreserve(bo); 653 ttm_bo_unreserve(bo);
662err_unlock: 654err_unlock:
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
index 01feb48af333..39d43a01d846 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
@@ -29,6 +29,25 @@
29#include "drmP.h" 29#include "drmP.h"
30#include "ttm/ttm_placement.h" 30#include "ttm/ttm_placement.h"
31 31
32bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
33{
34 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
35 uint32_t fifo_min, hwversion;
36
37 fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN);
38 if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
39 return false;
40
41 hwversion = ioread32(fifo_mem + SVGA_FIFO_3D_HWVERSION);
42 if (hwversion == 0)
43 return false;
44
45 if (hwversion < SVGA3D_HWVERSION_WS65_B1)
46 return false;
47
48 return true;
49}
50
32int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) 51int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
33{ 52{
34 __le32 __iomem *fifo_mem = dev_priv->mmio_virt; 53 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
@@ -55,6 +74,7 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
55 fifo->reserved_size = 0; 74 fifo->reserved_size = 0;
56 fifo->using_bounce_buffer = false; 75 fifo->using_bounce_buffer = false;
57 76
77 mutex_init(&fifo->fifo_mutex);
58 init_rwsem(&fifo->rwsem); 78 init_rwsem(&fifo->rwsem);
59 79
60 /* 80 /*
@@ -98,8 +118,7 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
98 (unsigned int) min, 118 (unsigned int) min,
99 (unsigned int) fifo->capabilities); 119 (unsigned int) fifo->capabilities);
100 120
101 dev_priv->fence_seq = (uint32_t) -100; 121 atomic_set(&dev_priv->fence_seq, dev_priv->last_read_sequence);
102 dev_priv->last_read_sequence = (uint32_t) -100;
103 iowrite32(dev_priv->last_read_sequence, fifo_mem + SVGA_FIFO_FENCE); 122 iowrite32(dev_priv->last_read_sequence, fifo_mem + SVGA_FIFO_FENCE);
104 123
105 return vmw_fifo_send_fence(dev_priv, &dummy); 124 return vmw_fifo_send_fence(dev_priv, &dummy);
@@ -265,7 +284,7 @@ void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
265 uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; 284 uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
266 int ret; 285 int ret;
267 286
268 down_write(&fifo_state->rwsem); 287 mutex_lock(&fifo_state->fifo_mutex);
269 max = ioread32(fifo_mem + SVGA_FIFO_MAX); 288 max = ioread32(fifo_mem + SVGA_FIFO_MAX);
270 min = ioread32(fifo_mem + SVGA_FIFO_MIN); 289 min = ioread32(fifo_mem + SVGA_FIFO_MIN);
271 next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); 290 next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
@@ -333,7 +352,7 @@ void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
333 } 352 }
334out_err: 353out_err:
335 fifo_state->reserved_size = 0; 354 fifo_state->reserved_size = 0;
336 up_write(&fifo_state->rwsem); 355 mutex_unlock(&fifo_state->fifo_mutex);
337 return NULL; 356 return NULL;
338} 357}
339 358
@@ -408,6 +427,7 @@ void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
408 427
409 } 428 }
410 429
430 down_write(&fifo_state->rwsem);
411 if (fifo_state->using_bounce_buffer || reserveable) { 431 if (fifo_state->using_bounce_buffer || reserveable) {
412 next_cmd += bytes; 432 next_cmd += bytes;
413 if (next_cmd >= max) 433 if (next_cmd >= max)
@@ -419,8 +439,9 @@ void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
419 if (reserveable) 439 if (reserveable)
420 iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED); 440 iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
421 mb(); 441 mb();
422 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
423 up_write(&fifo_state->rwsem); 442 up_write(&fifo_state->rwsem);
443 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
444 mutex_unlock(&fifo_state->fifo_mutex);
424} 445}
425 446
426int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence) 447int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence)
@@ -433,9 +454,7 @@ int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence)
433 454
434 fm = vmw_fifo_reserve(dev_priv, bytes); 455 fm = vmw_fifo_reserve(dev_priv, bytes);
435 if (unlikely(fm == NULL)) { 456 if (unlikely(fm == NULL)) {
436 down_write(&fifo_state->rwsem); 457 *sequence = atomic_read(&dev_priv->fence_seq);
437 *sequence = dev_priv->fence_seq;
438 up_write(&fifo_state->rwsem);
439 ret = -ENOMEM; 458 ret = -ENOMEM;
440 (void)vmw_fallback_wait(dev_priv, false, true, *sequence, 459 (void)vmw_fallback_wait(dev_priv, false, true, *sequence,
441 false, 3*HZ); 460 false, 3*HZ);
@@ -443,7 +462,7 @@ int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence)
443 } 462 }
444 463
445 do { 464 do {
446 *sequence = dev_priv->fence_seq++; 465 *sequence = atomic_add_return(1, &dev_priv->fence_seq);
447 } while (*sequence == 0); 466 } while (*sequence == 0);
448 467
449 if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) { 468 if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
index 5fa6a4ed238a..1c7a316454d8 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
@@ -43,11 +43,17 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
43 param->value = vmw_overlay_num_free_overlays(dev_priv); 43 param->value = vmw_overlay_num_free_overlays(dev_priv);
44 break; 44 break;
45 case DRM_VMW_PARAM_3D: 45 case DRM_VMW_PARAM_3D:
46 param->value = dev_priv->capabilities & SVGA_CAP_3D ? 1 : 0; 46 param->value = vmw_fifo_have_3d(dev_priv) ? 1 : 0;
47 break; 47 break;
48 case DRM_VMW_PARAM_FIFO_OFFSET: 48 case DRM_VMW_PARAM_FIFO_OFFSET:
49 param->value = dev_priv->mmio_start; 49 param->value = dev_priv->mmio_start;
50 break; 50 break;
51 case DRM_VMW_PARAM_HW_CAPS:
52 param->value = dev_priv->capabilities;
53 break;
54 case DRM_VMW_PARAM_FIFO_CAPS:
55 param->value = dev_priv->fifo.capabilities;
56 break;
51 default: 57 default:
52 DRM_ERROR("Illegal vmwgfx get param request: %d\n", 58 DRM_ERROR("Illegal vmwgfx get param request: %d\n",
53 param->param); 59 param->param);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
index d40086fc8647..4d7cb5393860 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
@@ -85,19 +85,12 @@ bool vmw_fence_signaled(struct vmw_private *dev_priv,
85 return true; 85 return true;
86 86
87 /** 87 /**
88 * Below is to signal stale fences that have wrapped.
89 * First, block fence submission.
90 */
91
92 down_read(&fifo_state->rwsem);
93
94 /**
95 * Then check if the sequence is higher than what we've actually 88 * Then check if the sequence is higher than what we've actually
96 * emitted. Then the fence is stale and signaled. 89 * emitted. Then the fence is stale and signaled.
97 */ 90 */
98 91
99 ret = ((dev_priv->fence_seq - sequence) > VMW_FENCE_WRAP); 92 ret = ((atomic_read(&dev_priv->fence_seq) - sequence)
100 up_read(&fifo_state->rwsem); 93 > VMW_FENCE_WRAP);
101 94
102 return ret; 95 return ret;
103} 96}
@@ -127,7 +120,7 @@ int vmw_fallback_wait(struct vmw_private *dev_priv,
127 120
128 if (fifo_idle) 121 if (fifo_idle)
129 down_read(&fifo_state->rwsem); 122 down_read(&fifo_state->rwsem);
130 signal_seq = dev_priv->fence_seq; 123 signal_seq = atomic_read(&dev_priv->fence_seq);
131 ret = 0; 124 ret = 0;
132 125
133 for (;;) { 126 for (;;) {
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index b1af76e371c3..31f9afed0a63 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -553,9 +553,7 @@ int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
553 } *cmd; 553 } *cmd;
554 int i, increment = 1; 554 int i, increment = 1;
555 555
556 if (!num_clips || 556 if (!num_clips) {
557 !(dev_priv->fifo.capabilities &
558 SVGA_FIFO_CAP_SCREEN_OBJECT)) {
559 num_clips = 1; 557 num_clips = 1;
560 clips = &norect; 558 clips = &norect;
561 norect.x1 = norect.y1 = 0; 559 norect.x1 = norect.y1 = 0;
@@ -574,10 +572,10 @@ int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
574 572
575 for (i = 0; i < num_clips; i++, clips += increment) { 573 for (i = 0; i < num_clips; i++, clips += increment) {
576 cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE); 574 cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
577 cmd[i].body.x = cpu_to_le32(clips[i].x1); 575 cmd[i].body.x = cpu_to_le32(clips->x1);
578 cmd[i].body.y = cpu_to_le32(clips[i].y1); 576 cmd[i].body.y = cpu_to_le32(clips->y1);
579 cmd[i].body.width = cpu_to_le32(clips[i].x2 - clips[i].x1); 577 cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
580 cmd[i].body.height = cpu_to_le32(clips[i].y2 - clips[i].y1); 578 cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
581 } 579 }
582 580
583 vmw_fifo_commit(dev_priv, sizeof(*cmd) * num_clips); 581 vmw_fifo_commit(dev_priv, sizeof(*cmd) * num_clips);
@@ -709,6 +707,9 @@ static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
709 if (ret) 707 if (ret)
710 goto try_dmabuf; 708 goto try_dmabuf;
711 709
710 if (!surface->scanout)
711 goto err_not_scanout;
712
712 ret = vmw_kms_new_framebuffer_surface(dev_priv, surface, &vfb, 713 ret = vmw_kms_new_framebuffer_surface(dev_priv, surface, &vfb,
713 mode_cmd->width, mode_cmd->height); 714 mode_cmd->width, mode_cmd->height);
714 715
@@ -742,6 +743,13 @@ try_dmabuf:
742 } 743 }
743 744
744 return &vfb->base; 745 return &vfb->base;
746
747err_not_scanout:
748 DRM_ERROR("surface not marked as scanout\n");
749 /* vmw_user_surface_lookup takes one ref */
750 vmw_surface_unreference(&surface);
751
752 return NULL;
745} 753}
746 754
747static int vmw_kms_fb_changed(struct drm_device *dev) 755static int vmw_kms_fb_changed(struct drm_device *dev)
@@ -761,10 +769,10 @@ int vmw_kms_init(struct vmw_private *dev_priv)
761 769
762 drm_mode_config_init(dev); 770 drm_mode_config_init(dev);
763 dev->mode_config.funcs = &vmw_kms_funcs; 771 dev->mode_config.funcs = &vmw_kms_funcs;
764 dev->mode_config.min_width = 640; 772 dev->mode_config.min_width = 1;
765 dev->mode_config.min_height = 480; 773 dev->mode_config.min_height = 1;
766 dev->mode_config.max_width = 2048; 774 dev->mode_config.max_width = dev_priv->fb_max_width;
767 dev->mode_config.max_height = 2048; 775 dev->mode_config.max_height = dev_priv->fb_max_height;
768 776
769 ret = vmw_kms_init_legacy_display_system(dev_priv); 777 ret = vmw_kms_init_legacy_display_system(dev_priv);
770 778
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c b/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
index bb6e6a096d25..5b6eabeb7f51 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
@@ -104,7 +104,6 @@ static int vmw_dmabuf_pin_in_vram(struct vmw_private *dev_priv,
104 bool pin, bool interruptible) 104 bool pin, bool interruptible)
105{ 105{
106 struct ttm_buffer_object *bo = &buf->base; 106 struct ttm_buffer_object *bo = &buf->base;
107 struct ttm_bo_global *glob = bo->glob;
108 struct ttm_placement *overlay_placement = &vmw_vram_placement; 107 struct ttm_placement *overlay_placement = &vmw_vram_placement;
109 int ret; 108 int ret;
110 109
@@ -116,14 +115,6 @@ static int vmw_dmabuf_pin_in_vram(struct vmw_private *dev_priv,
116 if (unlikely(ret != 0)) 115 if (unlikely(ret != 0))
117 goto err; 116 goto err;
118 117
119 if (buf->gmr_bound) {
120 vmw_gmr_unbind(dev_priv, buf->gmr_id);
121 spin_lock(&glob->lru_lock);
122 ida_remove(&dev_priv->gmr_ida, buf->gmr_id);
123 spin_unlock(&glob->lru_lock);
124 buf->gmr_bound = NULL;
125 }
126
127 if (pin) 118 if (pin)
128 overlay_placement = &vmw_vram_ne_placement; 119 overlay_placement = &vmw_vram_ne_placement;
129 120
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index c012d5927f65..f8fbbc67a406 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
@@ -574,6 +574,7 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
574 574
575 srf->flags = req->flags; 575 srf->flags = req->flags;
576 srf->format = req->format; 576 srf->format = req->format;
577 srf->scanout = req->scanout;
577 memcpy(srf->mip_levels, req->mip_levels, sizeof(srf->mip_levels)); 578 memcpy(srf->mip_levels, req->mip_levels, sizeof(srf->mip_levels));
578 srf->num_sizes = 0; 579 srf->num_sizes = 0;
579 for (i = 0; i < DRM_VMW_MAX_SURFACE_FACES; ++i) 580 for (i = 0; i < DRM_VMW_MAX_SURFACE_FACES; ++i)
@@ -599,6 +600,26 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
599 if (unlikely(ret != 0)) 600 if (unlikely(ret != 0))
600 goto out_err1; 601 goto out_err1;
601 602
603 if (srf->scanout &&
604 srf->num_sizes == 1 &&
605 srf->sizes[0].width == 64 &&
606 srf->sizes[0].height == 64 &&
607 srf->format == SVGA3D_A8R8G8B8) {
608
609 srf->snooper.image = kmalloc(64 * 64 * 4, GFP_KERNEL);
610 /* clear the image */
611 if (srf->snooper.image) {
612 memset(srf->snooper.image, 0x00, 64 * 64 * 4);
613 } else {
614 DRM_ERROR("Failed to allocate cursor_image\n");
615 ret = -ENOMEM;
616 goto out_err1;
617 }
618 } else {
619 srf->snooper.image = NULL;
620 }
621 srf->snooper.crtc = NULL;
622
602 user_srf->base.shareable = false; 623 user_srf->base.shareable = false;
603 user_srf->base.tfile = NULL; 624 user_srf->base.tfile = NULL;
604 625
@@ -622,24 +643,6 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
622 return ret; 643 return ret;
623 } 644 }
624 645
625 if (srf->flags & (1 << 9) &&
626 srf->num_sizes == 1 &&
627 srf->sizes[0].width == 64 &&
628 srf->sizes[0].height == 64 &&
629 srf->format == SVGA3D_A8R8G8B8) {
630
631 srf->snooper.image = kmalloc(64 * 64 * 4, GFP_KERNEL);
632 /* clear the image */
633 if (srf->snooper.image)
634 memset(srf->snooper.image, 0x00, 64 * 64 * 4);
635 else
636 DRM_ERROR("Failed to allocate cursor_image\n");
637
638 } else {
639 srf->snooper.image = NULL;
640 }
641 srf->snooper.crtc = NULL;
642
643 rep->sid = user_srf->base.hash.key; 646 rep->sid = user_srf->base.hash.key;
644 if (rep->sid == SVGA3D_INVALID_ID) 647 if (rep->sid == SVGA3D_INVALID_ID)
645 DRM_ERROR("Created bad Surface ID.\n"); 648 DRM_ERROR("Created bad Surface ID.\n");
@@ -754,20 +757,29 @@ static size_t vmw_dmabuf_acc_size(struct ttm_bo_global *glob,
754 return bo_user_size + page_array_size; 757 return bo_user_size + page_array_size;
755} 758}
756 759
757void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo) 760void vmw_dmabuf_gmr_unbind(struct ttm_buffer_object *bo)
758{ 761{
759 struct vmw_dma_buffer *vmw_bo = vmw_dma_buffer(bo); 762 struct vmw_dma_buffer *vmw_bo = vmw_dma_buffer(bo);
760 struct ttm_bo_global *glob = bo->glob; 763 struct ttm_bo_global *glob = bo->glob;
761 struct vmw_private *dev_priv = 764 struct vmw_private *dev_priv =
762 container_of(bo->bdev, struct vmw_private, bdev); 765 container_of(bo->bdev, struct vmw_private, bdev);
763 766
764 ttm_mem_global_free(glob->mem_glob, bo->acc_size);
765 if (vmw_bo->gmr_bound) { 767 if (vmw_bo->gmr_bound) {
766 vmw_gmr_unbind(dev_priv, vmw_bo->gmr_id); 768 vmw_gmr_unbind(dev_priv, vmw_bo->gmr_id);
767 spin_lock(&glob->lru_lock); 769 spin_lock(&glob->lru_lock);
768 ida_remove(&dev_priv->gmr_ida, vmw_bo->gmr_id); 770 ida_remove(&dev_priv->gmr_ida, vmw_bo->gmr_id);
769 spin_unlock(&glob->lru_lock); 771 spin_unlock(&glob->lru_lock);
772 vmw_bo->gmr_bound = false;
770 } 773 }
774}
775
776void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo)
777{
778 struct vmw_dma_buffer *vmw_bo = vmw_dma_buffer(bo);
779 struct ttm_bo_global *glob = bo->glob;
780
781 vmw_dmabuf_gmr_unbind(bo);
782 ttm_mem_global_free(glob->mem_glob, bo->acc_size);
771 kfree(vmw_bo); 783 kfree(vmw_bo);
772} 784}
773 785
@@ -813,18 +825,10 @@ int vmw_dmabuf_init(struct vmw_private *dev_priv,
813static void vmw_user_dmabuf_destroy(struct ttm_buffer_object *bo) 825static void vmw_user_dmabuf_destroy(struct ttm_buffer_object *bo)
814{ 826{
815 struct vmw_user_dma_buffer *vmw_user_bo = vmw_user_dma_buffer(bo); 827 struct vmw_user_dma_buffer *vmw_user_bo = vmw_user_dma_buffer(bo);
816 struct vmw_dma_buffer *vmw_bo = &vmw_user_bo->dma;
817 struct ttm_bo_global *glob = bo->glob; 828 struct ttm_bo_global *glob = bo->glob;
818 struct vmw_private *dev_priv =
819 container_of(bo->bdev, struct vmw_private, bdev);
820 829
830 vmw_dmabuf_gmr_unbind(bo);
821 ttm_mem_global_free(glob->mem_glob, bo->acc_size); 831 ttm_mem_global_free(glob->mem_glob, bo->acc_size);
822 if (vmw_bo->gmr_bound) {
823 vmw_gmr_unbind(dev_priv, vmw_bo->gmr_id);
824 spin_lock(&glob->lru_lock);
825 ida_remove(&dev_priv->gmr_ida, vmw_bo->gmr_id);
826 spin_unlock(&glob->lru_lock);
827 }
828 kfree(vmw_user_bo); 832 kfree(vmw_user_bo);
829} 833}
830 834
@@ -868,7 +872,7 @@ int vmw_dmabuf_alloc_ioctl(struct drm_device *dev, void *data,
868 } 872 }
869 873
870 ret = vmw_dmabuf_init(dev_priv, &vmw_user_bo->dma, req->size, 874 ret = vmw_dmabuf_init(dev_priv, &vmw_user_bo->dma, req->size,
871 &vmw_vram_placement, true, 875 &vmw_vram_sys_placement, true,
872 &vmw_user_dmabuf_destroy); 876 &vmw_user_dmabuf_destroy);
873 if (unlikely(ret != 0)) 877 if (unlikely(ret != 0))
874 return ret; 878 return ret;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 02:35:25 -0500