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-rw-r--r--drivers/gpu/drm/drm_drv.c9
-rw-r--r--drivers/gpu/drm/drm_edid.c2
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c8
-rw-r--r--drivers/gpu/drm/gma500/gtt.c1
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c15
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c5
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h8
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c109
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h12
-rw-r--r--drivers/gpu/drm/i915/intel_display.c38
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c2
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h1
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c13
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/mc/base.c2
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c54
-rw-r--r--drivers/gpu/drm/radeon/btc_dpm.c6
-rw-r--r--drivers/gpu/drm/radeon/cik.c10
-rw-r--r--drivers/gpu/drm/radeon/dce6_afmt.c3
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c2
-rw-r--r--drivers/gpu/drm/radeon/evergreen_hdmi.c6
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h4
-rw-r--r--drivers/gpu/drm/radeon/ni.c1
-rw-r--r--drivers/gpu/drm/radeon/r600.c1
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c24
-rw-r--r--drivers/gpu/drm/radeon/r600d.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c33
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_test.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_uvd.c6
-rw-r--r--drivers/gpu/drm/radeon/si.c11
-rw-r--r--drivers/gpu/drm/radeon/si_dpm.c6
-rw-r--r--drivers/gpu/drm/radeon/sid.h4
-rw-r--r--drivers/gpu/drm/radeon/trinity_dpm.c2
-rw-r--r--drivers/gpu/drm/radeon/uvd_v1_0.c4
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c17
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_resource.c2
38 files changed, 279 insertions, 158 deletions
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index e572dd20bdee..05ad9ba0a67e 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -402,9 +402,16 @@ long drm_ioctl(struct file *filp,
402 cmd = ioctl->cmd_drv; 402 cmd = ioctl->cmd_drv;
403 } 403 }
404 else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) { 404 else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) {
405 u32 drv_size;
406
405 ioctl = &drm_ioctls[nr]; 407 ioctl = &drm_ioctls[nr];
406 cmd = ioctl->cmd; 408
409 drv_size = _IOC_SIZE(ioctl->cmd);
407 usize = asize = _IOC_SIZE(cmd); 410 usize = asize = _IOC_SIZE(cmd);
411 if (drv_size > asize)
412 asize = drv_size;
413
414 cmd = ioctl->cmd;
408 } else 415 } else
409 goto err_i1; 416 goto err_i1;
410 417
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 1688ff500513..830f7501cb4d 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2925,6 +2925,8 @@ int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
2925 /* Speaker Allocation Data Block */ 2925 /* Speaker Allocation Data Block */
2926 if (dbl == 3) { 2926 if (dbl == 3) {
2927 *sadb = kmalloc(dbl, GFP_KERNEL); 2927 *sadb = kmalloc(dbl, GFP_KERNEL);
2928 if (!*sadb)
2929 return -ENOMEM;
2928 memcpy(*sadb, &db[1], dbl); 2930 memcpy(*sadb, &db[1], dbl);
2929 count = dbl; 2931 count = dbl;
2930 break; 2932 break;
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index f6f6cc7fc133..3d13ca6e257f 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -416,14 +416,6 @@ static void drm_fb_helper_dpms(struct fb_info *info, int dpms_mode)
416 return; 416 return;
417 417
418 /* 418 /*
419 * fbdev->blank can be called from irq context in case of a panic.
420 * Since we already have our own special panic handler which will
421 * restore the fbdev console mode completely, just bail out early.
422 */
423 if (oops_in_progress)
424 return;
425
426 /*
427 * For each CRTC in this fb, turn the connectors on/off. 419 * For each CRTC in this fb, turn the connectors on/off.
428 */ 420 */
429 drm_modeset_lock_all(dev); 421 drm_modeset_lock_all(dev);
diff --git a/drivers/gpu/drm/gma500/gtt.c b/drivers/gpu/drm/gma500/gtt.c
index 92babac362ec..2db731f00930 100644
--- a/drivers/gpu/drm/gma500/gtt.c
+++ b/drivers/gpu/drm/gma500/gtt.c
@@ -204,6 +204,7 @@ static int psb_gtt_attach_pages(struct gtt_range *gt)
204 if (IS_ERR(pages)) 204 if (IS_ERR(pages))
205 return PTR_ERR(pages); 205 return PTR_ERR(pages);
206 206
207 gt->npage = gt->gem.size / PAGE_SIZE;
207 gt->pages = pages; 208 gt->pages = pages;
208 209
209 return 0; 210 return 0;
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index c27a21034a5e..d5c784d48671 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1290,12 +1290,9 @@ static int i915_load_modeset_init(struct drm_device *dev)
1290 * then we do not take part in VGA arbitration and the 1290 * then we do not take part in VGA arbitration and the
1291 * vga_client_register() fails with -ENODEV. 1291 * vga_client_register() fails with -ENODEV.
1292 */ 1292 */
1293 if (!HAS_PCH_SPLIT(dev)) { 1293 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1294 ret = vga_client_register(dev->pdev, dev, NULL, 1294 if (ret && ret != -ENODEV)
1295 i915_vga_set_decode); 1295 goto out;
1296 if (ret && ret != -ENODEV)
1297 goto out;
1298 }
1299 1296
1300 intel_register_dsm_handler(); 1297 intel_register_dsm_handler();
1301 1298
@@ -1351,12 +1348,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
1351 */ 1348 */
1352 intel_fbdev_initial_config(dev); 1349 intel_fbdev_initial_config(dev);
1353 1350
1354 /*
1355 * Must do this after fbcon init so that
1356 * vgacon_save_screen() works during the handover.
1357 */
1358 i915_disable_vga_mem(dev);
1359
1360 /* Only enable hotplug handling once the fbdev is fully set up. */ 1351 /* Only enable hotplug handling once the fbdev is fully set up. */
1361 dev_priv->enable_hotplug_processing = true; 1352 dev_priv->enable_hotplug_processing = true;
1362 1353
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 69d8ed5416c3..2ad27880cd04 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -505,6 +505,8 @@ static int i915_drm_freeze(struct drm_device *dev)
505 intel_modeset_suspend_hw(dev); 505 intel_modeset_suspend_hw(dev);
506 } 506 }
507 507
508 i915_gem_suspend_gtt_mappings(dev);
509
508 i915_save_state(dev); 510 i915_save_state(dev);
509 511
510 intel_opregion_fini(dev); 512 intel_opregion_fini(dev);
@@ -648,7 +650,8 @@ static int i915_drm_thaw(struct drm_device *dev)
648 mutex_lock(&dev->struct_mutex); 650 mutex_lock(&dev->struct_mutex);
649 i915_gem_restore_gtt_mappings(dev); 651 i915_gem_restore_gtt_mappings(dev);
650 mutex_unlock(&dev->struct_mutex); 652 mutex_unlock(&dev->struct_mutex);
651 } 653 } else if (drm_core_check_feature(dev, DRIVER_MODESET))
654 i915_check_and_clear_faults(dev);
652 655
653 __i915_drm_thaw(dev); 656 __i915_drm_thaw(dev);
654 657
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 35874b3a86dc..ab0f2c0a440c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -497,10 +497,12 @@ struct i915_address_space {
497 497
498 /* FIXME: Need a more generic return type */ 498 /* FIXME: Need a more generic return type */
499 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, 499 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
500 enum i915_cache_level level); 500 enum i915_cache_level level,
501 bool valid); /* Create a valid PTE */
501 void (*clear_range)(struct i915_address_space *vm, 502 void (*clear_range)(struct i915_address_space *vm,
502 unsigned int first_entry, 503 unsigned int first_entry,
503 unsigned int num_entries); 504 unsigned int num_entries,
505 bool use_scratch);
504 void (*insert_entries)(struct i915_address_space *vm, 506 void (*insert_entries)(struct i915_address_space *vm,
505 struct sg_table *st, 507 struct sg_table *st,
506 unsigned int first_entry, 508 unsigned int first_entry,
@@ -2065,6 +2067,8 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
2065void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 2067void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
2066 struct drm_i915_gem_object *obj); 2068 struct drm_i915_gem_object *obj);
2067 2069
2070void i915_check_and_clear_faults(struct drm_device *dev);
2071void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
2068void i915_gem_restore_gtt_mappings(struct drm_device *dev); 2072void i915_gem_restore_gtt_mappings(struct drm_device *dev);
2069int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 2073int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
2070void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 2074void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 212f6d8c35ec..1f7b4caefb6e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -58,9 +58,10 @@
58#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 58#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
59 59
60static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, 60static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
61 enum i915_cache_level level) 61 enum i915_cache_level level,
62 bool valid)
62{ 63{
63 gen6_gtt_pte_t pte = GEN6_PTE_VALID; 64 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
64 pte |= GEN6_PTE_ADDR_ENCODE(addr); 65 pte |= GEN6_PTE_ADDR_ENCODE(addr);
65 66
66 switch (level) { 67 switch (level) {
@@ -79,9 +80,10 @@ static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
79} 80}
80 81
81static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, 82static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
82 enum i915_cache_level level) 83 enum i915_cache_level level,
84 bool valid)
83{ 85{
84 gen6_gtt_pte_t pte = GEN6_PTE_VALID; 86 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
85 pte |= GEN6_PTE_ADDR_ENCODE(addr); 87 pte |= GEN6_PTE_ADDR_ENCODE(addr);
86 88
87 switch (level) { 89 switch (level) {
@@ -105,9 +107,10 @@ static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
105#define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 107#define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
106 108
107static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, 109static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
108 enum i915_cache_level level) 110 enum i915_cache_level level,
111 bool valid)
109{ 112{
110 gen6_gtt_pte_t pte = GEN6_PTE_VALID; 113 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
111 pte |= GEN6_PTE_ADDR_ENCODE(addr); 114 pte |= GEN6_PTE_ADDR_ENCODE(addr);
112 115
113 /* Mark the page as writeable. Other platforms don't have a 116 /* Mark the page as writeable. Other platforms don't have a
@@ -122,9 +125,10 @@ static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
122} 125}
123 126
124static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, 127static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
125 enum i915_cache_level level) 128 enum i915_cache_level level,
129 bool valid)
126{ 130{
127 gen6_gtt_pte_t pte = GEN6_PTE_VALID; 131 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
128 pte |= HSW_PTE_ADDR_ENCODE(addr); 132 pte |= HSW_PTE_ADDR_ENCODE(addr);
129 133
130 if (level != I915_CACHE_NONE) 134 if (level != I915_CACHE_NONE)
@@ -134,9 +138,10 @@ static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
134} 138}
135 139
136static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, 140static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
137 enum i915_cache_level level) 141 enum i915_cache_level level,
142 bool valid)
138{ 143{
139 gen6_gtt_pte_t pte = GEN6_PTE_VALID; 144 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
140 pte |= HSW_PTE_ADDR_ENCODE(addr); 145 pte |= HSW_PTE_ADDR_ENCODE(addr);
141 146
142 switch (level) { 147 switch (level) {
@@ -236,7 +241,8 @@ static int gen6_ppgtt_enable(struct drm_device *dev)
236/* PPGTT support for Sandybdrige/Gen6 and later */ 241/* PPGTT support for Sandybdrige/Gen6 and later */
237static void gen6_ppgtt_clear_range(struct i915_address_space *vm, 242static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
238 unsigned first_entry, 243 unsigned first_entry,
239 unsigned num_entries) 244 unsigned num_entries,
245 bool use_scratch)
240{ 246{
241 struct i915_hw_ppgtt *ppgtt = 247 struct i915_hw_ppgtt *ppgtt =
242 container_of(vm, struct i915_hw_ppgtt, base); 248 container_of(vm, struct i915_hw_ppgtt, base);
@@ -245,7 +251,7 @@ static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
245 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; 251 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
246 unsigned last_pte, i; 252 unsigned last_pte, i;
247 253
248 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC); 254 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
249 255
250 while (num_entries) { 256 while (num_entries) {
251 last_pte = first_pte + num_entries; 257 last_pte = first_pte + num_entries;
@@ -282,7 +288,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
282 dma_addr_t page_addr; 288 dma_addr_t page_addr;
283 289
284 page_addr = sg_page_iter_dma_address(&sg_iter); 290 page_addr = sg_page_iter_dma_address(&sg_iter);
285 pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level); 291 pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true);
286 if (++act_pte == I915_PPGTT_PT_ENTRIES) { 292 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
287 kunmap_atomic(pt_vaddr); 293 kunmap_atomic(pt_vaddr);
288 act_pt++; 294 act_pt++;
@@ -367,7 +373,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
367 } 373 }
368 374
369 ppgtt->base.clear_range(&ppgtt->base, 0, 375 ppgtt->base.clear_range(&ppgtt->base, 0,
370 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES); 376 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true);
371 377
372 ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); 378 ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
373 379
@@ -444,7 +450,8 @@ void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
444{ 450{
445 ppgtt->base.clear_range(&ppgtt->base, 451 ppgtt->base.clear_range(&ppgtt->base,
446 i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, 452 i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
447 obj->base.size >> PAGE_SHIFT); 453 obj->base.size >> PAGE_SHIFT,
454 true);
448} 455}
449 456
450extern int intel_iommu_gfx_mapped; 457extern int intel_iommu_gfx_mapped;
@@ -485,15 +492,65 @@ static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
485 dev_priv->mm.interruptible = interruptible; 492 dev_priv->mm.interruptible = interruptible;
486} 493}
487 494
495void i915_check_and_clear_faults(struct drm_device *dev)
496{
497 struct drm_i915_private *dev_priv = dev->dev_private;
498 struct intel_ring_buffer *ring;
499 int i;
500
501 if (INTEL_INFO(dev)->gen < 6)
502 return;
503
504 for_each_ring(ring, dev_priv, i) {
505 u32 fault_reg;
506 fault_reg = I915_READ(RING_FAULT_REG(ring));
507 if (fault_reg & RING_FAULT_VALID) {
508 DRM_DEBUG_DRIVER("Unexpected fault\n"
509 "\tAddr: 0x%08lx\\n"
510 "\tAddress space: %s\n"
511 "\tSource ID: %d\n"
512 "\tType: %d\n",
513 fault_reg & PAGE_MASK,
514 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
515 RING_FAULT_SRCID(fault_reg),
516 RING_FAULT_FAULT_TYPE(fault_reg));
517 I915_WRITE(RING_FAULT_REG(ring),
518 fault_reg & ~RING_FAULT_VALID);
519 }
520 }
521 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
522}
523
524void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
525{
526 struct drm_i915_private *dev_priv = dev->dev_private;
527
528 /* Don't bother messing with faults pre GEN6 as we have little
529 * documentation supporting that it's a good idea.
530 */
531 if (INTEL_INFO(dev)->gen < 6)
532 return;
533
534 i915_check_and_clear_faults(dev);
535
536 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
537 dev_priv->gtt.base.start / PAGE_SIZE,
538 dev_priv->gtt.base.total / PAGE_SIZE,
539 false);
540}
541
488void i915_gem_restore_gtt_mappings(struct drm_device *dev) 542void i915_gem_restore_gtt_mappings(struct drm_device *dev)
489{ 543{
490 struct drm_i915_private *dev_priv = dev->dev_private; 544 struct drm_i915_private *dev_priv = dev->dev_private;
491 struct drm_i915_gem_object *obj; 545 struct drm_i915_gem_object *obj;
492 546
547 i915_check_and_clear_faults(dev);
548
493 /* First fill our portion of the GTT with scratch pages */ 549 /* First fill our portion of the GTT with scratch pages */
494 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, 550 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
495 dev_priv->gtt.base.start / PAGE_SIZE, 551 dev_priv->gtt.base.start / PAGE_SIZE,
496 dev_priv->gtt.base.total / PAGE_SIZE); 552 dev_priv->gtt.base.total / PAGE_SIZE,
553 true);
497 554
498 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 555 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
499 i915_gem_clflush_object(obj, obj->pin_display); 556 i915_gem_clflush_object(obj, obj->pin_display);
@@ -536,7 +593,7 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
536 593
537 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { 594 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
538 addr = sg_page_iter_dma_address(&sg_iter); 595 addr = sg_page_iter_dma_address(&sg_iter);
539 iowrite32(vm->pte_encode(addr, level), &gtt_entries[i]); 596 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
540 i++; 597 i++;
541 } 598 }
542 599
@@ -548,7 +605,7 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
548 */ 605 */
549 if (i != 0) 606 if (i != 0)
550 WARN_ON(readl(&gtt_entries[i-1]) != 607 WARN_ON(readl(&gtt_entries[i-1]) !=
551 vm->pte_encode(addr, level)); 608 vm->pte_encode(addr, level, true));
552 609
553 /* This next bit makes the above posting read even more important. We 610 /* This next bit makes the above posting read even more important. We
554 * want to flush the TLBs only after we're certain all the PTE updates 611 * want to flush the TLBs only after we're certain all the PTE updates
@@ -560,7 +617,8 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
560 617
561static void gen6_ggtt_clear_range(struct i915_address_space *vm, 618static void gen6_ggtt_clear_range(struct i915_address_space *vm,
562 unsigned int first_entry, 619 unsigned int first_entry,
563 unsigned int num_entries) 620 unsigned int num_entries,
621 bool use_scratch)
564{ 622{
565 struct drm_i915_private *dev_priv = vm->dev->dev_private; 623 struct drm_i915_private *dev_priv = vm->dev->dev_private;
566 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = 624 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
@@ -573,7 +631,8 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm,
573 first_entry, num_entries, max_entries)) 631 first_entry, num_entries, max_entries))
574 num_entries = max_entries; 632 num_entries = max_entries;
575 633
576 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC); 634 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
635
577 for (i = 0; i < num_entries; i++) 636 for (i = 0; i < num_entries; i++)
578 iowrite32(scratch_pte, &gtt_base[i]); 637 iowrite32(scratch_pte, &gtt_base[i]);
579 readl(gtt_base); 638 readl(gtt_base);
@@ -594,7 +653,8 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm,
594 653
595static void i915_ggtt_clear_range(struct i915_address_space *vm, 654static void i915_ggtt_clear_range(struct i915_address_space *vm,
596 unsigned int first_entry, 655 unsigned int first_entry,
597 unsigned int num_entries) 656 unsigned int num_entries,
657 bool unused)
598{ 658{
599 intel_gtt_clear_range(first_entry, num_entries); 659 intel_gtt_clear_range(first_entry, num_entries);
600} 660}
@@ -622,7 +682,8 @@ void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
622 682
623 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, 683 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
624 entry, 684 entry,
625 obj->base.size >> PAGE_SHIFT); 685 obj->base.size >> PAGE_SHIFT,
686 true);
626 687
627 obj->has_global_gtt_mapping = 0; 688 obj->has_global_gtt_mapping = 0;
628} 689}
@@ -709,11 +770,11 @@ void i915_gem_setup_global_gtt(struct drm_device *dev,
709 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; 770 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
710 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", 771 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
711 hole_start, hole_end); 772 hole_start, hole_end);
712 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count); 773 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true);
713 } 774 }
714 775
715 /* And finally clear the reserved guard page */ 776 /* And finally clear the reserved guard page */
716 ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1); 777 ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true);
717} 778}
718 779
719static bool 780static bool
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c159e1a6810f..ef9b35479f01 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -604,6 +604,10 @@
604#define ARB_MODE_SWIZZLE_IVB (1<<5) 604#define ARB_MODE_SWIZZLE_IVB (1<<5)
605#define RENDER_HWS_PGA_GEN7 (0x04080) 605#define RENDER_HWS_PGA_GEN7 (0x04080)
606#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) 606#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
607#define RING_FAULT_GTTSEL_MASK (1<<11)
608#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
609#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
610#define RING_FAULT_VALID (1<<0)
607#define DONE_REG 0x40b0 611#define DONE_REG 0x40b0
608#define BSD_HWS_PGA_GEN7 (0x04180) 612#define BSD_HWS_PGA_GEN7 (0x04180)
609#define BLT_HWS_PGA_GEN7 (0x04280) 613#define BLT_HWS_PGA_GEN7 (0x04280)
@@ -3881,6 +3885,9 @@
3881#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 3885#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
3882#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 3886#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
3883 3887
3888#define HSW_SCRATCH1 0xb038
3889#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
3890
3884#define HSW_FUSE_STRAP 0x42014 3891#define HSW_FUSE_STRAP 0x42014
3885#define HSW_CDCLK_LIMIT (1 << 24) 3892#define HSW_CDCLK_LIMIT (1 << 24)
3886 3893
@@ -4276,7 +4283,9 @@
4276#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 4283#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
4277 4284
4278#define SOUTH_DSPCLK_GATE_D 0xc2020 4285#define SOUTH_DSPCLK_GATE_D 0xc2020
4286#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
4279#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 4287#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
4288#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
4280#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 4289#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
4281 4290
4282/* CPU: FDI_TX */ 4291/* CPU: FDI_TX */
@@ -4728,6 +4737,9 @@
4728#define GEN7_ROW_CHICKEN2_GT2 0xf4f4 4737#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
4729#define DOP_CLOCK_GATING_DISABLE (1<<0) 4738#define DOP_CLOCK_GATING_DISABLE (1<<0)
4730 4739
4740#define HSW_ROW_CHICKEN3 0xe49c
4741#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
4742
4731#define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020) 4743#define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020)
4732#define INTEL_AUDIO_DEVCL 0x808629FB 4744#define INTEL_AUDIO_DEVCL 0x808629FB
4733#define INTEL_AUDIO_DEVBLC 0x80862801 4745#define INTEL_AUDIO_DEVBLC 0x80862801
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e5822e79f912..581fb4b2f766 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3941,8 +3941,6 @@ static void intel_connector_check_state(struct intel_connector *connector)
3941 * consider. */ 3941 * consider. */
3942void intel_connector_dpms(struct drm_connector *connector, int mode) 3942void intel_connector_dpms(struct drm_connector *connector, int mode)
3943{ 3943{
3944 struct intel_encoder *encoder = intel_attached_encoder(connector);
3945
3946 /* All the simple cases only support two dpms states. */ 3944 /* All the simple cases only support two dpms states. */
3947 if (mode != DRM_MODE_DPMS_ON) 3945 if (mode != DRM_MODE_DPMS_ON)
3948 mode = DRM_MODE_DPMS_OFF; 3946 mode = DRM_MODE_DPMS_OFF;
@@ -3953,10 +3951,8 @@ void intel_connector_dpms(struct drm_connector *connector, int mode)
3953 connector->dpms = mode; 3951 connector->dpms = mode;
3954 3952
3955 /* Only need to change hw state when actually enabled */ 3953 /* Only need to change hw state when actually enabled */
3956 if (encoder->base.crtc) 3954 if (connector->encoder)
3957 intel_encoder_dpms(encoder, mode); 3955 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
3958 else
3959 WARN_ON(encoder->connectors_active != false);
3960 3956
3961 intel_modeset_check_state(connector->dev); 3957 intel_modeset_check_state(connector->dev);
3962} 3958}
@@ -10049,33 +10045,6 @@ static void i915_disable_vga(struct drm_device *dev)
10049 POSTING_READ(vga_reg); 10045 POSTING_READ(vga_reg);
10050} 10046}
10051 10047
10052static void i915_enable_vga_mem(struct drm_device *dev)
10053{
10054 /* Enable VGA memory on Intel HD */
10055 if (HAS_PCH_SPLIT(dev)) {
10056 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10057 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10058 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10059 VGA_RSRC_LEGACY_MEM |
10060 VGA_RSRC_NORMAL_IO |
10061 VGA_RSRC_NORMAL_MEM);
10062 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10063 }
10064}
10065
10066void i915_disable_vga_mem(struct drm_device *dev)
10067{
10068 /* Disable VGA memory on Intel HD */
10069 if (HAS_PCH_SPLIT(dev)) {
10070 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10071 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10072 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10073 VGA_RSRC_NORMAL_IO |
10074 VGA_RSRC_NORMAL_MEM);
10075 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10076 }
10077}
10078
10079void intel_modeset_init_hw(struct drm_device *dev) 10048void intel_modeset_init_hw(struct drm_device *dev)
10080{ 10049{
10081 intel_init_power_well(dev); 10050 intel_init_power_well(dev);
@@ -10354,7 +10323,6 @@ void i915_redisable_vga(struct drm_device *dev)
10354 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { 10323 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10355 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); 10324 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10356 i915_disable_vga(dev); 10325 i915_disable_vga(dev);
10357 i915_disable_vga_mem(dev);
10358 } 10326 }
10359} 10327}
10360 10328
@@ -10568,8 +10536,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
10568 10536
10569 intel_disable_fbc(dev); 10537 intel_disable_fbc(dev);
10570 10538
10571 i915_enable_vga_mem(dev);
10572
10573 intel_disable_gt_powersave(dev); 10539 intel_disable_gt_powersave(dev);
10574 10540
10575 ironlake_teardown_rc6(dev); 10541 ironlake_teardown_rc6(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 79c14e298ba6..2c555f91bfae 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1467,7 +1467,7 @@ static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1467 1467
1468 /* Avoid continuous PSR exit by masking memup and hpd */ 1468 /* Avoid continuous PSR exit by masking memup and hpd */
1469 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP | 1469 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1470 EDP_PSR_DEBUG_MASK_HPD); 1470 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1471 1471
1472 intel_dp->psr_setup_done = true; 1472 intel_dp->psr_setup_done = true;
1473} 1473}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 28cae80495e2..9b7b68fd5d47 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -793,6 +793,5 @@ extern void hsw_pc8_disable_interrupts(struct drm_device *dev);
793extern void hsw_pc8_restore_interrupts(struct drm_device *dev); 793extern void hsw_pc8_restore_interrupts(struct drm_device *dev);
794extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); 794extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
795extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); 795extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
796extern void i915_disable_vga_mem(struct drm_device *dev);
797 796
798#endif /* __INTEL_DRV_H__ */ 797#endif /* __INTEL_DRV_H__ */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dd176b7296c1..26c2ea3e985c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3864,8 +3864,6 @@ static void valleyview_enable_rps(struct drm_device *dev)
3864 dev_priv->rps.rpe_delay), 3864 dev_priv->rps.rpe_delay),
3865 dev_priv->rps.rpe_delay); 3865 dev_priv->rps.rpe_delay);
3866 3866
3867 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3868
3869 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); 3867 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3870 3868
3871 gen6_enable_rps_interrupts(dev); 3869 gen6_enable_rps_interrupts(dev);
@@ -4761,7 +4759,9 @@ static void cpt_init_clock_gating(struct drm_device *dev)
4761 * gating for the panel power sequencer or it will fail to 4759 * gating for the panel power sequencer or it will fail to
4762 * start up when no ports are active. 4760 * start up when no ports are active.
4763 */ 4761 */
4764 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 4762 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4763 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4764 PCH_CPUNIT_CLOCK_GATE_DISABLE);
4765 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 4765 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4766 DPLS_EDP_PPS_FIX_DIS); 4766 DPLS_EDP_PPS_FIX_DIS);
4767 /* The below fixes the weird display corruption, a few pixels shifted 4767 /* The below fixes the weird display corruption, a few pixels shifted
@@ -4955,6 +4955,11 @@ static void haswell_init_clock_gating(struct drm_device *dev)
4955 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 4955 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4956 GEN7_WA_L3_CHICKEN_MODE); 4956 GEN7_WA_L3_CHICKEN_MODE);
4957 4957
4958 /* L3 caching of data atomics doesn't work -- disable it. */
4959 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4960 I915_WRITE(HSW_ROW_CHICKEN3,
4961 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
4962
4958 /* This is required by WaCatErrorRejectionIssue:hsw */ 4963 /* This is required by WaCatErrorRejectionIssue:hsw */
4959 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 4964 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4960 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 4965 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
@@ -5681,5 +5686,7 @@ void intel_pm_init(struct drm_device *dev)
5681 5686
5682 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 5687 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5683 intel_gen6_powersave_work); 5688 intel_gen6_powersave_work);
5689
5690 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
5684} 5691}
5685 5692
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c
index 37712a6df923..e290cfa4acee 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c
@@ -113,7 +113,7 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
113 pmc->use_msi = false; 113 pmc->use_msi = false;
114 break; 114 break;
115 default: 115 default:
116 pmc->use_msi = nouveau_boolopt(device->cfgopt, "NvMSI", true); 116 pmc->use_msi = nouveau_boolopt(device->cfgopt, "NvMSI", false);
117 if (pmc->use_msi) { 117 if (pmc->use_msi) {
118 pmc->use_msi = pci_enable_msi(device->pdev) == 0; 118 pmc->use_msi = pci_enable_msi(device->pdev) == 0;
119 if (pmc->use_msi) { 119 if (pmc->use_msi) {
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 32923d2f6002..5e891b226acf 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -707,24 +707,37 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
707 switch (connector->connector_type) { 707 switch (connector->connector_type) {
708 case DRM_MODE_CONNECTOR_DVII: 708 case DRM_MODE_CONNECTOR_DVII:
709 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 709 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
710 if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) || 710 if (radeon_audio != 0) {
711 (drm_detect_hdmi_monitor(radeon_connector->edid) && 711 if (radeon_connector->use_digital &&
712 (radeon_connector->audio == RADEON_AUDIO_AUTO))) 712 (radeon_connector->audio == RADEON_AUDIO_ENABLE))
713 return ATOM_ENCODER_MODE_HDMI; 713 return ATOM_ENCODER_MODE_HDMI;
714 else if (radeon_connector->use_digital) 714 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
715 (radeon_connector->audio == RADEON_AUDIO_AUTO))
716 return ATOM_ENCODER_MODE_HDMI;
717 else if (radeon_connector->use_digital)
718 return ATOM_ENCODER_MODE_DVI;
719 else
720 return ATOM_ENCODER_MODE_CRT;
721 } else if (radeon_connector->use_digital) {
715 return ATOM_ENCODER_MODE_DVI; 722 return ATOM_ENCODER_MODE_DVI;
716 else 723 } else {
717 return ATOM_ENCODER_MODE_CRT; 724 return ATOM_ENCODER_MODE_CRT;
725 }
718 break; 726 break;
719 case DRM_MODE_CONNECTOR_DVID: 727 case DRM_MODE_CONNECTOR_DVID:
720 case DRM_MODE_CONNECTOR_HDMIA: 728 case DRM_MODE_CONNECTOR_HDMIA:
721 default: 729 default:
722 if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) || 730 if (radeon_audio != 0) {
723 (drm_detect_hdmi_monitor(radeon_connector->edid) && 731 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
724 (radeon_connector->audio == RADEON_AUDIO_AUTO))) 732 return ATOM_ENCODER_MODE_HDMI;
725 return ATOM_ENCODER_MODE_HDMI; 733 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
726 else 734 (radeon_connector->audio == RADEON_AUDIO_AUTO))
735 return ATOM_ENCODER_MODE_HDMI;
736 else
737 return ATOM_ENCODER_MODE_DVI;
738 } else {
727 return ATOM_ENCODER_MODE_DVI; 739 return ATOM_ENCODER_MODE_DVI;
740 }
728 break; 741 break;
729 case DRM_MODE_CONNECTOR_LVDS: 742 case DRM_MODE_CONNECTOR_LVDS:
730 return ATOM_ENCODER_MODE_LVDS; 743 return ATOM_ENCODER_MODE_LVDS;
@@ -732,14 +745,19 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
732 case DRM_MODE_CONNECTOR_DisplayPort: 745 case DRM_MODE_CONNECTOR_DisplayPort:
733 dig_connector = radeon_connector->con_priv; 746 dig_connector = radeon_connector->con_priv;
734 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 747 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
735 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 748 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
736 return ATOM_ENCODER_MODE_DP; 749 return ATOM_ENCODER_MODE_DP;
737 else if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) || 750 } else if (radeon_audio != 0) {
738 (drm_detect_hdmi_monitor(radeon_connector->edid) && 751 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
739 (radeon_connector->audio == RADEON_AUDIO_AUTO))) 752 return ATOM_ENCODER_MODE_HDMI;
740 return ATOM_ENCODER_MODE_HDMI; 753 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
741 else 754 (radeon_connector->audio == RADEON_AUDIO_AUTO))
755 return ATOM_ENCODER_MODE_HDMI;
756 else
757 return ATOM_ENCODER_MODE_DVI;
758 } else {
742 return ATOM_ENCODER_MODE_DVI; 759 return ATOM_ENCODER_MODE_DVI;
760 }
743 break; 761 break;
744 case DRM_MODE_CONNECTOR_eDP: 762 case DRM_MODE_CONNECTOR_eDP:
745 return ATOM_ENCODER_MODE_DP; 763 return ATOM_ENCODER_MODE_DP;
@@ -1655,7 +1673,7 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1655 * does the same thing and more. 1673 * does the same thing and more.
1656 */ 1674 */
1657 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) && 1675 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
1658 (rdev->family != CHIP_RS880)) 1676 (rdev->family != CHIP_RS780) && (rdev->family != CHIP_RS880))
1659 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1677 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1660 } 1678 }
1661 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1679 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
index b162e98a2953..9b6950d9b3c0 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.c
+++ b/drivers/gpu/drm/radeon/btc_dpm.c
@@ -1930,7 +1930,7 @@ static int btc_set_mc_special_registers(struct radeon_device *rdev,
1930 } 1930 }
1931 j++; 1931 j++;
1932 1932
1933 if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1933 if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1934 return -EINVAL; 1934 return -EINVAL;
1935 1935
1936 tmp = RREG32(MC_PMG_CMD_MRS); 1936 tmp = RREG32(MC_PMG_CMD_MRS);
@@ -1945,7 +1945,7 @@ static int btc_set_mc_special_registers(struct radeon_device *rdev,
1945 } 1945 }
1946 j++; 1946 j++;
1947 1947
1948 if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1948 if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1949 return -EINVAL; 1949 return -EINVAL;
1950 break; 1950 break;
1951 case MC_SEQ_RESERVE_M >> 2: 1951 case MC_SEQ_RESERVE_M >> 2:
@@ -1959,7 +1959,7 @@ static int btc_set_mc_special_registers(struct radeon_device *rdev,
1959 } 1959 }
1960 j++; 1960 j++;
1961 1961
1962 if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1962 if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1963 return -EINVAL; 1963 return -EINVAL;
1964 break; 1964 break;
1965 default: 1965 default:
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index d02fd1c045d5..9cd2bc989ac7 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -77,6 +77,8 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev);
77static void cik_program_aspm(struct radeon_device *rdev); 77static void cik_program_aspm(struct radeon_device *rdev);
78static void cik_init_pg(struct radeon_device *rdev); 78static void cik_init_pg(struct radeon_device *rdev);
79static void cik_init_cg(struct radeon_device *rdev); 79static void cik_init_cg(struct radeon_device *rdev);
80static void cik_fini_pg(struct radeon_device *rdev);
81static void cik_fini_cg(struct radeon_device *rdev);
80static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev, 82static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
81 bool enable); 83 bool enable);
82 84
@@ -1692,6 +1694,7 @@ static int cik_init_microcode(struct radeon_device *rdev)
1692 fw_name); 1694 fw_name);
1693 release_firmware(rdev->smc_fw); 1695 release_firmware(rdev->smc_fw);
1694 rdev->smc_fw = NULL; 1696 rdev->smc_fw = NULL;
1697 err = 0;
1695 } else if (rdev->smc_fw->size != smc_req_size) { 1698 } else if (rdev->smc_fw->size != smc_req_size) {
1696 printk(KERN_ERR 1699 printk(KERN_ERR
1697 "cik_smc: Bogus length %zu in firmware \"%s\"\n", 1700 "cik_smc: Bogus length %zu in firmware \"%s\"\n",
@@ -3180,6 +3183,7 @@ int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3180 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3183 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3181 if (r) { 3184 if (r) {
3182 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3185 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3186 radeon_scratch_free(rdev, scratch);
3183 return r; 3187 return r;
3184 } 3188 }
3185 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 3189 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
@@ -3196,6 +3200,8 @@ int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3196 r = radeon_fence_wait(ib.fence, false); 3200 r = radeon_fence_wait(ib.fence, false);
3197 if (r) { 3201 if (r) {
3198 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3202 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3203 radeon_scratch_free(rdev, scratch);
3204 radeon_ib_free(rdev, &ib);
3199 return r; 3205 return r;
3200 } 3206 }
3201 for (i = 0; i < rdev->usec_timeout; i++) { 3207 for (i = 0; i < rdev->usec_timeout; i++) {
@@ -4185,6 +4191,10 @@ static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
4185 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 4191 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4186 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 4192 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4187 4193
4194 /* disable CG/PG */
4195 cik_fini_pg(rdev);
4196 cik_fini_cg(rdev);
4197
4188 /* stop the rlc */ 4198 /* stop the rlc */
4189 cik_rlc_stop(rdev); 4199 cik_rlc_stop(rdev);
4190 4200
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c
index 85a69d2ea3d2..9fcd338c0fcf 100644
--- a/drivers/gpu/drm/radeon/dce6_afmt.c
+++ b/drivers/gpu/drm/radeon/dce6_afmt.c
@@ -113,6 +113,9 @@ void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
113 u8 *sadb; 113 u8 *sadb;
114 int sad_count; 114 int sad_count;
115 115
116 /* XXX: setting this register causes hangs on some asics */
117 return;
118
116 if (!dig->afmt->pin) 119 if (!dig->afmt->pin)
117 return; 120 return;
118 121
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 555164e270a7..b5c67a99dda9 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3131,7 +3131,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
3131 rdev->config.evergreen.sx_max_export_size = 256; 3131 rdev->config.evergreen.sx_max_export_size = 256;
3132 rdev->config.evergreen.sx_max_export_pos_size = 64; 3132 rdev->config.evergreen.sx_max_export_pos_size = 64;
3133 rdev->config.evergreen.sx_max_export_smx_size = 192; 3133 rdev->config.evergreen.sx_max_export_smx_size = 192;
3134 rdev->config.evergreen.max_hw_contexts = 8; 3134 rdev->config.evergreen.max_hw_contexts = 4;
3135 rdev->config.evergreen.sq_num_cf_insts = 2; 3135 rdev->config.evergreen.sq_num_cf_insts = 2;
3136 3136
3137 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 3137 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index f71ce390aebe..fe1de855775e 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -67,6 +67,9 @@ static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
67 u8 *sadb; 67 u8 *sadb;
68 int sad_count; 68 int sad_count;
69 69
70 /* XXX: setting this register causes hangs on some asics */
71 return;
72
70 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 73 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
71 if (connector->encoder == encoder) 74 if (connector->encoder == encoder)
72 radeon_connector = to_radeon_connector(connector); 75 radeon_connector = to_radeon_connector(connector);
@@ -288,8 +291,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
288 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ 291 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
289 292
290 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 293 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
291 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 294 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
292 HDMI_ACR_SOURCE); /* select SW CTS value */
293 295
294 evergreen_hdmi_update_ACR(encoder, mode->clock); 296 evergreen_hdmi_update_ACR(encoder, mode->clock);
295 297
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 8768fd6a1e27..4f6d2962767d 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1501,7 +1501,7 @@
1501 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1501 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
1502 */ 1502 */
1503# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1503# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
1504 /* 0 - SRC_ADDR 1504 /* 0 - DST_ADDR
1505 * 1 - GDS 1505 * 1 - GDS
1506 */ 1506 */
1507# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 1507# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
@@ -1516,7 +1516,7 @@
1516# define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1516# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1517/* COMMAND */ 1517/* COMMAND */
1518# define PACKET3_CP_DMA_DIS_WC (1 << 21) 1518# define PACKET3_CP_DMA_DIS_WC (1 << 21)
1519# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1519# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
1520 /* 0 - none 1520 /* 0 - none
1521 * 1 - 8 in 16 1521 * 1 - 8 in 16
1522 * 2 - 8 in 32 1522 * 2 - 8 in 32
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 93c1f9ef5da9..cac2866d79da 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -804,6 +804,7 @@ int ni_init_microcode(struct radeon_device *rdev)
804 fw_name); 804 fw_name);
805 release_firmware(rdev->smc_fw); 805 release_firmware(rdev->smc_fw);
806 rdev->smc_fw = NULL; 806 rdev->smc_fw = NULL;
807 err = 0;
807 } else if (rdev->smc_fw->size != smc_req_size) { 808 } else if (rdev->smc_fw->size != smc_req_size) {
808 printk(KERN_ERR 809 printk(KERN_ERR
809 "ni_mc: Bogus length %zu in firmware \"%s\"\n", 810 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 2a1b1876b431..f9be22062df1 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2302,6 +2302,7 @@ int r600_init_microcode(struct radeon_device *rdev)
2302 fw_name); 2302 fw_name);
2303 release_firmware(rdev->smc_fw); 2303 release_firmware(rdev->smc_fw);
2304 rdev->smc_fw = NULL; 2304 rdev->smc_fw = NULL;
2305 err = 0;
2305 } else if (rdev->smc_fw->size != smc_req_size) { 2306 } else if (rdev->smc_fw->size != smc_req_size) {
2306 printk(KERN_ERR 2307 printk(KERN_ERR
2307 "smc: Bogus length %zu in firmware \"%s\"\n", 2308 "smc: Bogus length %zu in firmware \"%s\"\n",
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index b0fa6002af3e..06022e3b9c3b 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -57,15 +57,15 @@ enum r600_hdmi_iec_status_bits {
57static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { 57static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
58 /* 32kHz 44.1kHz 48kHz */ 58 /* 32kHz 44.1kHz 48kHz */
59 /* Clock N CTS N CTS N CTS */ 59 /* Clock N CTS N CTS N CTS */
60 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 60 { 25175, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
61 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ 61 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
62 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ 62 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
63 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ 63 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
64 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ 64 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
65 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ 65 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
66 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 66 { 74176, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
67 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ 67 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
68 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 68 { 148352, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
69 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ 69 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
70 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ 70 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
71}; 71};
@@ -75,8 +75,15 @@ static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
75 */ 75 */
76static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) 76static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
77{ 77{
78 if (*CTS == 0) 78 u64 n;
79 *CTS = clock * N / (128 * freq) * 1000; 79 u32 d;
80
81 if (*CTS == 0) {
82 n = (u64)clock * (u64)N * 1000ULL;
83 d = 128 * freq;
84 do_div(n, d);
85 *CTS = n;
86 }
80 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", 87 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
81 N, *CTS, freq); 88 N, *CTS, freq);
82} 89}
@@ -302,6 +309,9 @@ static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder)
302 u8 *sadb; 309 u8 *sadb;
303 int sad_count; 310 int sad_count;
304 311
312 /* XXX: setting this register causes hangs on some asics */
313 return;
314
305 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 315 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
306 if (connector->encoder == encoder) 316 if (connector->encoder == encoder)
307 radeon_connector = to_radeon_connector(connector); 317 radeon_connector = to_radeon_connector(connector);
@@ -444,8 +454,8 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
444 } 454 }
445 455
446 WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 456 WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
447 HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 457 HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
448 HDMI0_ACR_SOURCE); /* select SW CTS value */ 458 HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
449 459
450 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 460 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
451 HDMI0_NULL_SEND | /* send null packets when required */ 461 HDMI0_NULL_SEND | /* send null packets when required */
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index e673fe26ea84..7b3c7b5932c5 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -1523,7 +1523,7 @@
1523 */ 1523 */
1524# define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1524# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1525/* COMMAND */ 1525/* COMMAND */
1526# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1526# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
1527 /* 0 - none 1527 /* 0 - none
1528 * 1 - 8 in 16 1528 * 1 - 8 in 16
1529 * 2 - 8 in 32 1529 * 2 - 8 in 32
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 79159b5da05b..64565732cb98 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1658,9 +1658,12 @@ radeon_add_atom_connector(struct drm_device *dev,
1658 drm_object_attach_property(&radeon_connector->base.base, 1658 drm_object_attach_property(&radeon_connector->base.base,
1659 rdev->mode_info.underscan_vborder_property, 1659 rdev->mode_info.underscan_vborder_property,
1660 0); 1660 0);
1661 drm_object_attach_property(&radeon_connector->base.base, 1661 if (radeon_audio != 0)
1662 rdev->mode_info.audio_property, 1662 drm_object_attach_property(&radeon_connector->base.base,
1663 RADEON_AUDIO_DISABLE); 1663 rdev->mode_info.audio_property,
1664 (radeon_audio == 1) ?
1665 RADEON_AUDIO_AUTO :
1666 RADEON_AUDIO_DISABLE);
1664 subpixel_order = SubPixelHorizontalRGB; 1667 subpixel_order = SubPixelHorizontalRGB;
1665 connector->interlace_allowed = true; 1668 connector->interlace_allowed = true;
1666 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1669 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
@@ -1754,10 +1757,12 @@ radeon_add_atom_connector(struct drm_device *dev,
1754 rdev->mode_info.underscan_vborder_property, 1757 rdev->mode_info.underscan_vborder_property,
1755 0); 1758 0);
1756 } 1759 }
1757 if (ASIC_IS_DCE2(rdev)) { 1760 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
1758 drm_object_attach_property(&radeon_connector->base.base, 1761 drm_object_attach_property(&radeon_connector->base.base,
1759 rdev->mode_info.audio_property, 1762 rdev->mode_info.audio_property,
1760 RADEON_AUDIO_DISABLE); 1763 (radeon_audio == 1) ?
1764 RADEON_AUDIO_AUTO :
1765 RADEON_AUDIO_DISABLE);
1761 } 1766 }
1762 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1767 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1763 radeon_connector->dac_load_detect = true; 1768 radeon_connector->dac_load_detect = true;
@@ -1799,10 +1804,12 @@ radeon_add_atom_connector(struct drm_device *dev,
1799 rdev->mode_info.underscan_vborder_property, 1804 rdev->mode_info.underscan_vborder_property,
1800 0); 1805 0);
1801 } 1806 }
1802 if (ASIC_IS_DCE2(rdev)) { 1807 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
1803 drm_object_attach_property(&radeon_connector->base.base, 1808 drm_object_attach_property(&radeon_connector->base.base,
1804 rdev->mode_info.audio_property, 1809 rdev->mode_info.audio_property,
1805 RADEON_AUDIO_DISABLE); 1810 (radeon_audio == 1) ?
1811 RADEON_AUDIO_AUTO :
1812 RADEON_AUDIO_DISABLE);
1806 } 1813 }
1807 subpixel_order = SubPixelHorizontalRGB; 1814 subpixel_order = SubPixelHorizontalRGB;
1808 connector->interlace_allowed = true; 1815 connector->interlace_allowed = true;
@@ -1843,10 +1850,12 @@ radeon_add_atom_connector(struct drm_device *dev,
1843 rdev->mode_info.underscan_vborder_property, 1850 rdev->mode_info.underscan_vborder_property,
1844 0); 1851 0);
1845 } 1852 }
1846 if (ASIC_IS_DCE2(rdev)) { 1853 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
1847 drm_object_attach_property(&radeon_connector->base.base, 1854 drm_object_attach_property(&radeon_connector->base.base,
1848 rdev->mode_info.audio_property, 1855 rdev->mode_info.audio_property,
1849 RADEON_AUDIO_DISABLE); 1856 (radeon_audio == 1) ?
1857 RADEON_AUDIO_AUTO :
1858 RADEON_AUDIO_DISABLE);
1850 } 1859 }
1851 connector->interlace_allowed = true; 1860 connector->interlace_allowed = true;
1852 /* in theory with a DP to VGA converter... */ 1861 /* in theory with a DP to VGA converter... */
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 66c222836631..80285e35bc65 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -85,9 +85,8 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
85 VRAM, also but everything into VRAM on AGP cards to avoid 85 VRAM, also but everything into VRAM on AGP cards to avoid
86 image corruptions */ 86 image corruptions */
87 if (p->ring == R600_RING_TYPE_UVD_INDEX && 87 if (p->ring == R600_RING_TYPE_UVD_INDEX &&
88 p->rdev->family < CHIP_PALM &&
89 (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) { 88 (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
90 89 /* TODO: is this still needed for NI+ ? */
91 p->relocs[i].lobj.domain = 90 p->relocs[i].lobj.domain =
92 RADEON_GEM_DOMAIN_VRAM; 91 RADEON_GEM_DOMAIN_VRAM;
93 92
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index cdd12dcd988b..9c14a1ba1de4 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -153,7 +153,7 @@ int radeon_benchmarking = 0;
153int radeon_testing = 0; 153int radeon_testing = 0;
154int radeon_connector_table = 0; 154int radeon_connector_table = 0;
155int radeon_tv = 1; 155int radeon_tv = 1;
156int radeon_audio = 1; 156int radeon_audio = -1;
157int radeon_disp_priority = 0; 157int radeon_disp_priority = 0;
158int radeon_hw_i2c = 0; 158int radeon_hw_i2c = 0;
159int radeon_pcie_gen2 = -1; 159int radeon_pcie_gen2 = -1;
@@ -196,7 +196,7 @@ module_param_named(connector_table, radeon_connector_table, int, 0444);
196MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 196MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
197module_param_named(tv, radeon_tv, int, 0444); 197module_param_named(tv, radeon_tv, int, 0444);
198 198
199MODULE_PARM_DESC(audio, "Audio enable (1 = enable)"); 199MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
200module_param_named(audio, radeon_audio, int, 0444); 200module_param_named(audio, radeon_audio, int, 0444);
201 201
202MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 202MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index ac07ad1d4f8c..4f6b7fc7ad3c 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -945,6 +945,8 @@ void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
945 if (enable) { 945 if (enable) {
946 mutex_lock(&rdev->pm.mutex); 946 mutex_lock(&rdev->pm.mutex);
947 rdev->pm.dpm.uvd_active = true; 947 rdev->pm.dpm.uvd_active = true;
948 /* disable this for now */
949#if 0
948 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) 950 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
949 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; 951 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
950 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) 952 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
@@ -954,6 +956,7 @@ void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
954 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) 956 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
955 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; 957 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
956 else 958 else
959#endif
957 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; 960 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
958 rdev->pm.dpm.state = dpm_state; 961 rdev->pm.dpm.state = dpm_state;
959 mutex_unlock(&rdev->pm.mutex); 962 mutex_unlock(&rdev->pm.mutex);
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c
index f4d6bcee9006..12e8099a0823 100644
--- a/drivers/gpu/drm/radeon/radeon_test.c
+++ b/drivers/gpu/drm/radeon/radeon_test.c
@@ -36,8 +36,8 @@ static void radeon_do_test_moves(struct radeon_device *rdev, int flag)
36 struct radeon_bo *vram_obj = NULL; 36 struct radeon_bo *vram_obj = NULL;
37 struct radeon_bo **gtt_obj = NULL; 37 struct radeon_bo **gtt_obj = NULL;
38 uint64_t gtt_addr, vram_addr; 38 uint64_t gtt_addr, vram_addr;
39 unsigned i, n, size; 39 unsigned n, size;
40 int r, ring; 40 int i, r, ring;
41 41
42 switch (flag) { 42 switch (flag) {
43 case RADEON_TEST_COPY_DMA: 43 case RADEON_TEST_COPY_DMA:
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
index a0f11856ddde..308eff5be1b4 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -476,7 +476,8 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
476 return -EINVAL; 476 return -EINVAL;
477 } 477 }
478 478
479 if (p->rdev->family < CHIP_PALM && (cmd == 0 || cmd == 0x3) && 479 /* TODO: is this still necessary on NI+ ? */
480 if ((cmd == 0 || cmd == 0x3) &&
480 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) { 481 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
481 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 482 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
482 start, end); 483 start, end);
@@ -798,7 +799,8 @@ void radeon_uvd_note_usage(struct radeon_device *rdev)
798 (rdev->pm.dpm.hd != hd)) { 799 (rdev->pm.dpm.hd != hd)) {
799 rdev->pm.dpm.sd = sd; 800 rdev->pm.dpm.sd = sd;
800 rdev->pm.dpm.hd = hd; 801 rdev->pm.dpm.hd = hd;
801 streams_changed = true; 802 /* disable this for now */
803 /*streams_changed = true;*/
802 } 804 }
803 } 805 }
804 806
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index c354c1094967..d96f7cbca0a1 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -85,6 +85,9 @@ extern void si_dma_vm_set_page(struct radeon_device *rdev,
85 uint32_t incr, uint32_t flags); 85 uint32_t incr, uint32_t flags);
86static void si_enable_gui_idle_interrupt(struct radeon_device *rdev, 86static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
87 bool enable); 87 bool enable);
88static void si_fini_pg(struct radeon_device *rdev);
89static void si_fini_cg(struct radeon_device *rdev);
90static void si_rlc_stop(struct radeon_device *rdev);
88 91
89static const u32 verde_rlc_save_restore_register_list[] = 92static const u32 verde_rlc_save_restore_register_list[] =
90{ 93{
@@ -1678,6 +1681,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1678 fw_name); 1681 fw_name);
1679 release_firmware(rdev->smc_fw); 1682 release_firmware(rdev->smc_fw);
1680 rdev->smc_fw = NULL; 1683 rdev->smc_fw = NULL;
1684 err = 0;
1681 } else if (rdev->smc_fw->size != smc_req_size) { 1685 } else if (rdev->smc_fw->size != smc_req_size) {
1682 printk(KERN_ERR 1686 printk(KERN_ERR
1683 "si_smc: Bogus length %zu in firmware \"%s\"\n", 1687 "si_smc: Bogus length %zu in firmware \"%s\"\n",
@@ -3608,6 +3612,13 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
3608 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 3612 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3609 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 3613 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3610 3614
3615 /* disable PG/CG */
3616 si_fini_pg(rdev);
3617 si_fini_cg(rdev);
3618
3619 /* stop the rlc */
3620 si_rlc_stop(rdev);
3621
3611 /* Disable CP parsing/prefetching */ 3622 /* Disable CP parsing/prefetching */
3612 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); 3623 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
3613 3624
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 9ace28702c76..2332aa1bf93c 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -5208,7 +5208,7 @@ static int si_set_mc_special_registers(struct radeon_device *rdev,
5208 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5208 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5209 } 5209 }
5210 j++; 5210 j++;
5211 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5211 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5212 return -EINVAL; 5212 return -EINVAL;
5213 5213
5214 if (!pi->mem_gddr5) { 5214 if (!pi->mem_gddr5) {
@@ -5218,7 +5218,7 @@ static int si_set_mc_special_registers(struct radeon_device *rdev,
5218 table->mc_reg_table_entry[k].mc_data[j] = 5218 table->mc_reg_table_entry[k].mc_data[j] =
5219 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5219 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5220 j++; 5220 j++;
5221 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5221 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5222 return -EINVAL; 5222 return -EINVAL;
5223 } 5223 }
5224 break; 5224 break;
@@ -5231,7 +5231,7 @@ static int si_set_mc_special_registers(struct radeon_device *rdev,
5231 (temp_reg & 0xffff0000) | 5231 (temp_reg & 0xffff0000) |
5232 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5232 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5233 j++; 5233 j++;
5234 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5234 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5235 return -EINVAL; 5235 return -EINVAL;
5236 break; 5236 break;
5237 default: 5237 default:
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 52d2ab6b67a0..7e2e0ea66a00 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -1553,7 +1553,7 @@
1553 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 1553 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
1554 */ 1554 */
1555# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1555# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
1556 /* 0 - SRC_ADDR 1556 /* 0 - DST_ADDR
1557 * 1 - GDS 1557 * 1 - GDS
1558 */ 1558 */
1559# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 1559# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
@@ -1568,7 +1568,7 @@
1568# define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1568# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1569/* COMMAND */ 1569/* COMMAND */
1570# define PACKET3_CP_DMA_DIS_WC (1 << 21) 1570# define PACKET3_CP_DMA_DIS_WC (1 << 21)
1571# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1571# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
1572 /* 0 - none 1572 /* 0 - none
1573 * 1 - 8 in 16 1573 * 1 - 8 in 16
1574 * 2 - 8 in 32 1574 * 2 - 8 in 32
diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c
index 7f998bf1cc9d..9364129ba292 100644
--- a/drivers/gpu/drm/radeon/trinity_dpm.c
+++ b/drivers/gpu/drm/radeon/trinity_dpm.c
@@ -1868,7 +1868,7 @@ int trinity_dpm_init(struct radeon_device *rdev)
1868 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) 1868 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
1869 pi->at[i] = TRINITY_AT_DFLT; 1869 pi->at[i] = TRINITY_AT_DFLT;
1870 1870
1871 pi->enable_bapm = true; 1871 pi->enable_bapm = false;
1872 pi->enable_nbps_policy = true; 1872 pi->enable_nbps_policy = true;
1873 pi->enable_sclk_ds = true; 1873 pi->enable_sclk_ds = true;
1874 pi->enable_gfx_power_gating = true; 1874 pi->enable_gfx_power_gating = true;
diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c b/drivers/gpu/drm/radeon/uvd_v1_0.c
index 3100fa9cb52f..7266805d9786 100644
--- a/drivers/gpu/drm/radeon/uvd_v1_0.c
+++ b/drivers/gpu/drm/radeon/uvd_v1_0.c
@@ -212,8 +212,8 @@ int uvd_v1_0_start(struct radeon_device *rdev)
212 /* enable VCPU clock */ 212 /* enable VCPU clock */
213 WREG32(UVD_VCPU_CNTL, 1 << 9); 213 WREG32(UVD_VCPU_CNTL, 1 << 9);
214 214
215 /* enable UMC and NC0 */ 215 /* enable UMC */
216 WREG32_P(UVD_LMI_CTRL2, 1 << 13, ~((1 << 8) | (1 << 13))); 216 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
217 217
218 /* boot up the VCPU */ 218 /* boot up the VCPU */
219 WREG32(UVD_SOFT_RESET, 0); 219 WREG32(UVD_SOFT_RESET, 0);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 1a90f0a2f7e5..0508f93b9795 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -740,9 +740,17 @@ static void vmw_postclose(struct drm_device *dev,
740 struct vmw_fpriv *vmw_fp; 740 struct vmw_fpriv *vmw_fp;
741 741
742 vmw_fp = vmw_fpriv(file_priv); 742 vmw_fp = vmw_fpriv(file_priv);
743 ttm_object_file_release(&vmw_fp->tfile); 743
744 if (vmw_fp->locked_master) 744 if (vmw_fp->locked_master) {
745 struct vmw_master *vmaster =
746 vmw_master(vmw_fp->locked_master);
747
748 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
749 ttm_vt_unlock(&vmaster->lock);
745 drm_master_put(&vmw_fp->locked_master); 750 drm_master_put(&vmw_fp->locked_master);
751 }
752
753 ttm_object_file_release(&vmw_fp->tfile);
746 kfree(vmw_fp); 754 kfree(vmw_fp);
747} 755}
748 756
@@ -925,14 +933,13 @@ static void vmw_master_drop(struct drm_device *dev,
925 933
926 vmw_fp->locked_master = drm_master_get(file_priv->master); 934 vmw_fp->locked_master = drm_master_get(file_priv->master);
927 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); 935 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
928 vmw_execbuf_release_pinned_bo(dev_priv);
929
930 if (unlikely((ret != 0))) { 936 if (unlikely((ret != 0))) {
931 DRM_ERROR("Unable to lock TTM at VT switch.\n"); 937 DRM_ERROR("Unable to lock TTM at VT switch.\n");
932 drm_master_put(&vmw_fp->locked_master); 938 drm_master_put(&vmw_fp->locked_master);
933 } 939 }
934 940
935 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 941 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
942 vmw_execbuf_release_pinned_bo(dev_priv);
936 943
937 if (!dev_priv->enable_fb) { 944 if (!dev_priv->enable_fb) {
938 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); 945 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index 0e67cf41065d..37fb4befec82 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
@@ -970,7 +970,7 @@ void vmw_resource_unreserve(struct vmw_resource *res,
970 if (new_backup) 970 if (new_backup)
971 res->backup_offset = new_backup_offset; 971 res->backup_offset = new_backup_offset;
972 972
973 if (!res->func->may_evict) 973 if (!res->func->may_evict || res->id == -1)
974 return; 974 return;
975 975
976 write_lock(&dev_priv->resource_lock); 976 write_lock(&dev_priv->resource_lock);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-26 00:38:43 -0400