55 files changed, 831 insertions, 525 deletions

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index eb92fe257a39..a8743c399e83 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -610,7 +610,7 @@ static bool
 drm_monitor_supports_rb(struct edid *edid)
 {
         if (edid->revision >= 4) {
-                bool ret;
+                bool ret = false;
                 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
                 return ret;
         }
@@ -1039,6 +1039,24 @@ mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
         return true;
 }
 
+static bool valid_inferred_mode(const struct drm_connector *connector,
+                                const struct drm_display_mode *mode)
+{
+        struct drm_display_mode *m;
+        bool ok = false;
+
+        list_for_each_entry(m, &connector->probed_modes, head) {
+                if (mode->hdisplay == m->hdisplay &&
+                    mode->vdisplay == m->vdisplay &&
+                    drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
+                        return false; /* duplicated */
+                if (mode->hdisplay <= m->hdisplay &&
+                    mode->vdisplay <= m->vdisplay)
+                        ok = true;
+        }
+        return ok;
+}
+
 static int
 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
                         struct detailed_timing *timing)
@@ -1048,7 +1066,8 @@ drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
         struct drm_device *dev = connector->dev;
 
         for (i = 0; i < drm_num_dmt_modes; i++) {
-                if (mode_in_range(drm_dmt_modes + i, edid, timing)) {
+                if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
+                    valid_inferred_mode(connector, drm_dmt_modes + i)) {
                         newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
                         if (newmode) {
                                 drm_mode_probed_add(connector, newmode);
@@ -1088,7 +1107,8 @@ drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
                         return modes;
 
                 fixup_mode_1366x768(newmode);
-                if (!mode_in_range(newmode, edid, timing)) {
+                if (!mode_in_range(newmode, edid, timing) ||
+                    !valid_inferred_mode(connector, newmode)) {
                         drm_mode_destroy(dev, newmode);
                         continue;
                 }
@@ -1116,7 +1136,8 @@ drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
                         return modes;
 
                 fixup_mode_1366x768(newmode);
-                if (!mode_in_range(newmode, edid, timing)) {
+                if (!mode_in_range(newmode, edid, timing) ||
+                    !valid_inferred_mode(connector, newmode)) {
                         drm_mode_destroy(dev, newmode);
                         continue;
                 }
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index 420953197d0a..d6de2e07fa03 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -244,8 +244,8 @@ static const struct file_operations exynos_drm_driver_fops = {
 };
 
 static struct drm_driver exynos_drm_driver = {
-        .driver_features        = DRIVER_HAVE_IRQ | DRIVER_BUS_PLATFORM |
-                                  DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME,
+        .driver_features        = DRIVER_HAVE_IRQ | DRIVER_MODESET |
+                                        DRIVER_GEM | DRIVER_PRIME,
         .load                   = exynos_drm_load,
         .unload                 = exynos_drm_unload,
         .open                   = exynos_drm_open,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_encoder.c b/drivers/gpu/drm/exynos/exynos_drm_encoder.c
index 6e9ac7bd1dcf..23d5ad379f86 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_encoder.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_encoder.c
@@ -172,19 +172,12 @@ static void exynos_drm_encoder_commit(struct drm_encoder *encoder)
                 manager_ops->commit(manager->dev);
 }
 
-static struct drm_crtc *
-exynos_drm_encoder_get_crtc(struct drm_encoder *encoder)
-{
-        return encoder->crtc;
-}
-
 static struct drm_encoder_helper_funcs exynos_encoder_helper_funcs = {
         .dpms           = exynos_drm_encoder_dpms,
         .mode_fixup     = exynos_drm_encoder_mode_fixup,
         .mode_set       = exynos_drm_encoder_mode_set,
         .prepare        = exynos_drm_encoder_prepare,
         .commit         = exynos_drm_encoder_commit,
-        .get_crtc       = exynos_drm_encoder_get_crtc,
 };
 
 static void exynos_drm_encoder_destroy(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c
index f82a299553fb..4ccfe4328fab 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fb.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c
@@ -51,11 +51,22 @@ struct exynos_drm_fb {
 static void exynos_drm_fb_destroy(struct drm_framebuffer *fb)
 {
         struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb);
+        unsigned int i;
 
         DRM_DEBUG_KMS("%s\n", __FILE__);
 
         drm_framebuffer_cleanup(fb);
 
+        for (i = 0; i < ARRAY_SIZE(exynos_fb->exynos_gem_obj); i++) {
+                struct drm_gem_object *obj;
+
+                if (exynos_fb->exynos_gem_obj[i] == NULL)
+                        continue;
+
+                obj = &exynos_fb->exynos_gem_obj[i]->base;
+                drm_gem_object_unreference_unlocked(obj);
+        }
+
         kfree(exynos_fb);
         exynos_fb = NULL;
 }
@@ -134,11 +145,11 @@ exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv,
                 return ERR_PTR(-ENOENT);
         }
 
-        drm_gem_object_unreference_unlocked(obj);
-
         fb = exynos_drm_framebuffer_init(dev, mode_cmd, obj);
-        if (IS_ERR(fb))
+        if (IS_ERR(fb)) {
+                drm_gem_object_unreference_unlocked(obj);
                 return fb;
+        }
 
         exynos_fb = to_exynos_fb(fb);
         nr = exynos_drm_format_num_buffers(fb->pixel_format);
@@ -152,8 +163,6 @@ exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv,
                         return ERR_PTR(-ENOENT);
                 }
 
-                drm_gem_object_unreference_unlocked(obj);
-
                 exynos_fb->exynos_gem_obj[i] = to_exynos_gem_obj(obj);
         }
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.h b/drivers/gpu/drm/exynos/exynos_drm_fb.h
index 3ecb30d93552..50823756cdea 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fb.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.h
@@ -31,10 +31,10 @@
 static inline int exynos_drm_format_num_buffers(uint32_t format)
 {
         switch (format) {
-        case DRM_FORMAT_NV12M:
+        case DRM_FORMAT_NV12:
         case DRM_FORMAT_NV12MT:
                 return 2;
-        case DRM_FORMAT_YUV420M:
+        case DRM_FORMAT_YUV420:
                 return 3;
         default:
                 return 1;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index fc91293c4560..5c8b683029ea 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -689,7 +689,6 @@ int exynos_drm_gem_dumb_map_offset(struct drm_file *file_priv,
                                    struct drm_device *dev, uint32_t handle,
                                    uint64_t *offset)
 {
-        struct exynos_drm_gem_obj *exynos_gem_obj;
         struct drm_gem_object *obj;
         int ret = 0;
 
@@ -710,15 +709,13 @@ int exynos_drm_gem_dumb_map_offset(struct drm_file *file_priv,
                 goto unlock;
         }
 
-        exynos_gem_obj = to_exynos_gem_obj(obj);
-
-        if (!exynos_gem_obj->base.map_list.map) {
-                ret = drm_gem_create_mmap_offset(&exynos_gem_obj->base);
+        if (!obj->map_list.map) {
+                ret = drm_gem_create_mmap_offset(obj);
                 if (ret)
                         goto out;
         }
 
-        *offset = (u64)exynos_gem_obj->base.map_list.hash.key << PAGE_SHIFT;
+        *offset = (u64)obj->map_list.hash.key << PAGE_SHIFT;
         DRM_DEBUG_KMS("offset = 0x%lx\n", (unsigned long)*offset);
 
 out:
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 68ef01028375..e2147a2ddcec 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -365,7 +365,7 @@ static void vp_video_buffer(struct mixer_context *ctx, int win)
         switch (win_data->pixel_format) {
         case DRM_FORMAT_NV12MT:
                 tiled_mode = true;
-        case DRM_FORMAT_NV12M:
+        case DRM_FORMAT_NV12:
                 crcb_mode = false;
                 buf_num = 2;
                 break;
@@ -601,18 +601,20 @@ static void mixer_win_reset(struct mixer_context *ctx)
         mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);
 
         /* setting graphical layers */
-
         val  = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
         val |= MXR_GRP_CFG_WIN_BLEND_EN;
+        val |= MXR_GRP_CFG_BLEND_PRE_MUL;
+        val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
         val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
 
         /* the same configuration for both layers */
         mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);
-
-        val |= MXR_GRP_CFG_BLEND_PRE_MUL;
-        val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
         mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);
 
+        /* setting video layers */
+        val = MXR_GRP_CFG_ALPHA_VAL(0);
+        mixer_reg_write(res, MXR_VIDEO_CFG, val);
+
         /* configuration of Video Processor Registers */
         vp_win_reset(ctx);
         vp_default_filter(res);
diff --git a/drivers/gpu/drm/gma500/cdv_device.c b/drivers/gpu/drm/gma500/cdv_device.c
index 9764045428ce..b7e7b49d8f62 100644
--- a/drivers/gpu/drm/gma500/cdv_device.c
+++ b/drivers/gpu/drm/gma500/cdv_device.c
@@ -78,21 +78,6 @@ static int cdv_backlight_combination_mode(struct drm_device *dev)
         return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE;
 }
 
-static int cdv_get_brightness(struct backlight_device *bd)
-{
-        struct drm_device *dev = bl_get_data(bd);
-        u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
-
-        if (cdv_backlight_combination_mode(dev)) {
-                u8 lbpc;
-
-                val &= ~1;
-                pci_read_config_byte(dev->pdev, 0xF4, &lbpc);
-                val *= lbpc;
-        }
-        return val;
-}
-
 static u32 cdv_get_max_backlight(struct drm_device *dev)
 {
         u32 max = REG_READ(BLC_PWM_CTL);
@@ -110,6 +95,22 @@ static u32 cdv_get_max_backlight(struct drm_device *dev)
         return max;
 }
 
+static int cdv_get_brightness(struct backlight_device *bd)
+{
+        struct drm_device *dev = bl_get_data(bd);
+        u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
+
+        if (cdv_backlight_combination_mode(dev)) {
+                u8 lbpc;
+
+                val &= ~1;
+                pci_read_config_byte(dev->pdev, 0xF4, &lbpc);
+                val *= lbpc;
+        }
+        return (val * 100)/cdv_get_max_backlight(dev);
+
+}
+
 static int cdv_set_brightness(struct backlight_device *bd)
 {
         struct drm_device *dev = bl_get_data(bd);
@@ -120,6 +121,9 @@ static int cdv_set_brightness(struct backlight_device *bd)
         if (level < 1)
                 level = 1;
 
+        level *= cdv_get_max_backlight(dev);
+        level /= 100;
+
         if (cdv_backlight_combination_mode(dev)) {
                 u32 max = cdv_get_max_backlight(dev);
                 u8 lbpc;
@@ -157,7 +161,6 @@ static int cdv_backlight_init(struct drm_device *dev)
 
         cdv_backlight_device->props.brightness =
                         cdv_get_brightness(cdv_backlight_device);
-        cdv_backlight_device->props.max_brightness = cdv_get_max_backlight(dev);
         backlight_update_status(cdv_backlight_device);
         dev_priv->backlight_device = cdv_backlight_device;
         return 0;
diff --git a/drivers/gpu/drm/gma500/opregion.c b/drivers/gpu/drm/gma500/opregion.c
index 4f186eca3a30..c430bd424681 100644
--- a/drivers/gpu/drm/gma500/opregion.c
+++ b/drivers/gpu/drm/gma500/opregion.c
@@ -144,6 +144,8 @@ struct opregion_asle {
 
 #define ASLE_CBLV_VALID         (1<<31)
 
+static struct psb_intel_opregion *system_opregion;
+
 static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
 {
         struct drm_psb_private *dev_priv = dev->dev_private;
@@ -205,7 +207,7 @@ void psb_intel_opregion_enable_asle(struct drm_device *dev)
         struct drm_psb_private *dev_priv = dev->dev_private;
         struct opregion_asle *asle = dev_priv->opregion.asle;
 
-        if (asle) {
+        if (asle && system_opregion ) {
                 /* Don't do this on Medfield or other non PC like devices, they
                    use the bit for something different altogether */
                 psb_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
@@ -221,7 +223,6 @@ void psb_intel_opregion_enable_asle(struct drm_device *dev)
 #define ACPI_EV_LID            (1<<1)
 #define ACPI_EV_DOCK           (1<<2)
 
-static struct psb_intel_opregion *system_opregion;
 
 static int psb_intel_opregion_video_event(struct notifier_block *nb,
                                           unsigned long val, void *data)
@@ -266,9 +267,6 @@ void psb_intel_opregion_init(struct drm_device *dev)
                 system_opregion = opregion;
                 register_acpi_notifier(&psb_intel_opregion_notifier);
         }
-
-        if (opregion->asle)
-                psb_intel_opregion_enable_asle(dev);
 }
 
 void psb_intel_opregion_fini(struct drm_device *dev)
diff --git a/drivers/gpu/drm/gma500/opregion.h b/drivers/gpu/drm/gma500/opregion.h
index 72dc6b921265..4a90f8b0e16c 100644
--- a/drivers/gpu/drm/gma500/opregion.h
+++ b/drivers/gpu/drm/gma500/opregion.h
@@ -27,6 +27,7 @@ extern void psb_intel_opregion_asle_intr(struct drm_device *dev);
 extern void psb_intel_opregion_init(struct drm_device *dev);
 extern void psb_intel_opregion_fini(struct drm_device *dev);
 extern int psb_intel_opregion_setup(struct drm_device *dev);
+extern void psb_intel_opregion_enable_asle(struct drm_device *dev);
 
 #else
 
@@ -46,4 +47,8 @@ extern inline int psb_intel_opregion_setup(struct drm_device *dev)
 {
         return 0;
 }
+
+extern inline void psb_intel_opregion_enable_asle(struct drm_device *dev)
+{
+}
 #endif
diff --git a/drivers/gpu/drm/gma500/psb_device.c b/drivers/gpu/drm/gma500/psb_device.c
index eff039bf92d4..5971bc82b765 100644
--- a/drivers/gpu/drm/gma500/psb_device.c
+++ b/drivers/gpu/drm/gma500/psb_device.c
@@ -144,6 +144,10 @@ static int psb_backlight_init(struct drm_device *dev)
         psb_backlight_device->props.max_brightness = 100;
         backlight_update_status(psb_backlight_device);
         dev_priv->backlight_device = psb_backlight_device;
+
+        /* This must occur after the backlight is properly initialised */
+        psb_lid_timer_init(dev_priv);
+
         return 0;
 }
 
@@ -354,13 +358,6 @@ static int psb_chip_setup(struct drm_device *dev)
         return 0;
 }
 
-/* Not exactly an erratum more an irritation */
-static void psb_chip_errata(struct drm_device *dev)
-{
-        struct drm_psb_private *dev_priv = dev->dev_private;
-        psb_lid_timer_init(dev_priv);
-}
-
 static void psb_chip_teardown(struct drm_device *dev)
 {
         struct drm_psb_private *dev_priv = dev->dev_private;
@@ -379,7 +376,6 @@ const struct psb_ops psb_chip_ops = {
         .sgx_offset = PSB_SGX_OFFSET,
         .chip_setup = psb_chip_setup,
         .chip_teardown = psb_chip_teardown,
-        .errata = psb_chip_errata,
 
         .crtc_helper = &psb_intel_helper_funcs,
         .crtc_funcs = &psb_intel_crtc_funcs,
diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c
index caba6e08693c..a8858a907f47 100644
--- a/drivers/gpu/drm/gma500/psb_drv.c
+++ b/drivers/gpu/drm/gma500/psb_drv.c
@@ -374,6 +374,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
 
         if (ret)
                 return ret;
+        psb_intel_opregion_enable_asle(dev);
 #if 0
         /*enable runtime pm at last*/
         pm_runtime_enable(&dev->pdev->dev);
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index f94792626b94..36822b924eb1 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1401,6 +1401,27 @@ i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
         }
 }
 
+static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
+{
+        struct apertures_struct *ap;
+        struct pci_dev *pdev = dev_priv->dev->pdev;
+        bool primary;
+
+        ap = alloc_apertures(1);
+        if (!ap)
+                return;
+
+        ap->ranges[0].base = dev_priv->dev->agp->base;
+        ap->ranges[0].size =
+                dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
+        primary =
+                pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
+
+        remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
+
+        kfree(ap);
+}
+
 /**
  * i915_driver_load - setup chip and create an initial config
  * @dev: DRM device
@@ -1446,6 +1467,15 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
                 goto free_priv;
         }
 
+        dev_priv->mm.gtt = intel_gtt_get();
+        if (!dev_priv->mm.gtt) {
+                DRM_ERROR("Failed to initialize GTT\n");
+                ret = -ENODEV;
+                goto put_bridge;
+        }
+
+        i915_kick_out_firmware_fb(dev_priv);
+
         pci_set_master(dev->pdev);
 
         /* overlay on gen2 is broken and can't address above 1G */
@@ -1471,13 +1501,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
                 goto put_bridge;
         }
 
-        dev_priv->mm.gtt = intel_gtt_get();
-        if (!dev_priv->mm.gtt) {
-                DRM_ERROR("Failed to initialize GTT\n");
-                ret = -ENODEV;
-                goto out_rmmap;
-        }
-
         aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
 
         dev_priv->mm.gtt_mapping =
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 238a52165833..9fe9ebe52a7a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -233,6 +233,7 @@ static const struct intel_device_info intel_sandybridge_d_info = {
         .has_blt_ring = 1,
         .has_llc = 1,
         .has_pch_split = 1,
+        .has_force_wake = 1,
 };
 
 static const struct intel_device_info intel_sandybridge_m_info = {
@@ -243,6 +244,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
         .has_blt_ring = 1,
         .has_llc = 1,
         .has_pch_split = 1,
+        .has_force_wake = 1,
 };
 
 static const struct intel_device_info intel_ivybridge_d_info = {
@@ -252,6 +254,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
         .has_blt_ring = 1,
         .has_llc = 1,
         .has_pch_split = 1,
+        .has_force_wake = 1,
 };
 
 static const struct intel_device_info intel_ivybridge_m_info = {
@@ -262,6 +265,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
         .has_blt_ring = 1,
         .has_llc = 1,
         .has_pch_split = 1,
+        .has_force_wake = 1,
 };
 
 static const struct intel_device_info intel_valleyview_m_info = {
@@ -289,6 +293,7 @@ static const struct intel_device_info intel_haswell_d_info = {
         .has_blt_ring = 1,
         .has_llc = 1,
         .has_pch_split = 1,
+        .has_force_wake = 1,
 };
 
 static const struct intel_device_info intel_haswell_m_info = {
@@ -298,6 +303,7 @@ static const struct intel_device_info intel_haswell_m_info = {
         .has_blt_ring = 1,
         .has_llc = 1,
         .has_pch_split = 1,
+        .has_force_wake = 1,
 };
 
 static const struct pci_device_id pciidlist[] = {               /* aka */
@@ -1139,10 +1145,9 @@ MODULE_LICENSE("GPL and additional rights");
 
 /* We give fast paths for the really cool registers */
 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
-       (((dev_priv)->info->gen >= 6) && \
-        ((reg) < 0x40000) &&            \
-        ((reg) != FORCEWAKE)) && \
-       (!IS_VALLEYVIEW((dev_priv)->dev))
+        ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
+         ((reg) < 0x40000) &&            \
+         ((reg) != FORCEWAKE))
 
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9cfc67c2cf5..b0b676abde0d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -285,6 +285,7 @@ struct intel_device_info {
         u8 is_ivybridge:1;
         u8 is_valleyview:1;
         u8 has_pch_split:1;
+        u8 has_force_wake:1;
         u8 is_haswell:1;
         u8 has_fbc:1;
         u8 has_pipe_cxsr:1;
@@ -1101,6 +1102,8 @@ struct drm_i915_file_private {
 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
 
+#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
+
 #include "i915_trace.h"
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1417660a93ec..ed3224c37423 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -412,7 +412,6 @@ static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
          */
 
         spin_lock_irqsave(&dev_priv->rps_lock, flags);
-        WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
         dev_priv->pm_iir |= pm_iir;
         I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
         POSTING_READ(GEN6_PMIMR);
@@ -510,7 +509,7 @@ out:
         return ret;
 }
 
-static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
+static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 {
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
         int pipe;
@@ -550,6 +549,35 @@ static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 }
 
+static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
+{
+        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+        int pipe;
+
+        if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
+                DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
+                                 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
+                                 SDE_AUDIO_POWER_SHIFT_CPT);
+
+        if (pch_iir & SDE_AUX_MASK_CPT)
+                DRM_DEBUG_DRIVER("AUX channel interrupt\n");
+
+        if (pch_iir & SDE_GMBUS_CPT)
+                DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
+
+        if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
+                DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
+
+        if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
+                DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
+
+        if (pch_iir & SDE_FDI_MASK_CPT)
+                for_each_pipe(pipe)
+                        DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
+                                         pipe_name(pipe),
+                                         I915_READ(FDI_RX_IIR(pipe)));
+}
+
 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 {
         struct drm_device *dev = (struct drm_device *) arg;
@@ -591,7 +619,7 @@ static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 
                         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
                                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
-                        pch_irq_handler(dev, pch_iir);
+                        cpt_irq_handler(dev, pch_iir);
 
                         /* clear PCH hotplug event before clear CPU irq */
                         I915_WRITE(SDEIIR, pch_iir);
@@ -684,7 +712,10 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
         if (de_iir & DE_PCH_EVENT) {
                 if (pch_iir & hotplug_mask)
                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
-                pch_irq_handler(dev, pch_iir);
+                if (HAS_PCH_CPT(dev))
+                        cpt_irq_handler(dev, pch_iir);
+                else
+                        ibx_irq_handler(dev, pch_iir);
         }
 
         if (de_iir & DE_PCU_EVENT) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2d49b9507ed0..48d5e8e051cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -210,6 +210,14 @@
 #define MI_DISPLAY_FLIP         MI_INSTR(0x14, 2)
 #define MI_DISPLAY_FLIP_I915    MI_INSTR(0x14, 1)
 #define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
+/* IVB has funny definitions for which plane to flip. */
+#define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
+#define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
+#define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
+#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
+#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
+#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
+
 #define MI_SET_CONTEXT          MI_INSTR(0x18, 0)
 #define   MI_MM_SPACE_GTT               (1<<8)
 #define   MI_MM_SPACE_PHYSICAL          (0<<8)
@@ -3313,7 +3321,7 @@
 
 /* PCH */
 
-/* south display engine interrupt */
+/* south display engine interrupt: IBX */
 #define SDE_AUDIO_POWER_D       (1 << 27)
 #define SDE_AUDIO_POWER_C       (1 << 26)
 #define SDE_AUDIO_POWER_B       (1 << 25)
@@ -3349,15 +3357,44 @@
 #define SDE_TRANSA_CRC_ERR      (1 << 1)
 #define SDE_TRANSA_FIFO_UNDER   (1 << 0)
 #define SDE_TRANS_MASK          (0x3f)
-/* CPT */
-#define SDE_CRT_HOTPLUG_CPT     (1 << 19)
+
+/* south display engine interrupt: CPT/PPT */
+#define SDE_AUDIO_POWER_D_CPT   (1 << 31)
+#define SDE_AUDIO_POWER_C_CPT   (1 << 30)
+#define SDE_AUDIO_POWER_B_CPT   (1 << 29)
+#define SDE_AUDIO_POWER_SHIFT_CPT   29
+#define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
+#define SDE_AUXD_CPT            (1 << 27)
+#define SDE_AUXC_CPT            (1 << 26)
+#define SDE_AUXB_CPT            (1 << 25)
+#define SDE_AUX_MASK_CPT        (7 << 25)
 #define SDE_PORTD_HOTPLUG_CPT   (1 << 23)
 #define SDE_PORTC_HOTPLUG_CPT   (1 << 22)
 #define SDE_PORTB_HOTPLUG_CPT   (1 << 21)
+#define SDE_CRT_HOTPLUG_CPT     (1 << 19)
 #define SDE_HOTPLUG_MASK_CPT    (SDE_CRT_HOTPLUG_CPT |          \
                                  SDE_PORTD_HOTPLUG_CPT |        \
                                  SDE_PORTC_HOTPLUG_CPT |        \
                                  SDE_PORTB_HOTPLUG_CPT)
+#define SDE_GMBUS_CPT           (1 << 17)
+#define SDE_AUDIO_CP_REQ_C_CPT  (1 << 10)
+#define SDE_AUDIO_CP_CHG_C_CPT  (1 << 9)
+#define SDE_FDI_RXC_CPT         (1 << 8)
+#define SDE_AUDIO_CP_REQ_B_CPT  (1 << 6)
+#define SDE_AUDIO_CP_CHG_B_CPT  (1 << 5)
+#define SDE_FDI_RXB_CPT         (1 << 4)
+#define SDE_AUDIO_CP_REQ_A_CPT  (1 << 2)
+#define SDE_AUDIO_CP_CHG_A_CPT  (1 << 1)
+#define SDE_FDI_RXA_CPT         (1 << 0)
+#define SDE_AUDIO_CP_REQ_CPT    (SDE_AUDIO_CP_REQ_C_CPT | \
+                                 SDE_AUDIO_CP_REQ_B_CPT | \
+                                 SDE_AUDIO_CP_REQ_A_CPT)
+#define SDE_AUDIO_CP_CHG_CPT    (SDE_AUDIO_CP_CHG_C_CPT | \
+                                 SDE_AUDIO_CP_CHG_B_CPT | \
+                                 SDE_AUDIO_CP_CHG_A_CPT)
+#define SDE_FDI_MASK_CPT        (SDE_FDI_RXC_CPT | \
+                                 SDE_FDI_RXB_CPT | \
+                                 SDE_FDI_RXA_CPT)
 
 #define SDEISR  0xc4000
 #define SDEIMR  0xc4004
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 0ede02a99d91..a748e5cabe14 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -740,8 +740,11 @@ static void i915_restore_display(struct drm_device *dev)
         if (HAS_PCH_SPLIT(dev)) {
                 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
                 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
-                I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
+                /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
+                 * otherwise we get blank eDP screen after S3 on some machines
+                 */
                 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
+                I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
                 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
                 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
                 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 914789420906..a8538ac0299d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6158,17 +6158,34 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
+        uint32_t plane_bit = 0;
         int ret;
 
         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
         if (ret)
                 goto err;
 
+        switch(intel_crtc->plane) {
+        case PLANE_A:
+                plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
+                break;
+        case PLANE_B:
+                plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
+                break;
+        case PLANE_C:
+                plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
+                break;
+        default:
+                WARN_ONCE(1, "unknown plane in flip command\n");
+                ret = -ENODEV;
+                goto err;
+        }
+
         ret = intel_ring_begin(ring, 4);
         if (ret)
                 goto err_unpin;
 
-        intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
+        intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
         intel_ring_emit(ring, (obj->gtt_offset));
         intel_ring_emit(ring, (MI_NOOP));
@@ -6541,7 +6558,7 @@ static void intel_setup_outputs(struct drm_device *dev)
                 if (I915_READ(HDMIC) & PORT_DETECTED)
                         intel_hdmi_init(dev, HDMIC);
 
-                if (I915_READ(HDMID) & PORT_DETECTED)
+                if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
                         intel_hdmi_init(dev, HDMID);
 
                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
@@ -6904,19 +6921,6 @@ static void i915_disable_vga(struct drm_device *dev)
         POSTING_READ(vga_reg);
 }
 
-static void ivb_pch_pwm_override(struct drm_device *dev)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-
-        /*
-         * IVB has CPU eDP backlight regs too, set things up to let the
-         * PCH regs control the backlight
-         */
-        I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
-        I915_WRITE(BLC_PWM_CPU_CTL, 0);
-        I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
-}
-
 void intel_modeset_init_hw(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6933,9 +6937,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
                 gen6_enable_rps(dev_priv);
                 gen6_update_ring_freq(dev_priv);
         }
-
-        if (IS_IVYBRIDGE(dev))
-                ivb_pch_pwm_override(dev);
 }
 
 void intel_modeset_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 296cfc201a81..c0449324143c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -32,6 +32,7 @@
 #include "drm.h"
 #include "drm_crtc.h"
 #include "drm_crtc_helper.h"
+#include "drm_edid.h"
 #include "intel_drv.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
@@ -67,6 +68,8 @@ struct intel_dp {
         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
         struct delayed_work panel_vdd_work;
         bool want_panel_vdd;
+        struct edid *edid; /* cached EDID for eDP */
+        int edid_mode_count;
 };
 
 /**
@@ -371,7 +374,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
         int recv_bytes;
         uint32_t status;
         uint32_t aux_clock_divider;
-        int try, precharge = 5;
+        int try, precharge;
 
         intel_dp_check_edp(intel_dp);
         /* The clock divider is based off the hrawclk,
@@ -391,6 +394,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
         else
                 aux_clock_divider = intel_hrawclk(dev) / 2;
 
+        if (IS_GEN6(dev))
+                precharge = 3;
+        else
+                precharge = 5;
+
         /* Try to wait for any previous AUX channel activity */
         for (try = 0; try < 3; try++) {
                 status = I915_READ(ch_ctl);
@@ -1973,6 +1981,8 @@ intel_dp_probe_oui(struct intel_dp *intel_dp)
         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
                 return;
 
+        ironlake_edp_panel_vdd_on(intel_dp);
+
         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
                               buf[0], buf[1], buf[2]);
@@ -1980,6 +1990,8 @@ intel_dp_probe_oui(struct intel_dp *intel_dp)
         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
                               buf[0], buf[1], buf[2]);
+
+        ironlake_edp_panel_vdd_off(intel_dp, false);
 }
 
 static bool
@@ -2116,10 +2128,22 @@ intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
 {
         struct intel_dp *intel_dp = intel_attached_dp(connector);
         struct edid     *edid;
+        int size;
+
+        if (is_edp(intel_dp)) {
+                if (!intel_dp->edid)
+                        return NULL;
+
+                size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
+                edid = kmalloc(size, GFP_KERNEL);
+                if (!edid)
+                        return NULL;
+
+                memcpy(edid, intel_dp->edid, size);
+                return edid;
+        }
 
-        ironlake_edp_panel_vdd_on(intel_dp);
         edid = drm_get_edid(connector, adapter);
-        ironlake_edp_panel_vdd_off(intel_dp, false);
         return edid;
 }
 
@@ -2129,9 +2153,17 @@ intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *ada
         struct intel_dp *intel_dp = intel_attached_dp(connector);
         int     ret;
 
-        ironlake_edp_panel_vdd_on(intel_dp);
+        if (is_edp(intel_dp)) {
+                drm_mode_connector_update_edid_property(connector,
+                                                        intel_dp->edid);
+                ret = drm_add_edid_modes(connector, intel_dp->edid);
+                drm_edid_to_eld(connector,
+                                intel_dp->edid);
+                connector->display_info.raw_edid = NULL;
+                return intel_dp->edid_mode_count;
+        }
+
         ret = intel_ddc_get_modes(connector, adapter);
-        ironlake_edp_panel_vdd_off(intel_dp, false);
         return ret;
 }
 
@@ -2321,6 +2353,7 @@ static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
         i2c_del_adapter(&intel_dp->adapter);
         drm_encoder_cleanup(encoder);
         if (is_edp(intel_dp)) {
+                kfree(intel_dp->edid);
                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
                 ironlake_panel_vdd_off_sync(intel_dp);
         }
@@ -2504,11 +2537,14 @@ intel_dp_init(struct drm_device *dev, int output_reg)
                         break;
         }
 
+        intel_dp_i2c_init(intel_dp, intel_connector, name);
+
         /* Cache some DPCD data in the eDP case */
         if (is_edp(intel_dp)) {
                 bool ret;
                 struct edp_power_seq    cur, vbt;
                 u32 pp_on, pp_off, pp_div;
+                struct edid *edid;
 
                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
@@ -2576,9 +2612,19 @@ intel_dp_init(struct drm_device *dev, int output_reg)
                         intel_dp_destroy(&intel_connector->base);
                         return;
                 }
-        }
 
-        intel_dp_i2c_init(intel_dp, intel_connector, name);
+                ironlake_edp_panel_vdd_on(intel_dp);
+                edid = drm_get_edid(connector, &intel_dp->adapter);
+                if (edid) {
+                        drm_mode_connector_update_edid_property(connector,
+                                                                edid);
+                        intel_dp->edid_mode_count =
+                                drm_add_edid_modes(connector, edid);
+                        drm_edid_to_eld(connector, edid);
+                        intel_dp->edid = edid;
+                }
+                ironlake_edp_panel_vdd_off(intel_dp, false);
+        }
 
         intel_encoder->hot_plug = intel_dp_hot_plug;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b59b6d5b7583..e5b84ff89ca5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -266,10 +266,15 @@ u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 
 static int init_ring_common(struct intel_ring_buffer *ring)
 {
-        drm_i915_private_t *dev_priv = ring->dev->dev_private;
+        struct drm_device *dev = ring->dev;
+        drm_i915_private_t *dev_priv = dev->dev_private;
         struct drm_i915_gem_object *obj = ring->obj;
+        int ret = 0;
         u32 head;
 
+        if (HAS_FORCE_WAKE(dev))
+                gen6_gt_force_wake_get(dev_priv);
+
         /* Stop the ring if it's running. */
         I915_WRITE_CTL(ring, 0);
         I915_WRITE_HEAD(ring, 0);
@@ -317,7 +322,8 @@ static int init_ring_common(struct intel_ring_buffer *ring)
                                 I915_READ_HEAD(ring),
                                 I915_READ_TAIL(ring),
                                 I915_READ_START(ring));
-                return -EIO;
+                ret = -EIO;
+                goto out;
         }
 
         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
@@ -326,9 +332,14 @@ static int init_ring_common(struct intel_ring_buffer *ring)
                 ring->head = I915_READ_HEAD(ring);
                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
                 ring->space = ring_space(ring);
+                ring->last_retired_head = -1;
         }
 
-        return 0;
+out:
+        if (HAS_FORCE_WAKE(dev))
+                gen6_gt_force_wake_put(dev_priv);
+
+        return ret;
 }
 
 static int
@@ -987,6 +998,10 @@ static int intel_init_ring_buffer(struct drm_device *dev,
         if (ret)
                 goto err_unref;
 
+        ret = i915_gem_object_set_to_gtt_domain(obj, true);
+        if (ret)
+                goto err_unpin;
+
         ring->virtual_start = ioremap_wc(dev->agp->base + obj->gtt_offset,
                                          ring->size);
         if (ring->virtual_start == NULL) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 153b9a15469b..1074bc5dd418 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -467,7 +467,7 @@ int nouveau_fbcon_init(struct drm_device *dev)
         nfbdev->helper.funcs = &nouveau_fbcon_helper_funcs;
 
         ret = drm_fb_helper_init(dev, &nfbdev->helper,
-                                 nv_two_heads(dev) ? 2 : 1, 4);
+                                 dev->mode_config.num_crtc, 4);
         if (ret) {
                 kfree(nfbdev);
                 return ret;
diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c b/drivers/gpu/drm/nouveau/nouveau_prime.c
index a89240e5fb29..a25cf2cb931f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_prime.c
+++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
@@ -1,3 +1,26 @@
+/*
+ * Copyright 2011 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ */
 
 #include "drmP.h"
 #include "drm.h"
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 01d77d1554f4..3904d7964a4b 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1149,7 +1149,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
         }
 
         if (tiling_flags & RADEON_TILING_MACRO) {
-                if (rdev->family >= CHIP_CAYMAN)
+                if (rdev->family >= CHIP_TAHITI)
+                        tmp = rdev->config.si.tile_config;
+                else if (rdev->family >= CHIP_CAYMAN)
                         tmp = rdev->config.cayman.tile_config;
                 else
                         tmp = rdev->config.evergreen.tile_config;
@@ -1177,6 +1179,12 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
         } else if (tiling_flags & RADEON_TILING_MICRO)
                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
 
+        if ((rdev->family == CHIP_TAHITI) ||
+            (rdev->family == CHIP_PITCAIRN))
+                fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
+        else if (rdev->family == CHIP_VERDE)
+                fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
+
         switch (radeon_crtc->crtc_id) {
         case 0:
                 WREG32(AVIVO_D1VGA_CONTROL, 0);
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index e7b1ec5ae8c6..486ccdf4aacd 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -1926,7 +1926,9 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
 
         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
                 r600_hdmi_enable(encoder);
-                if (ASIC_IS_DCE4(rdev))
+                if (ASIC_IS_DCE6(rdev))
+                        ; /* TODO (use pointers instead of if-s?) */
+                else if (ASIC_IS_DCE4(rdev))
                         evergreen_hdmi_setmode(encoder, adjusted_mode);
                 else
                         r600_hdmi_setmode(encoder, adjusted_mode);
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 01550d05e273..7fb3d2e0434c 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1932,6 +1932,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 
+        if (rdev->family <= CHIP_SUMO2)
+                WREG32(SMX_SAR_CTL0, 0x00010000);
+
         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 4e7dd2b4843d..c16554122ccd 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -52,6 +52,7 @@ struct evergreen_cs_track {
         u32                     cb_color_view[12];
         u32                     cb_color_pitch[12];
         u32                     cb_color_slice[12];
+        u32                     cb_color_slice_idx[12];
         u32                     cb_color_attrib[12];
         u32                     cb_color_cmask_slice[8];/* unused */
         u32                     cb_color_fmask_slice[8];/* unused */
@@ -127,12 +128,14 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track)
                 track->cb_color_info[i] = 0;
                 track->cb_color_view[i] = 0xFFFFFFFF;
                 track->cb_color_pitch[i] = 0;
-                track->cb_color_slice[i] = 0;
+                track->cb_color_slice[i] = 0xfffffff;
+                track->cb_color_slice_idx[i] = 0;
         }
         track->cb_target_mask = 0xFFFFFFFF;
         track->cb_shader_mask = 0xFFFFFFFF;
         track->cb_dirty = true;
 
+        track->db_depth_slice = 0xffffffff;
         track->db_depth_view = 0xFFFFC000;
         track->db_depth_size = 0xFFFFFFFF;
         track->db_depth_control = 0xFFFFFFFF;
@@ -250,10 +253,9 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
 {
         struct evergreen_cs_track *track = p->track;
         unsigned palign, halign, tileb, slice_pt;
+        unsigned mtile_pr, mtile_ps, mtileb;
 
         tileb = 64 * surf->bpe * surf->nsamples;
-        palign = track->group_size / (8 * surf->bpe * surf->nsamples);
-        palign = MAX(8, palign);
         slice_pt = 1;
         if (tileb > surf->tsplit) {
                 slice_pt = tileb / surf->tsplit;
@@ -262,7 +264,10 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
         /* macro tile width & height */
         palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
         halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
-        surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt;
+        mtileb = (palign / 8) * (halign / 8) * tileb;;
+        mtile_pr = surf->nbx / palign;
+        mtile_ps = (mtile_pr * surf->nby) / halign;
+        surf->layer_size = mtile_ps * mtileb * slice_pt;
         surf->base_align = (palign / 8) * (halign / 8) * tileb;
         surf->palign = palign;
         surf->halign = halign;
@@ -434,6 +439,39 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
 
         offset += surf.layer_size * mslice;
         if (offset > radeon_bo_size(track->cb_color_bo[id])) {
+                /* old ddx are broken they allocate bo with w*h*bpp but
+                 * program slice with ALIGN(h, 8), catch this and patch
+                 * command stream.
+                 */
+                if (!surf.mode) {
+                        volatile u32 *ib = p->ib.ptr;
+                        unsigned long tmp, nby, bsize, size, min = 0;
+
+                        /* find the height the ddx wants */
+                        if (surf.nby > 8) {
+                                min = surf.nby - 8;
+                        }
+                        bsize = radeon_bo_size(track->cb_color_bo[id]);
+                        tmp = track->cb_color_bo_offset[id] << 8;
+                        for (nby = surf.nby; nby > min; nby--) {
+                                size = nby * surf.nbx * surf.bpe * surf.nsamples;
+                                if ((tmp + size * mslice) <= bsize) {
+                                        break;
+                                }
+                        }
+                        if (nby > min) {
+                                surf.nby = nby;
+                                slice = ((nby * surf.nbx) / 64) - 1;
+                                if (!evergreen_surface_check(p, &surf, "cb")) {
+                                        /* check if this one works */
+                                        tmp += surf.layer_size * mslice;
+                                        if (tmp <= bsize) {
+                                                ib[track->cb_color_slice_idx[id]] = slice;
+                                                goto old_ddx_ok;
+                                        }
+                                }
+                        }
+                }
                 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
                          "offset %d, max layer %d, bo size %ld, slice %d)\n",
                          __func__, __LINE__, id, surf.layer_size,
@@ -446,6 +484,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
                         surf.tsplit, surf.mtilea);
                 return -EINVAL;
         }
+old_ddx_ok:
 
         return 0;
 }
@@ -1532,6 +1571,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
         case CB_COLOR7_SLICE:
                 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
                 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
+                track->cb_color_slice_idx[tmp] = idx;
                 track->cb_dirty = true;
                 break;
         case CB_COLOR8_SLICE:
@@ -1540,6 +1580,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
         case CB_COLOR11_SLICE:
                 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
                 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
+                track->cb_color_slice_idx[tmp] = idx;
                 track->cb_dirty = true;
                 break;
         case CB_COLOR0_ATTRIB:
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index a51f880985f8..65c54160028b 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -156,9 +156,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
         uint32_t offset;
 
-        if (ASIC_IS_DCE5(rdev))
-                return;
-
         /* Silent, r600_hdmi_enable will raise WARN for us */
         if (!dig->afmt->enabled)
                 return;
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 2773039b4902..b50b15c70498 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -503,6 +503,7 @@
 #define SCRATCH_UMSK                                    0x8540
 #define SCRATCH_ADDR                                    0x8544
 
+#define SMX_SAR_CTL0                                    0xA008
 #define SMX_DC_CTL0                                     0xA020
 #define         USE_HASH_FUNCTION                               (1 << 0)
 #define         NUMBER_OF_SETS(x)                               ((x) << 1)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 3df4efa11942..b7bf18e40215 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -460,15 +460,28 @@ static void cayman_gpu_init(struct radeon_device *rdev)
                 rdev->config.cayman.max_pipes_per_simd = 4;
                 rdev->config.cayman.max_tile_pipes = 2;
                 if ((rdev->pdev->device == 0x9900) ||
-                    (rdev->pdev->device == 0x9901)) {
+                    (rdev->pdev->device == 0x9901) ||
+                    (rdev->pdev->device == 0x9905) ||
+                    (rdev->pdev->device == 0x9906) ||
+                    (rdev->pdev->device == 0x9907) ||
+                    (rdev->pdev->device == 0x9908) ||
+                    (rdev->pdev->device == 0x9909) ||
+                    (rdev->pdev->device == 0x9910) ||
+                    (rdev->pdev->device == 0x9917)) {
                         rdev->config.cayman.max_simds_per_se = 6;
                         rdev->config.cayman.max_backends_per_se = 2;
                 } else if ((rdev->pdev->device == 0x9903) ||
-                           (rdev->pdev->device == 0x9904)) {
+                           (rdev->pdev->device == 0x9904) ||
+                           (rdev->pdev->device == 0x990A) ||
+                           (rdev->pdev->device == 0x9913) ||
+                           (rdev->pdev->device == 0x9918)) {
                         rdev->config.cayman.max_simds_per_se = 4;
                         rdev->config.cayman.max_backends_per_se = 2;
-                } else if ((rdev->pdev->device == 0x9990) ||
-                           (rdev->pdev->device == 0x9991)) {
+                } else if ((rdev->pdev->device == 0x9919) ||
+                           (rdev->pdev->device == 0x9990) ||
+                           (rdev->pdev->device == 0x9991) ||
+                           (rdev->pdev->device == 0x9994) ||
+                           (rdev->pdev->device == 0x99A0)) {
                         rdev->config.cayman.max_simds_per_se = 3;
                         rdev->config.cayman.max_backends_per_se = 1;
                 } else {
@@ -1290,6 +1303,10 @@ static int cayman_startup(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        r = r600_audio_init(rdev);
+        if (r)
+                return r;
+
         return 0;
 }
 
@@ -1316,6 +1333,7 @@ int cayman_resume(struct radeon_device *rdev)
 
 int cayman_suspend(struct radeon_device *rdev)
 {
+        r600_audio_fini(rdev);
         /* FIXME: we should wait for ring to be empty */
         radeon_ib_pool_suspend(rdev);
         radeon_vm_manager_suspend(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 45cfcea63507..bff627293812 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1839,6 +1839,7 @@ void r600_gpu_init(struct radeon_device *rdev)
         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
                                NUM_CLIP_SEQ(3)));
         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
+        WREG32(VC_ENHANCE, 0);
 }
 
 
@@ -2426,6 +2427,12 @@ int r600_startup(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        r = r600_audio_init(rdev);
+        if (r) {
+                DRM_ERROR("radeon: audio init failed\n");
+                return r;
+        }
+
         return 0;
 }
 
@@ -2462,12 +2469,6 @@ int r600_resume(struct radeon_device *rdev)
                 return r;
         }
 
-        r = r600_audio_init(rdev);
-        if (r) {
-                DRM_ERROR("radeon: audio resume failed\n");
-                return r;
-        }
-
         return r;
 }
 
@@ -2577,9 +2578,6 @@ int r600_init(struct radeon_device *rdev)
                 rdev->accel_working = false;
         }
 
-        r = r600_audio_init(rdev);
-        if (r)
-                return r; /* TODO error handling */
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index 7c4fa77f018f..79b55916cf90 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -57,7 +57,7 @@ static bool radeon_dig_encoder(struct drm_encoder *encoder)
  */
 static int r600_audio_chipset_supported(struct radeon_device *rdev)
 {
-        return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE5(rdev))
+        return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE6(rdev))
                 || rdev->family == CHIP_RS600
                 || rdev->family == CHIP_RS690
                 || rdev->family == CHIP_RS740;
@@ -192,6 +192,7 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
         struct radeon_device *rdev = dev->dev_private;
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
         int base_rate = 48000;
 
         switch (radeon_encoder->encoder_id) {
@@ -217,8 +218,8 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
                 WREG32(EVERGREEN_AUDIO_PLL1_DIV, clock * 10);
                 WREG32(EVERGREEN_AUDIO_PLL1_UNK, 0x00000071);
 
-                /* Some magic trigger or src sel? */
-                WREG32_P(0x5ac, 0x01, ~0x77);
+                /* Select DTO source */
+                WREG32(0x5ac, radeon_crtc->crtc_id);
         } else {
                 switch (dig->dig_encoder) {
                 case 0:
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 0133f5f09bd6..ca87f7afaf23 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -2079,6 +2079,48 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                         return -EINVAL;
                 }
                 break;
+        case PACKET3_STRMOUT_BASE_UPDATE:
+                if (p->family < CHIP_RV770) {
+                        DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
+                        return -EINVAL;
+                }
+                if (pkt->count != 1) {
+                        DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
+                        return -EINVAL;
+                }
+                if (idx_value > 3) {
+                        DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
+                        return -EINVAL;
+                }
+                {
+                        u64 offset;
+
+                        r = r600_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
+                                return -EINVAL;
+                        }
+
+                        if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
+                                DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
+                                return -EINVAL;
+                        }
+
+                        offset = radeon_get_ib_value(p, idx+1) << 8;
+                        if (offset != track->vgt_strmout_bo_offset[idx_value]) {
+                                DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
+                                          offset, track->vgt_strmout_bo_offset[idx_value]);
+                                return -EINVAL;
+                        }
+
+                        if ((offset + 4) > radeon_bo_size(reloc->robj)) {
+                                DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
+                                          offset + 4, radeon_bo_size(reloc->robj));
+                                return -EINVAL;
+                        }
+                        ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                }
+                break;
         case PACKET3_SURFACE_BASE_UPDATE:
                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 226379e00ac1..82a0a4c919c0 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -322,9 +322,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
         uint32_t offset;
 
-        if (ASIC_IS_DCE5(rdev))
-                return;
-
         /* Silent, r600_hdmi_enable will raise WARN for us */
         if (!dig->afmt->enabled)
                 return;
@@ -348,7 +345,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
                 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
                        HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
                        HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
-                       HDMI0_AUDIO_SEND_MAX_PACKETS | /* send NULL packets if no audio is available */
                        HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
                        HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
         }
@@ -484,7 +480,7 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
         uint32_t offset;
         u32 hdmi;
 
-        if (ASIC_IS_DCE5(rdev))
+        if (ASIC_IS_DCE6(rdev))
                 return;
 
         /* Silent, r600_hdmi_enable will raise WARN for us */
@@ -544,7 +540,7 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
         uint32_t offset;
 
-        if (ASIC_IS_DCE5(rdev))
+        if (ASIC_IS_DCE6(rdev))
                 return;
 
         /* Called for ATOM_ENCODER_MODE_HDMI only */
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index a0dbf1fe6a40..025fd5b6c08c 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -485,6 +485,7 @@
 #define         TC_L2_SIZE(x)                                   ((x)<<5)
 #define         L2_DISABLE_LATE_HIT                             (1<<9)
 
+#define VC_ENHANCE                                      0x9714
 
 #define VGT_CACHE_INVALIDATION                          0x88C4
 #define         CACHE_INVALIDATION(x)                           ((x)<<0)
@@ -1163,6 +1164,7 @@
 #define PACKET3_SET_CTL_CONST                           0x6F
 #define         PACKET3_SET_CTL_CONST_OFFSET                    0x0003cff0
 #define         PACKET3_SET_CTL_CONST_END                       0x0003e200
+#define PACKET3_STRMOUT_BASE_UPDATE                     0x72 /* r7xx */
 #define PACKET3_SURFACE_BASE_UPDATE                     0x73
 
 
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 85dac33e3cce..fefcca55c1eb 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1374,9 +1374,9 @@ struct cayman_asic {
 
 struct si_asic {
         unsigned max_shader_engines;
-        unsigned max_pipes_per_simd;
         unsigned max_tile_pipes;
-        unsigned max_simds_per_se;
+        unsigned max_cu_per_sh;
+        unsigned max_sh_per_se;
         unsigned max_backends_per_se;
         unsigned max_texture_channel_caches;
         unsigned max_gprs;
@@ -1387,7 +1387,6 @@ struct si_asic {
         unsigned sc_hiz_tile_fifo_size;
         unsigned sc_earlyz_tile_fifo_size;
 
-        unsigned num_shader_engines;
         unsigned num_tile_pipes;
         unsigned num_backends_per_se;
         unsigned backend_disable_mask_per_asic;
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index f0bb2b543b13..2c4d53fd20c5 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -57,9 +57,11 @@
  *   2.13.0 - virtual memory support, streamout
  *   2.14.0 - add evergreen tiling informations
  *   2.15.0 - add max_pipes query
+ *   2.16.0 - fix evergreen 2D tiled surface calculation
+ *   2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
  */
 #define KMS_DRIVER_MAJOR        2
-#define KMS_DRIVER_MINOR        15
+#define KMS_DRIVER_MINOR        17
 #define KMS_DRIVER_PATCHLEVEL   0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index 79db56e6c2ac..84b648a7ddd8 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -289,8 +289,9 @@ int radeon_vm_manager_init(struct radeon_device *rdev)
         rdev->vm_manager.enabled = false;
 
         /* mark first vm as always in use, it's the system one */
+        /* allocate enough for 2 full VM pts */
         r = radeon_sa_bo_manager_init(rdev, &rdev->vm_manager.sa_manager,
-                                      rdev->vm_manager.max_pfn * 8,
+                                      rdev->vm_manager.max_pfn * 8 * 2,
                                       RADEON_GEM_DOMAIN_VRAM);
         if (r) {
                 dev_err(rdev->dev, "failed to allocate vm bo (%dKB)\n",
@@ -476,12 +477,18 @@ int radeon_vm_bo_add(struct radeon_device *rdev,
 
         mutex_lock(&vm->mutex);
         if (last_pfn > vm->last_pfn) {
-                /* grow va space 32M by 32M */
-                unsigned align = ((32 << 20) >> 12) - 1;
+                /* release mutex and lock in right order */
+                mutex_unlock(&vm->mutex);
                 radeon_mutex_lock(&rdev->cs_mutex);
-                radeon_vm_unbind_locked(rdev, vm);
+                mutex_lock(&vm->mutex);
+                /* and check again */
+                if (last_pfn > vm->last_pfn) {
+                        /* grow va space 32M by 32M */
+                        unsigned align = ((32 << 20) >> 12) - 1;
+                        radeon_vm_unbind_locked(rdev, vm);
+                        vm->last_pfn = (last_pfn + align) & ~align;
+                }
                 radeon_mutex_unlock(&rdev->cs_mutex);
-                vm->last_pfn = (last_pfn + align) & ~align;
         }
         head = &vm->va;
         last_offset = 0;
@@ -595,8 +602,8 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev,
         if (bo_va == NULL)
                 return 0;
 
-        mutex_lock(&vm->mutex);
         radeon_mutex_lock(&rdev->cs_mutex);
+        mutex_lock(&vm->mutex);
         radeon_vm_bo_update_pte(rdev, vm, bo, NULL);
         radeon_mutex_unlock(&rdev->cs_mutex);
         list_del(&bo_va->vm_list);
@@ -627,7 +634,15 @@ int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
         mutex_init(&vm->mutex);
         INIT_LIST_HEAD(&vm->list);
         INIT_LIST_HEAD(&vm->va);
-        vm->last_pfn = 0;
+        /* SI requires equal sized PTs for all VMs, so always set
+         * last_pfn to max_pfn.  cayman allows variable sized
+         * pts so we can grow then as needed.  Once we switch
+         * to two level pts we can unify this again.
+         */
+        if (rdev->family >= CHIP_TAHITI)
+                vm->last_pfn = rdev->vm_manager.max_pfn;
+        else
+                vm->last_pfn = 0;
         /* map the ib pool buffer at 0 in virtual address space, set
          * read only
          */
@@ -641,9 +656,8 @@ void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
         struct radeon_bo_va *bo_va, *tmp;
         int r;
 
-        mutex_lock(&vm->mutex);
-
         radeon_mutex_lock(&rdev->cs_mutex);
+        mutex_lock(&vm->mutex);
         radeon_vm_unbind_locked(rdev, vm);
         radeon_mutex_unlock(&rdev->cs_mutex);
 
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index f28bd4b7ef98..21ec9f5653ce 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -292,6 +292,7 @@ int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
                           struct drm_file *filp)
 {
+        struct radeon_device *rdev = dev->dev_private;
         struct drm_radeon_gem_busy *args = data;
         struct drm_gem_object *gobj;
         struct radeon_bo *robj;
@@ -317,13 +318,14 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
                 break;
         }
         drm_gem_object_unreference_unlocked(gobj);
-        r = radeon_gem_handle_lockup(robj->rdev, r);
+        r = radeon_gem_handle_lockup(rdev, r);
         return r;
 }
 
 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
                               struct drm_file *filp)
 {
+        struct radeon_device *rdev = dev->dev_private;
         struct drm_radeon_gem_wait_idle *args = data;
         struct drm_gem_object *gobj;
         struct radeon_bo *robj;
@@ -336,10 +338,10 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
         robj = gem_to_radeon_bo(gobj);
         r = radeon_bo_wait(robj, NULL, false);
         /* callback hw specific functions if any */
-        if (robj->rdev->asic->ioctl_wait_idle)
-                robj->rdev->asic->ioctl_wait_idle(robj->rdev, robj);
+        if (rdev->asic->ioctl_wait_idle)
+                robj->rdev->asic->ioctl_wait_idle(rdev, robj);
         drm_gem_object_unreference_unlocked(gobj);
-        r = radeon_gem_handle_lockup(robj->rdev, r);
+        r = radeon_gem_handle_lockup(rdev, r);
         return r;
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index f1016a5820d1..5c58d7d90cb2 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -273,7 +273,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                 break;
         case RADEON_INFO_MAX_PIPES:
                 if (rdev->family >= CHIP_TAHITI)
-                        value = rdev->config.si.max_pipes_per_simd;
+                        value = rdev->config.si.max_cu_per_sh;
                 else if (rdev->family >= CHIP_CAYMAN)
                         value = rdev->config.cayman.max_pipes_per_simd;
                 else if (rdev->family >= CHIP_CEDAR)
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 08825548ee69..5b37e283ec38 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -801,9 +801,13 @@ static void radeon_dynpm_idle_work_handler(struct work_struct *work)
                 int i;
 
                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
-                        not_processed += radeon_fence_count_emitted(rdev, i);
-                        if (not_processed >= 3)
-                                break;
+                        struct radeon_ring *ring = &rdev->ring[i];
+
+                        if (ring->ready) {
+                                not_processed += radeon_fence_count_emitted(rdev, i);
+                                if (not_processed >= 3)
+                                        break;
+                        }
                 }
 
                 if (not_processed >= 3) { /* should upclock */
diff --git a/drivers/gpu/drm/radeon/radeon_prime.c b/drivers/gpu/drm/radeon/radeon_prime.c
index 8ddab4c76710..6bef46ace831 100644
--- a/drivers/gpu/drm/radeon/radeon_prime.c
+++ b/drivers/gpu/drm/radeon/radeon_prime.c
@@ -169,11 +169,17 @@ struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
         struct radeon_bo *bo = gem_to_radeon_bo(obj);
         int ret = 0;
 
+        ret = radeon_bo_reserve(bo, false);
+        if (unlikely(ret != 0))
+                return ERR_PTR(ret);
+
         /* pin buffer into GTT */
         ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL);
-        if (ret)
+        if (ret) {
+                radeon_bo_unreserve(bo);
                 return ERR_PTR(ret);
-
+        }
+        radeon_bo_unreserve(bo);
         return dma_buf_export(bo, &radeon_dmabuf_ops, obj->size, flags);
 }
 
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 25f9eef12c42..e95c5e61d4e2 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -908,12 +908,6 @@ static int rs600_startup(struct radeon_device *rdev)
                 return r;
         }
 
-        r = r600_audio_init(rdev);
-        if (r) {
-                dev_err(rdev->dev, "failed initializing audio\n");
-                return r;
-        }
-
         r = radeon_ib_pool_start(rdev);
         if (r)
                 return r;
@@ -922,6 +916,12 @@ static int rs600_startup(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        r = r600_audio_init(rdev);
+        if (r) {
+                dev_err(rdev->dev, "failed initializing audio\n");
+                return r;
+        }
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 3277ddecfe9f..159b6a43fda0 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -637,12 +637,6 @@ static int rs690_startup(struct radeon_device *rdev)
                 return r;
         }
 
-        r = r600_audio_init(rdev);
-        if (r) {
-                dev_err(rdev->dev, "failed initializing audio\n");
-                return r;
-        }
-
         r = radeon_ib_pool_start(rdev);
         if (r)
                 return r;
@@ -651,6 +645,12 @@ static int rs690_startup(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        r = r600_audio_init(rdev);
+        if (r) {
+                dev_err(rdev->dev, "failed initializing audio\n");
+                return r;
+        }
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 04ddc365a908..b4f51c569c36 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -616,6 +616,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
                                        ACK_FLUSH_CTL(3) |
                                        SYNC_FLUSH_CTL));
 
+        if (rdev->family != CHIP_RV770)
+                WREG32(SMX_SAR_CTL0, 0x00003f3f);
+
         db_debug3 = RREG32(DB_DEBUG3);
         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
         switch (rdev->family) {
@@ -792,7 +795,7 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 
         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
                                           NUM_CLIP_SEQ(3)));
-
+        WREG32(VC_ENHANCE, 0);
 }
 
 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
@@ -956,6 +959,12 @@ static int rv770_startup(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        r = r600_audio_init(rdev);
+        if (r) {
+                DRM_ERROR("radeon: audio init failed\n");
+                return r;
+        }
+
         return 0;
 }
 
@@ -978,12 +987,6 @@ int rv770_resume(struct radeon_device *rdev)
                 return r;
         }
 
-        r = r600_audio_init(rdev);
-        if (r) {
-                dev_err(rdev->dev, "radeon: audio init failed\n");
-                return r;
-        }
-
         return r;
 
 }
@@ -1092,12 +1095,6 @@ int rv770_init(struct radeon_device *rdev)
                 rdev->accel_working = false;
         }
 
-        r = r600_audio_init(rdev);
-        if (r) {
-                dev_err(rdev->dev, "radeon: audio init failed\n");
-                return r;
-        }
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index fdc089896011..b0adfc595d75 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -211,6 +211,7 @@
 #define SCRATCH_UMSK                                    0x8540
 #define SCRATCH_ADDR                                    0x8544
 
+#define SMX_SAR_CTL0                                    0xA008
 #define SMX_DC_CTL0                                     0xA020
 #define         USE_HASH_FUNCTION                               (1 << 0)
 #define         CACHE_DEPTH(x)                                  ((x) << 1)
@@ -310,6 +311,8 @@
 #define TCP_CNTL                                        0x9610
 #define TCP_CHAN_STEER                                  0x9614
 
+#define VC_ENHANCE                                      0x9714
+
 #define VGT_CACHE_INVALIDATION                          0x88C4
 #define         CACHE_INVALIDATION(x)                           ((x)<<0)
 #define                 VC_ONLY                                         0
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 549732e56ca9..0b0279291a73 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -867,200 +867,6 @@ void dce6_bandwidth_update(struct radeon_device *rdev)
 /*
  * Core functions
  */
-static u32 si_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
-                                           u32 num_tile_pipes,
-                                           u32 num_backends_per_asic,
-                                           u32 *backend_disable_mask_per_asic,
-                                           u32 num_shader_engines)
-{
-        u32 backend_map = 0;
-        u32 enabled_backends_mask = 0;
-        u32 enabled_backends_count = 0;
-        u32 num_backends_per_se;
-        u32 cur_pipe;
-        u32 swizzle_pipe[SI_MAX_PIPES];
-        u32 cur_backend = 0;
-        u32 i;
-        bool force_no_swizzle;
-
-        /* force legal values */
-        if (num_tile_pipes < 1)
-                num_tile_pipes = 1;
-        if (num_tile_pipes > rdev->config.si.max_tile_pipes)
-                num_tile_pipes = rdev->config.si.max_tile_pipes;
-        if (num_shader_engines < 1)
-                num_shader_engines = 1;
-        if (num_shader_engines > rdev->config.si.max_shader_engines)
-                num_shader_engines = rdev->config.si.max_shader_engines;
-        if (num_backends_per_asic < num_shader_engines)
-                num_backends_per_asic = num_shader_engines;
-        if (num_backends_per_asic > (rdev->config.si.max_backends_per_se * num_shader_engines))
-                num_backends_per_asic = rdev->config.si.max_backends_per_se * num_shader_engines;
-
-        /* make sure we have the same number of backends per se */
-        num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
-        /* set up the number of backends per se */
-        num_backends_per_se = num_backends_per_asic / num_shader_engines;
-        if (num_backends_per_se > rdev->config.si.max_backends_per_se) {
-                num_backends_per_se = rdev->config.si.max_backends_per_se;
-                num_backends_per_asic = num_backends_per_se * num_shader_engines;
-        }
-
-        /* create enable mask and count for enabled backends */
-        for (i = 0; i < SI_MAX_BACKENDS; ++i) {
-                if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
-                        enabled_backends_mask |= (1 << i);
-                        ++enabled_backends_count;
-                }
-                if (enabled_backends_count == num_backends_per_asic)
-                        break;
-        }
-
-        /* force the backends mask to match the current number of backends */
-        if (enabled_backends_count != num_backends_per_asic) {
-                u32 this_backend_enabled;
-                u32 shader_engine;
-                u32 backend_per_se;
-
-                enabled_backends_mask = 0;
-                enabled_backends_count = 0;
-                *backend_disable_mask_per_asic = SI_MAX_BACKENDS_MASK;
-                for (i = 0; i < SI_MAX_BACKENDS; ++i) {
-                        /* calc the current se */
-                        shader_engine = i / rdev->config.si.max_backends_per_se;
-                        /* calc the backend per se */
-                        backend_per_se = i % rdev->config.si.max_backends_per_se;
-                        /* default to not enabled */
-                        this_backend_enabled = 0;
-                        if ((shader_engine < num_shader_engines) &&
-                            (backend_per_se < num_backends_per_se))
-                                this_backend_enabled = 1;
-                        if (this_backend_enabled) {
-                                enabled_backends_mask |= (1 << i);
-                                *backend_disable_mask_per_asic &= ~(1 << i);
-                                ++enabled_backends_count;
-                        }
-                }
-        }
-
-
-        memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * SI_MAX_PIPES);
-        switch (rdev->family) {
-        case CHIP_TAHITI:
-        case CHIP_PITCAIRN:
-        case CHIP_VERDE:
-                force_no_swizzle = true;
-                break;
-        default:
-                force_no_swizzle = false;
-                break;
-        }
-        if (force_no_swizzle) {
-                bool last_backend_enabled = false;
-
-                force_no_swizzle = false;
-                for (i = 0; i < SI_MAX_BACKENDS; ++i) {
-                        if (((enabled_backends_mask >> i) & 1) == 1) {
-                                if (last_backend_enabled)
-                                        force_no_swizzle = true;
-                                last_backend_enabled = true;
-                        } else
-                                last_backend_enabled = false;
-                }
-        }
-
-        switch (num_tile_pipes) {
-        case 1:
-        case 3:
-        case 5:
-        case 7:
-                DRM_ERROR("odd number of pipes!\n");
-                break;
-        case 2:
-                swizzle_pipe[0] = 0;
-                swizzle_pipe[1] = 1;
-                break;
-        case 4:
-                if (force_no_swizzle) {
-                        swizzle_pipe[0] = 0;
-                        swizzle_pipe[1] = 1;
-                        swizzle_pipe[2] = 2;
-                        swizzle_pipe[3] = 3;
-                } else {
-                        swizzle_pipe[0] = 0;
-                        swizzle_pipe[1] = 2;
-                        swizzle_pipe[2] = 1;
-                        swizzle_pipe[3] = 3;
-                }
-                break;
-        case 6:
-                if (force_no_swizzle) {
-                        swizzle_pipe[0] = 0;
-                        swizzle_pipe[1] = 1;
-                        swizzle_pipe[2] = 2;
-                        swizzle_pipe[3] = 3;
-                        swizzle_pipe[4] = 4;
-                        swizzle_pipe[5] = 5;
-                } else {
-                        swizzle_pipe[0] = 0;
-                        swizzle_pipe[1] = 2;
-                        swizzle_pipe[2] = 4;
-                        swizzle_pipe[3] = 1;
-                        swizzle_pipe[4] = 3;
-                        swizzle_pipe[5] = 5;
-                }
-                break;
-        case 8:
-                if (force_no_swizzle) {
-                        swizzle_pipe[0] = 0;
-                        swizzle_pipe[1] = 1;
-                        swizzle_pipe[2] = 2;
-                        swizzle_pipe[3] = 3;
-                        swizzle_pipe[4] = 4;
-                        swizzle_pipe[5] = 5;
-                        swizzle_pipe[6] = 6;
-                        swizzle_pipe[7] = 7;
-                } else {
-                        swizzle_pipe[0] = 0;
-                        swizzle_pipe[1] = 2;
-                        swizzle_pipe[2] = 4;
-                        swizzle_pipe[3] = 6;
-                        swizzle_pipe[4] = 1;
-                        swizzle_pipe[5] = 3;
-                        swizzle_pipe[6] = 5;
-                        swizzle_pipe[7] = 7;
-                }
-                break;
-        }
-
-        for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
-                while (((1 << cur_backend) & enabled_backends_mask) == 0)
-                        cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
-
-                backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
-
-                cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
-        }
-
-        return backend_map;
-}
-
-static u32 si_get_disable_mask_per_asic(struct radeon_device *rdev,
-                                        u32 disable_mask_per_se,
-                                        u32 max_disable_mask_per_se,
-                                        u32 num_shader_engines)
-{
-        u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
-        u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
-
-        if (num_shader_engines == 1)
-                return disable_mask_per_asic;
-        else if (num_shader_engines == 2)
-                return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
-        else
-                return 0xffffffff;
-}
-
 static void si_tiling_mode_table_init(struct radeon_device *rdev)
 {
         const u32 num_tile_mode_states = 32;
@@ -1562,18 +1368,151 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
                 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
 }
 
+static void si_select_se_sh(struct radeon_device *rdev,
+                            u32 se_num, u32 sh_num)
+{
+        u32 data = INSTANCE_BROADCAST_WRITES;
+
+        if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
+                data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
+        else if (se_num == 0xffffffff)
+                data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
+        else if (sh_num == 0xffffffff)
+                data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
+        else
+                data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
+        WREG32(GRBM_GFX_INDEX, data);
+}
+
+static u32 si_create_bitmask(u32 bit_width)
+{
+        u32 i, mask = 0;
+
+        for (i = 0; i < bit_width; i++) {
+                mask <<= 1;
+                mask |= 1;
+        }
+        return mask;
+}
+
+static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
+{
+        u32 data, mask;
+
+        data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
+        if (data & 1)
+                data &= INACTIVE_CUS_MASK;
+        else
+                data = 0;
+        data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
+
+        data >>= INACTIVE_CUS_SHIFT;
+
+        mask = si_create_bitmask(cu_per_sh);
+
+        return ~data & mask;
+}
+
+static void si_setup_spi(struct radeon_device *rdev,
+                         u32 se_num, u32 sh_per_se,
+                         u32 cu_per_sh)
+{
+        int i, j, k;
+        u32 data, mask, active_cu;
+
+        for (i = 0; i < se_num; i++) {
+                for (j = 0; j < sh_per_se; j++) {
+                        si_select_se_sh(rdev, i, j);
+                        data = RREG32(SPI_STATIC_THREAD_MGMT_3);
+                        active_cu = si_get_cu_enabled(rdev, cu_per_sh);
+
+                        mask = 1;
+                        for (k = 0; k < 16; k++) {
+                                mask <<= k;
+                                if (active_cu & mask) {
+                                        data &= ~mask;
+                                        WREG32(SPI_STATIC_THREAD_MGMT_3, data);
+                                        break;
+                                }
+                        }
+                }
+        }
+        si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
+}
+
+static u32 si_get_rb_disabled(struct radeon_device *rdev,
+                              u32 max_rb_num, u32 se_num,
+                              u32 sh_per_se)
+{
+        u32 data, mask;
+
+        data = RREG32(CC_RB_BACKEND_DISABLE);
+        if (data & 1)
+                data &= BACKEND_DISABLE_MASK;
+        else
+                data = 0;
+        data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
+
+        data >>= BACKEND_DISABLE_SHIFT;
+
+        mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
+
+        return data & mask;
+}
+
+static void si_setup_rb(struct radeon_device *rdev,
+                        u32 se_num, u32 sh_per_se,
+                        u32 max_rb_num)
+{
+        int i, j;
+        u32 data, mask;
+        u32 disabled_rbs = 0;
+        u32 enabled_rbs = 0;
+
+        for (i = 0; i < se_num; i++) {
+                for (j = 0; j < sh_per_se; j++) {
+                        si_select_se_sh(rdev, i, j);
+                        data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
+                        disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
+                }
+        }
+        si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
+
+        mask = 1;
+        for (i = 0; i < max_rb_num; i++) {
+                if (!(disabled_rbs & mask))
+                        enabled_rbs |= mask;
+                mask <<= 1;
+        }
+
+        for (i = 0; i < se_num; i++) {
+                si_select_se_sh(rdev, i, 0xffffffff);
+                data = 0;
+                for (j = 0; j < sh_per_se; j++) {
+                        switch (enabled_rbs & 3) {
+                        case 1:
+                                data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
+                                break;
+                        case 2:
+                                data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
+                                break;
+                        case 3:
+                        default:
+                                data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
+                                break;
+                        }
+                        enabled_rbs >>= 2;
+                }
+                WREG32(PA_SC_RASTER_CONFIG, data);
+        }
+        si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
+}
+
 static void si_gpu_init(struct radeon_device *rdev)
 {
-        u32 cc_rb_backend_disable = 0;
-        u32 cc_gc_shader_array_config;
         u32 gb_addr_config = 0;
         u32 mc_shared_chmap, mc_arb_ramcfg;
-        u32 gb_backend_map;
-        u32 cgts_tcc_disable;
         u32 sx_debug_1;
-        u32 gc_user_shader_array_config;
-        u32 gc_user_rb_backend_disable;
-        u32 cgts_user_tcc_disable;
         u32 hdp_host_path_cntl;
         u32 tmp;
         int i, j;
@@ -1581,9 +1520,9 @@ static void si_gpu_init(struct radeon_device *rdev)
         switch (rdev->family) {
         case CHIP_TAHITI:
                 rdev->config.si.max_shader_engines = 2;
-                rdev->config.si.max_pipes_per_simd = 4;
                 rdev->config.si.max_tile_pipes = 12;
-                rdev->config.si.max_simds_per_se = 8;
+                rdev->config.si.max_cu_per_sh = 8;
+                rdev->config.si.max_sh_per_se = 2;
                 rdev->config.si.max_backends_per_se = 4;
                 rdev->config.si.max_texture_channel_caches = 12;
                 rdev->config.si.max_gprs = 256;
@@ -1594,12 +1533,13 @@ static void si_gpu_init(struct radeon_device *rdev)
                 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
                 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
                 break;
         case CHIP_PITCAIRN:
                 rdev->config.si.max_shader_engines = 2;
-                rdev->config.si.max_pipes_per_simd = 4;
                 rdev->config.si.max_tile_pipes = 8;
-                rdev->config.si.max_simds_per_se = 5;
+                rdev->config.si.max_cu_per_sh = 5;
+                rdev->config.si.max_sh_per_se = 2;
                 rdev->config.si.max_backends_per_se = 4;
                 rdev->config.si.max_texture_channel_caches = 8;
                 rdev->config.si.max_gprs = 256;
@@ -1610,13 +1550,14 @@ static void si_gpu_init(struct radeon_device *rdev)
                 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
                 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
                 break;
         case CHIP_VERDE:
         default:
                 rdev->config.si.max_shader_engines = 1;
-                rdev->config.si.max_pipes_per_simd = 4;
                 rdev->config.si.max_tile_pipes = 4;
-                rdev->config.si.max_simds_per_se = 2;
+                rdev->config.si.max_cu_per_sh = 2;
+                rdev->config.si.max_sh_per_se = 2;
                 rdev->config.si.max_backends_per_se = 4;
                 rdev->config.si.max_texture_channel_caches = 4;
                 rdev->config.si.max_gprs = 256;
@@ -1627,6 +1568,7 @@ static void si_gpu_init(struct radeon_device *rdev)
                 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
                 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
                 break;
         }
 
@@ -1648,31 +1590,7 @@ static void si_gpu_init(struct radeon_device *rdev)
         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 
-        cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
-        cc_gc_shader_array_config = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
-        cgts_tcc_disable = 0xffff0000;
-        for (i = 0; i < rdev->config.si.max_texture_channel_caches; i++)
-                cgts_tcc_disable &= ~(1 << (16 + i));
-        gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
-        gc_user_shader_array_config = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
-        cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
-
-        rdev->config.si.num_shader_engines = rdev->config.si.max_shader_engines;
         rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
-        tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
-        rdev->config.si.num_backends_per_se = r600_count_pipe_bits(tmp);
-        tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
-        rdev->config.si.backend_disable_mask_per_asic =
-                si_get_disable_mask_per_asic(rdev, tmp, SI_MAX_BACKENDS_PER_SE_MASK,
-                                             rdev->config.si.num_shader_engines);
-        rdev->config.si.backend_map =
-                si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
-                                                rdev->config.si.num_backends_per_se *
-                                                rdev->config.si.num_shader_engines,
-                                                &rdev->config.si.backend_disable_mask_per_asic,
-                                                rdev->config.si.num_shader_engines);
-        tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
-        rdev->config.si.num_texture_channel_caches = r600_count_pipe_bits(tmp);
         rdev->config.si.mem_max_burst_length_bytes = 256;
         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
         rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
@@ -1683,55 +1601,8 @@ static void si_gpu_init(struct radeon_device *rdev)
         rdev->config.si.num_gpus = 1;
         rdev->config.si.multi_gpu_tile_size = 64;
 
-        gb_addr_config = 0;
-        switch (rdev->config.si.num_tile_pipes) {
-        case 1:
-                gb_addr_config |= NUM_PIPES(0);
-                break;
-        case 2:
-                gb_addr_config |= NUM_PIPES(1);
-                break;
-        case 4:
-                gb_addr_config |= NUM_PIPES(2);
-                break;
-        case 8:
-        default:
-                gb_addr_config |= NUM_PIPES(3);
-                break;
-        }
-
-        tmp = (rdev->config.si.mem_max_burst_length_bytes / 256) - 1;
-        gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
-        gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.si.num_shader_engines - 1);
-        tmp = (rdev->config.si.shader_engine_tile_size / 16) - 1;
-        gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
-        switch (rdev->config.si.num_gpus) {
-        case 1:
-        default:
-                gb_addr_config |= NUM_GPUS(0);
-                break;
-        case 2:
-                gb_addr_config |= NUM_GPUS(1);
-                break;
-        case 4:
-                gb_addr_config |= NUM_GPUS(2);
-                break;
-        }
-        switch (rdev->config.si.multi_gpu_tile_size) {
-        case 16:
-                gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
-                break;
-        case 32:
-        default:
-                gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
-                break;
-        case 64:
-                gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
-                break;
-        case 128:
-                gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
-                break;
-        }
+        /* fix up row size */
+        gb_addr_config &= ~ROW_SIZE_MASK;
         switch (rdev->config.si.mem_row_size_in_kb) {
         case 1:
         default:
@@ -1745,26 +1616,6 @@ static void si_gpu_init(struct radeon_device *rdev)
                 break;
         }
 
-        tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
-        rdev->config.si.num_tile_pipes = (1 << tmp);
-        tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
-        rdev->config.si.mem_max_burst_length_bytes = (tmp + 1) * 256;
-        tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
-        rdev->config.si.num_shader_engines = tmp + 1;
-        tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
-        rdev->config.si.num_gpus = tmp + 1;
-        tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
-        rdev->config.si.multi_gpu_tile_size = 1 << tmp;
-        tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
-        rdev->config.si.mem_row_size_in_kb = 1 << tmp;
-
-        gb_backend_map =
-                si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
-                                                rdev->config.si.num_backends_per_se *
-                                                rdev->config.si.num_shader_engines,
-                                                &rdev->config.si.backend_disable_mask_per_asic,
-                                                rdev->config.si.num_shader_engines);
-
         /* setup tiling info dword.  gb_addr_config is not adequate since it does
          * not have bank info, so create a custom tiling dword.
          * bits 3:0   num_pipes
@@ -1789,33 +1640,29 @@ static void si_gpu_init(struct radeon_device *rdev)
                 rdev->config.si.tile_config |= (3 << 0);
                 break;
         }
-        rdev->config.si.tile_config |=
-                ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
+        if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
+                rdev->config.si.tile_config |= 1 << 4;
+        else
+                rdev->config.si.tile_config |= 0 << 4;
         rdev->config.si.tile_config |=
                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
         rdev->config.si.tile_config |=
                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
 
-        rdev->config.si.backend_map = gb_backend_map;
         WREG32(GB_ADDR_CONFIG, gb_addr_config);
         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 
-        /* primary versions */
-        WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
-        WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
-        WREG32(CC_GC_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
-
-        WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
+        si_tiling_mode_table_init(rdev);
 
-        /* user versions */
-        WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
-        WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
-        WREG32(GC_USER_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
+        si_setup_rb(rdev, rdev->config.si.max_shader_engines,
+                    rdev->config.si.max_sh_per_se,
+                    rdev->config.si.max_backends_per_se);
 
-        WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
+        si_setup_spi(rdev, rdev->config.si.max_shader_engines,
+                     rdev->config.si.max_sh_per_se,
+                     rdev->config.si.max_cu_per_sh);
 
-        si_tiling_mode_table_init(rdev);
 
         /* set HW defaults for 3D engine */
         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
@@ -2518,12 +2365,12 @@ int si_pcie_gart_enable(struct radeon_device *rdev)
         WREG32(0x15DC, 0);
 
         /* empty context1-15 */
-        /* FIXME start with 1G, once using 2 level pt switch to full
+        /* FIXME start with 4G, once using 2 level pt switch to full
          * vm size space
          */
         /* set vm size, must be a multiple of 4 */
         WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
-        WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, (1 << 30) / RADEON_GPU_PAGE_SIZE);
+        WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
         for (i = 1; i < 16; i++) {
                 if (i < 8)
                         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
diff --git a/drivers/gpu/drm/radeon/si_reg.h b/drivers/gpu/drm/radeon/si_reg.h
index eda938a7cb6e..501f9d431d57 100644
--- a/drivers/gpu/drm/radeon/si_reg.h
+++ b/drivers/gpu/drm/radeon/si_reg.h
@@ -30,4 +30,76 @@
 #define SI_DC_GPIO_HPD_EN                        0x65b8
 #define SI_DC_GPIO_HPD_Y                         0x65bc
 
+#define SI_GRPH_CONTROL                          0x6804
+#       define SI_GRPH_DEPTH(x)                  (((x) & 0x3) << 0)
+#       define SI_GRPH_DEPTH_8BPP                0
+#       define SI_GRPH_DEPTH_16BPP               1
+#       define SI_GRPH_DEPTH_32BPP               2
+#       define SI_GRPH_NUM_BANKS(x)              (((x) & 0x3) << 2)
+#       define SI_ADDR_SURF_2_BANK               0
+#       define SI_ADDR_SURF_4_BANK               1
+#       define SI_ADDR_SURF_8_BANK               2
+#       define SI_ADDR_SURF_16_BANK              3
+#       define SI_GRPH_Z(x)                      (((x) & 0x3) << 4)
+#       define SI_GRPH_BANK_WIDTH(x)             (((x) & 0x3) << 6)
+#       define SI_ADDR_SURF_BANK_WIDTH_1         0
+#       define SI_ADDR_SURF_BANK_WIDTH_2         1
+#       define SI_ADDR_SURF_BANK_WIDTH_4         2
+#       define SI_ADDR_SURF_BANK_WIDTH_8         3
+#       define SI_GRPH_FORMAT(x)                 (((x) & 0x7) << 8)
+/* 8 BPP */
+#       define SI_GRPH_FORMAT_INDEXED            0
+/* 16 BPP */
+#       define SI_GRPH_FORMAT_ARGB1555           0
+#       define SI_GRPH_FORMAT_ARGB565            1
+#       define SI_GRPH_FORMAT_ARGB4444           2
+#       define SI_GRPH_FORMAT_AI88               3
+#       define SI_GRPH_FORMAT_MONO16             4
+#       define SI_GRPH_FORMAT_BGRA5551           5
+/* 32 BPP */
+#       define SI_GRPH_FORMAT_ARGB8888           0
+#       define SI_GRPH_FORMAT_ARGB2101010        1
+#       define SI_GRPH_FORMAT_32BPP_DIG          2
+#       define SI_GRPH_FORMAT_8B_ARGB2101010     3
+#       define SI_GRPH_FORMAT_BGRA1010102        4
+#       define SI_GRPH_FORMAT_8B_BGRA1010102     5
+#       define SI_GRPH_FORMAT_RGB111110          6
+#       define SI_GRPH_FORMAT_BGR101111          7
+#       define SI_GRPH_BANK_HEIGHT(x)            (((x) & 0x3) << 11)
+#       define SI_ADDR_SURF_BANK_HEIGHT_1        0
+#       define SI_ADDR_SURF_BANK_HEIGHT_2        1
+#       define SI_ADDR_SURF_BANK_HEIGHT_4        2
+#       define SI_ADDR_SURF_BANK_HEIGHT_8        3
+#       define SI_GRPH_TILE_SPLIT(x)             (((x) & 0x7) << 13)
+#       define SI_ADDR_SURF_TILE_SPLIT_64B       0
+#       define SI_ADDR_SURF_TILE_SPLIT_128B      1
+#       define SI_ADDR_SURF_TILE_SPLIT_256B      2
+#       define SI_ADDR_SURF_TILE_SPLIT_512B      3
+#       define SI_ADDR_SURF_TILE_SPLIT_1KB       4
+#       define SI_ADDR_SURF_TILE_SPLIT_2KB       5
+#       define SI_ADDR_SURF_TILE_SPLIT_4KB       6
+#       define SI_GRPH_MACRO_TILE_ASPECT(x)      (((x) & 0x3) << 18)
+#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_1  0
+#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_2  1
+#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_4  2
+#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_8  3
+#       define SI_GRPH_ARRAY_MODE(x)             (((x) & 0x7) << 20)
+#       define SI_GRPH_ARRAY_LINEAR_GENERAL      0
+#       define SI_GRPH_ARRAY_LINEAR_ALIGNED      1
+#       define SI_GRPH_ARRAY_1D_TILED_THIN1      2
+#       define SI_GRPH_ARRAY_2D_TILED_THIN1      4
+#       define SI_GRPH_PIPE_CONFIG(x)            (((x) & 0x1f) << 24)
+#       define SI_ADDR_SURF_P2                   0
+#       define SI_ADDR_SURF_P4_8x16              4
+#       define SI_ADDR_SURF_P4_16x16             5
+#       define SI_ADDR_SURF_P4_16x32             6
+#       define SI_ADDR_SURF_P4_32x32             7
+#       define SI_ADDR_SURF_P8_16x16_8x16        8
+#       define SI_ADDR_SURF_P8_16x32_8x16        9
+#       define SI_ADDR_SURF_P8_32x32_8x16        10
+#       define SI_ADDR_SURF_P8_16x32_16x16       11
+#       define SI_ADDR_SURF_P8_32x32_16x16       12
+#       define SI_ADDR_SURF_P8_32x32_16x32       13
+#       define SI_ADDR_SURF_P8_32x64_32x32       14
+
 #endif
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 53ea2c42dbd6..db4067962868 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -24,6 +24,11 @@
 #ifndef SI_H
 #define SI_H
 
+#define TAHITI_RB_BITMAP_WIDTH_PER_SH  2
+
+#define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003
+#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002
+
 #define CG_MULT_THERMAL_STATUS                                  0x714
 #define         ASIC_MAX_TEMP(x)                                ((x) << 0)
 #define         ASIC_MAX_TEMP_MASK                              0x000001ff
@@ -408,6 +413,12 @@
 #define         SOFT_RESET_IA                                   (1 << 15)
 
 #define GRBM_GFX_INDEX                                  0x802C
+#define         INSTANCE_INDEX(x)                       ((x) << 0)
+#define         SH_INDEX(x)                             ((x) << 8)
+#define         SE_INDEX(x)                             ((x) << 16)
+#define         SH_BROADCAST_WRITES                     (1 << 29)
+#define         INSTANCE_BROADCAST_WRITES               (1 << 30)
+#define         SE_BROADCAST_WRITES                     (1 << 31)
 
 #define GRBM_INT_CNTL                                   0x8060
 #       define RDERR_INT_ENABLE                         (1 << 0)
@@ -480,6 +491,8 @@
 #define VGT_TF_MEMORY_BASE                              0x89B8
 
 #define CC_GC_SHADER_ARRAY_CONFIG                       0x89bc
+#define         INACTIVE_CUS_MASK                       0xFFFF0000
+#define         INACTIVE_CUS_SHIFT                      16
 #define GC_USER_SHADER_ARRAY_CONFIG                     0x89c0
 
 #define PA_CL_ENHANCE                                   0x8A14
@@ -688,6 +701,12 @@
 #define RLC_MC_CNTL                                       0xC344
 #define RLC_UCODE_CNTL                                    0xC348
 
+#define PA_SC_RASTER_CONFIG                             0x28350
+#       define RASTER_CONFIG_RB_MAP_0                   0
+#       define RASTER_CONFIG_RB_MAP_1                   1
+#       define RASTER_CONFIG_RB_MAP_2                   2
+#       define RASTER_CONFIG_RB_MAP_3                   3
+
 #define VGT_EVENT_INITIATOR                             0x28a90
 #       define SAMPLE_STREAMOUTSTATS1                   (1 << 0)
 #       define SAMPLE_STREAMOUTSTATS2                   (2 << 0)
diff --git a/drivers/gpu/drm/sis/sis_drv.c b/drivers/gpu/drm/sis/sis_drv.c
index 30d98d14b5c5..dd14cd1a0033 100644
--- a/drivers/gpu/drm/sis/sis_drv.c
+++ b/drivers/gpu/drm/sis/sis_drv.c
@@ -47,9 +47,9 @@ static int sis_driver_load(struct drm_device *dev, unsigned long chipset)
         if (dev_priv == NULL)
                 return -ENOMEM;
 
+        idr_init(&dev_priv->object_idr);
         dev->dev_private = (void *)dev_priv;
         dev_priv->chipset = chipset;
-        idr_init(&dev->object_name_idr);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index b67cfcaa661f..36f4b28c1b90 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -1204,6 +1204,7 @@ int ttm_bo_init(struct ttm_bo_device *bdev,
                         (*destroy)(bo);
                 else
                         kfree(bo);
+                ttm_mem_global_free(mem_glob, acc_size);
                 return -EINVAL;
         }
         bo->destroy = destroy;
@@ -1307,22 +1308,14 @@ int ttm_bo_create(struct ttm_bo_device *bdev,
                         struct ttm_buffer_object **p_bo)
 {
         struct ttm_buffer_object *bo;
-        struct ttm_mem_global *mem_glob = bdev->glob->mem_glob;
         size_t acc_size;
         int ret;
 
-        acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct ttm_buffer_object));
-        ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false);
-        if (unlikely(ret != 0))
-                return ret;
-
         bo = kzalloc(sizeof(*bo), GFP_KERNEL);
-
-        if (unlikely(bo == NULL)) {
-                ttm_mem_global_free(mem_glob, acc_size);
+        if (unlikely(bo == NULL))
                 return -ENOMEM;
-        }
 
+        acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct ttm_buffer_object));
         ret = ttm_bo_init(bdev, bo, size, type, placement, page_alignment,
                                 buffer_start, interruptible,
                           persistent_swap_storage, acc_size, NULL, NULL);
diff --git a/drivers/gpu/drm/udl/udl_drv.c b/drivers/gpu/drm/udl/udl_drv.c
index 4d02c46a9420..6e52069894b3 100644
--- a/drivers/gpu/drm/udl/udl_drv.c
+++ b/drivers/gpu/drm/udl/udl_drv.c
@@ -13,8 +13,21 @@
 
 static struct drm_driver driver;
 
+/*
+ * There are many DisplayLink-based graphics products, all with unique PIDs.
+ * So we match on DisplayLink's VID + Vendor-Defined Interface Class (0xff)
+ * We also require a match on SubClass (0x00) and Protocol (0x00),
+ * which is compatible with all known USB 2.0 era graphics chips and firmware,
+ * but allows DisplayLink to increment those for any future incompatible chips
+ */
 static struct usb_device_id id_table[] = {
-        {.idVendor = 0x17e9, .match_flags = USB_DEVICE_ID_MATCH_VENDOR,},
+        {.idVendor = 0x17e9, .bInterfaceClass = 0xff,
+         .bInterfaceSubClass = 0x00,
+         .bInterfaceProtocol = 0x00,
+         .match_flags = USB_DEVICE_ID_MATCH_VENDOR |
+                        USB_DEVICE_ID_MATCH_INT_CLASS |
+                        USB_DEVICE_ID_MATCH_INT_SUBCLASS |
+                        USB_DEVICE_ID_MATCH_INT_PROTOCOL,},
         {},
 };
 MODULE_DEVICE_TABLE(usb, id_table);
diff --git a/drivers/gpu/drm/udl/udl_main.c b/drivers/gpu/drm/udl/udl_main.c
index a8d5f09428c7..4c2d836a0893 100644
--- a/drivers/gpu/drm/udl/udl_main.c
+++ b/drivers/gpu/drm/udl/udl_main.c
@@ -61,7 +61,7 @@ static int udl_parse_vendor_descriptor(struct drm_device *dev,
                         u8 length;
                         u16 key;
 
-                        key = *((u16 *) desc);
+                        key = le16_to_cpu(*((u16 *) desc));
                         desc += sizeof(u16);
                         length = *desc;
                         desc++;
diff --git a/drivers/gpu/drm/via/via_map.c b/drivers/gpu/drm/via/via_map.c
index 1f182254e81e..c126182ac07e 100644
--- a/drivers/gpu/drm/via/via_map.c
+++ b/drivers/gpu/drm/via/via_map.c
@@ -100,12 +100,11 @@ int via_driver_load(struct drm_device *dev, unsigned long chipset)
         if (dev_priv == NULL)
                 return -ENOMEM;
 
+        idr_init(&dev_priv->object_idr);
         dev->dev_private = (void *)dev_priv;
 
         dev_priv->chipset = chipset;
 
-        idr_init(&dev->object_name_idr);
-
         pci_set_master(dev->pdev);
 
         ret = drm_vblank_init(dev, 1);
diff --git a/drivers/gpu/vga/vga_switcheroo.c b/drivers/gpu/vga/vga_switcheroo.c
index 38f9534ac513..5b3c7d135dc9 100644
--- a/drivers/gpu/vga/vga_switcheroo.c
+++ b/drivers/gpu/vga/vga_switcheroo.c
@@ -190,6 +190,19 @@ find_active_client(struct list_head *head)
         return NULL;
 }
 
+int vga_switcheroo_get_client_state(struct pci_dev *pdev)
+{
+        struct vga_switcheroo_client *client;
+
+        client = find_client_from_pci(&vgasr_priv.clients, pdev);
+        if (!client)
+                return VGA_SWITCHEROO_NOT_FOUND;
+        if (!vgasr_priv.active)
+                return VGA_SWITCHEROO_INIT;
+        return client->pwr_state;
+}
+EXPORT_SYMBOL(vga_switcheroo_get_client_state);
+
 void vga_switcheroo_unregister_client(struct pci_dev *pdev)
 {
         struct vga_switcheroo_client *client;
@@ -291,8 +304,6 @@ static int vga_switchto_stage1(struct vga_switcheroo_client *new_client)
                 vga_switchon(new_client);
 
         vga_set_default_device(new_client->pdev);
-        set_audio_state(new_client->id, VGA_SWITCHEROO_ON);
-
         return 0;
 }
 
@@ -308,6 +319,8 @@ static int vga_switchto_stage2(struct vga_switcheroo_client *new_client)
 
         active->active = false;
 
+        set_audio_state(active->id, VGA_SWITCHEROO_OFF);
+
         if (new_client->fb_info) {
                 struct fb_event event;
                 event.info = new_client->fb_info;
@@ -321,11 +334,11 @@ static int vga_switchto_stage2(struct vga_switcheroo_client *new_client)
         if (new_client->ops->reprobe)
                 new_client->ops->reprobe(new_client->pdev);
 
-        set_audio_state(active->id, VGA_SWITCHEROO_OFF);
-
         if (active->pwr_state == VGA_SWITCHEROO_ON)
                 vga_switchoff(active);
 
+        set_audio_state(new_client->id, VGA_SWITCHEROO_ON);
+
         new_client->active = true;
         return 0;
 }
@@ -371,8 +384,9 @@ vga_switcheroo_debugfs_write(struct file *filp, const char __user *ubuf,
         /* pwr off the device not in use */
         if (strncmp(usercmd, "OFF", 3) == 0) {
                 list_for_each_entry(client, &vgasr_priv.clients, list) {
-                        if (client->active)
+                        if (client->active || client_is_audio(client))
                                 continue;
+                        set_audio_state(client->id, VGA_SWITCHEROO_OFF);
                         if (client->pwr_state == VGA_SWITCHEROO_ON)
                                 vga_switchoff(client);
                 }
@@ -381,10 +395,11 @@ vga_switcheroo_debugfs_write(struct file *filp, const char __user *ubuf,
         /* pwr on the device not in use */
         if (strncmp(usercmd, "ON", 2) == 0) {
                 list_for_each_entry(client, &vgasr_priv.clients, list) {
-                        if (client->active)
+                        if (client->active || client_is_audio(client))
                                 continue;
                         if (client->pwr_state == VGA_SWITCHEROO_OFF)
                                 vga_switchon(client);
+                        set_audio_state(client->id, VGA_SWITCHEROO_ON);
                 }
                 goto out;
         }