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-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c28
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c44
-rw-r--r--drivers/gpu/drm/radeon/ni.c32
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c29
-rw-r--r--drivers/gpu/drm/radeon/radeon_cursor.c40
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c9
-rw-r--r--drivers/gpu/drm/radeon/rv770.c51
7 files changed, 54 insertions, 179 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 7ad43c6b1db7..79e8ebc05307 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -115,6 +115,7 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
115 u8 msg[20]; 115 u8 msg[20];
116 int msg_bytes = send_bytes + 4; 116 int msg_bytes = send_bytes + 4;
117 u8 ack; 117 u8 ack;
118 unsigned retry;
118 119
119 if (send_bytes > 16) 120 if (send_bytes > 16)
120 return -1; 121 return -1;
@@ -125,20 +126,22 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
125 msg[3] = (msg_bytes << 4) | (send_bytes - 1); 126 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
126 memcpy(&msg[4], send, send_bytes); 127 memcpy(&msg[4], send, send_bytes);
127 128
128 while (1) { 129 for (retry = 0; retry < 4; retry++) {
129 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 130 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
130 msg, msg_bytes, NULL, 0, delay, &ack); 131 msg, msg_bytes, NULL, 0, delay, &ack);
131 if (ret < 0) 132 if (ret == -EBUSY)
133 continue;
134 else if (ret < 0)
132 return ret; 135 return ret;
133 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 136 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
134 break; 137 return send_bytes;
135 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 138 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
136 udelay(400); 139 udelay(400);
137 else 140 else
138 return -EIO; 141 return -EIO;
139 } 142 }
140 143
141 return send_bytes; 144 return -EIO;
142} 145}
143 146
144static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, 147static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
@@ -149,26 +152,31 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
149 int msg_bytes = 4; 152 int msg_bytes = 4;
150 u8 ack; 153 u8 ack;
151 int ret; 154 int ret;
155 unsigned retry;
152 156
153 msg[0] = address; 157 msg[0] = address;
154 msg[1] = address >> 8; 158 msg[1] = address >> 8;
155 msg[2] = AUX_NATIVE_READ << 4; 159 msg[2] = AUX_NATIVE_READ << 4;
156 msg[3] = (msg_bytes << 4) | (recv_bytes - 1); 160 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
157 161
158 while (1) { 162 for (retry = 0; retry < 4; retry++) {
159 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 163 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
160 msg, msg_bytes, recv, recv_bytes, delay, &ack); 164 msg, msg_bytes, recv, recv_bytes, delay, &ack);
161 if (ret == 0) 165 if (ret == -EBUSY)
162 return -EPROTO; 166 continue;
163 if (ret < 0) 167 else if (ret < 0)
164 return ret; 168 return ret;
165 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 169 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
166 return ret; 170 return ret;
167 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 171 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
168 udelay(400); 172 udelay(400);
173 else if (ret == 0)
174 return -EPROTO;
169 else 175 else
170 return -EIO; 176 return -EIO;
171 } 177 }
178
179 return -EIO;
172} 180}
173 181
174static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, 182static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
@@ -232,7 +240,9 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
232 for (retry = 0; retry < 4; retry++) { 240 for (retry = 0; retry < 4; retry++) {
233 ret = radeon_process_aux_ch(auxch, 241 ret = radeon_process_aux_ch(auxch,
234 msg, msg_bytes, reply, reply_bytes, 0, &ack); 242 msg, msg_bytes, reply, reply_bytes, 0, &ack);
235 if (ret < 0) { 243 if (ret == -EBUSY)
244 continue;
245 else if (ret < 0) {
236 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 246 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
237 return ret; 247 return ret;
238 } 248 }
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e8a746712b5b..c4ffa14fb2f4 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1590,48 +1590,6 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1590 return backend_map; 1590 return backend_map;
1591} 1591}
1592 1592
1593static void evergreen_program_channel_remap(struct radeon_device *rdev)
1594{
1595 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1596
1597 tmp = RREG32(MC_SHARED_CHMAP);
1598 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1599 case 0:
1600 case 1:
1601 case 2:
1602 case 3:
1603 default:
1604 /* default mapping */
1605 mc_shared_chremap = 0x00fac688;
1606 break;
1607 }
1608
1609 switch (rdev->family) {
1610 case CHIP_HEMLOCK:
1611 case CHIP_CYPRESS:
1612 case CHIP_BARTS:
1613 tcp_chan_steer_lo = 0x54763210;
1614 tcp_chan_steer_hi = 0x0000ba98;
1615 break;
1616 case CHIP_JUNIPER:
1617 case CHIP_REDWOOD:
1618 case CHIP_CEDAR:
1619 case CHIP_PALM:
1620 case CHIP_SUMO:
1621 case CHIP_SUMO2:
1622 case CHIP_TURKS:
1623 case CHIP_CAICOS:
1624 default:
1625 tcp_chan_steer_lo = 0x76543210;
1626 tcp_chan_steer_hi = 0x0000ba98;
1627 break;
1628 }
1629
1630 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1631 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1632 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1633}
1634
1635static void evergreen_gpu_init(struct radeon_device *rdev) 1593static void evergreen_gpu_init(struct radeon_device *rdev)
1636{ 1594{
1637 u32 cc_rb_backend_disable = 0; 1595 u32 cc_rb_backend_disable = 0;
@@ -2078,8 +2036,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2078 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 2036 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2079 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 2037 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2080 2038
2081 evergreen_program_channel_remap(rdev);
2082
2083 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; 2039 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2084 grbm_gfx_index = INSTANCE_BROADCAST_WRITES; 2040 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2085 2041
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 99fbd793c08c..8c79ca97753d 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -569,36 +569,6 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
569 return backend_map; 569 return backend_map;
570} 570}
571 571
572static void cayman_program_channel_remap(struct radeon_device *rdev)
573{
574 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
575
576 tmp = RREG32(MC_SHARED_CHMAP);
577 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
578 case 0:
579 case 1:
580 case 2:
581 case 3:
582 default:
583 /* default mapping */
584 mc_shared_chremap = 0x00fac688;
585 break;
586 }
587
588 switch (rdev->family) {
589 case CHIP_CAYMAN:
590 default:
591 //tcp_chan_steer_lo = 0x54763210
592 tcp_chan_steer_lo = 0x76543210;
593 tcp_chan_steer_hi = 0x0000ba98;
594 break;
595 }
596
597 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
598 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
599 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
600}
601
602static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev, 572static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
603 u32 disable_mask_per_se, 573 u32 disable_mask_per_se,
604 u32 max_disable_mask_per_se, 574 u32 max_disable_mask_per_se,
@@ -842,8 +812,6 @@ static void cayman_gpu_init(struct radeon_device *rdev)
842 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 812 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
843 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 813 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
844 814
845 cayman_program_channel_remap(rdev);
846
847 /* primary versions */ 815 /* primary versions */
848 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 816 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
849 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 817 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index c4b8741dbf58..449c3d8c6836 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -68,11 +68,11 @@ void radeon_connector_hotplug(struct drm_connector *connector)
68 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 68 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
69 int saved_dpms = connector->dpms; 69 int saved_dpms = connector->dpms;
70 70
71 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) && 71 /* Only turn off the display it it's physically disconnected */
72 radeon_dp_needs_link_train(radeon_connector)) 72 if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
73 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
74 else
75 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 73 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
74 else if (radeon_dp_needs_link_train(radeon_connector))
75 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
76 connector->dpms = saved_dpms; 76 connector->dpms = saved_dpms;
77 } 77 }
78} 78}
@@ -1303,23 +1303,14 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
1303 /* get the DPCD from the bridge */ 1303 /* get the DPCD from the bridge */
1304 radeon_dp_getdpcd(radeon_connector); 1304 radeon_dp_getdpcd(radeon_connector);
1305 1305
1306 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1306 if (encoder) {
1307 ret = connector_status_connected; 1307 /* setup ddc on the bridge */
1308 else { 1308 radeon_atom_ext_encoder_setup_ddc(encoder);
1309 /* need to setup ddc on the bridge */
1310 if (encoder)
1311 radeon_atom_ext_encoder_setup_ddc(encoder);
1312 if (radeon_ddc_probe(radeon_connector, 1309 if (radeon_ddc_probe(radeon_connector,
1313 radeon_connector->requires_extended_probe)) 1310 radeon_connector->requires_extended_probe)) /* try DDC */
1314 ret = connector_status_connected; 1311 ret = connector_status_connected;
1315 } 1312 else if (radeon_connector->dac_load_detect) { /* try load detection */
1316 1313 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1317 if ((ret == connector_status_disconnected) &&
1318 radeon_connector->dac_load_detect) {
1319 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1320 struct drm_encoder_helper_funcs *encoder_funcs;
1321 if (encoder) {
1322 encoder_funcs = encoder->helper_private;
1323 ret = encoder_funcs->detect(encoder, connector); 1314 ret = encoder_funcs->detect(encoder, connector);
1324 } 1315 }
1325 } 1316 }
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index 3189a7efb2e9..fde25c0d65a0 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -208,23 +208,25 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
208 int xorigin = 0, yorigin = 0; 208 int xorigin = 0, yorigin = 0;
209 int w = radeon_crtc->cursor_width; 209 int w = radeon_crtc->cursor_width;
210 210
211 if (x < 0)
212 xorigin = -x + 1;
213 if (y < 0)
214 yorigin = -y + 1;
215 if (xorigin >= CURSOR_WIDTH)
216 xorigin = CURSOR_WIDTH - 1;
217 if (yorigin >= CURSOR_HEIGHT)
218 yorigin = CURSOR_HEIGHT - 1;
219
220 if (ASIC_IS_AVIVO(rdev)) { 211 if (ASIC_IS_AVIVO(rdev)) {
221 int i = 0;
222 struct drm_crtc *crtc_p;
223
224 /* avivo cursor are offset into the total surface */ 212 /* avivo cursor are offset into the total surface */
225 x += crtc->x; 213 x += crtc->x;
226 y += crtc->y; 214 y += crtc->y;
227 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 215 }
216 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
217
218 if (x < 0) {
219 xorigin = min(-x, CURSOR_WIDTH - 1);
220 x = 0;
221 }
222 if (y < 0) {
223 yorigin = min(-y, CURSOR_HEIGHT - 1);
224 y = 0;
225 }
226
227 if (ASIC_IS_AVIVO(rdev)) {
228 int i = 0;
229 struct drm_crtc *crtc_p;
228 230
229 /* avivo cursor image can't end on 128 pixel boundary or 231 /* avivo cursor image can't end on 128 pixel boundary or
230 * go past the end of the frame if both crtcs are enabled 232 * go past the end of the frame if both crtcs are enabled
@@ -253,16 +255,12 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
253 255
254 radeon_lock_cursor(crtc, true); 256 radeon_lock_cursor(crtc, true);
255 if (ASIC_IS_DCE4(rdev)) { 257 if (ASIC_IS_DCE4(rdev)) {
256 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, 258 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
257 ((xorigin ? 0 : x) << 16) |
258 (yorigin ? 0 : y));
259 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 259 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
260 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, 260 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
261 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 261 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
262 } else if (ASIC_IS_AVIVO(rdev)) { 262 } else if (ASIC_IS_AVIVO(rdev)) {
263 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, 263 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
264 ((xorigin ? 0 : x) << 16) |
265 (yorigin ? 0 : y));
266 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 264 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
267 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, 265 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
268 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 266 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
@@ -276,8 +274,8 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
276 | yorigin)); 274 | yorigin));
277 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, 275 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
278 (RADEON_CUR_LOCK 276 (RADEON_CUR_LOCK
279 | ((xorigin ? 0 : x) << 16) 277 | (x << 16)
280 | (yorigin ? 0 : y))); 278 | y));
281 /* offset is from DISP(2)_BASE_ADDRESS */ 279 /* offset is from DISP(2)_BASE_ADDRESS */
282 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset + 280 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
283 (yorigin * 256))); 281 (yorigin * 256)));
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 13690f3eb4a4..8a171b21b453 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1755,9 +1755,12 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1755 /* DCE4/5 */ 1755 /* DCE4/5 */
1756 if (ASIC_IS_DCE4(rdev)) { 1756 if (ASIC_IS_DCE4(rdev)) {
1757 dig = radeon_encoder->enc_priv; 1757 dig = radeon_encoder->enc_priv;
1758 if (ASIC_IS_DCE41(rdev)) 1758 if (ASIC_IS_DCE41(rdev)) {
1759 return radeon_crtc->crtc_id; 1759 if (dig->linkb)
1760 else { 1760 return 1;
1761 else
1762 return 0;
1763 } else {
1761 switch (radeon_encoder->encoder_id) { 1764 switch (radeon_encoder->encoder_id) {
1762 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1765 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1763 if (dig->linkb) 1766 if (dig->linkb)
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 4720d000d440..b13c2eedc321 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -536,55 +536,6 @@ static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
536 return backend_map; 536 return backend_map;
537} 537}
538 538
539static void rv770_program_channel_remap(struct radeon_device *rdev)
540{
541 u32 tcp_chan_steer, mc_shared_chremap, tmp;
542 bool force_no_swizzle;
543
544 switch (rdev->family) {
545 case CHIP_RV770:
546 case CHIP_RV730:
547 force_no_swizzle = false;
548 break;
549 case CHIP_RV710:
550 case CHIP_RV740:
551 default:
552 force_no_swizzle = true;
553 break;
554 }
555
556 tmp = RREG32(MC_SHARED_CHMAP);
557 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
558 case 0:
559 case 1:
560 default:
561 /* default mapping */
562 mc_shared_chremap = 0x00fac688;
563 break;
564 case 2:
565 case 3:
566 if (force_no_swizzle)
567 mc_shared_chremap = 0x00fac688;
568 else
569 mc_shared_chremap = 0x00bbc298;
570 break;
571 }
572
573 if (rdev->family == CHIP_RV740)
574 tcp_chan_steer = 0x00ef2a60;
575 else
576 tcp_chan_steer = 0x00fac688;
577
578 /* RV770 CE has special chremap setup */
579 if (rdev->pdev->device == 0x944e) {
580 tcp_chan_steer = 0x00b08b08;
581 mc_shared_chremap = 0x00b08b08;
582 }
583
584 WREG32(TCP_CHAN_STEER, tcp_chan_steer);
585 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
586}
587
588static void rv770_gpu_init(struct radeon_device *rdev) 539static void rv770_gpu_init(struct radeon_device *rdev)
589{ 540{
590 int i, j, num_qd_pipes; 541 int i, j, num_qd_pipes;
@@ -785,8 +736,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
785 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 736 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
786 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 737 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
787 738
788 rv770_program_channel_remap(rdev);
789
790 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 739 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
791 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 740 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
792 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 741 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);