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-rw-r--r--drivers/gpu/drm/drm_crtc.c4
-rw-r--r--drivers/gpu/drm/drm_mm.c2
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c20
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c2
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c24
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo_regs.h2
-rw-r--r--drivers/gpu/drm/mga/mga_dma.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_channel.c4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c2
-rw-r--r--drivers/gpu/drm/nouveau/nv04_crtc.c4
-rw-r--r--drivers/gpu/drm/nouveau/nv40_graph.c2
-rw-r--r--drivers/gpu/drm/radeon/atombios.h34
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c2
-rw-r--r--drivers/gpu/drm/radeon/r300.c2
-rw-r--r--drivers/gpu/drm/radeon/r300_reg.h4
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c2
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon.h4
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_cursor.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_state.c2
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_kms.c2
-rw-r--r--drivers/gpu/vga/vgaarb.c4
29 files changed, 49 insertions, 93 deletions
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 799e1490cf24..872747c5a544 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1699,7 +1699,7 @@ int drm_mode_addfb(struct drm_device *dev,
1699 1699
1700 mutex_lock(&dev->mode_config.mutex); 1700 mutex_lock(&dev->mode_config.mutex);
1701 1701
1702 /* TODO check buffer is sufficently large */ 1702 /* TODO check buffer is sufficiently large */
1703 /* TODO setup destructor callback */ 1703 /* TODO setup destructor callback */
1704 1704
1705 fb = dev->mode_config.funcs->fb_create(dev, file_priv, r); 1705 fb = dev->mode_config.funcs->fb_create(dev, file_priv, r);
@@ -1750,7 +1750,7 @@ int drm_mode_rmfb(struct drm_device *dev,
1750 1750
1751 mutex_lock(&dev->mode_config.mutex); 1751 mutex_lock(&dev->mode_config.mutex);
1752 obj = drm_mode_object_find(dev, *id, DRM_MODE_OBJECT_FB); 1752 obj = drm_mode_object_find(dev, *id, DRM_MODE_OBJECT_FB);
1753 /* TODO check that we realy get a framebuffer back. */ 1753 /* TODO check that we really get a framebuffer back. */
1754 if (!obj) { 1754 if (!obj) {
1755 DRM_ERROR("mode invalid framebuffer id\n"); 1755 DRM_ERROR("mode invalid framebuffer id\n");
1756 ret = -EINVAL; 1756 ret = -EINVAL;
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index add1737dae0d..5d00b0fc0d91 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -551,7 +551,7 @@ EXPORT_SYMBOL(drm_mm_scan_add_block);
551 * corrupted. 551 * corrupted.
552 * 552 *
553 * When the scan list is empty, the selected memory nodes can be freed. An 553 * When the scan list is empty, the selected memory nodes can be freed. An
554 * immediatly following drm_mm_search_free with best_match = 0 will then return 554 * immediately following drm_mm_search_free with best_match = 0 will then return
555 * the just freed block (because its at the top of the free_stack list). 555 * the just freed block (because its at the top of the free_stack list).
556 * 556 *
557 * Returns one if this block should be evicted, zero otherwise. Will always 557 * Returns one if this block should be evicted, zero otherwise. Will always
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5004724ea57e..1c1b27c97e5c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -630,7 +630,7 @@ typedef struct drm_i915_private {
630 * Flag if the hardware appears to be wedged. 630 * Flag if the hardware appears to be wedged.
631 * 631 *
632 * This is set when attempts to idle the device timeout. 632 * This is set when attempts to idle the device timeout.
633 * It prevents command submission from occuring and makes 633 * It prevents command submission from occurring and makes
634 * every pending request fail 634 * every pending request fail
635 */ 635 */
636 atomic_t wedged; 636 atomic_t wedged;
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 8342259f3160..d03fc05b39c0 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -269,21 +269,6 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
269 return ret; 269 return ret;
270} 270}
271 271
272static bool intel_crt_ddc_probe(struct drm_i915_private *dev_priv, int ddc_bus)
273{
274 u8 buf;
275 struct i2c_msg msgs[] = {
276 {
277 .addr = 0xA0,
278 .flags = 0,
279 .len = 1,
280 .buf = &buf,
281 },
282 };
283 /* DDC monitor detect: Does it ACK a write to 0xA0? */
284 return i2c_transfer(&dev_priv->gmbus[ddc_bus].adapter, msgs, 1) == 1;
285}
286
287static bool intel_crt_detect_ddc(struct drm_connector *connector) 272static bool intel_crt_detect_ddc(struct drm_connector *connector)
288{ 273{
289 struct intel_crt *crt = intel_attached_crt(connector); 274 struct intel_crt *crt = intel_attached_crt(connector);
@@ -293,11 +278,6 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
293 if (crt->base.type != INTEL_OUTPUT_ANALOG) 278 if (crt->base.type != INTEL_OUTPUT_ANALOG)
294 return false; 279 return false;
295 280
296 if (intel_crt_ddc_probe(dev_priv, dev_priv->crt_ddc_pin)) {
297 DRM_DEBUG_KMS("CRT detected via DDC:0xa0\n");
298 return true;
299 }
300
301 if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) { 281 if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) {
302 struct edid *edid; 282 struct edid *edid;
303 bool is_digital = false; 283 bool is_digital = false;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0daefca5cbb8..cb8578b7e443 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -213,7 +213,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
213 return MODE_PANEL; 213 return MODE_PANEL;
214 } 214 }
215 215
216 /* only refuse the mode on non eDP since we have seen some wierd eDP panels 216 /* only refuse the mode on non eDP since we have seen some weird eDP panels
217 which are outside spec tolerances but somehow work by magic */ 217 which are outside spec tolerances but somehow work by magic */
218 if (!is_edp(intel_dp) && 218 if (!is_edp(intel_dp) &&
219 (intel_dp_link_required(connector->dev, intel_dp, mode->clock) 219 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 86cd30bcb619..a562bd2648c7 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -829,25 +829,6 @@ static bool lvds_is_present_in_vbt(struct drm_device *dev,
829 return false; 829 return false;
830} 830}
831 831
832static bool intel_lvds_ddc_probe(struct drm_device *dev, u8 pin)
833{
834 struct drm_i915_private *dev_priv = dev->dev_private;
835 u8 buf = 0;
836 struct i2c_msg msgs[] = {
837 {
838 .addr = 0xA0,
839 .flags = 0,
840 .len = 1,
841 .buf = &buf,
842 },
843 };
844 struct i2c_adapter *i2c = &dev_priv->gmbus[pin].adapter;
845 /* XXX this only appears to work when using GMBUS */
846 if (intel_gmbus_is_forced_bit(i2c))
847 return true;
848 return i2c_transfer(i2c, msgs, 1) == 1;
849}
850
851/** 832/**
852 * intel_lvds_init - setup LVDS connectors on this device 833 * intel_lvds_init - setup LVDS connectors on this device
853 * @dev: drm device 834 * @dev: drm device
@@ -888,11 +869,6 @@ bool intel_lvds_init(struct drm_device *dev)
888 } 869 }
889 } 870 }
890 871
891 if (!intel_lvds_ddc_probe(dev, pin)) {
892 DRM_DEBUG_KMS("LVDS did not respond to DDC probe\n");
893 return false;
894 }
895
896 intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL); 872 intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL);
897 if (!intel_lvds) { 873 if (!intel_lvds) {
898 return false; 874 return false;
diff --git a/drivers/gpu/drm/i915/intel_sdvo_regs.h b/drivers/gpu/drm/i915/intel_sdvo_regs.h
index a386b022e538..4f4e23bc2d16 100644
--- a/drivers/gpu/drm/i915/intel_sdvo_regs.h
+++ b/drivers/gpu/drm/i915/intel_sdvo_regs.h
@@ -230,7 +230,7 @@ struct intel_sdvo_set_target_input_args {
230} __attribute__((packed)); 230} __attribute__((packed));
231 231
232/** 232/**
233 * Takes a struct intel_sdvo_output_flags of which outputs are targetted by 233 * Takes a struct intel_sdvo_output_flags of which outputs are targeted by
234 * future output commands. 234 * future output commands.
235 * 235 *
236 * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12], 236 * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
diff --git a/drivers/gpu/drm/mga/mga_dma.c b/drivers/gpu/drm/mga/mga_dma.c
index 1e1eb1d7e971..5ccb65deb83c 100644
--- a/drivers/gpu/drm/mga/mga_dma.c
+++ b/drivers/gpu/drm/mga/mga_dma.c
@@ -426,7 +426,7 @@ int mga_driver_load(struct drm_device *dev, unsigned long flags)
426 * Bootstrap the driver for AGP DMA. 426 * Bootstrap the driver for AGP DMA.
427 * 427 *
428 * \todo 428 * \todo
429 * Investigate whether there is any benifit to storing the WARP microcode in 429 * Investigate whether there is any benefit to storing the WARP microcode in
430 * AGP memory. If not, the microcode may as well always be put in PCI 430 * AGP memory. If not, the microcode may as well always be put in PCI
431 * memory. 431 * memory.
432 * 432 *
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 3837090d66af..4cea35c57d15 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -200,7 +200,7 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
200 /* disable the fifo caches */ 200 /* disable the fifo caches */
201 pfifo->reassign(dev, false); 201 pfifo->reassign(dev, false);
202 202
203 /* Construct inital RAMFC for new channel */ 203 /* Construct initial RAMFC for new channel */
204 ret = pfifo->create_context(chan); 204 ret = pfifo->create_context(chan);
205 if (ret) { 205 if (ret) {
206 nouveau_channel_put(&chan); 206 nouveau_channel_put(&chan);
@@ -278,7 +278,7 @@ nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
278 return; 278 return;
279 } 279 }
280 280
281 /* noone wants the channel anymore */ 281 /* no one wants the channel anymore */
282 NV_DEBUG(dev, "freeing channel %d\n", chan->id); 282 NV_DEBUG(dev, "freeing channel %d\n", chan->id);
283 nouveau_debugfs_channel_fini(chan); 283 nouveau_debugfs_channel_fini(chan);
284 284
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index fff180a99867..57e5302503db 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -216,7 +216,7 @@ struct nouveau_channel {
216 /* mapping of the fifo itself */ 216 /* mapping of the fifo itself */
217 struct drm_local_map *map; 217 struct drm_local_map *map;
218 218
219 /* mapping of the regs controling the fifo */ 219 /* mapping of the regs controlling the fifo */
220 void __iomem *user; 220 void __iomem *user;
221 uint32_t user_get; 221 uint32_t user_get;
222 uint32_t user_put; 222 uint32_t user_put;
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 4fcbd091a117..5bb2859001e2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -963,7 +963,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
963 if (ret) 963 if (ret)
964 goto err_mmio; 964 goto err_mmio;
965 965
966 /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */ 966 /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
967 if (dev_priv->card_type >= NV_40) { 967 if (dev_priv->card_type >= NV_40) {
968 int ramin_bar = 2; 968 int ramin_bar = 2;
969 if (pci_resource_len(dev->pdev, ramin_bar) == 0) 969 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index a260fbbe3d9b..748b9d9c2949 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -164,7 +164,7 @@ nv_crtc_dpms(struct drm_crtc *crtc, int mode)
164 NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode, 164 NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode,
165 nv_crtc->index); 165 nv_crtc->index);
166 166
167 if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */ 167 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */
168 return; 168 return;
169 169
170 nv_crtc->last_dpms = mode; 170 nv_crtc->last_dpms = mode;
@@ -677,7 +677,7 @@ static void nv_crtc_prepare(struct drm_crtc *crtc)
677 677
678 NVBlankScreen(dev, nv_crtc->index, true); 678 NVBlankScreen(dev, nv_crtc->index, true);
679 679
680 /* Some more preperation. */ 680 /* Some more preparation. */
681 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); 681 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
682 if (dev_priv->card_type == NV_40) { 682 if (dev_priv->card_type == NV_40) {
683 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); 683 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 18d30c2c1aa6..fceb44c0ec74 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -181,7 +181,7 @@ nv40_graph_load_context(struct nouveau_channel *chan)
181 NV40_PGRAPH_CTXCTL_CUR_LOADED); 181 NV40_PGRAPH_CTXCTL_CUR_LOADED);
182 /* 0x32E0 records the instance address of the active FIFO's PGRAPH 182 /* 0x32E0 records the instance address of the active FIFO's PGRAPH
183 * context. If at any time this doesn't match 0x40032C, you will 183 * context. If at any time this doesn't match 0x40032C, you will
184 * recieve PGRAPH_INTR_CONTEXT_SWITCH 184 * receive PGRAPH_INTR_CONTEXT_SWITCH
185 */ 185 */
186 nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst); 186 nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
187 return 0; 187 return 0;
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 04b269d14a59..7fd88497b930 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -738,13 +738,13 @@ typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
738{ 738{
739#if ATOM_BIG_ENDIAN 739#if ATOM_BIG_ENDIAN
740 UCHAR ucReserved1:1; 740 UCHAR ucReserved1:1;
741 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F) 741 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
742 UCHAR ucReserved:3; 742 UCHAR ucReserved:3;
743 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 743 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
744#else 744#else
745 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 745 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
746 UCHAR ucReserved:3; 746 UCHAR ucReserved:3;
747 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F) 747 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
748 UCHAR ucReserved1:1; 748 UCHAR ucReserved1:1;
749#endif 749#endif
750}ATOM_DIG_ENCODER_CONFIG_V3; 750}ATOM_DIG_ENCODER_CONFIG_V3;
@@ -785,13 +785,13 @@ typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
785{ 785{
786#if ATOM_BIG_ENDIAN 786#if ATOM_BIG_ENDIAN
787 UCHAR ucReserved1:1; 787 UCHAR ucReserved1:1;
788 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F) 788 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
789 UCHAR ucReserved:2; 789 UCHAR ucReserved:2;
790 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 790 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
791#else 791#else
792 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 792 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
793 UCHAR ucReserved:2; 793 UCHAR ucReserved:2;
794 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F) 794 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
795 UCHAR ucReserved1:1; 795 UCHAR ucReserved1:1;
796#endif 796#endif
797}ATOM_DIG_ENCODER_CONFIG_V4; 797}ATOM_DIG_ENCODER_CONFIG_V4;
@@ -2126,7 +2126,7 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
2126// Structures used in FirmwareInfoTable 2126// Structures used in FirmwareInfoTable
2127/****************************************************************************/ 2127/****************************************************************************/
2128 2128
2129// usBIOSCapability Defintion: 2129// usBIOSCapability Definition:
2130// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2130// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
2131// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2131// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
2132// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2132// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
@@ -3341,7 +3341,7 @@ typedef struct _ATOM_SPREAD_SPECTRUM_INFO
3341/****************************************************************************/ 3341/****************************************************************************/
3342// Structure used in AnalogTV_InfoTable (Top level) 3342// Structure used in AnalogTV_InfoTable (Top level)
3343/****************************************************************************/ 3343/****************************************************************************/
3344//ucTVBootUpDefaultStd definiton: 3344//ucTVBootUpDefaultStd definition:
3345 3345
3346//ATOM_TV_NTSC 1 3346//ATOM_TV_NTSC 1
3347//ATOM_TV_NTSCJ 2 3347//ATOM_TV_NTSCJ 2
@@ -3816,7 +3816,7 @@ typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
3816 UCHAR Reserved [6]; // for potential expansion 3816 UCHAR Reserved [6]; // for potential expansion
3817}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 3817}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
3818 3818
3819//Related definitions, all records are differnt but they have a commond header 3819//Related definitions, all records are different but they have a commond header
3820typedef struct _ATOM_COMMON_RECORD_HEADER 3820typedef struct _ATOM_COMMON_RECORD_HEADER
3821{ 3821{
3822 UCHAR ucRecordType; //An emun to indicate the record type 3822 UCHAR ucRecordType; //An emun to indicate the record type
@@ -4365,14 +4365,14 @@ ucUMAChannelNumber: System memory channel numbers.
4365ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 4365ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
4366ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 4366ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
4367ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 4367ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
4368sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 4368sAvail_SCLK[5]: Arrays to provide available list of SLCK and corresponding voltage, order from low to high
4369ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 4369ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
4370ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 4370ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
4371ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 4371ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4372ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 4372ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
4373ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 4373ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
4374usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. 4374usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
4375usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. 4375usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
4376usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 4376usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
4377usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4377usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4378usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4378usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
@@ -4555,7 +4555,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
4555#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 4555#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
4556#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 4556#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
4557 4557
4558//Byte aligned defintion for BIOS usage 4558//Byte aligned definition for BIOS usage
4559#define ATOM_S0_CRT1_MONOb0 0x01 4559#define ATOM_S0_CRT1_MONOb0 0x01
4560#define ATOM_S0_CRT1_COLORb0 0x02 4560#define ATOM_S0_CRT1_COLORb0 0x02
4561#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 4561#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
@@ -4621,7 +4621,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
4621#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 4621#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L
4622 4622
4623 4623
4624//Byte aligned defintion for BIOS usage 4624//Byte aligned definition for BIOS usage
4625#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 4625#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F
4626#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 4626#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
4627#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 4627#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01
@@ -4671,7 +4671,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
4671#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 4671#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L
4672#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 4672#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
4673 4673
4674//Byte aligned defintion for BIOS usage 4674//Byte aligned definition for BIOS usage
4675#define ATOM_S3_CRT1_ACTIVEb0 0x01 4675#define ATOM_S3_CRT1_ACTIVEb0 0x01
4676#define ATOM_S3_LCD1_ACTIVEb0 0x02 4676#define ATOM_S3_LCD1_ACTIVEb0 0x02
4677#define ATOM_S3_TV1_ACTIVEb0 0x04 4677#define ATOM_S3_TV1_ACTIVEb0 0x04
@@ -4707,7 +4707,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
4707#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 4707#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L
4708#define ATOM_S4_LCD1_REFRESH_SHIFT 8 4708#define ATOM_S4_LCD1_REFRESH_SHIFT 8
4709 4709
4710//Byte aligned defintion for BIOS usage 4710//Byte aligned definition for BIOS usage
4711#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 4711#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF
4712#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 4712#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0
4713#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 4713#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0
@@ -4786,7 +4786,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
4786#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 4786#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L
4787#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 4787#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L
4788 4788
4789//Byte aligned defintion for BIOS usage 4789//Byte aligned definition for BIOS usage
4790#define ATOM_S6_DEVICE_CHANGEb0 0x01 4790#define ATOM_S6_DEVICE_CHANGEb0 0x01
4791#define ATOM_S6_SCALER_CHANGEb0 0x02 4791#define ATOM_S6_SCALER_CHANGEb0 0x02
4792#define ATOM_S6_LID_CHANGEb0 0x04 4792#define ATOM_S6_LID_CHANGEb0 0x04
@@ -5027,7 +5027,7 @@ typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
5027 5027
5028typedef struct _MEMORY_CLEAN_UP_PARAMETERS 5028typedef struct _MEMORY_CLEAN_UP_PARAMETERS
5029{ 5029{
5030 USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address 5030 USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address
5031 USHORT usMemorySize; //8Kb blocks aligned 5031 USHORT usMemorySize; //8Kb blocks aligned
5032}MEMORY_CLEAN_UP_PARAMETERS; 5032}MEMORY_CLEAN_UP_PARAMETERS;
5033#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 5033#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
@@ -6855,7 +6855,7 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
6855/**************************************************************************/ 6855/**************************************************************************/
6856 6856
6857 6857
6858// Following definitions are for compatiblity issue in different SW components. 6858// Following definitions are for compatibility issue in different SW components.
6859#define ATOM_MASTER_DATA_TABLE_REVISION 0x01 6859#define ATOM_MASTER_DATA_TABLE_REVISION 0x01
6860#define Object_Info Object_Header 6860#define Object_Info Object_Header
6861#define AdjustARB_SEQ MC_InitParameter 6861#define AdjustARB_SEQ MC_InitParameter
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index edde90b37554..23d36417158d 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -442,7 +442,7 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
442 } 442 }
443 ib = p->ib->ptr; 443 ib = p->ib->ptr;
444 switch (reg) { 444 switch (reg) {
445 /* force following reg to 0 in an attemp to disable out buffer 445 /* force following reg to 0 in an attempt to disable out buffer
446 * which will need us to better understand how it works to perform 446 * which will need us to better understand how it works to perform
447 * security check on it (Jerome) 447 * security check on it (Jerome)
448 */ 448 */
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 8713731fa014..55a7f190027e 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -437,7 +437,7 @@ int r300_asic_reset(struct radeon_device *rdev)
437 status = RREG32(R_000E40_RBBM_STATUS); 437 status = RREG32(R_000E40_RBBM_STATUS);
438 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 438 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
439 /* resetting the CP seems to be problematic sometimes it end up 439 /* resetting the CP seems to be problematic sometimes it end up
440 * hard locking the computer, but it's necessary for successfull 440 * hard locking the computer, but it's necessary for successful
441 * reset more test & playing is needed on R3XX/R4XX to find a 441 * reset more test & playing is needed on R3XX/R4XX to find a
442 * reliable (if any solution) 442 * reliable (if any solution)
443 */ 443 */
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h
index f0bce399c9f3..00c0d2ba22d3 100644
--- a/drivers/gpu/drm/radeon/r300_reg.h
+++ b/drivers/gpu/drm/radeon/r300_reg.h
@@ -608,7 +608,7 @@
608 * My guess is that there are two bits for each zbias primitive 608 * My guess is that there are two bits for each zbias primitive
609 * (FILL, LINE, POINT). 609 * (FILL, LINE, POINT).
610 * One to enable depth test and one for depth write. 610 * One to enable depth test and one for depth write.
611 * Yet this doesnt explain why depth writes work ... 611 * Yet this doesn't explain why depth writes work ...
612 */ 612 */
613#define R300_RE_OCCLUSION_CNTL 0x42B4 613#define R300_RE_OCCLUSION_CNTL 0x42B4
614# define R300_OCCLUSION_ON (1<<1) 614# define R300_OCCLUSION_ON (1<<1)
@@ -817,7 +817,7 @@
817# define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11) 817# define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11)
818# define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11) 818# define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11)
819 819
820/* NOTE: NEAREST doesnt seem to exist. 820/* NOTE: NEAREST doesn't seem to exist.
821 * Im not seting MAG_FILTER_MASK and (3 << 11) on for all 821 * Im not seting MAG_FILTER_MASK and (3 << 11) on for all
822 * anisotropy modes because that would void selected mag filter 822 * anisotropy modes because that would void selected mag filter
823 */ 823 */
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 3324620b2db6..fd18be9871ab 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -921,7 +921,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
921 return 0; 921 return 0;
922 ib = p->ib->ptr; 922 ib = p->ib->ptr;
923 switch (reg) { 923 switch (reg) {
924 /* force following reg to 0 in an attemp to disable out buffer 924 /* force following reg to 0 in an attempt to disable out buffer
925 * which will need us to better understand how it works to perform 925 * which will need us to better understand how it works to perform
926 * security check on it (Jerome) 926 * security check on it (Jerome)
927 */ 927 */
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 50db6d62eec2..f5ac7e788d81 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -334,7 +334,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
334 r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0, 334 r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,
335 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 335 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
336 336
337 /* it's unknown what these bits do excatly, but it's indeed quite usefull for debugging */ 337 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
338 WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF); 338 WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF);
339 WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF); 339 WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF);
340 WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001); 340 WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index cfe3af1a7935..93f536594c73 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -679,11 +679,11 @@ struct radeon_wb {
679 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 679 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
680 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 680 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
681 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 681 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
682 * @sclk: GPU clock Mhz (core bandwith depends of this clock) 682 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
683 * @needed_bandwidth: current bandwidth needs 683 * @needed_bandwidth: current bandwidth needs
684 * 684 *
685 * It keeps track of various data needed to take powermanagement decision. 685 * It keeps track of various data needed to take powermanagement decision.
686 * Bandwith need is used to determine minimun clock of the GPU and memory. 686 * Bandwidth need is used to determine minimun clock of the GPU and memory.
687 * Equation between gpu/memory clock and available bandwidth is hw dependent 687 * Equation between gpu/memory clock and available bandwidth is hw dependent
688 * (type of memory, bus size, efficiency, ...) 688 * (type of memory, bus size, efficiency, ...)
689 */ 689 */
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 3d599e33b9cc..75867792a4e2 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -244,7 +244,7 @@ void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
244 u32 agp_base_lo = agp_base & 0xffffffff; 244 u32 agp_base_lo = agp_base & 0xffffffff;
245 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff; 245 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
246 246
247 /* R6xx/R7xx must be aligned to a 4MB boundry */ 247 /* R6xx/R7xx must be aligned to a 4MB boundary */
248 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 248 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
249 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base); 249 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
250 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 250 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index 017ac54920fb..bdf2fa1189ae 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -226,7 +226,7 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
226 y += crtc->y; 226 y += crtc->y;
227 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 227 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
228 228
229 /* avivo cursor image can't end on 128 pixel boundry or 229 /* avivo cursor image can't end on 128 pixel boundary or
230 * go past the end of the frame if both crtcs are enabled 230 * go past the end of the frame if both crtcs are enabled
231 */ 231 */
232 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) { 232 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index f0209be7a34b..890217e678d3 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -262,7 +262,7 @@ int radeon_wb_init(struct radeon_device *rdev)
262 * Note: GTT start, end, size should be initialized before calling this 262 * Note: GTT start, end, size should be initialized before calling this
263 * function on AGP platform. 263 * function on AGP platform.
264 * 264 *
265 * Note: We don't explictly enforce VRAM start to be aligned on VRAM size, 265 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
266 * this shouldn't be a problem as we are using the PCI aperture as a reference. 266 * this shouldn't be a problem as we are using the PCI aperture as a reference.
267 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 267 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
268 * not IGP. 268 * not IGP.
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 4be58793dc17..bdbab5c43bdc 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1492,7 +1492,7 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1492 * 1492 *
1493 * \return Flags, or'ed together as follows: 1493 * \return Flags, or'ed together as follows:
1494 * 1494 *
1495 * DRM_SCANOUTPOS_VALID = Query successfull. 1495 * DRM_SCANOUTPOS_VALID = Query successful.
1496 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1496 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1497 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1497 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1498 * this flag means that returned position may be offset by a constant but 1498 * this flag means that returned position may be offset by a constant but
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 5cba46b9779a..a1b59ca96d01 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -271,7 +271,7 @@ typedef struct drm_radeon_private {
271 271
272 int have_z_offset; 272 int have_z_offset;
273 273
274 /* starting from here on, data is preserved accross an open */ 274 /* starting from here on, data is preserved across an open */
275 uint32_t flags; /* see radeon_chip_flags */ 275 uint32_t flags; /* see radeon_chip_flags */
276 resource_size_t fb_aper_offset; 276 resource_size_t fb_aper_offset;
277 277
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
index 7f8e778dba46..ede6c13628f2 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -87,7 +87,7 @@ static inline void radeon_bo_unreserve(struct radeon_bo *bo)
87 * Returns current GPU offset of the object. 87 * Returns current GPU offset of the object.
88 * 88 *
89 * Note: object should either be pinned or reserved when calling this 89 * Note: object should either be pinned or reserved when calling this
90 * function, it might be usefull to add check for this for debugging. 90 * function, it might be useful to add check for this for debugging.
91 */ 91 */
92static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo) 92static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)
93{ 93{
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index 4ae5a3d1074e..92e7ea73b7c5 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -980,7 +980,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
980 } 980 }
981 981
982 /* hyper z clear */ 982 /* hyper z clear */
983 /* no docs available, based on reverse engeneering by Stephane Marchesin */ 983 /* no docs available, based on reverse engineering by Stephane Marchesin */
984 if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) 984 if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
985 && (flags & RADEON_CLEAR_FASTZ)) { 985 && (flags & RADEON_CLEAR_FASTZ)) {
986 986
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index cceeb42789b6..dfe32e62bd90 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -245,7 +245,7 @@ void vmw_kms_cursor_snoop(struct vmw_surface *srf,
245 /* TODO handle none page aligned offsets */ 245 /* TODO handle none page aligned offsets */
246 /* TODO handle partial uploads and pitch != 256 */ 246 /* TODO handle partial uploads and pitch != 256 */
247 /* TODO handle more then one copy (size != 64) */ 247 /* TODO handle more then one copy (size != 64) */
248 DRM_ERROR("lazy programer, cant handle wierd stuff\n"); 248 DRM_ERROR("lazy programmer, can't handle weird stuff\n");
249 return; 249 return;
250 } 250 }
251 251
diff --git a/drivers/gpu/vga/vgaarb.c b/drivers/gpu/vga/vgaarb.c
index ace2b1623b21..be8d4cb5861c 100644
--- a/drivers/gpu/vga/vgaarb.c
+++ b/drivers/gpu/vga/vgaarb.c
@@ -151,7 +151,7 @@ static inline void vga_irq_set_state(struct vga_device *vgadev, bool state)
151static void vga_check_first_use(void) 151static void vga_check_first_use(void)
152{ 152{
153 /* we should inform all GPUs in the system that 153 /* we should inform all GPUs in the system that
154 * VGA arb has occured and to try and disable resources 154 * VGA arb has occurred and to try and disable resources
155 * if they can */ 155 * if they can */
156 if (!vga_arbiter_used) { 156 if (!vga_arbiter_used) {
157 vga_arbiter_used = true; 157 vga_arbiter_used = true;
@@ -774,7 +774,7 @@ static ssize_t vga_arb_read(struct file *file, char __user * buf,
774 */ 774 */
775 spin_lock_irqsave(&vga_lock, flags); 775 spin_lock_irqsave(&vga_lock, flags);
776 776
777 /* If we are targetting the default, use it */ 777 /* If we are targeting the default, use it */
778 pdev = priv->target; 778 pdev = priv->target;
779 if (pdev == NULL || pdev == PCI_INVALID_CARD) { 779 if (pdev == NULL || pdev == PCI_INVALID_CARD) {
780 spin_unlock_irqrestore(&vga_lock, flags); 780 spin_unlock_irqrestore(&vga_lock, flags);