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-rw-r--r--drivers/gpu/drm/nouveau/Makefile1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/copy/nve0.c156
-rw-r--r--drivers/gpu/drm/nouveau/core/include/engine/copy.h2
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/device/nve0.c5
4 files changed, 164 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 97a091961a9b..cb237af3b21d 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -103,6 +103,7 @@ nouveau-y += core/engine/dmaobj/nvc0.o
103nouveau-y += core/engine/bsp/nv84.o 103nouveau-y += core/engine/bsp/nv84.o
104nouveau-y += core/engine/copy/nva3.o 104nouveau-y += core/engine/copy/nva3.o
105nouveau-y += core/engine/copy/nvc0.o 105nouveau-y += core/engine/copy/nvc0.o
106nouveau-y += core/engine/copy/nve0.o
106nouveau-y += core/engine/crypt/nv84.o 107nouveau-y += core/engine/crypt/nv84.o
107nouveau-y += core/engine/crypt/nv98.o 108nouveau-y += core/engine/crypt/nv98.o
108nouveau-y += core/engine/disp/nv04.o 109nouveau-y += core/engine/disp/nv04.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
new file mode 100644
index 000000000000..2017c1579ac5
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
@@ -0,0 +1,156 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <core/os.h>
26#include <core/enum.h>
27#include <core/class.h>
28#include <core/engctx.h>
29
30#include <engine/copy.h>
31
32struct nve0_copy_priv {
33 struct nouveau_copy base;
34};
35
36struct nve0_copy_chan {
37 struct nouveau_copy_chan base;
38};
39
40/*******************************************************************************
41 * Copy object classes
42 ******************************************************************************/
43
44static struct nouveau_oclass
45nve0_copy_sclass[] = {
46 { 0xa0b5, &nouveau_object_ofuncs },
47 {},
48};
49
50/*******************************************************************************
51 * PCOPY context
52 ******************************************************************************/
53
54static int
55nve0_copy_context_ctor(struct nouveau_object *parent,
56 struct nouveau_object *engine,
57 struct nouveau_oclass *oclass, void *data, u32 size,
58 struct nouveau_object **pobject)
59{
60 struct nve0_copy_chan *priv;
61 int ret;
62
63 ret = nouveau_copy_context_create(parent, engine, oclass, NULL, 256,
64 256, NVOBJ_FLAG_ZERO_ALLOC, &priv);
65 *pobject = nv_object(priv);
66 if (ret)
67 return ret;
68
69 return 0;
70}
71
72static struct nouveau_ofuncs
73nve0_copy_context_ofuncs = {
74 .ctor = nve0_copy_context_ctor,
75 .dtor = _nouveau_copy_context_dtor,
76 .init = _nouveau_copy_context_init,
77 .fini = _nouveau_copy_context_fini,
78 .rd32 = _nouveau_copy_context_rd32,
79 .wr32 = _nouveau_copy_context_wr32,
80};
81
82static struct nouveau_oclass
83nve0_copy_cclass = {
84 .handle = NV_ENGCTX(COPY0, 0xc0),
85 .ofuncs = &nve0_copy_context_ofuncs,
86};
87
88/*******************************************************************************
89 * PCOPY engine/subdev functions
90 ******************************************************************************/
91
92static int
93nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
94 struct nouveau_oclass *oclass, void *data, u32 size,
95 struct nouveau_object **pobject)
96{
97 struct nve0_copy_priv *priv;
98 int ret;
99
100 if (nv_rd32(parent, 0x022500) & 0x00000100)
101 return -ENODEV;
102
103 ret = nouveau_copy_create(parent, engine, oclass, true, 0, &priv);
104 *pobject = nv_object(priv);
105 if (ret)
106 return ret;
107
108 nv_subdev(priv)->unit = 0x00000040;
109 nv_engine(priv)->cclass = &nve0_copy_cclass;
110 nv_engine(priv)->sclass = nve0_copy_sclass;
111 return 0;
112}
113
114static int
115nve0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
116 struct nouveau_oclass *oclass, void *data, u32 size,
117 struct nouveau_object **pobject)
118{
119 struct nve0_copy_priv *priv;
120 int ret;
121
122 if (nv_rd32(parent, 0x022500) & 0x00000200)
123 return -ENODEV;
124
125 ret = nouveau_copy_create(parent, engine, oclass, true, 1, &priv);
126 *pobject = nv_object(priv);
127 if (ret)
128 return ret;
129
130 nv_subdev(priv)->unit = 0x00000080;
131 nv_engine(priv)->cclass = &nve0_copy_cclass;
132 nv_engine(priv)->sclass = nve0_copy_sclass;
133 return 0;
134}
135
136struct nouveau_oclass
137nve0_copy0_oclass = {
138 .handle = NV_ENGINE(COPY0, 0xe0),
139 .ofuncs = &(struct nouveau_ofuncs) {
140 .ctor = nve0_copy0_ctor,
141 .dtor = _nouveau_copy_dtor,
142 .init = _nouveau_copy_init,
143 .fini = _nouveau_copy_fini,
144 },
145};
146
147struct nouveau_oclass
148nve0_copy1_oclass = {
149 .handle = NV_ENGINE(COPY1, 0xe0),
150 .ofuncs = &(struct nouveau_ofuncs) {
151 .ctor = nve0_copy1_ctor,
152 .dtor = _nouveau_copy_dtor,
153 .init = _nouveau_copy_init,
154 .fini = _nouveau_copy_fini,
155 },
156};
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/copy.h b/drivers/gpu/drm/nouveau/core/include/engine/copy.h
index 23bb9dfeaf67..70b9d8c5fcf5 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/copy.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/copy.h
@@ -43,5 +43,7 @@ struct nouveau_copy {
43extern struct nouveau_oclass nva3_copy_oclass; 43extern struct nouveau_oclass nva3_copy_oclass;
44extern struct nouveau_oclass nvc0_copy0_oclass; 44extern struct nouveau_oclass nvc0_copy0_oclass;
45extern struct nouveau_oclass nvc0_copy1_oclass; 45extern struct nouveau_oclass nvc0_copy1_oclass;
46extern struct nouveau_oclass nve0_copy0_oclass;
47extern struct nouveau_oclass nve0_copy1_oclass;
46 48
47#endif 49#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c
index 2547ac032df3..efb8ddcff56c 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c
@@ -42,6 +42,7 @@
42#include <engine/software.h> 42#include <engine/software.h>
43#include <engine/graph.h> 43#include <engine/graph.h>
44#include <engine/disp.h> 44#include <engine/disp.h>
45#include <engine/copy.h>
45 46
46int 47int
47nve0_identify(struct nouveau_device *device) 48nve0_identify(struct nouveau_device *device)
@@ -67,6 +68,8 @@ nve0_identify(struct nouveau_device *device)
67 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 68 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
68 device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass; 69 device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass;
69 device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass; 70 device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
71 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
72 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
70 break; 73 break;
71 case 0xe7: 74 case 0xe7:
72 device->cname = "GK107"; 75 device->cname = "GK107";
@@ -88,6 +91,8 @@ nve0_identify(struct nouveau_device *device)
88 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 91 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
89 device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass; 92 device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass;
90 device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass; 93 device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
94 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
95 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
91 break; 96 break;
92 default: 97 default:
93 nv_fatal(device, "unknown Kepler chipset\n"); 98 nv_fatal(device, "unknown Kepler chipset\n");