44 files changed, 3508 insertions, 477 deletions
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index c961fe415aef..39b393d38bb3 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -81,6 +81,7 @@ config DRM_I830
 config DRM_I915
        tristate "i915 driver"
+        depends on AGP_INTEL
        select FB_CFB_FILLRECT
        select FB_CFB_COPYAREA
        select FB_CFB_IMAGEBLIT
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 4e89ab08b7b8..fe23f29f7cba 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -16,6 +16,7 @@ drm-y       :=	drm_auth.o drm_bufs.o drm_cache.o \
 drm-$(CONFIG_COMPAT) += drm_ioc32.o
 obj-$(CONFIG_DRM)       += drm.o
+obj-$(CONFIG_DRM_TTM)   += ttm/
 obj-$(CONFIG_DRM_TDFX)  += tdfx/
 obj-$(CONFIG_DRM_R128)  += r128/
 obj-$(CONFIG_DRM_RADEON)+= radeon/
@@ -26,4 +27,3 @@ obj-$(CONFIG_DRM_I915)  += i915/
 obj-$(CONFIG_DRM_SIS)   += sis/
 obj-$(CONFIG_DRM_SAVAGE)+= savage/
 obj-$(CONFIG_DRM_VIA)   +=via/
-obj-$(CONFIG_DRM_TTM)   += ttm/
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index a6f73f1e99d9..3da9cfa31848 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -1090,6 +1090,8 @@ int drm_helper_resume_force_mode(struct drm_device *dev)
                if (ret == false)
                        DRM_ERROR("failed to set mode on crtc %p\n", crtc);
        }
+        /* disable the unused connectors while restoring the modesetting */
+        drm_helper_disable_unused_functions(dev);
        return 0;
 }
 EXPORT_SYMBOL(drm_helper_resume_force_mode);
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 7d0835226f6e..80cc6d06d61b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -294,10 +294,10 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
        unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
        unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
        unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
-        unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 8 | pt->hsync_offset_lo;
+        unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
-        unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 6 | pt->hsync_pulse_width_lo;
+        unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
-        unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) | (pt->vsync_offset_pulse_width_lo & 0xf);
+        unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) >> 2 | pt->vsync_offset_pulse_width_lo >> 4;
-        unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) >> 2 | pt->vsync_offset_pulse_width_lo >> 4;
+        unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
        /* ignore tiny modes */
        if (hactive < 64 || vactive < 64)
@@ -347,8 +347,8 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
        mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
                DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
-        mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
+        mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
-        mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
+        mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
        if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
                mode->width_mm *= 10;
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 51c5a050aa73..30d6b99fb302 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -13,6 +13,8 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
          intel_crt.o \
          intel_lvds.o \
          intel_bios.o \
+          intel_dp.o \
+          intel_dp_i2c.o \
          intel_hdmi.o \
          intel_sdvo.o \
          intel_modes.o \
diff --git a/drivers/gpu/drm/i915/dvo.h b/drivers/gpu/drm/i915/dvo.h
index e747ac42fe3a..288fc50627e2 100644
--- a/drivers/gpu/drm/i915/dvo.h
+++ b/drivers/gpu/drm/i915/dvo.h
@@ -37,7 +37,7 @@ struct intel_dvo_device {
        /* GPIO register used for i2c bus to control this device */
        u32 gpio;
        int slave_addr;
-        struct intel_i2c_chan *i2c_bus;
+        struct i2c_adapter *i2c_bus;
        const struct intel_dvo_dev_ops *dev_ops;
        void *dev_priv;
@@ -52,7 +52,7 @@ struct intel_dvo_dev_ops {
         * Returns NULL if the device does not exist.
         */
        bool (*init)(struct intel_dvo_device *dvo,
-                     struct intel_i2c_chan *i2cbus);
+                     struct i2c_adapter *i2cbus);
        /*
         * Called to allow the output a chance to create properties after the
diff --git a/drivers/gpu/drm/i915/dvo_ch7017.c b/drivers/gpu/drm/i915/dvo_ch7017.c
index 03d4b4973b02..621815b531db 100644
--- a/drivers/gpu/drm/i915/dvo_ch7017.c
+++ b/drivers/gpu/drm/i915/dvo_ch7017.c
@@ -176,19 +176,20 @@ static void ch7017_dpms(struct intel_dvo_device *dvo, int mode);
 static bool ch7017_read(struct intel_dvo_device *dvo, int addr, uint8_t *val)
 {
-        struct intel_i2c_chan *i2cbus = dvo->i2c_bus;
+        struct i2c_adapter *adapter = dvo->i2c_bus;
+        struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
        u8 out_buf[2];
        u8 in_buf[2];
        struct i2c_msg msgs[] = {
                {
-                        .addr = i2cbus->slave_addr,
+                        .addr = dvo->slave_addr,
                        .flags = 0,
                        .len = 1,
                        .buf = out_buf,
                },
                {
-                        .addr = i2cbus->slave_addr,
+                        .addr = dvo->slave_addr,
                        .flags = I2C_M_RD,
                        .len = 1,
                        .buf = in_buf,
@@ -208,10 +209,11 @@ static bool ch7017_read(struct intel_dvo_device *dvo, int addr, uint8_t *val)
 static bool ch7017_write(struct intel_dvo_device *dvo, int addr, uint8_t val)
 {
-        struct intel_i2c_chan *i2cbus = dvo->i2c_bus;
+        struct i2c_adapter *adapter = dvo->i2c_bus;
+        struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
        uint8_t out_buf[2];
        struct i2c_msg msg = {
-                .addr = i2cbus->slave_addr,
+                .addr = dvo->slave_addr,
                .flags = 0,
                .len = 2,
                .buf = out_buf,
@@ -228,8 +230,9 @@ static bool ch7017_write(struct intel_dvo_device *dvo, int addr, uint8_t val)
 /** Probes for a CH7017 on the given bus and slave address. */
 static bool ch7017_init(struct intel_dvo_device *dvo,
-                        struct intel_i2c_chan *i2cbus)
+                        struct i2c_adapter *adapter)
 {
+        struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
        struct ch7017_priv *priv;
        uint8_t val;
@@ -237,8 +240,7 @@ static bool ch7017_init(struct intel_dvo_device *dvo,
        if (priv == NULL)
                return false;
-        dvo->i2c_bus = i2cbus;
+        dvo->i2c_bus = adapter;
-        dvo->i2c_bus->slave_addr = dvo->slave_addr;
        dvo->dev_priv = priv;
        if (!ch7017_read(dvo, CH7017_DEVICE_ID, &val))
@@ -248,7 +250,7 @@ static bool ch7017_init(struct intel_dvo_device *dvo,
            val != CH7018_DEVICE_ID_VALUE &&
            val != CH7019_DEVICE_ID_VALUE) {
                DRM_DEBUG("ch701x not detected, got %d: from %s Slave %d.\n",
-                          val, i2cbus->adapter.name,i2cbus->slave_addr);
+                          val, i2cbus->adapter.name,dvo->slave_addr);
                goto fail;
        }
diff --git a/drivers/gpu/drm/i915/dvo_ch7xxx.c b/drivers/gpu/drm/i915/dvo_ch7xxx.c
index d2fd95dbd034..a9b896289680 100644
--- a/drivers/gpu/drm/i915/dvo_ch7xxx.c
+++ b/drivers/gpu/drm/i915/dvo_ch7xxx.c
@@ -123,19 +123,20 @@ static char *ch7xxx_get_id(uint8_t vid)
 static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
 {
        struct ch7xxx_priv *ch7xxx= dvo->dev_priv;
-        struct intel_i2c_chan *i2cbus = dvo->i2c_bus;
+        struct i2c_adapter *adapter = dvo->i2c_bus;
+        struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
        u8 out_buf[2];
        u8 in_buf[2];
        struct i2c_msg msgs[] = {
                {
-                        .addr = i2cbus->slave_addr,
+                        .addr = dvo->slave_addr,
                        .flags = 0,
                        .len = 1,
                        .buf = out_buf,
                },
                {
-                        .addr = i2cbus->slave_addr,
+                        .addr = dvo->slave_addr,
                        .flags = I2C_M_RD,
                        .len = 1,
                        .buf = in_buf,
@@ -152,7 +153,7 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
        if (!ch7xxx->quiet) {
                DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n",
-                          addr, i2cbus->adapter.name, i2cbus->slave_addr);
+                          addr, i2cbus->adapter.name, dvo->slave_addr);
        }
        return false;
 }
@@ -161,10 +162,11 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
 static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
 {
        struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
-        struct intel_i2c_chan *i2cbus = dvo->i2c_bus;
+        struct i2c_adapter *adapter = dvo->i2c_bus;
+        struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
        uint8_t out_buf[2];
        struct i2c_msg msg = {
-                .addr = i2cbus->slave_addr,
+                .addr = dvo->slave_addr,
                .flags = 0,
                .len = 2,
                .buf = out_buf,
@@ -178,14 +180,14 @@ static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
        if (!ch7xxx->quiet) {
                DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n",
-                          addr, i2cbus->adapter.name, i2cbus->slave_addr);
+                          addr, i2cbus->adapter.name, dvo->slave_addr);
        }
        return false;
 }
 static bool ch7xxx_init(struct intel_dvo_device *dvo,
-                        struct intel_i2c_chan *i2cbus)
+                        struct i2c_adapter *adapter)
 {
        /* this will detect the CH7xxx chip on the specified i2c bus */
        struct ch7xxx_priv *ch7xxx;
@@ -196,8 +198,7 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo,
        if (ch7xxx == NULL)
                return false;
-        dvo->i2c_bus = i2cbus;
+        dvo->i2c_bus = adapter;
-        dvo->i2c_bus->slave_addr = dvo->slave_addr;
        dvo->dev_priv = ch7xxx;
        ch7xxx->quiet = true;
@@ -207,7 +208,7 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo,
        name = ch7xxx_get_id(vendor);
        if (!name) {
                DRM_DEBUG("ch7xxx not detected; got 0x%02x from %s slave %d.\n",
-                          vendor, i2cbus->adapter.name, i2cbus->slave_addr);
+                          vendor, adapter->name, dvo->slave_addr);
                goto out;
        }
@@ -217,7 +218,7 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo,
        if (device != CH7xxx_DID) {
                DRM_DEBUG("ch7xxx not detected; got 0x%02x from %s slave %d.\n",
-                          vendor, i2cbus->adapter.name, i2cbus->slave_addr);
+                          vendor, adapter->name, dvo->slave_addr);
                goto out;
        }
diff --git a/drivers/gpu/drm/i915/dvo_ivch.c b/drivers/gpu/drm/i915/dvo_ivch.c
index 0c8d375e8e37..aa176f9921fe 100644
--- a/drivers/gpu/drm/i915/dvo_ivch.c
+++ b/drivers/gpu/drm/i915/dvo_ivch.c
@@ -169,13 +169,14 @@ static void ivch_dump_regs(struct intel_dvo_device *dvo);
 static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
 {
        struct ivch_priv *priv = dvo->dev_priv;
-        struct intel_i2c_chan *i2cbus = dvo->i2c_bus;
+        struct i2c_adapter *adapter = dvo->i2c_bus;
+        struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
        u8 out_buf[1];
        u8 in_buf[2];
        struct i2c_msg msgs[] = {
                {
-                        .addr = i2cbus->slave_addr,
+                        .addr = dvo->slave_addr,
                        .flags = I2C_M_RD,
                        .len = 0,
                },
@@ -186,7 +187,7 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
                        .buf = out_buf,
                },
                {
-                        .addr = i2cbus->slave_addr,
+                        .addr = dvo->slave_addr,
                        .flags = I2C_M_RD | I2C_M_NOSTART,
                        .len = 2,
                        .buf = in_buf,
@@ -202,7 +203,7 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
        if (!priv->quiet) {
                DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n",
-                          addr, i2cbus->adapter.name, i2cbus->slave_addr);
+                          addr, i2cbus->adapter.name, dvo->slave_addr);
        }
        return false;
 }
@@ -211,10 +212,11 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
 static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
 {
        struct ivch_priv *priv = dvo->dev_priv;
-        struct intel_i2c_chan *i2cbus = dvo->i2c_bus;
+        struct i2c_adapter *adapter = dvo->i2c_bus;
+        struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
        u8 out_buf[3];
        struct i2c_msg msg = {
-                .addr = i2cbus->slave_addr,
+                .addr = dvo->slave_addr,
                .flags = 0,
                .len = 3,
                .buf = out_buf,
@@ -229,7 +231,7 @@ static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
        if (!priv->quiet) {
                DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n",
-                          addr, i2cbus->adapter.name, i2cbus->slave_addr);
+                          addr, i2cbus->adapter.name, dvo->slave_addr);
        }
        return false;
@@ -237,7 +239,7 @@ static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
 /** Probes the given bus and slave address for an ivch */
 static bool ivch_init(struct intel_dvo_device *dvo,
-                      struct intel_i2c_chan *i2cbus)
+                      struct i2c_adapter *adapter)
 {
        struct ivch_priv *priv;
        uint16_t temp;
@@ -246,8 +248,7 @@ static bool ivch_init(struct intel_dvo_device *dvo,
        if (priv == NULL)
                return false;
-        dvo->i2c_bus = i2cbus;
+        dvo->i2c_bus = adapter;
-        dvo->i2c_bus->slave_addr = dvo->slave_addr;
        dvo->dev_priv = priv;
        priv->quiet = true;
diff --git a/drivers/gpu/drm/i915/dvo_sil164.c b/drivers/gpu/drm/i915/dvo_sil164.c
index 033a4bb070b2..e1c1f7341e5c 100644
--- a/drivers/gpu/drm/i915/dvo_sil164.c
+++ b/drivers/gpu/drm/i915/dvo_sil164.c
@@ -76,19 +76,20 @@ struct sil164_priv {
 static bool sil164_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
 {
        struct sil164_priv *sil = dvo->dev_priv;
-        struct intel_i2c_chan *i2cbus = dvo->i2c_bus;
+        struct i2c_adapter *adapter = dvo->i2c_bus;
+        struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
        u8 out_buf[2];
        u8 in_buf[2];
        struct i2c_msg msgs[] = {
                {
-                        .addr = i2cbus->slave_addr,
+                        .addr = dvo->slave_addr,
                        .flags = 0,
                        .len = 1,
                        .buf = out_buf,
                },
                {
-                        .addr = i2cbus->slave_addr,
+                        .addr = dvo->slave_addr,
                        .flags = I2C_M_RD,
                        .len = 1,
                        .buf = in_buf,
@@ -105,7 +106,7 @@ static bool sil164_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
        if (!sil->quiet) {
                DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n",
-                          addr, i2cbus->adapter.name, i2cbus->slave_addr);
+                          addr, i2cbus->adapter.name, dvo->slave_addr);
        }
        return false;
 }
@@ -113,10 +114,11 @@ static bool sil164_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
 static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
 {
        struct sil164_priv *sil= dvo->dev_priv;
-        struct intel_i2c_chan *i2cbus = dvo->i2c_bus;
+        struct i2c_adapter *adapter = dvo->i2c_bus;
+        struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
        uint8_t out_buf[2];
        struct i2c_msg msg = {
-                .addr = i2cbus->slave_addr,
+                .addr = dvo->slave_addr,
                .flags = 0,
                .len = 2,
                .buf = out_buf,
@@ -130,7 +132,7 @@ static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
        if (!sil->quiet) {
                DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n",
-                          addr, i2cbus->adapter.name, i2cbus->slave_addr);
+                          addr, i2cbus->adapter.name, dvo->slave_addr);
        }
        return false;
@@ -138,7 +140,7 @@ static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
 /* Silicon Image 164 driver for chip on i2c bus */
 static bool sil164_init(struct intel_dvo_device *dvo,
-                        struct intel_i2c_chan *i2cbus)
+                        struct i2c_adapter *adapter)
 {
        /* this will detect the SIL164 chip on the specified i2c bus */
        struct sil164_priv *sil;
@@ -148,8 +150,7 @@ static bool sil164_init(struct intel_dvo_device *dvo,
        if (sil == NULL)
                return false;
-        dvo->i2c_bus = i2cbus;
+        dvo->i2c_bus = adapter;
-        dvo->i2c_bus->slave_addr = dvo->slave_addr;
        dvo->dev_priv = sil;
        sil->quiet = true;
@@ -158,7 +159,7 @@ static bool sil164_init(struct intel_dvo_device *dvo,
        if (ch != (SIL164_VID & 0xff)) {
                DRM_DEBUG("sil164 not detected got %d: from %s Slave %d.\n",
-                          ch, i2cbus->adapter.name, i2cbus->slave_addr);
+                          ch, adapter->name, dvo->slave_addr);
                goto out;
        }
@@ -167,7 +168,7 @@ static bool sil164_init(struct intel_dvo_device *dvo,
        if (ch != (SIL164_DID & 0xff)) {
                DRM_DEBUG("sil164 not detected got %d: from %s Slave %d.\n",
-                          ch, i2cbus->adapter.name, i2cbus->slave_addr);
+                          ch, adapter->name, dvo->slave_addr);
                goto out;
        }
        sil->quiet = false;
diff --git a/drivers/gpu/drm/i915/dvo_tfp410.c b/drivers/gpu/drm/i915/dvo_tfp410.c
index 207fda806ebf..9ecc907384ec 100644
--- a/drivers/gpu/drm/i915/dvo_tfp410.c
+++ b/drivers/gpu/drm/i915/dvo_tfp410.c
@@ -101,19 +101,20 @@ struct tfp410_priv {
 static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
 {
        struct tfp410_priv *tfp = dvo->dev_priv;
-        struct intel_i2c_chan *i2cbus = dvo->i2c_bus;
+        struct i2c_adapter *adapter = dvo->i2c_bus;
+        struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
        u8 out_buf[2];
        u8 in_buf[2];
        struct i2c_msg msgs[] = {
                {
-                        .addr = i2cbus->slave_addr,
+                        .addr = dvo->slave_addr,
                        .flags = 0,
                        .len = 1,
                        .buf = out_buf,
                },
                {
-                        .addr = i2cbus->slave_addr,
+                        .addr = dvo->slave_addr,
                        .flags = I2C_M_RD,
                        .len = 1,
                        .buf = in_buf,
@@ -130,7 +131,7 @@ static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
        if (!tfp->quiet) {
                DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n",
-                          addr, i2cbus->adapter.name, i2cbus->slave_addr);
+                          addr, i2cbus->adapter.name, dvo->slave_addr);
        }
        return false;
 }
@@ -138,10 +139,11 @@ static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
 static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
 {
        struct tfp410_priv *tfp = dvo->dev_priv;
-        struct intel_i2c_chan *i2cbus = dvo->i2c_bus;
+        struct i2c_adapter *adapter = dvo->i2c_bus;
+        struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
        uint8_t out_buf[2];
        struct i2c_msg msg = {
-                .addr = i2cbus->slave_addr,
+                .addr = dvo->slave_addr,
                .flags = 0,
                .len = 2,
                .buf = out_buf,
@@ -155,7 +157,7 @@ static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
        if (!tfp->quiet) {
                DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n",
-                          addr, i2cbus->adapter.name, i2cbus->slave_addr);
+                          addr, i2cbus->adapter.name, dvo->slave_addr);
        }
        return false;
@@ -174,7 +176,7 @@ static int tfp410_getid(struct intel_dvo_device *dvo, int addr)
 /* Ti TFP410 driver for chip on i2c bus */
 static bool tfp410_init(struct intel_dvo_device *dvo,
-                        struct intel_i2c_chan *i2cbus)
+                        struct i2c_adapter *adapter)
 {
        /* this will detect the tfp410 chip on the specified i2c bus */
        struct tfp410_priv *tfp;
@@ -184,20 +186,19 @@ static bool tfp410_init(struct intel_dvo_device *dvo,
        if (tfp == NULL)
                return false;
-        dvo->i2c_bus = i2cbus;
+        dvo->i2c_bus = adapter;
-        dvo->i2c_bus->slave_addr = dvo->slave_addr;
        dvo->dev_priv = tfp;
        tfp->quiet = true;
        if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) {
                DRM_DEBUG("tfp410 not detected got VID %X: from %s Slave %d.\n",
-                          id, i2cbus->adapter.name, i2cbus->slave_addr);
+                          id, adapter->name, dvo->slave_addr);
                goto out;
        }
        if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) {
                DRM_DEBUG("tfp410 not detected got DID %X: from %s Slave %d.\n",
-                          id, i2cbus->adapter.name, i2cbus->slave_addr);
+                          id, adapter->name, dvo->slave_addr);
                goto out;
        }
        tfp->quiet = false;
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index f112c769d533..8c4783180bf6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -846,7 +846,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
                return 0;
        }
-        printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr);
+        DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
        dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
@@ -885,8 +885,8 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
 * some RAM for the framebuffer at early boot.  This code figures out
 * how much was set aside so we can use it for our own purposes.
 */
-static int i915_probe_agp(struct drm_device *dev, unsigned long *aperture_size,
+static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
-                          unsigned long *preallocated_size)
+                          uint32_t *preallocated_size)
 {
        struct pci_dev *bridge_dev;
        u16 tmp = 0;
@@ -984,10 +984,11 @@ static int i915_probe_agp(struct drm_device *dev, unsigned long *aperture_size,
        return 0;
 }
-static int i915_load_modeset_init(struct drm_device *dev)
+static int i915_load_modeset_init(struct drm_device *dev,
+                                  unsigned long prealloc_size,
+                                  unsigned long agp_size)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
-        unsigned long agp_size, prealloc_size;
        int fb_bar = IS_I9XX(dev) ? 2 : 0;
        int ret = 0;
@@ -1002,10 +1003,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
        if (IS_I965G(dev) || IS_G33(dev))
                dev_priv->cursor_needs_physical = false;
-        ret = i915_probe_agp(dev, &agp_size, &prealloc_size);
-        if (ret)
-                goto out;
        /* Basic memrange allocator for stolen space (aka vram) */
        drm_mm_init(&dev_priv->vram, 0, prealloc_size);
@@ -1082,6 +1079,44 @@ void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
        master->driver_priv = NULL;
 }
+static void i915_get_mem_freq(struct drm_device *dev)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        u32 tmp;
+        if (!IS_IGD(dev))
+                return;
+        tmp = I915_READ(CLKCFG);
+        switch (tmp & CLKCFG_FSB_MASK) {
+        case CLKCFG_FSB_533:
+                dev_priv->fsb_freq = 533; /* 133*4 */
+                break;
+        case CLKCFG_FSB_800:
+                dev_priv->fsb_freq = 800; /* 200*4 */
+                break;
+        case CLKCFG_FSB_667:
+                dev_priv->fsb_freq =  667; /* 167*4 */
+                break;
+        case CLKCFG_FSB_400:
+                dev_priv->fsb_freq = 400; /* 100*4 */
+                break;
+        }
+        switch (tmp & CLKCFG_MEM_MASK) {
+        case CLKCFG_MEM_533:
+                dev_priv->mem_freq = 533;
+                break;
+        case CLKCFG_MEM_667:
+                dev_priv->mem_freq = 667;
+                break;
+        case CLKCFG_MEM_800:
+                dev_priv->mem_freq = 800;
+                break;
+        }
+}
 /**
 * i915_driver_load - setup chip and create an initial config
 * @dev: DRM device
@@ -1098,6 +1133,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
        struct drm_i915_private *dev_priv = dev->dev_private;
        resource_size_t base, size;
        int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
+        uint32_t agp_size, prealloc_size;
        /* i915 has 4 more counters */
        dev->counters += 4;
@@ -1146,9 +1182,22 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
                         "performance may suffer.\n");
        }
+        ret = i915_probe_agp(dev, &agp_size, &prealloc_size);
+        if (ret)
+                goto out_iomapfree;
        /* enable GEM by default */
        dev_priv->has_gem = 1;
+        if (prealloc_size > agp_size * 3 / 4) {
+                DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
+                          "memory stolen.\n",
+                          prealloc_size / 1024, agp_size / 1024);
+                DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
+                          "updating the BIOS to fix).\n");
+                dev_priv->has_gem = 0;
+        }
        dev->driver->get_vblank_counter = i915_get_vblank_counter;
        dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
        if (IS_G4X(dev) || IS_IGDNG(dev)) {
@@ -1165,6 +1214,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
                        goto out_iomapfree;
        }
+        i915_get_mem_freq(dev);
        /* On the 945G/GM, the chipset reports the MSI capability on the
         * integrated graphics even though the support isn't actually there
         * according to the published specs.  It doesn't appear to function
@@ -1180,6 +1231,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
                pci_enable_msi(dev->pdev);
        spin_lock_init(&dev_priv->user_irq_lock);
+        spin_lock_init(&dev_priv->error_lock);
        dev_priv->user_irq_refcount = 0;
        ret = drm_vblank_init(dev, I915_NUM_PIPE);
@@ -1190,7 +1242,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
        }
        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                ret = i915_load_modeset_init(dev);
+                ret = i915_load_modeset_init(dev, prealloc_size, agp_size);
                if (ret < 0) {
                        DRM_ERROR("failed to init modeset\n");
                        goto out_rmmap;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 98560e1e899a..fc4b68aa2d05 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -35,6 +35,7 @@
 #include "drm_pciids.h"
 #include <linux/console.h>
+#include "drm_crtc_helper.h"
 static unsigned int i915_modeset = -1;
 module_param_named(modeset, i915_modeset, int, 0400);
@@ -57,8 +58,8 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
        struct drm_i915_private *dev_priv = dev->dev_private;
        if (!dev || !dev_priv) {
-                printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
+                DRM_ERROR("dev: %p, dev_priv: %p\n", dev, dev_priv);
-                printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
+                DRM_ERROR("DRM not initialized, aborting suspend.\n");
                return -ENODEV;
        }
@@ -67,8 +68,6 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
        pci_save_state(dev->pdev);
-        i915_save_state(dev);
        /* If KMS is active, we do the leavevt stuff here */
        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
                if (i915_gem_idle(dev))
@@ -77,6 +76,8 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
                drm_irq_uninstall(dev);
        }
+        i915_save_state(dev);
        intel_opregion_free(dev, 1);
        if (state.event == PM_EVENT_SUSPEND) {
@@ -115,6 +116,10 @@ static int i915_resume(struct drm_device *dev)
                drm_irq_install(dev);
        }
+        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+                /* Resume the modeset for every activated CRTC */
+                drm_helper_resume_force_mode(dev);
+        }
        return ret;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7a84f04e8439..d08752875885 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -133,6 +133,22 @@ struct sdvo_device_mapping {
        u8 initialized;
 };
+struct drm_i915_error_state {
+        u32 eir;
+        u32 pgtbl_er;
+        u32 pipeastat;
+        u32 pipebstat;
+        u32 ipeir;
+        u32 ipehr;
+        u32 instdone;
+        u32 acthd;
+        u32 instpm;
+        u32 instps;
+        u32 instdone1;
+        u32 seqno;
+        struct timeval time;
+};
 typedef struct drm_i915_private {
        struct drm_device *dev;
@@ -209,6 +225,11 @@ typedef struct drm_i915_private {
        int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
        int num_fence_regs; /* 8 on pre-965, 16 otherwise */
+        unsigned int fsb_freq, mem_freq;
+        spinlock_t error_lock;
+        struct drm_i915_error_state *first_error;
        /* Register state */
        u8 saveLBB;
        u32 saveDSPACNTR;
@@ -306,6 +327,17 @@ typedef struct drm_i915_private {
        u32 saveCURBPOS;
        u32 saveCURBBASE;
        u32 saveCURSIZE;
+        u32 saveDP_B;
+        u32 saveDP_C;
+        u32 saveDP_D;
+        u32 savePIPEA_GMCH_DATA_M;
+        u32 savePIPEB_GMCH_DATA_M;
+        u32 savePIPEA_GMCH_DATA_N;
+        u32 savePIPEB_GMCH_DATA_N;
+        u32 savePIPEA_DP_LINK_M;
+        u32 savePIPEB_DP_LINK_M;
+        u32 savePIPEA_DP_LINK_N;
+        u32 savePIPEB_DP_LINK_N;
        struct {
                struct drm_mm gtt_space;
@@ -457,9 +489,6 @@ struct drm_i915_gem_object {
         */
        int fence_reg;
-        /** Boolean whether this object has a valid gtt offset. */
-        int gtt_bound;
        /** How many users have pinned this object in GTT space */
        int pin_count;
@@ -644,6 +673,7 @@ void i915_gem_free_object(struct drm_gem_object *obj);
 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
 void i915_gem_object_unpin(struct drm_gem_object *obj);
 int i915_gem_object_unbind(struct drm_gem_object *obj);
+void i915_gem_release_mmap(struct drm_gem_object *obj);
 void i915_gem_lastclose(struct drm_device *dev);
 uint32_t i915_get_gem_seqno(struct drm_device *dev);
 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
@@ -857,7 +887,10 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
                                                      IS_I915GM(dev)))
 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_IGDNG(dev))
+#define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_IGDNG(dev))
 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
+/* dsparb controlled by hw only */
+#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fd2b8bdffe3f..5bf420378b6d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1006,7 +1006,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
        mutex_lock(&dev->struct_mutex);
 #if WATCH_BUF
-        DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
+        DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
                 obj, obj->size, read_domains, write_domain);
 #endif
        if (read_domains & I915_GEM_DOMAIN_GTT) {
@@ -1050,7 +1050,7 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
        }
 #if WATCH_BUF
-        DRM_INFO("%s: sw_finish %d (%p %d)\n",
+        DRM_INFO("%s: sw_finish %d (%p %zd)\n",
                 __func__, args->handle, obj, obj->size);
 #endif
        obj_priv = obj->driver_private;
@@ -1252,6 +1252,31 @@ out_free_list:
        return ret;
 }
+/**
+ * i915_gem_release_mmap - remove physical page mappings
+ * @obj: obj in question
+ *
+ * Preserve the reservation of the mmaping with the DRM core code, but
+ * relinquish ownership of the pages back to the system.
+ *
+ * It is vital that we remove the page mapping if we have mapped a tiled
+ * object through the GTT and then lose the fence register due to
+ * resource pressure. Similarly if the object has been moved out of the
+ * aperture, than pages mapped into userspace must be revoked. Removing the
+ * mapping will then trigger a page fault on the next user access, allowing
+ * fixup by i915_gem_fault().
+ */
+void
+i915_gem_release_mmap(struct drm_gem_object *obj)
+{
+        struct drm_device *dev = obj->dev;
+        struct drm_i915_gem_object *obj_priv = obj->driver_private;
+        if (dev->dev_mapping)
+                unmap_mapping_range(dev->dev_mapping,
+                                    obj_priv->mmap_offset, obj->size, 1);
+}
 static void
 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
 {
@@ -1861,7 +1886,6 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
 {
        struct drm_device *dev = obj->dev;
        struct drm_i915_gem_object *obj_priv = obj->driver_private;
-        loff_t offset;
        int ret = 0;
 #if WATCH_BUF
@@ -1898,9 +1922,7 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
        BUG_ON(obj_priv->active);
        /* blow away mappings if mapped through GTT */
-        offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT;
+        i915_gem_release_mmap(obj);
-        if (dev->dev_mapping)
-                unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1);
        if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
                i915_gem_clear_fence_reg(obj);
@@ -2222,7 +2244,6 @@ try_again:
        /* None available, try to steal one or wait for a user to finish */
        if (i == dev_priv->num_fence_regs) {
                uint32_t seqno = dev_priv->mm.next_gem_seqno;
-                loff_t offset;
                if (avail == 0)
                        return -ENOSPC;
@@ -2274,10 +2295,7 @@ try_again:
                 * Zap this virtual mapping so we can set up a fence again
                 * for this object next time we need it.
                 */
-                offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT;
+                i915_gem_release_mmap(reg->obj);
-                if (dev->dev_mapping)
-                        unmap_mapping_range(dev->dev_mapping, offset,
-                                            reg->obj->size, 1);
                old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
        }
@@ -2423,7 +2441,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
        }
 #if WATCH_BUF
-        DRM_INFO("Binding object of size %d at 0x%08x\n",
+        DRM_INFO("Binding object of size %zd at 0x%08x\n",
                 obj->size, obj_priv->gtt_offset);
 #endif
        ret = i915_gem_object_get_pages(obj);
@@ -4227,6 +4245,7 @@ i915_gem_lastclose(struct drm_device *dev)
 void
 i915_gem_load(struct drm_device *dev)
 {
+        int i;
        drm_i915_private_t *dev_priv = dev->dev_private;
        spin_lock_init(&dev_priv->mm.active_list_lock);
@@ -4246,6 +4265,18 @@ i915_gem_load(struct drm_device *dev)
        else
                dev_priv->num_fence_regs = 8;
+        /* Initialize fence registers to zero */
+        if (IS_I965G(dev)) {
+                for (i = 0; i < 16; i++)
+                        I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
+        } else {
+                for (i = 0; i < 8; i++)
+                        I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
+                if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
+                        for (i = 0; i < 8; i++)
+                                I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
+        }
        i915_gem_detect_bit_6_swizzle(dev);
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_debug.c b/drivers/gpu/drm/i915/i915_gem_debug.c
index 8d0b943e2c5a..e602614bd3f8 100644
--- a/drivers/gpu/drm/i915/i915_gem_debug.c
+++ b/drivers/gpu/drm/i915/i915_gem_debug.c
@@ -87,7 +87,7 @@ i915_gem_dump_object(struct drm_gem_object *obj, int len,
                        chunk_len = page_len - chunk;
                        if (chunk_len > 128)
                                chunk_len = 128;
-                        i915_gem_dump_page(obj_priv->page_list[page],
+                        i915_gem_dump_page(obj_priv->pages[page],
                                           chunk, chunk + chunk_len,
                                           obj_priv->gtt_offset +
                                           page * PAGE_SIZE,
@@ -143,7 +143,7 @@ i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle)
        uint32_t *backing_map = NULL;
        int bad_count = 0;
-        DRM_INFO("%s: checking coherency of object %p@0x%08x (%d, %dkb):\n",
+        DRM_INFO("%s: checking coherency of object %p@0x%08x (%d, %zdkb):\n",
                 __func__, obj, obj_priv->gtt_offset, handle,
                 obj->size / 1024);
@@ -157,7 +157,7 @@ i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle)
        for (page = 0; page < obj->size / PAGE_SIZE; page++) {
                int i;
-                backing_map = kmap_atomic(obj_priv->page_list[page], KM_USER0);
+                backing_map = kmap_atomic(obj_priv->pages[page], KM_USER0);
                if (backing_map == NULL) {
                        DRM_ERROR("failed to map backing page\n");
diff --git a/drivers/gpu/drm/i915/i915_gem_debugfs.c b/drivers/gpu/drm/i915/i915_gem_debugfs.c
index 28146e405e87..9a44bfcb8139 100644
--- a/drivers/gpu/drm/i915/i915_gem_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_gem_debugfs.c
@@ -75,11 +75,10 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data)
        case ACTIVE_LIST:
                seq_printf(m, "Active:\n");
                lock = &dev_priv->mm.active_list_lock;
-                spin_lock(lock);
                head = &dev_priv->mm.active_list;
                break;
        case INACTIVE_LIST:
-                seq_printf(m, "Inctive:\n");
+                seq_printf(m, "Inactive:\n");
                head = &dev_priv->mm.inactive_list;
                break;
        case FLUSHING_LIST:
@@ -91,6 +90,8 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data)
                return 0;
        }
+        if (lock)
+                spin_lock(lock);
        list_for_each_entry(obj_priv, head, list)
        {
                struct drm_gem_object *obj = obj_priv->obj;
@@ -104,7 +105,10 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data)
                if (obj->name)
                        seq_printf(m, " (name: %d)", obj->name);
                if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
-                        seq_printf(m, " (fence: %d)\n", obj_priv->fence_reg);
+                        seq_printf(m, " (fence: %d)", obj_priv->fence_reg);
+                if (obj_priv->gtt_space != NULL)
+                        seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset);
                seq_printf(m, "\n");
        }
@@ -323,6 +327,39 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data)
        return 0;
 }
+static int i915_error_state(struct seq_file *m, void *unused)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        struct drm_i915_error_state *error;
+        unsigned long flags;
+        spin_lock_irqsave(&dev_priv->error_lock, flags);
+        if (!dev_priv->first_error) {
+                seq_printf(m, "no error state collected\n");
+                goto out;
+        }
+        error = dev_priv->first_error;
+        seq_printf(m, "EIR: 0x%08x\n", error->eir);
+        seq_printf(m, "  PGTBL_ER: 0x%08x\n", error->pgtbl_er);
+        seq_printf(m, "  INSTPM: 0x%08x\n", error->instpm);
+        seq_printf(m, "  IPEIR: 0x%08x\n", error->ipeir);
+        seq_printf(m, "  IPEHR: 0x%08x\n", error->ipehr);
+        seq_printf(m, "  INSTDONE: 0x%08x\n", error->instdone);
+        seq_printf(m, "  ACTHD: 0x%08x\n", error->acthd);
+        if (IS_I965G(dev)) {
+                seq_printf(m, "  INSTPS: 0x%08x\n", error->instps);
+                seq_printf(m, "  INSTDONE1: 0x%08x\n", error->instdone1);
+        }
+out:
+        spin_unlock_irqrestore(&dev_priv->error_lock, flags);
+        return 0;
+}
 static struct drm_info_list i915_gem_debugfs_list[] = {
        {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
@@ -336,6 +373,7 @@ static struct drm_info_list i915_gem_debugfs_list[] = {
        {"i915_ringbuffer_data", i915_ringbuffer_data, 0},
        {"i915_ringbuffer_info", i915_ringbuffer_info, 0},
        {"i915_batchbuffers", i915_batchbuffer_info, 0},
+        {"i915_error_state", i915_error_state, 0},
 };
 #define I915_GEM_DEBUGFS_ENTRIES ARRAY_SIZE(i915_gem_debugfs_list)
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 5c1ceec49f5b..a2d527b22ec4 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -114,11 +114,13 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
        mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
        /* If ACPI doesn't have it, assume we need to allocate it ourselves */
+#ifdef CONFIG_PNP
        if (mchbar_addr &&
            pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
                ret = 0;
                goto out_put;
        }
+#endif
        /* Get some space for it */
        ret = pci_bus_alloc_resource(bridge_dev->bus, &dev_priv->mch_res,
@@ -519,6 +521,12 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
                        goto err;
                }
+                /* If we've changed tiling, GTT-mappings of the object
+                 * need to re-fault to ensure that the correct fence register
+                 * setup is in place.
+                 */
+                i915_gem_release_mmap(obj);
                obj_priv->tiling_mode = args->tiling_mode;
                obj_priv->stride = args->stride;
        }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b86b7b7130c6..7ba23a69a0c0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -26,6 +26,7 @@
 *
 */
+#include <linux/sysrq.h>
 #include "drmP.h"
 #include "drm.h"
 #include "i915_drm.h"
@@ -41,9 +42,10 @@
 * we leave them always unmasked in IMR and then control enabling them through
 * PIPESTAT alone.
 */
-#define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
+#define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT |                 \
-                                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |  \
+                                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
-                                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
+                                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
+                                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 /** Interrupts that we mask and unmask at runtime. */
 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
@@ -232,7 +234,17 @@ static void i915_hotplug_work_func(struct work_struct *work)
        drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
                                                    hotplug_work);
        struct drm_device *dev = dev_priv->dev;
+        struct drm_mode_config *mode_config = &dev->mode_config;
+        struct drm_connector *connector;
+        if (mode_config->num_connector) {
+                list_for_each_entry(connector, &mode_config->connector_list, head) {
+                        struct intel_output *intel_output = to_intel_output(connector);
+        
+                        if (intel_output->hot_plug)
+                                (*intel_output->hot_plug) (intel_output);
+                }
+        }
        /* Just fire off a uevent and let userspace tell us what to do */
        drm_sysfs_hotplug_event(dev);
 }
@@ -278,6 +290,47 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
        return ret;
 }
+static void i915_capture_error_state(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct drm_i915_error_state *error;
+        unsigned long flags;
+        spin_lock_irqsave(&dev_priv->error_lock, flags);
+        if (dev_priv->first_error)
+                goto out;
+        error = kmalloc(sizeof(*error), GFP_ATOMIC);
+        if (!error) {
+                DRM_DEBUG("out ot memory, not capturing error state\n");
+                goto out;
+        }
+        error->eir = I915_READ(EIR);
+        error->pgtbl_er = I915_READ(PGTBL_ER);
+        error->pipeastat = I915_READ(PIPEASTAT);
+        error->pipebstat = I915_READ(PIPEBSTAT);
+        error->instpm = I915_READ(INSTPM);
+        if (!IS_I965G(dev)) {
+                error->ipeir = I915_READ(IPEIR);
+                error->ipehr = I915_READ(IPEHR);
+                error->instdone = I915_READ(INSTDONE);
+                error->acthd = I915_READ(ACTHD);
+        } else {
+                error->ipeir = I915_READ(IPEIR_I965);
+                error->ipehr = I915_READ(IPEHR_I965);
+                error->instdone = I915_READ(INSTDONE_I965);
+                error->instps = I915_READ(INSTPS);
+                error->instdone1 = I915_READ(INSTDONE1);
+                error->acthd = I915_READ(ACTHD_I965);
+        }
+        dev_priv->first_error = error;
+out:
+        spin_unlock_irqrestore(&dev_priv->error_lock, flags);
+}
 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 {
        struct drm_device *dev = (struct drm_device *) arg;
@@ -323,11 +376,15 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
                 * Clear the PIPE(A|B)STAT regs before the IIR
                 */
                if (pipea_stats & 0x8000ffff) {
+                        if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
+                                DRM_DEBUG("pipe a underrun\n");
                        I915_WRITE(PIPEASTAT, pipea_stats);
                        irq_received = 1;
                }
                if (pipeb_stats & 0x8000ffff) {
+                        if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
+                                DRM_DEBUG("pipe b underrun\n");
                        I915_WRITE(PIPEBSTAT, pipeb_stats);
                        irq_received = 1;
                }
@@ -352,6 +409,80 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
                        I915_READ(PORT_HOTPLUG_STAT);
                }
+                if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) {
+                        u32 eir = I915_READ(EIR);
+                        i915_capture_error_state(dev);
+                        printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
+                               eir);
+                        if (eir & I915_ERROR_PAGE_TABLE) {
+                                u32 pgtbl_err = I915_READ(PGTBL_ER);
+                                printk(KERN_ERR "page table error\n");
+                                printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
+                                       pgtbl_err);
+                                I915_WRITE(PGTBL_ER, pgtbl_err);
+                                (void)I915_READ(PGTBL_ER);
+                        }
+                        if (eir & I915_ERROR_MEMORY_REFRESH) {
+                                printk(KERN_ERR "memory refresh error\n");
+                                printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
+                                       pipea_stats);
+                                printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
+                                       pipeb_stats);
+                                /* pipestat has already been acked */
+                        }
+                        if (eir & I915_ERROR_INSTRUCTION) {
+                                printk(KERN_ERR "instruction error\n");
+                                printk(KERN_ERR "  INSTPM: 0x%08x\n",
+                                       I915_READ(INSTPM));
+                                if (!IS_I965G(dev)) {
+                                        u32 ipeir = I915_READ(IPEIR);
+                                        printk(KERN_ERR "  IPEIR: 0x%08x\n",
+                                               I915_READ(IPEIR));
+                                        printk(KERN_ERR "  IPEHR: 0x%08x\n",
+                                                   I915_READ(IPEHR));
+                                        printk(KERN_ERR "  INSTDONE: 0x%08x\n",
+                                                   I915_READ(INSTDONE));
+                                        printk(KERN_ERR "  ACTHD: 0x%08x\n",
+                                                   I915_READ(ACTHD));
+                                        I915_WRITE(IPEIR, ipeir);
+                                        (void)I915_READ(IPEIR);
+                                } else {
+                                        u32 ipeir = I915_READ(IPEIR_I965);
+                                        printk(KERN_ERR "  IPEIR: 0x%08x\n",
+                                               I915_READ(IPEIR_I965));
+                                        printk(KERN_ERR "  IPEHR: 0x%08x\n",
+                                               I915_READ(IPEHR_I965));
+                                        printk(KERN_ERR "  INSTDONE: 0x%08x\n",
+                                               I915_READ(INSTDONE_I965));
+                                        printk(KERN_ERR "  INSTPS: 0x%08x\n",
+                                               I915_READ(INSTPS));
+                                        printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
+                                               I915_READ(INSTDONE1));
+                                        printk(KERN_ERR "  ACTHD: 0x%08x\n",
+                                               I915_READ(ACTHD_I965));
+                                        I915_WRITE(IPEIR_I965, ipeir);
+                                        (void)I915_READ(IPEIR_I965);
+                                }
+                        }
+                        I915_WRITE(EIR, eir);
+                        (void)I915_READ(EIR);
+                        eir = I915_READ(EIR);
+                        if (eir) {
+                                /*
+                                 * some errors might have become stuck,
+                                 * mask them.
+                                 */
+                                DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
+                                I915_WRITE(EMR, I915_READ(EMR) | eir);
+                                I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
+                        }
+                }
                I915_WRITE(IIR, iir);
                new_iir = I915_READ(IIR); /* Flush posted writes */
@@ -722,6 +853,7 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
 {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
        u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
+        u32 error_mask;
        DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
@@ -758,6 +890,21 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
                i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
        }
+        /*
+         * Enable some error detection, note the instruction error mask
+         * bit is reserved, so we leave it masked.
+         */
+        if (IS_G4X(dev)) {
+                error_mask = ~(GM45_ERROR_PAGE_TABLE |
+                               GM45_ERROR_MEM_PRIV |
+                               GM45_ERROR_CP_PRIV |
+                               I915_ERROR_MEMORY_REFRESH);
+        } else {
+                error_mask = ~(I915_ERROR_PAGE_TABLE |
+                               I915_ERROR_MEMORY_REFRESH);
+        }
+        I915_WRITE(EMR, error_mask);
        /* Disable pipe interrupt enables, clear pending pipe status */
        I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
        I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6237a0b1133..6c0858484094 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -206,6 +206,7 @@
 /*
 * Instruction and interrupt control regs
 */
+#define PGTBL_ER        0x02024
 #define PRB0_TAIL       0x02030
 #define PRB0_HEAD       0x02034
 #define PRB0_START      0x02038
@@ -226,11 +227,18 @@
 #define PRB1_HEAD       0x02044 /* 915+ only */
 #define PRB1_START      0x02048 /* 915+ only */
 #define PRB1_CTL        0x0204c /* 915+ only */
+#define IPEIR_I965      0x02064
+#define IPEHR_I965      0x02068
+#define INSTDONE_I965   0x0206c
+#define INSTPS          0x02070 /* 965+ only */
+#define INSTDONE1       0x0207c /* 965+ only */
 #define ACTHD_I965      0x02074
 #define HWS_PGA         0x02080
 #define HWS_ADDRESS_MASK        0xfffff000
 #define HWS_START_ADDRESS_SHIFT 4
 #define IPEIR           0x02088
+#define IPEHR           0x0208c
+#define INSTDONE        0x02090
 #define NOPID           0x02094
 #define HWSTAM          0x02098
 #define SCPD0           0x0209c /* 915+ only */
@@ -258,10 +266,22 @@
 #define EIR             0x020b0
 #define EMR             0x020b4
 #define ESR             0x020b8
+#define   GM45_ERROR_PAGE_TABLE                         (1<<5)
+#define   GM45_ERROR_MEM_PRIV                           (1<<4)
+#define   I915_ERROR_PAGE_TABLE                         (1<<4)
+#define   GM45_ERROR_CP_PRIV                            (1<<3)
+#define   I915_ERROR_MEMORY_REFRESH                     (1<<1)
+#define   I915_ERROR_INSTRUCTION                        (1<<0)
 #define INSTPM          0x020c0
 #define ACTHD           0x020c8
 #define FW_BLC          0x020d8
+#define FW_BLC2         0x020dc
 #define FW_BLC_SELF     0x020e0 /* 915+ only */
+#define   FW_BLC_SELF_EN (1<<15)
+#define MM_BURST_LENGTH     0x00700000
+#define MM_FIFO_WATERMARK   0x0001F000
+#define LM_BURST_LENGTH     0x00000700
+#define LM_FIFO_WATERMARK   0x0000001F
 #define MI_ARB_STATE    0x020e4 /* 915+ only */
 #define CACHE_MODE_0    0x02120 /* 915+ only */
 #define   CM0_MASK_SHIFT          16
@@ -569,6 +589,23 @@
 #define C0DRB3                  0x10206
 #define C1DRB3                  0x10606
+/* Clocking configuration register */
+#define CLKCFG                  0x10c00
+#define CLKCFG_FSB_400                                  (5 << 0)        /* hrawclk 100 */
+#define CLKCFG_FSB_533                                  (1 << 0)        /* hrawclk 133 */
+#define CLKCFG_FSB_667                                  (3 << 0)        /* hrawclk 166 */
+#define CLKCFG_FSB_800                                  (2 << 0)        /* hrawclk 200 */
+#define CLKCFG_FSB_1067                                 (6 << 0)        /* hrawclk 266 */
+#define CLKCFG_FSB_1333                                 (7 << 0)        /* hrawclk 333 */
+/* Note, below two are guess */
+#define CLKCFG_FSB_1600                                 (4 << 0)        /* hrawclk 400 */
+#define CLKCFG_FSB_1600_ALT                             (0 << 0)        /* hrawclk 400 */
+#define CLKCFG_FSB_MASK                                 (7 << 0)
+#define CLKCFG_MEM_533                                  (1 << 4)
+#define CLKCFG_MEM_667                                  (2 << 4)
+#define CLKCFG_MEM_800                                  (3 << 4)
+#define CLKCFG_MEM_MASK                                 (7 << 4)
 /** GM965 GM45 render standby register */
 #define MCHBAR_RENDER_STANDBY   0x111B8
@@ -834,9 +871,25 @@
 #define   HORIZ_INTERP_MASK     (3 << 6)
 #define   HORIZ_AUTO_SCALE      (1 << 5)
 #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
+#define   PFIT_FILTER_FUZZY     (0 << 24)
+#define   PFIT_SCALING_AUTO     (0 << 26)
+#define   PFIT_SCALING_PROGRAMMED (1 << 26)
+#define   PFIT_SCALING_PILLAR   (2 << 26)
+#define   PFIT_SCALING_LETTER   (3 << 26)
 #define PFIT_PGM_RATIOS 0x61234
 #define   PFIT_VERT_SCALE_MASK                  0xfff00000
 #define   PFIT_HORIZ_SCALE_MASK                 0x0000fff0
+/* Pre-965 */
+#define         PFIT_VERT_SCALE_SHIFT           20
+#define         PFIT_VERT_SCALE_MASK            0xfff00000
+#define         PFIT_HORIZ_SCALE_SHIFT          4
+#define         PFIT_HORIZ_SCALE_MASK           0x0000fff0
+/* 965+ */
+#define         PFIT_VERT_SCALE_SHIFT_965       16
+#define         PFIT_VERT_SCALE_MASK_965        0x1fff0000
+#define         PFIT_HORIZ_SCALE_SHIFT_965      0
+#define         PFIT_HORIZ_SCALE_MASK_965       0x00001fff
 #define PFIT_AUTO_RATIOS 0x61238
 /* Backlight control */
@@ -1552,6 +1605,34 @@
 #define   DSPARB_CSTART_SHIFT   7
 #define   DSPARB_BSTART_MASK    (0x7f)
 #define   DSPARB_BSTART_SHIFT   0
+#define   DSPARB_BEND_SHIFT     9 /* on 855 */
+#define   DSPARB_AEND_SHIFT     0
+#define DSPFW1                  0x70034
+#define DSPFW2                  0x70038
+#define DSPFW3                  0x7003c
+#define   IGD_SELF_REFRESH_EN   (1<<30)
+/* FIFO watermark sizes etc */
+#define I915_FIFO_LINE_SIZE     64
+#define I830_FIFO_LINE_SIZE     32
+#define I945_FIFO_SIZE          127 /* 945 & 965 */
+#define I915_FIFO_SIZE          95
+#define I855GM_FIFO_SIZE        255
+#define I830_FIFO_SIZE          95
+#define I915_MAX_WM             0x3f
+#define IGD_DISPLAY_FIFO        512 /* in 64byte unit */
+#define IGD_FIFO_LINE_SIZE      64
+#define IGD_MAX_WM              0x1ff
+#define IGD_DFT_WM              0x3f
+#define IGD_DFT_HPLLOFF_WM      0
+#define IGD_GUARD_WM            10
+#define IGD_CURSOR_FIFO         64
+#define IGD_CURSOR_MAX_WM       0x3f
+#define IGD_CURSOR_DFT_WM       0
+#define IGD_CURSOR_GUARD_WM     5
 /*
 * The two pipe frame counter registers are not synchronized, so
 * reading a stable value is somewhat tricky. The following code
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index a98e2831ed31..9e1d16e5c3ea 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -222,23 +222,12 @@ static void i915_restore_vga(struct drm_device *dev)
        I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
 }
-int i915_save_state(struct drm_device *dev)
+static void i915_save_modeset_reg(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
-        int i;
-        pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
-        /* Render Standby */
-        if (IS_I965G(dev) && IS_MOBILE(dev))
-                dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
-        /* Hardware status page */
-        dev_priv->saveHWS = I915_READ(HWS_PGA);
-        /* Display arbitration control */
-        dev_priv->saveDSPARB = I915_READ(DSPARB);
+        if (drm_core_check_feature(dev, DRIVER_MODESET))
+                return;
        /* Pipe & plane A info */
        dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
        dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
@@ -294,7 +283,122 @@ int i915_save_state(struct drm_device *dev)
        }
        i915_save_palette(dev, PIPE_B);
        dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
+        return;
+}
+static void i915_restore_modeset_reg(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        if (drm_core_check_feature(dev, DRIVER_MODESET))
+                return;
+        /* Pipe & plane A info */
+        /* Prime the clock */
+        if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
+                I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
+                           ~DPLL_VCO_ENABLE);
+                DRM_UDELAY(150);
+        }
+        I915_WRITE(FPA0, dev_priv->saveFPA0);
+        I915_WRITE(FPA1, dev_priv->saveFPA1);
+        /* Actually enable it */
+        I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
+        DRM_UDELAY(150);
+        if (IS_I965G(dev))
+                I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
+        DRM_UDELAY(150);
+        /* Restore mode */
+        I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
+        I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
+        I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
+        I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
+        I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
+        I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
+        I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
+        /* Restore plane info */
+        I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
+        I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
+        I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
+        I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
+        I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
+        if (IS_I965G(dev)) {
+                I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
+                I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
+        }
+        I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
+        i915_restore_palette(dev, PIPE_A);
+        /* Enable the plane */
+        I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
+        I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
+        /* Pipe & plane B info */
+        if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
+                I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
+                           ~DPLL_VCO_ENABLE);
+                DRM_UDELAY(150);
+        }
+        I915_WRITE(FPB0, dev_priv->saveFPB0);
+        I915_WRITE(FPB1, dev_priv->saveFPB1);
+        /* Actually enable it */
+        I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
+        DRM_UDELAY(150);
+        if (IS_I965G(dev))
+                I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
+        DRM_UDELAY(150);
+        /* Restore mode */
+        I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
+        I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
+        I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
+        I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
+        I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
+        I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
+        I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
+        /* Restore plane info */
+        I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
+        I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
+        I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
+        I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
+        I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
+        if (IS_I965G(dev)) {
+                I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
+                I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
+        }
+        I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
+        i915_restore_palette(dev, PIPE_B);
+        /* Enable the plane */
+        I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
+        I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
+        return;
+}
+int i915_save_state(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        int i;
+        pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
+        /* Render Standby */
+        if (IS_I965G(dev) && IS_MOBILE(dev))
+                dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
+        /* Hardware status page */
+        dev_priv->saveHWS = I915_READ(HWS_PGA);
+        /* Display arbitration control */
+        dev_priv->saveDSPARB = I915_READ(DSPARB);
+        /* This is only meaningful in non-KMS mode */
+        /* Don't save them in KMS mode */
+        i915_save_modeset_reg(dev);
        /* Cursor state */
        dev_priv->saveCURACNTR = I915_READ(CURACNTR);
        dev_priv->saveCURAPOS = I915_READ(CURAPOS);
@@ -322,6 +426,20 @@ int i915_save_state(struct drm_device *dev)
        dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
        dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
+        /* Display Port state */
+        if (SUPPORTS_INTEGRATED_DP(dev)) {
+                dev_priv->saveDP_B = I915_READ(DP_B);
+                dev_priv->saveDP_C = I915_READ(DP_C);
+                dev_priv->saveDP_D = I915_READ(DP_D);
+                dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M);
+                dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M);
+                dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N);
+                dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N);
+                dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M);
+                dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M);
+                dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N);
+                dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N);
+        }
        /* FIXME: save TV & SDVO state */
        /* FBC state */
@@ -404,92 +522,21 @@ int i915_restore_state(struct drm_device *dev)
                        for (i = 0; i < 8; i++)
                                I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
        }
+        
-        /* Pipe & plane A info */
+        /* Display port ratios (must be done before clock is set) */
-        /* Prime the clock */
+        if (SUPPORTS_INTEGRATED_DP(dev)) {
-        if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
+                I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
-                I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
+                I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
-                           ~DPLL_VCO_ENABLE);
+                I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
-                DRM_UDELAY(150);
+                I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
+                I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
+                I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
+                I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
+                I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
        }
-        I915_WRITE(FPA0, dev_priv->saveFPA0);
+        /* This is only meaningful in non-KMS mode */
-        I915_WRITE(FPA1, dev_priv->saveFPA1);
+        /* Don't restore them in KMS mode */
-        /* Actually enable it */
+        i915_restore_modeset_reg(dev);
-        I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
-        DRM_UDELAY(150);
-        if (IS_I965G(dev))
-                I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
-        DRM_UDELAY(150);
-        /* Restore mode */
-        I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
-        I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
-        I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
-        I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
-        I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
-        I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
-        I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
-        /* Restore plane info */
-        I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
-        I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
-        I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
-        I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
-        I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
-        if (IS_I965G(dev)) {
-                I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
-                I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
-        }
-        I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
-        i915_restore_palette(dev, PIPE_A);
-        /* Enable the plane */
-        I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
-        I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
-        /* Pipe & plane B info */
-        if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
-                I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
-                           ~DPLL_VCO_ENABLE);
-                DRM_UDELAY(150);
-        }
-        I915_WRITE(FPB0, dev_priv->saveFPB0);
-        I915_WRITE(FPB1, dev_priv->saveFPB1);
-        /* Actually enable it */
-        I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
-        DRM_UDELAY(150);
-        if (IS_I965G(dev))
-                I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
-        DRM_UDELAY(150);
-        /* Restore mode */
-        I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
-        I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
-        I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
-        I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
-        I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
-        I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
-        I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
-        /* Restore plane info */
-        I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
-        I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
-        I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
-        I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
-        I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
-        if (IS_I965G(dev)) {
-                I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
-                I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
-        }
-        I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
-        i915_restore_palette(dev, PIPE_B);
-        /* Enable the plane */
-        I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
-        I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
        /* Cursor state */
        I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
        I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
@@ -518,6 +565,12 @@ int i915_restore_state(struct drm_device *dev)
        I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
        I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
+        /* Display Port state */
+        if (SUPPORTS_INTEGRATED_DP(dev)) {
+                I915_WRITE(DP_B, dev_priv->saveDP_B);
+                I915_WRITE(DP_C, dev_priv->saveDP_C);
+                I915_WRITE(DP_D, dev_priv->saveDP_D);
+        }
        /* FIXME: restore TV & SDVO state */
        /* FBC info */
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index cdd126d068a7..7cc447191028 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -97,11 +97,14 @@ static void
 parse_lfp_panel_data(struct drm_i915_private *dev_priv,
                            struct bdb_header *bdb)
 {
+        struct drm_device *dev = dev_priv->dev;
        struct bdb_lvds_options *lvds_options;
        struct bdb_lvds_lfp_data *lvds_lfp_data;
+        struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
        struct bdb_lvds_lfp_data_entry *entry;
        struct lvds_dvo_timing *dvo_timing;
        struct drm_display_mode *panel_fixed_mode;
+        int lfp_data_size;
        /* Defaults if we can't find VBT info */
        dev_priv->lvds_dither = 0;
@@ -119,10 +122,25 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
        if (!lvds_lfp_data)
                return;
+        lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
+        if (!lvds_lfp_data_ptrs)
+                return;
        dev_priv->lvds_vbt = 1;
-        entry = &lvds_lfp_data->data[lvds_options->panel_type];
+        lfp_data_size = lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset -
-        dvo_timing = &entry->dvo_timing;
+                lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;
+        entry = (struct bdb_lvds_lfp_data_entry *)
+                ((uint8_t *)lvds_lfp_data->data + (lfp_data_size *
+                                                   lvds_options->panel_type));
+        /* On IGDNG mobile, LVDS data block removes panel fitting registers.
+           So dec 2 dword from dvo_timing offset */
+        if (IS_IGDNG(dev))
+                dvo_timing = (struct lvds_dvo_timing *)
+                                        ((u8 *)&entry->dvo_timing - 8);
+        else
+                dvo_timing = &entry->dvo_timing;
        panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
@@ -185,10 +203,12 @@ parse_general_features(struct drm_i915_private *dev_priv,
                dev_priv->lvds_use_ssc = general->enable_ssc;
                if (dev_priv->lvds_use_ssc) {
-                  if (IS_I855(dev_priv->dev))
+                        if (IS_I85X(dev_priv->dev))
-                    dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
+                                dev_priv->lvds_ssc_freq =
-                  else
+                                        general->ssc_freq ? 66 : 48;
-                    dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
+                        else
+                                dev_priv->lvds_ssc_freq =
+                                        general->ssc_freq ? 100 : 96;
                }
        }
 }
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 6de97fc66029..d6a1a6e5539a 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -46,7 +46,7 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
        temp = I915_READ(reg);
        temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
-        temp |= ADPA_DAC_ENABLE;
+        temp &= ~ADPA_DAC_ENABLE;
        switch(mode) {
        case DRM_MODE_DPMS_ON:
@@ -428,8 +428,34 @@ static void intel_crt_destroy(struct drm_connector *connector)
 static int intel_crt_get_modes(struct drm_connector *connector)
 {
+        int ret;
        struct intel_output *intel_output = to_intel_output(connector);
-        return intel_ddc_get_modes(intel_output);
+        struct i2c_adapter *ddcbus;
+        struct drm_device *dev = connector->dev;
+        ret = intel_ddc_get_modes(intel_output);
+        if (ret || !IS_G4X(dev))
+                goto end;
+        ddcbus = intel_output->ddc_bus;
+        /* Try to probe digital port for output in DVI-I -> VGA mode. */
+        intel_output->ddc_bus =
+                intel_i2c_create(connector->dev, GPIOD, "CRTDDC_D");
+        if (!intel_output->ddc_bus) {
+                intel_output->ddc_bus = ddcbus;
+                dev_printk(KERN_ERR, &connector->dev->pdev->dev,
+                           "DDC bus registration failed for CRTDDC_D.\n");
+                goto end;
+        }
+        /* Try to get modes by GPIOD port */
+        ret = intel_ddc_get_modes(intel_output);
+        intel_i2c_destroy(ddcbus);
+end:
+        return ret;
 }
 static int intel_crt_set_property(struct drm_connector *connector,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3e1c78162119..508838ee31e0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -25,14 +25,17 @@
 */
 #include <linux/i2c.h>
+#include <linux/kernel.h>
 #include "drmP.h"
 #include "intel_drv.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
+#include "intel_dp.h"
 #include "drm_crtc_helper.h"
 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
+static void intel_update_watermarks(struct drm_device *dev);
 typedef struct {
    /* given values */
@@ -127,19 +130,6 @@ struct intel_limit {
 #define I9XX_P2_LVDS_FAST                     7
 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
-#define INTEL_LIMIT_I8XX_DVO_DAC    0
-#define INTEL_LIMIT_I8XX_LVDS       1
-#define INTEL_LIMIT_I9XX_SDVO_DAC   2
-#define INTEL_LIMIT_I9XX_LVDS       3
-#define INTEL_LIMIT_G4X_SDVO        4
-#define INTEL_LIMIT_G4X_HDMI_DAC   5
-#define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS   6
-#define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS   7
-#define INTEL_LIMIT_IGD_SDVO_DAC    8
-#define INTEL_LIMIT_IGD_LVDS        9
-#define INTEL_LIMIT_IGDNG_SDVO_DAC  10
-#define INTEL_LIMIT_IGDNG_LVDS      11
 /*The parameter is for SDVO on G4x platform*/
 #define G4X_DOT_SDVO_MIN           25000
 #define G4X_DOT_SDVO_MAX           270000
@@ -218,6 +208,25 @@ struct intel_limit {
 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
+/*The parameter is for DISPLAY PORT on G4x platform*/
+#define G4X_DOT_DISPLAY_PORT_MIN           161670
+#define G4X_DOT_DISPLAY_PORT_MAX           227000
+#define G4X_N_DISPLAY_PORT_MIN             1
+#define G4X_N_DISPLAY_PORT_MAX             2
+#define G4X_M_DISPLAY_PORT_MIN             97
+#define G4X_M_DISPLAY_PORT_MAX             108
+#define G4X_M1_DISPLAY_PORT_MIN            0x10
+#define G4X_M1_DISPLAY_PORT_MAX            0x12
+#define G4X_M2_DISPLAY_PORT_MIN            0x05
+#define G4X_M2_DISPLAY_PORT_MAX            0x06
+#define G4X_P_DISPLAY_PORT_MIN             10
+#define G4X_P_DISPLAY_PORT_MAX             20
+#define G4X_P1_DISPLAY_PORT_MIN            1
+#define G4X_P1_DISPLAY_PORT_MAX            2
+#define G4X_P2_DISPLAY_PORT_SLOW           10
+#define G4X_P2_DISPLAY_PORT_FAST           10
+#define G4X_P2_DISPLAY_PORT_LIMIT          0
 /* IGDNG */
 /* as we calculate clock using (register_value + 2) for
   N/M1/M2, so here the range value for them is (actual_value-2).
@@ -256,8 +265,11 @@ static bool
 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                        int target, int refclk, intel_clock_t *best_clock);
-static const intel_limit_t intel_limits[] = {
+static bool
-    { /* INTEL_LIMIT_I8XX_DVO_DAC */
+intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
+                      int target, int refclk, intel_clock_t *best_clock);
+static const intel_limit_t intel_limits_i8xx_dvo = {
        .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
        .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
        .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
@@ -269,8 +281,9 @@ static const intel_limit_t intel_limits[] = {
        .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
                 .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
        .find_pll = intel_find_best_PLL,
-    },
+};
-    { /* INTEL_LIMIT_I8XX_LVDS */
+static const intel_limit_t intel_limits_i8xx_lvds = {
        .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
        .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
        .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
@@ -282,8 +295,9 @@ static const intel_limit_t intel_limits[] = {
        .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
                 .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
        .find_pll = intel_find_best_PLL,
-    },
+};
-    { /* INTEL_LIMIT_I9XX_SDVO_DAC */
+        
+static const intel_limit_t intel_limits_i9xx_sdvo = {
        .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
        .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
        .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
@@ -295,8 +309,9 @@ static const intel_limit_t intel_limits[] = {
        .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
                 .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
        .find_pll = intel_find_best_PLL,
-    },
+};
-    { /* INTEL_LIMIT_I9XX_LVDS */
+static const intel_limit_t intel_limits_i9xx_lvds = {
        .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
        .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
        .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
@@ -311,9 +326,10 @@ static const intel_limit_t intel_limits[] = {
        .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
                 .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
        .find_pll = intel_find_best_PLL,
-    },
+};
    /* below parameter and function is for G4X Chipset Family*/
-    { /* INTEL_LIMIT_G4X_SDVO */
+static const intel_limit_t intel_limits_g4x_sdvo = {
        .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
        .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
        .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
@@ -327,8 +343,9 @@ static const intel_limit_t intel_limits[] = {
                 .p2_fast = G4X_P2_SDVO_FAST
        },
        .find_pll = intel_g4x_find_best_PLL,
-    },
+};
-    { /* INTEL_LIMIT_G4X_HDMI_DAC */
+static const intel_limit_t intel_limits_g4x_hdmi = {
        .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
        .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
        .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
@@ -342,8 +359,9 @@ static const intel_limit_t intel_limits[] = {
                 .p2_fast = G4X_P2_HDMI_DAC_FAST
        },
        .find_pll = intel_g4x_find_best_PLL,
-    },
+};
-    { /* INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS */
+static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
        .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
                 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
        .vco = { .min = G4X_VCO_MIN,
@@ -365,8 +383,9 @@ static const intel_limit_t intel_limits[] = {
                 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
        },
        .find_pll = intel_g4x_find_best_PLL,
-    },
+};
-    { /* INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS */
+static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
        .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
                 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
        .vco = { .min = G4X_VCO_MIN,
@@ -388,8 +407,32 @@ static const intel_limit_t intel_limits[] = {
                 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
        },
        .find_pll = intel_g4x_find_best_PLL,
-    },
+};
-    { /* INTEL_LIMIT_IGD_SDVO */
+static const intel_limit_t intel_limits_g4x_display_port = {
+        .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
+                 .max = G4X_DOT_DISPLAY_PORT_MAX },
+        .vco = { .min = G4X_VCO_MIN,
+                 .max = G4X_VCO_MAX},
+        .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
+                 .max = G4X_N_DISPLAY_PORT_MAX },
+        .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
+                 .max = G4X_M_DISPLAY_PORT_MAX },
+        .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
+                 .max = G4X_M1_DISPLAY_PORT_MAX },
+        .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
+                 .max = G4X_M2_DISPLAY_PORT_MAX },
+        .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
+                 .max = G4X_P_DISPLAY_PORT_MAX },
+        .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
+                 .max = G4X_P1_DISPLAY_PORT_MAX},
+        .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
+                 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
+                 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
+        .find_pll = intel_find_pll_g4x_dp,
+};
+static const intel_limit_t intel_limits_igd_sdvo = {
        .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
        .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
        .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
@@ -401,8 +444,9 @@ static const intel_limit_t intel_limits[] = {
        .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
                 .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
        .find_pll = intel_find_best_PLL,
-    },
+};
-    { /* INTEL_LIMIT_IGD_LVDS */
+static const intel_limit_t intel_limits_igd_lvds = {
        .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
        .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
        .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
@@ -415,8 +459,9 @@ static const intel_limit_t intel_limits[] = {
        .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
                 .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
        .find_pll = intel_find_best_PLL,
-    },
+};
-    { /* INTEL_LIMIT_IGDNG_SDVO_DAC */
+static const intel_limit_t intel_limits_igdng_sdvo = {
        .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
        .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
        .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
@@ -429,8 +474,9 @@ static const intel_limit_t intel_limits[] = {
                 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
                 .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
        .find_pll = intel_igdng_find_best_PLL,
-    },
+};
-    { /* INTEL_LIMIT_IGDNG_LVDS */
+static const intel_limit_t intel_limits_igdng_lvds = {
        .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
        .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
        .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
@@ -443,16 +489,15 @@ static const intel_limit_t intel_limits[] = {
                 .p2_slow = IGDNG_P2_LVDS_SLOW,
                 .p2_fast = IGDNG_P2_LVDS_FAST },
        .find_pll = intel_igdng_find_best_PLL,
-    },
 };
 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 {
        const intel_limit_t *limit;
        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
-                limit = &intel_limits[INTEL_LIMIT_IGDNG_LVDS];
+                limit = &intel_limits_igdng_lvds;
        else
-                limit = &intel_limits[INTEL_LIMIT_IGDNG_SDVO_DAC];
+                limit = &intel_limits_igdng_sdvo;
        return limit;
 }
@@ -467,19 +512,19 @@ static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
                if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
                    LVDS_CLKB_POWER_UP)
                        /* LVDS with dual channel */
-                        limit = &intel_limits
+                        limit = &intel_limits_g4x_dual_channel_lvds;
-                                        [INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS];
                else
                        /* LVDS with dual channel */
-                        limit = &intel_limits
+                        limit = &intel_limits_g4x_single_channel_lvds;
-                                        [INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS];
        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
                   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
-                limit = &intel_limits[INTEL_LIMIT_G4X_HDMI_DAC];
+                limit = &intel_limits_g4x_hdmi;
        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
-                limit = &intel_limits[INTEL_LIMIT_G4X_SDVO];
+                limit = &intel_limits_g4x_sdvo;
+        } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
+                limit = &intel_limits_g4x_display_port;
        } else /* The option is for other outputs */
-                limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
+                limit = &intel_limits_i9xx_sdvo;
        return limit;
 }
@@ -495,19 +540,19 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
                limit = intel_g4x_limit(crtc);
        } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
-                        limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
+                        limit = &intel_limits_i9xx_lvds;
                else
-                        limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
+                        limit = &intel_limits_i9xx_sdvo;
        } else if (IS_IGD(dev)) {
                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
-                        limit = &intel_limits[INTEL_LIMIT_IGD_LVDS];
+                        limit = &intel_limits_igd_lvds;
                else
-                        limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC];
+                        limit = &intel_limits_igd_sdvo;
        } else {
                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
-                        limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
+                        limit = &intel_limits_i8xx_lvds;
                else
-                        limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC];
+                        limit = &intel_limits_i8xx_dvo;
        }
        return limit;
 }
@@ -764,6 +809,32 @@ out:
        return found;
 }
+/* DisplayPort has only two frequencies, 162MHz and 270MHz */
+static bool
+intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
+                      int target, int refclk, intel_clock_t *best_clock)
+{
+    intel_clock_t clock;
+    if (target < 200000) {
+        clock.p1 = 2;
+        clock.p2 = 10;
+        clock.n = 2;
+        clock.m1 = 23;
+        clock.m2 = 8;
+    } else {
+        clock.p1 = 1;
+        clock.p2 = 10;
+        clock.n = 1;
+        clock.m1 = 14;
+        clock.m2 = 2;
+    }
+    clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
+    clock.p = (clock.p1 * clock.p2);
+    clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
+    memcpy(best_clock, &clock, sizeof(intel_clock_t));
+    return true;
+}
 void
 intel_wait_for_vblank(struct drm_device *dev)
 {
@@ -933,7 +1004,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
-        int plane = intel_crtc->pipe;
+        int plane = intel_crtc->plane;
        int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
        int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
        int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
@@ -1263,8 +1334,10 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
                /* Give the overlay scaler a chance to enable if it's on this pipe */
                //intel_crtc_dpms_video(crtc, true); TODO
+                intel_update_watermarks(dev);
        break;
        case DRM_MODE_DPMS_OFF:
+                intel_update_watermarks(dev);
                /* Give the overlay scaler a chance to disable if it's on this pipe */
                //intel_crtc_dpms_video(crtc, FALSE); TODO
@@ -1443,7 +1516,6 @@ static int intel_get_core_clock_speed(struct drm_device *dev)
        return 0; /* Silence gcc warning */
 }
 /**
 * Return the pipe currently connected to the panel fitter,
 * or -1 if the panel fitter is not present or not in use
@@ -1502,7 +1574,7 @@ igdng_compute_m_n(int bytes_per_pixel, int nlanes,
        temp = (u64) DATA_N * pixel_clock;
        temp = div_u64(temp, link_clock);
-        m_n->gmch_m = (temp * bytes_per_pixel) / nlanes;
+        m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
        m_n->gmch_n = DATA_N;
        fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
@@ -1513,6 +1585,420 @@ igdng_compute_m_n(int bytes_per_pixel, int nlanes,
 }
+struct intel_watermark_params {
+        unsigned long fifo_size;
+        unsigned long max_wm;
+        unsigned long default_wm;
+        unsigned long guard_size;
+        unsigned long cacheline_size;
+};
+/* IGD has different values for various configs */
+static struct intel_watermark_params igd_display_wm = {
+        IGD_DISPLAY_FIFO,
+        IGD_MAX_WM,
+        IGD_DFT_WM,
+        IGD_GUARD_WM,
+        IGD_FIFO_LINE_SIZE
+};
+static struct intel_watermark_params igd_display_hplloff_wm = {
+        IGD_DISPLAY_FIFO,
+        IGD_MAX_WM,
+        IGD_DFT_HPLLOFF_WM,
+        IGD_GUARD_WM,
+        IGD_FIFO_LINE_SIZE
+};
+static struct intel_watermark_params igd_cursor_wm = {
+        IGD_CURSOR_FIFO,
+        IGD_CURSOR_MAX_WM,
+        IGD_CURSOR_DFT_WM,
+        IGD_CURSOR_GUARD_WM,
+        IGD_FIFO_LINE_SIZE,
+};
+static struct intel_watermark_params igd_cursor_hplloff_wm = {
+        IGD_CURSOR_FIFO,
+        IGD_CURSOR_MAX_WM,
+        IGD_CURSOR_DFT_WM,
+        IGD_CURSOR_GUARD_WM,
+        IGD_FIFO_LINE_SIZE
+};
+static struct intel_watermark_params i945_wm_info = {
+        I915_FIFO_LINE_SIZE,
+        I915_MAX_WM,
+        1,
+        0,
+        IGD_FIFO_LINE_SIZE
+};
+static struct intel_watermark_params i915_wm_info = {
+        I945_FIFO_SIZE,
+        I915_MAX_WM,
+        1,
+        0,
+        I915_FIFO_LINE_SIZE
+};
+static struct intel_watermark_params i855_wm_info = {
+        I855GM_FIFO_SIZE,
+        I915_MAX_WM,
+        1,
+        0,
+        I830_FIFO_LINE_SIZE
+};
+static struct intel_watermark_params i830_wm_info = {
+        I830_FIFO_SIZE,
+        I915_MAX_WM,
+        1,
+        0,
+        I830_FIFO_LINE_SIZE
+};
+static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
+                                        struct intel_watermark_params *wm,
+                                        int pixel_size,
+                                        unsigned long latency_ns)
+{
+        unsigned long bytes_required, wm_size;
+        bytes_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
+        bytes_required /= wm->cacheline_size;
+        wm_size = wm->fifo_size - bytes_required - wm->guard_size;
+        if (wm_size > wm->max_wm)
+                wm_size = wm->max_wm;
+        if (wm_size == 0)
+                wm_size = wm->default_wm;
+        return wm_size;
+}
+struct cxsr_latency {
+        int is_desktop;
+        unsigned long fsb_freq;
+        unsigned long mem_freq;
+        unsigned long display_sr;
+        unsigned long display_hpll_disable;
+        unsigned long cursor_sr;
+        unsigned long cursor_hpll_disable;
+};
+static struct cxsr_latency cxsr_latency_table[] = {
+        {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
+        {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
+        {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
+        {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
+        {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
+        {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
+        {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
+        {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
+        {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
+        {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
+        {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
+        {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
+        {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
+        {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
+        {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
+        {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
+        {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
+        {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
+};
+static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
+                                                   int mem)
+{
+        int i;
+        struct cxsr_latency *latency;
+        if (fsb == 0 || mem == 0)
+                return NULL;
+        for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
+                latency = &cxsr_latency_table[i];
+                if (is_desktop == latency->is_desktop &&
+                        fsb == latency->fsb_freq && mem == latency->mem_freq)
+                        break;
+        }
+        if (i >= ARRAY_SIZE(cxsr_latency_table)) {
+                DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
+                return NULL;
+        }
+        return latency;
+}
+static void igd_disable_cxsr(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 reg;
+        /* deactivate cxsr */
+        reg = I915_READ(DSPFW3);
+        reg &= ~(IGD_SELF_REFRESH_EN);
+        I915_WRITE(DSPFW3, reg);
+        DRM_INFO("Big FIFO is disabled\n");
+}
+static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
+                            int pixel_size)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 reg;
+        unsigned long wm;
+        struct cxsr_latency *latency;
+        latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
+                dev_priv->mem_freq);
+        if (!latency) {
+                DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
+                igd_disable_cxsr(dev);
+                return;
+        }
+        /* Display SR */
+        wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
+                                latency->display_sr);
+        reg = I915_READ(DSPFW1);
+        reg &= 0x7fffff;
+        reg |= wm << 23;
+        I915_WRITE(DSPFW1, reg);
+        DRM_DEBUG("DSPFW1 register is %x\n", reg);
+        /* cursor SR */
+        wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
+                                latency->cursor_sr);
+        reg = I915_READ(DSPFW3);
+        reg &= ~(0x3f << 24);
+        reg |= (wm & 0x3f) << 24;
+        I915_WRITE(DSPFW3, reg);
+        /* Display HPLL off SR */
+        wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
+                latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
+        reg = I915_READ(DSPFW3);
+        reg &= 0xfffffe00;
+        reg |= wm & 0x1ff;
+        I915_WRITE(DSPFW3, reg);
+        /* cursor HPLL off SR */
+        wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
+                                latency->cursor_hpll_disable);
+        reg = I915_READ(DSPFW3);
+        reg &= ~(0x3f << 16);
+        reg |= (wm & 0x3f) << 16;
+        I915_WRITE(DSPFW3, reg);
+        DRM_DEBUG("DSPFW3 register is %x\n", reg);
+        /* activate cxsr */
+        reg = I915_READ(DSPFW3);
+        reg |= IGD_SELF_REFRESH_EN;
+        I915_WRITE(DSPFW3, reg);
+        DRM_INFO("Big FIFO is enabled\n");
+        return;
+}
+const static int latency_ns = 5000; /* default for non-igd platforms */
+static void i965_update_wm(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
+        /* 965 has limitations... */
+        I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
+        I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
+}
+static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
+                           int planeb_clock, int sr_hdisplay, int pixel_size)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK;
+        uint32_t fwater_hi = I915_READ(FW_BLC2) & LM_FIFO_WATERMARK;
+        int bsize, asize, cwm, bwm = 1, awm = 1, srwm = 1;
+        uint32_t dsparb = I915_READ(DSPARB);
+        int planea_entries, planeb_entries;
+        struct intel_watermark_params *wm_params;
+        unsigned long line_time_us;
+        int sr_clock, sr_entries = 0;
+        if (IS_I965GM(dev) || IS_I945GM(dev))
+                wm_params = &i945_wm_info;
+        else if (IS_I9XX(dev))
+                wm_params = &i915_wm_info;
+        else
+                wm_params = &i855_wm_info;
+        planea_entries = intel_calculate_wm(planea_clock, wm_params,
+                                            pixel_size, latency_ns);
+        planeb_entries = intel_calculate_wm(planeb_clock, wm_params,
+                                            pixel_size, latency_ns);
+        DRM_DEBUG("FIFO entries - A: %d, B: %d\n", planea_entries,
+                  planeb_entries);
+        if (IS_I9XX(dev)) {
+                asize = dsparb & 0x7f;
+                bsize = (dsparb >> DSPARB_CSTART_SHIFT) & 0x7f;
+        } else {
+                asize = dsparb & 0x1ff;
+                bsize = (dsparb >> DSPARB_BEND_SHIFT) & 0x1ff;
+        }
+        DRM_DEBUG("FIFO size - A: %d, B: %d\n", asize, bsize);
+        /* Two extra entries for padding */
+        awm = asize - (planea_entries + 2);
+        bwm = bsize - (planeb_entries + 2);
+        /* Sanity check against potentially bad FIFO allocations */
+        if (awm <= 0) {
+                /* pipe is on but has too few FIFO entries */
+                if (planea_entries != 0)
+                        DRM_DEBUG("plane A needs more FIFO entries\n");
+                awm = 1;
+        }
+        if (bwm <= 0) {
+                if (planeb_entries != 0)
+                        DRM_DEBUG("plane B needs more FIFO entries\n");
+                bwm = 1;
+        }
+        /*
+         * Overlay gets an aggressive default since video jitter is bad.
+         */
+        cwm = 2;
+        /* Calc sr entries for one pipe configs */
+        if (!planea_clock || !planeb_clock) {
+                sr_clock = planea_clock ? planea_clock : planeb_clock;
+                line_time_us = (sr_hdisplay * 1000) / sr_clock;
+                sr_entries = (((latency_ns / line_time_us) + 1) * pixel_size *
+                              sr_hdisplay) / 1000;
+                sr_entries = roundup(sr_entries / wm_params->cacheline_size, 1);
+                if (sr_entries < wm_params->fifo_size)
+                        srwm = wm_params->fifo_size - sr_entries;
+        }
+        DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
+                  awm, bwm, cwm, srwm);
+        fwater_lo = fwater_lo | ((bwm & 0x3f) << 16) | (awm & 0x3f);
+        fwater_hi = fwater_hi | (cwm & 0x1f);
+        I915_WRITE(FW_BLC, fwater_lo);
+        I915_WRITE(FW_BLC2, fwater_hi);
+        if (IS_I9XX(dev))
+                I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
+}
+static void i830_update_wm(struct drm_device *dev, int planea_clock,
+                           int pixel_size)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        uint32_t dsparb = I915_READ(DSPARB);
+        uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK;
+        unsigned int asize, awm;
+        int planea_entries;
+        planea_entries = intel_calculate_wm(planea_clock, &i830_wm_info,
+                                            pixel_size, latency_ns);
+        asize = dsparb & 0x7f;
+        awm = asize - planea_entries;
+        fwater_lo = fwater_lo | awm;
+        I915_WRITE(FW_BLC, fwater_lo);
+}
+/**
+ * intel_update_watermarks - update FIFO watermark values based on current modes
+ *
+ * Calculate watermark values for the various WM regs based on current mode
+ * and plane configuration.
+ *
+ * There are several cases to deal with here:
+ *   - normal (i.e. non-self-refresh)
+ *   - self-refresh (SR) mode
+ *   - lines are large relative to FIFO size (buffer can hold up to 2)
+ *   - lines are small relative to FIFO size (buffer can hold more than 2
+ *     lines), so need to account for TLB latency
+ *
+ *   The normal calculation is:
+ *     watermark = dotclock * bytes per pixel * latency
+ *   where latency is platform & configuration dependent (we assume pessimal
+ *   values here).
+ *
+ *   The SR calculation is:
+ *     watermark = (trunc(latency/line time)+1) * surface width *
+ *       bytes per pixel
+ *   where
+ *     line time = htotal / dotclock
+ *   and latency is assumed to be high, as above.
+ *
+ * The final value programmed to the register should always be rounded up,
+ * and include an extra 2 entries to account for clock crossings.
+ *
+ * We don't use the sprite, so we can ignore that.  And on Crestline we have
+ * to set the non-SR watermarks to 8.
+  */
+static void intel_update_watermarks(struct drm_device *dev)
+{
+        struct drm_crtc *crtc;
+        struct intel_crtc *intel_crtc;
+        int sr_hdisplay = 0;
+        unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
+        int enabled = 0, pixel_size = 0;
+        if (DSPARB_HWCONTROL(dev))
+                return;
+        /* Get the clock config from both planes */
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                intel_crtc = to_intel_crtc(crtc);
+                if (crtc->enabled) {
+                        enabled++;
+                        if (intel_crtc->plane == 0) {
+                                DRM_DEBUG("plane A (pipe %d) clock: %d\n",
+                                          intel_crtc->pipe, crtc->mode.clock);
+                                planea_clock = crtc->mode.clock;
+                        } else {
+                                DRM_DEBUG("plane B (pipe %d) clock: %d\n",
+                                          intel_crtc->pipe, crtc->mode.clock);
+                                planeb_clock = crtc->mode.clock;
+                        }
+                        sr_hdisplay = crtc->mode.hdisplay;
+                        sr_clock = crtc->mode.clock;
+                        if (crtc->fb)
+                                pixel_size = crtc->fb->bits_per_pixel / 8;
+                        else
+                                pixel_size = 4; /* by default */
+                }
+        }
+        if (enabled <= 0)
+                return;
+        /* Single pipe configs can enable self refresh */
+        if (enabled == 1 && IS_IGD(dev))
+                igd_enable_cxsr(dev, sr_clock, pixel_size);
+        else if (IS_IGD(dev))
+                igd_disable_cxsr(dev);
+        if (IS_I965G(dev))
+                i965_update_wm(dev);
+        else if (IS_I9XX(dev) || IS_MOBILE(dev))
+                i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
+                               pixel_size);
+        else
+                i830_update_wm(dev, planea_clock, pixel_size);
+}
 static int intel_crtc_mode_set(struct drm_crtc *crtc,
                               struct drm_display_mode *mode,
                               struct drm_display_mode *adjusted_mode,
@@ -1541,7 +2027,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
        intel_clock_t clock;
        u32 dpll = 0, fp = 0, dspcntr, pipeconf;
        bool ok, is_sdvo = false, is_dvo = false;
-        bool is_crt = false, is_lvds = false, is_tv = false;
+        bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
        struct drm_mode_config *mode_config = &dev->mode_config;
        struct drm_connector *connector;
        const intel_limit_t *limit;
@@ -1585,6 +2071,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                case INTEL_OUTPUT_ANALOG:
                        is_crt = true;
                        break;
+                case INTEL_OUTPUT_DISPLAYPORT:
+                        is_dp = true;
+                        break;
                }
                num_outputs++;
@@ -1600,6 +2089,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
        } else {
                refclk = 48000;
        }
+        
        /*
         * Returns a set of divisors for the desired target clock with the given
@@ -1662,6 +2152,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                        else if (IS_IGDNG(dev))
                                dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
                }
+                if (is_dp)
+                        dpll |= DPLL_DVO_HIGH_SPEED;
                /* compute bitmask from p1 value */
                if (IS_IGD(dev))
@@ -1809,6 +2301,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                I915_WRITE(lvds_reg, lvds);
                I915_READ(lvds_reg);
        }
+        if (is_dp)
+                intel_dp_set_m_n(crtc, mode, adjusted_mode);
        I915_WRITE(fp_reg, fp);
        I915_WRITE(dpll_reg, dpll);
@@ -1871,6 +2365,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
        /* Flush the plane changes */
        ret = intel_pipe_set_base(crtc, x, y, old_fb);
+        intel_update_watermarks(dev);
        drm_vblank_post_modeset(dev, pipe);
        return ret;
@@ -2359,6 +2856,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
        drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
        intel_crtc->pipe = pipe;
+        intel_crtc->plane = pipe;
        for (i = 0; i < 256; i++) {
                intel_crtc->lut_r[i] = i;
                intel_crtc->lut_g[i] = i;
@@ -2475,6 +2973,8 @@ static void intel_setup_outputs(struct drm_device *dev)
                        found = intel_sdvo_init(dev, SDVOB);
                        if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
                                intel_hdmi_init(dev, SDVOB);
+                        if (!found && SUPPORTS_INTEGRATED_DP(dev))
+                                intel_dp_init(dev, DP_B);
                }
                /* Before G4X SDVOC doesn't have its own detect register */
@@ -2487,7 +2987,11 @@ static void intel_setup_outputs(struct drm_device *dev)
                        found = intel_sdvo_init(dev, SDVOC);
                        if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
                                intel_hdmi_init(dev, SDVOC);
+                        if (!found && SUPPORTS_INTEGRATED_DP(dev))
+                                intel_dp_init(dev, DP_C);
                }
+                if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
+                        intel_dp_init(dev, DP_D);
        } else
                intel_dvo_init(dev);
@@ -2530,6 +3034,11 @@ static void intel_setup_outputs(struct drm_device *dev)
                                     (1 << 1));
                        clone_mask = (1 << INTEL_OUTPUT_TVOUT);
                        break;
+                case INTEL_OUTPUT_DISPLAYPORT:
+                        crtc_mask = ((1 << 0) |
+                                     (1 << 1));
+                        clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
+                        break;
                }
                encoder->possible_crtcs = crtc_mask;
                encoder->possible_clones = intel_connector_clones(dev, clone_mask);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
new file mode 100644
index 000000000000..6770ae88370d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -0,0 +1,1156 @@
+/*
+ * Copyright © 2008 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Keith Packard <keithp@keithp.com>
+ *
+ */
+#include <linux/i2c.h>
+#include "drmP.h"
+#include "drm.h"
+#include "drm_crtc.h"
+#include "drm_crtc_helper.h"
+#include "intel_drv.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+#include "intel_dp.h"
+#define DP_LINK_STATUS_SIZE     6
+#define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
+#define DP_LINK_CONFIGURATION_SIZE      9
+struct intel_dp_priv {
+        uint32_t output_reg;
+        uint32_t DP;
+        uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
+        uint32_t save_DP;
+        uint8_t  save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
+        bool has_audio;
+        int dpms_mode;
+        uint8_t link_bw;
+        uint8_t lane_count;
+        uint8_t dpcd[4];
+        struct intel_output *intel_output;
+        struct i2c_adapter adapter;
+        struct i2c_algo_dp_aux_data algo;
+};
+static void
+intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
+                    uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
+static void
+intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
+static int
+intel_dp_max_lane_count(struct intel_output *intel_output)
+{
+        struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
+        int max_lane_count = 4;
+        if (dp_priv->dpcd[0] >= 0x11) {
+                max_lane_count = dp_priv->dpcd[2] & 0x1f;
+                switch (max_lane_count) {
+                case 1: case 2: case 4:
+                        break;
+                default:
+                        max_lane_count = 4;
+                }
+        }
+        return max_lane_count;
+}
+static int
+intel_dp_max_link_bw(struct intel_output *intel_output)
+{
+        struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
+        int max_link_bw = dp_priv->dpcd[1];
+        switch (max_link_bw) {
+        case DP_LINK_BW_1_62:
+        case DP_LINK_BW_2_7:
+                break;
+        default:
+                max_link_bw = DP_LINK_BW_1_62;
+                break;
+        }
+        return max_link_bw;
+}
+static int
+intel_dp_link_clock(uint8_t link_bw)
+{
+        if (link_bw == DP_LINK_BW_2_7)
+                return 270000;
+        else
+                return 162000;
+}
+/* I think this is a fiction */
+static int
+intel_dp_link_required(int pixel_clock)
+{
+        return pixel_clock * 3;
+}
+static int
+intel_dp_mode_valid(struct drm_connector *connector,
+                    struct drm_display_mode *mode)
+{
+        struct intel_output *intel_output = to_intel_output(connector);
+        int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
+        int max_lanes = intel_dp_max_lane_count(intel_output);
+        if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes)
+                return MODE_CLOCK_HIGH;
+        if (mode->clock < 10000)
+                return MODE_CLOCK_LOW;
+        return MODE_OK;
+}
+static uint32_t
+pack_aux(uint8_t *src, int src_bytes)
+{
+        int     i;
+        uint32_t v = 0;
+        if (src_bytes > 4)
+                src_bytes = 4;
+        for (i = 0; i < src_bytes; i++)
+                v |= ((uint32_t) src[i]) << ((3-i) * 8);
+        return v;
+}
+static void
+unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
+{
+        int i;
+        if (dst_bytes > 4)
+                dst_bytes = 4;
+        for (i = 0; i < dst_bytes; i++)
+                dst[i] = src >> ((3-i) * 8);
+}
+/* hrawclock is 1/4 the FSB frequency */
+static int
+intel_hrawclk(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        uint32_t clkcfg;
+        clkcfg = I915_READ(CLKCFG);
+        switch (clkcfg & CLKCFG_FSB_MASK) {
+        case CLKCFG_FSB_400:
+                return 100;
+        case CLKCFG_FSB_533:
+                return 133;
+        case CLKCFG_FSB_667:
+                return 166;
+        case CLKCFG_FSB_800:
+                return 200;
+        case CLKCFG_FSB_1067:
+                return 266;
+        case CLKCFG_FSB_1333:
+                return 333;
+        /* these two are just a guess; one of them might be right */
+        case CLKCFG_FSB_1600:
+        case CLKCFG_FSB_1600_ALT:
+                return 400;
+        default:
+                return 133;
+        }
+}
+static int
+intel_dp_aux_ch(struct intel_output *intel_output,
+                uint8_t *send, int send_bytes,
+                uint8_t *recv, int recv_size)
+{
+        struct intel_dp_priv *dp_priv = intel_output->dev_priv;
+        uint32_t output_reg = dp_priv->output_reg;
+        struct drm_device *dev = intel_output->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        uint32_t ch_ctl = output_reg + 0x10;
+        uint32_t ch_data = ch_ctl + 4;
+        int i;
+        int recv_bytes;
+        uint32_t ctl;
+        uint32_t status;
+        uint32_t aux_clock_divider;
+        int try;
+        /* The clock divider is based off the hrawclk,
+         * and would like to run at 2MHz. So, take the
+         * hrawclk value and divide by 2 and use that
+         */
+        aux_clock_divider = intel_hrawclk(dev) / 2;
+        /* Must try at least 3 times according to DP spec */
+        for (try = 0; try < 5; try++) {
+                /* Load the send data into the aux channel data registers */
+                for (i = 0; i < send_bytes; i += 4) {
+                        uint32_t    d = pack_aux(send + i, send_bytes - i);;
+        
+                        I915_WRITE(ch_data + i, d);
+                }
+        
+                ctl = (DP_AUX_CH_CTL_SEND_BUSY |
+                       DP_AUX_CH_CTL_TIME_OUT_400us |
+                       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+                       (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
+                       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
+                       DP_AUX_CH_CTL_DONE |
+                       DP_AUX_CH_CTL_TIME_OUT_ERROR |
+                       DP_AUX_CH_CTL_RECEIVE_ERROR);
+        
+                /* Send the command and wait for it to complete */
+                I915_WRITE(ch_ctl, ctl);
+                (void) I915_READ(ch_ctl);
+                for (;;) {
+                        udelay(100);
+                        status = I915_READ(ch_ctl);
+                        if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+                                break;
+                }
+        
+                /* Clear done status and any errors */
+                I915_WRITE(ch_ctl, (ctl |
+                                DP_AUX_CH_CTL_DONE |
+                                DP_AUX_CH_CTL_TIME_OUT_ERROR |
+                                DP_AUX_CH_CTL_RECEIVE_ERROR));
+                (void) I915_READ(ch_ctl);
+                if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
+                        break;
+        }
+        if ((status & DP_AUX_CH_CTL_DONE) == 0) {
+                DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
+                return -EBUSY;
+        }
+        /* Check for timeout or receive error.
+         * Timeouts occur when the sink is not connected
+         */
+        if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+                DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
+                return -EIO;
+        }
+        /* Timeouts occur when the device isn't connected, so they're
+         * "normal" -- don't fill the kernel log with these */
+        if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
+                DRM_DEBUG("dp_aux_ch timeout status 0x%08x\n", status);
+                return -ETIMEDOUT;
+        }
+        /* Unload any bytes sent back from the other side */
+        recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
+                      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
+        if (recv_bytes > recv_size)
+                recv_bytes = recv_size;
+        
+        for (i = 0; i < recv_bytes; i += 4) {
+                uint32_t    d = I915_READ(ch_data + i);
+                unpack_aux(d, recv + i, recv_bytes - i);
+        }
+        return recv_bytes;
+}
+/* Write data to the aux channel in native mode */
+static int
+intel_dp_aux_native_write(struct intel_output *intel_output,
+                          uint16_t address, uint8_t *send, int send_bytes)
+{
+        int ret;
+        uint8_t msg[20];
+        int msg_bytes;
+        uint8_t ack;
+        if (send_bytes > 16)
+                return -1;
+        msg[0] = AUX_NATIVE_WRITE << 4;
+        msg[1] = address >> 8;
+        msg[2] = address;
+        msg[3] = send_bytes - 1;
+        memcpy(&msg[4], send, send_bytes);
+        msg_bytes = send_bytes + 4;
+        for (;;) {
+                ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1);
+                if (ret < 0)
+                        return ret;
+                if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
+                        break;
+                else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
+                        udelay(100);
+                else
+                        return -EIO;
+        }
+        return send_bytes;
+}
+/* Write a single byte to the aux channel in native mode */
+static int
+intel_dp_aux_native_write_1(struct intel_output *intel_output,
+                            uint16_t address, uint8_t byte)
+{
+        return intel_dp_aux_native_write(intel_output, address, &byte, 1);
+}
+/* read bytes from a native aux channel */
+static int
+intel_dp_aux_native_read(struct intel_output *intel_output,
+                         uint16_t address, uint8_t *recv, int recv_bytes)
+{
+        uint8_t msg[4];
+        int msg_bytes;
+        uint8_t reply[20];
+        int reply_bytes;
+        uint8_t ack;
+        int ret;
+        msg[0] = AUX_NATIVE_READ << 4;
+        msg[1] = address >> 8;
+        msg[2] = address & 0xff;
+        msg[3] = recv_bytes - 1;
+        msg_bytes = 4;
+        reply_bytes = recv_bytes + 1;
+        for (;;) {
+                ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
+                                      reply, reply_bytes);
+                if (ret == 0)
+                        return -EPROTO;
+                if (ret < 0)
+                        return ret;
+                ack = reply[0];
+                if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
+                        memcpy(recv, reply + 1, ret - 1);
+                        return ret - 1;
+                }
+                else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
+                        udelay(100);
+                else
+                        return -EIO;
+        }
+}
+static int
+intel_dp_i2c_aux_ch(struct i2c_adapter *adapter,
+                    uint8_t *send, int send_bytes,
+                    uint8_t *recv, int recv_bytes)
+{
+        struct intel_dp_priv *dp_priv = container_of(adapter,
+                                                     struct intel_dp_priv,
+                                                     adapter);
+        struct intel_output *intel_output = dp_priv->intel_output;
+        return intel_dp_aux_ch(intel_output,
+                               send, send_bytes, recv, recv_bytes);
+}
+static int
+intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
+{
+        struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
+        DRM_ERROR("i2c_init %s\n", name);
+        dp_priv->algo.running = false;
+        dp_priv->algo.address = 0;
+        dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
+        memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
+        dp_priv->adapter.owner = THIS_MODULE;
+        dp_priv->adapter.class = I2C_CLASS_DDC;
+        strncpy (dp_priv->adapter.name, name, sizeof dp_priv->adapter.name - 1);
+        dp_priv->adapter.name[sizeof dp_priv->adapter.name - 1] = '\0';
+        dp_priv->adapter.algo_data = &dp_priv->algo;
+        dp_priv->adapter.dev.parent = &intel_output->base.kdev;
+        
+        return i2c_dp_aux_add_bus(&dp_priv->adapter);
+}
+static bool
+intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
+                    struct drm_display_mode *adjusted_mode)
+{
+        struct intel_output *intel_output = enc_to_intel_output(encoder);
+        struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
+        int lane_count, clock;
+        int max_lane_count = intel_dp_max_lane_count(intel_output);
+        int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0;
+        static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
+        for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
+                for (clock = 0; clock <= max_clock; clock++) {
+                        int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
+                        if (intel_dp_link_required(mode->clock) <= link_avail) {
+                                dp_priv->link_bw = bws[clock];
+                                dp_priv->lane_count = lane_count;
+                                adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
+                                DRM_DEBUG("Display port link bw %02x lane count %d clock %d\n",
+                                       dp_priv->link_bw, dp_priv->lane_count,
+                                       adjusted_mode->clock);
+                                return true;
+                        }
+                }
+        }
+        return false;
+}
+struct intel_dp_m_n {
+        uint32_t        tu;
+        uint32_t        gmch_m;
+        uint32_t        gmch_n;
+        uint32_t        link_m;
+        uint32_t        link_n;
+};
+static void
+intel_reduce_ratio(uint32_t *num, uint32_t *den)
+{
+        while (*num > 0xffffff || *den > 0xffffff) {
+                *num >>= 1;
+                *den >>= 1;
+        }
+}
+static void
+intel_dp_compute_m_n(int bytes_per_pixel,
+                     int nlanes,
+                     int pixel_clock,
+                     int link_clock,
+                     struct intel_dp_m_n *m_n)
+{
+        m_n->tu = 64;
+        m_n->gmch_m = pixel_clock * bytes_per_pixel;
+        m_n->gmch_n = link_clock * nlanes;
+        intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
+        m_n->link_m = pixel_clock;
+        m_n->link_n = link_clock;
+        intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
+}
+void
+intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
+                 struct drm_display_mode *adjusted_mode)
+{
+        struct drm_device *dev = crtc->dev;
+        struct drm_mode_config *mode_config = &dev->mode_config;
+        struct drm_connector *connector;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        int lane_count = 4;
+        struct intel_dp_m_n m_n;
+        /*
+         * Find the lane count in the intel_output private
+         */
+        list_for_each_entry(connector, &mode_config->connector_list, head) {
+                struct intel_output *intel_output = to_intel_output(connector);
+                struct intel_dp_priv *dp_priv = intel_output->dev_priv;
+                if (!connector->encoder || connector->encoder->crtc != crtc)
+                        continue;
+                if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
+                        lane_count = dp_priv->lane_count;
+                        break;
+                }
+        }
+        /*
+         * Compute the GMCH and Link ratios. The '3' here is
+         * the number of bytes_per_pixel post-LUT, which we always
+         * set up for 8-bits of R/G/B, or 3 bytes total.
+         */
+        intel_dp_compute_m_n(3, lane_count,
+                             mode->clock, adjusted_mode->clock, &m_n);
+        if (intel_crtc->pipe == 0) {
+                I915_WRITE(PIPEA_GMCH_DATA_M,
+                       ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
+                       m_n.gmch_m);
+                I915_WRITE(PIPEA_GMCH_DATA_N,
+                       m_n.gmch_n);
+                I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
+                I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
+        } else {
+                I915_WRITE(PIPEB_GMCH_DATA_M,
+                       ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
+                       m_n.gmch_m);
+                I915_WRITE(PIPEB_GMCH_DATA_N,
+                       m_n.gmch_n);
+                I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
+                I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
+        }
+}
+static void
+intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
+                  struct drm_display_mode *adjusted_mode)
+{
+        struct intel_output *intel_output = enc_to_intel_output(encoder);
+        struct intel_dp_priv *dp_priv = intel_output->dev_priv;
+        struct drm_crtc *crtc = intel_output->enc.crtc;
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        dp_priv->DP = (DP_LINK_TRAIN_OFF |
+                        DP_VOLTAGE_0_4 |
+                        DP_PRE_EMPHASIS_0 |
+                        DP_SYNC_VS_HIGH |
+                        DP_SYNC_HS_HIGH);
+        switch (dp_priv->lane_count) {
+        case 1:
+                dp_priv->DP |= DP_PORT_WIDTH_1;
+                break;
+        case 2:
+                dp_priv->DP |= DP_PORT_WIDTH_2;
+                break;
+        case 4:
+                dp_priv->DP |= DP_PORT_WIDTH_4;
+                break;
+        }
+        if (dp_priv->has_audio)
+                dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
+        memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
+        dp_priv->link_configuration[0] = dp_priv->link_bw;
+        dp_priv->link_configuration[1] = dp_priv->lane_count;
+        /*
+         * Check for DPCD version > 1.1,
+         * enable enahanced frame stuff in that case
+         */
+        if (dp_priv->dpcd[0] >= 0x11) {
+                dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+                dp_priv->DP |= DP_ENHANCED_FRAMING;
+        }
+        if (intel_crtc->pipe == 1)
+                dp_priv->DP |= DP_PIPEB_SELECT;
+}
+static void
+intel_dp_dpms(struct drm_encoder *encoder, int mode)
+{
+        struct intel_output *intel_output = enc_to_intel_output(encoder);
+        struct intel_dp_priv *dp_priv = intel_output->dev_priv;
+        struct drm_device *dev = intel_output->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        uint32_t dp_reg = I915_READ(dp_priv->output_reg);
+        if (mode != DRM_MODE_DPMS_ON) {
+                if (dp_reg & DP_PORT_EN)
+                        intel_dp_link_down(intel_output, dp_priv->DP);
+        } else {
+                if (!(dp_reg & DP_PORT_EN))
+                        intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
+        }
+        dp_priv->dpms_mode = mode;
+}
+/*
+ * Fetch AUX CH registers 0x202 - 0x207 which contain
+ * link status information
+ */
+static bool
+intel_dp_get_link_status(struct intel_output *intel_output,
+                         uint8_t link_status[DP_LINK_STATUS_SIZE])
+{
+        int ret;
+        ret = intel_dp_aux_native_read(intel_output,
+                                       DP_LANE0_1_STATUS,
+                                       link_status, DP_LINK_STATUS_SIZE);
+        if (ret != DP_LINK_STATUS_SIZE)
+                return false;
+        return true;
+}
+static uint8_t
+intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
+                     int r)
+{
+        return link_status[r - DP_LANE0_1_STATUS];
+}
+static void
+intel_dp_save(struct drm_connector *connector)
+{
+        struct intel_output *intel_output = to_intel_output(connector);
+        struct drm_device *dev = intel_output->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_dp_priv *dp_priv = intel_output->dev_priv;
+        dp_priv->save_DP = I915_READ(dp_priv->output_reg);
+        intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET,
+                                 dp_priv->save_link_configuration,
+                                 sizeof (dp_priv->save_link_configuration));
+}
+static uint8_t
+intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
+                                 int lane)
+{
+        int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
+        int         s = ((lane & 1) ?
+                         DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
+                         DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
+        uint8_t l = intel_dp_link_status(link_status, i);
+        return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
+}
+static uint8_t
+intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
+                                      int lane)
+{
+        int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
+        int         s = ((lane & 1) ?
+                         DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
+                         DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
+        uint8_t l = intel_dp_link_status(link_status, i);
+        return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
+}
+#if 0
+static char     *voltage_names[] = {
+        "0.4V", "0.6V", "0.8V", "1.2V"
+};
+static char     *pre_emph_names[] = {
+        "0dB", "3.5dB", "6dB", "9.5dB"
+};
+static char     *link_train_names[] = {
+        "pattern 1", "pattern 2", "idle", "off"
+};
+#endif
+/*
+ * These are source-specific values; current Intel hardware supports
+ * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
+ */
+#define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
+static uint8_t
+intel_dp_pre_emphasis_max(uint8_t voltage_swing)
+{
+        switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+        case DP_TRAIN_VOLTAGE_SWING_400:
+                return DP_TRAIN_PRE_EMPHASIS_6;
+        case DP_TRAIN_VOLTAGE_SWING_600:
+                return DP_TRAIN_PRE_EMPHASIS_6;
+        case DP_TRAIN_VOLTAGE_SWING_800:
+                return DP_TRAIN_PRE_EMPHASIS_3_5;
+        case DP_TRAIN_VOLTAGE_SWING_1200:
+        default:
+                return DP_TRAIN_PRE_EMPHASIS_0;
+        }
+}
+static void
+intel_get_adjust_train(struct intel_output *intel_output,
+                       uint8_t link_status[DP_LINK_STATUS_SIZE],
+                       int lane_count,
+                       uint8_t train_set[4])
+{
+        uint8_t v = 0;
+        uint8_t p = 0;
+        int lane;
+        for (lane = 0; lane < lane_count; lane++) {
+                uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
+                uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
+                if (this_v > v)
+                        v = this_v;
+                if (this_p > p)
+                        p = this_p;
+        }
+        if (v >= I830_DP_VOLTAGE_MAX)
+                v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
+        if (p >= intel_dp_pre_emphasis_max(v))
+                p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+        for (lane = 0; lane < 4; lane++)
+                train_set[lane] = v | p;
+}
+static uint32_t
+intel_dp_signal_levels(uint8_t train_set, int lane_count)
+{
+        uint32_t        signal_levels = 0;
+        switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
+        case DP_TRAIN_VOLTAGE_SWING_400:
+        default:
+                signal_levels |= DP_VOLTAGE_0_4;
+                break;
+        case DP_TRAIN_VOLTAGE_SWING_600:
+                signal_levels |= DP_VOLTAGE_0_6;
+                break;
+        case DP_TRAIN_VOLTAGE_SWING_800:
+                signal_levels |= DP_VOLTAGE_0_8;
+                break;
+        case DP_TRAIN_VOLTAGE_SWING_1200:
+                signal_levels |= DP_VOLTAGE_1_2;
+                break;
+        }
+        switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
+        case DP_TRAIN_PRE_EMPHASIS_0:
+        default:
+                signal_levels |= DP_PRE_EMPHASIS_0;
+                break;
+        case DP_TRAIN_PRE_EMPHASIS_3_5:
+                signal_levels |= DP_PRE_EMPHASIS_3_5;
+                break;
+        case DP_TRAIN_PRE_EMPHASIS_6:
+                signal_levels |= DP_PRE_EMPHASIS_6;
+                break;
+        case DP_TRAIN_PRE_EMPHASIS_9_5:
+                signal_levels |= DP_PRE_EMPHASIS_9_5;
+                break;
+        }
+        return signal_levels;
+}
+static uint8_t
+intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
+                      int lane)
+{
+        int i = DP_LANE0_1_STATUS + (lane >> 1);
+        int s = (lane & 1) * 4;
+        uint8_t l = intel_dp_link_status(link_status, i);
+        return (l >> s) & 0xf;
+}
+/* Check for clock recovery is done on all channels */
+static bool
+intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
+{
+        int lane;
+        uint8_t lane_status;
+        for (lane = 0; lane < lane_count; lane++) {
+                lane_status = intel_get_lane_status(link_status, lane);
+                if ((lane_status & DP_LANE_CR_DONE) == 0)
+                        return false;
+        }
+        return true;
+}
+/* Check to see if channel eq is done on all channels */
+#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
+                         DP_LANE_CHANNEL_EQ_DONE|\
+                         DP_LANE_SYMBOL_LOCKED)
+static bool
+intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
+{
+        uint8_t lane_align;
+        uint8_t lane_status;
+        int lane;
+        lane_align = intel_dp_link_status(link_status,
+                                          DP_LANE_ALIGN_STATUS_UPDATED);
+        if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
+                return false;
+        for (lane = 0; lane < lane_count; lane++) {
+                lane_status = intel_get_lane_status(link_status, lane);
+                if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
+                        return false;
+        }
+        return true;
+}
+static bool
+intel_dp_set_link_train(struct intel_output *intel_output,
+                        uint32_t dp_reg_value,
+                        uint8_t dp_train_pat,
+                        uint8_t train_set[4],
+                        bool first)
+{
+        struct drm_device *dev = intel_output->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_dp_priv *dp_priv = intel_output->dev_priv;
+        int ret;
+        I915_WRITE(dp_priv->output_reg, dp_reg_value);
+        POSTING_READ(dp_priv->output_reg);
+        if (first)
+                intel_wait_for_vblank(dev);
+        intel_dp_aux_native_write_1(intel_output,
+                                    DP_TRAINING_PATTERN_SET,
+                                    dp_train_pat);
+        ret = intel_dp_aux_native_write(intel_output,
+                                        DP_TRAINING_LANE0_SET, train_set, 4);
+        if (ret != 4)
+                return false;
+        return true;
+}
+static void
+intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
+                    uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
+{
+        struct drm_device *dev = intel_output->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_dp_priv *dp_priv = intel_output->dev_priv;
+        uint8_t train_set[4];
+        uint8_t link_status[DP_LINK_STATUS_SIZE];
+        int i;
+        uint8_t voltage;
+        bool clock_recovery = false;
+        bool channel_eq = false;
+        bool first = true;
+        int tries;
+        /* Write the link configuration data */
+        intel_dp_aux_native_write(intel_output, 0x100,
+                                  link_configuration, DP_LINK_CONFIGURATION_SIZE);
+        DP |= DP_PORT_EN;
+        DP &= ~DP_LINK_TRAIN_MASK;
+        memset(train_set, 0, 4);
+        voltage = 0xff;
+        tries = 0;
+        clock_recovery = false;
+        for (;;) {
+                /* Use train_set[0] to set the voltage and pre emphasis values */
+                uint32_t    signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
+                DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
+                if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1,
+                                             DP_TRAINING_PATTERN_1, train_set, first))
+                        break;
+                first = false;
+                /* Set training pattern 1 */
+                udelay(100);
+                if (!intel_dp_get_link_status(intel_output, link_status))
+                        break;
+                if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
+                        clock_recovery = true;
+                        break;
+                }
+                /* Check to see if we've tried the max voltage */
+                for (i = 0; i < dp_priv->lane_count; i++)
+                        if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
+                                break;
+                if (i == dp_priv->lane_count)
+                        break;
+                /* Check to see if we've tried the same voltage 5 times */
+                if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
+                        ++tries;
+                        if (tries == 5)
+                                break;
+                } else
+                        tries = 0;
+                voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
+                /* Compute new train_set as requested by target */
+                intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
+        }
+        /* channel equalization */
+        tries = 0;
+        channel_eq = false;
+        for (;;) {
+                /* Use train_set[0] to set the voltage and pre emphasis values */
+                uint32_t    signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
+                DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
+                /* channel eq pattern */
+                if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2,
+                                             DP_TRAINING_PATTERN_2, train_set,
+                                             false))
+                        break;
+                udelay(400);
+                if (!intel_dp_get_link_status(intel_output, link_status))
+                        break;
+                if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
+                        channel_eq = true;
+                        break;
+                }
+                /* Try 5 times */
+                if (tries > 5)
+                        break;
+                /* Compute new train_set as requested by target */
+                intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
+                ++tries;
+        }
+        I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
+        POSTING_READ(dp_priv->output_reg);
+        intel_dp_aux_native_write_1(intel_output,
+                                    DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
+}
+static void
+intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
+{
+        struct drm_device *dev = intel_output->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_dp_priv *dp_priv = intel_output->dev_priv;
+        I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
+        POSTING_READ(dp_priv->output_reg);
+}
+static void
+intel_dp_restore(struct drm_connector *connector)
+{
+        struct intel_output *intel_output = to_intel_output(connector);
+        struct intel_dp_priv *dp_priv = intel_output->dev_priv;
+        if (dp_priv->save_DP & DP_PORT_EN)
+                intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration);
+        else
+                intel_dp_link_down(intel_output,  dp_priv->save_DP);
+}
+/*
+ * According to DP spec
+ * 5.1.2:
+ *  1. Read DPCD
+ *  2. Configure link according to Receiver Capabilities
+ *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
+ *  4. Check link status on receipt of hot-plug interrupt
+ */
+static void
+intel_dp_check_link_status(struct intel_output *intel_output)
+{
+        struct intel_dp_priv *dp_priv = intel_output->dev_priv;
+        uint8_t link_status[DP_LINK_STATUS_SIZE];
+        if (!intel_output->enc.crtc)
+                return;
+        if (!intel_dp_get_link_status(intel_output, link_status)) {
+                intel_dp_link_down(intel_output, dp_priv->DP);
+                return;
+        }
+        if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
+                intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
+}
+/**
+ * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
+ *
+ * \return true if DP port is connected.
+ * \return false if DP port is disconnected.
+ */
+static enum drm_connector_status
+intel_dp_detect(struct drm_connector *connector)
+{
+        struct intel_output *intel_output = to_intel_output(connector);
+        struct drm_device *dev = intel_output->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_dp_priv *dp_priv = intel_output->dev_priv;
+        uint32_t temp, bit;
+        enum drm_connector_status status;
+        dp_priv->has_audio = false;
+        temp = I915_READ(PORT_HOTPLUG_EN);
+        I915_WRITE(PORT_HOTPLUG_EN,
+               temp |
+               DPB_HOTPLUG_INT_EN |
+               DPC_HOTPLUG_INT_EN |
+               DPD_HOTPLUG_INT_EN);
+        POSTING_READ(PORT_HOTPLUG_EN);
+        switch (dp_priv->output_reg) {
+        case DP_B:
+                bit = DPB_HOTPLUG_INT_STATUS;
+                break;
+        case DP_C:
+                bit = DPC_HOTPLUG_INT_STATUS;
+                break;
+        case DP_D:
+                bit = DPD_HOTPLUG_INT_STATUS;
+                break;
+        default:
+                return connector_status_unknown;
+        }
+        temp = I915_READ(PORT_HOTPLUG_STAT);
+        if ((temp & bit) == 0)
+                return connector_status_disconnected;
+        status = connector_status_disconnected;
+        if (intel_dp_aux_native_read(intel_output,
+                                     0x000, dp_priv->dpcd,
+                                     sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
+        {
+                if (dp_priv->dpcd[0] != 0)
+                        status = connector_status_connected;
+        }
+        return status;
+}
+static int intel_dp_get_modes(struct drm_connector *connector)
+{
+        struct intel_output *intel_output = to_intel_output(connector);
+        /* We should parse the EDID data and find out if it has an audio sink
+         */
+        return intel_ddc_get_modes(intel_output);
+}
+static void
+intel_dp_destroy (struct drm_connector *connector)
+{
+        struct intel_output *intel_output = to_intel_output(connector);
+        if (intel_output->i2c_bus)
+                intel_i2c_destroy(intel_output->i2c_bus);
+        drm_sysfs_connector_remove(connector);
+        drm_connector_cleanup(connector);
+        kfree(intel_output);
+}
+static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
+        .dpms = intel_dp_dpms,
+        .mode_fixup = intel_dp_mode_fixup,
+        .prepare = intel_encoder_prepare,
+        .mode_set = intel_dp_mode_set,
+        .commit = intel_encoder_commit,
+};
+static const struct drm_connector_funcs intel_dp_connector_funcs = {
+        .dpms = drm_helper_connector_dpms,
+        .save = intel_dp_save,
+        .restore = intel_dp_restore,
+        .detect = intel_dp_detect,
+        .fill_modes = drm_helper_probe_single_connector_modes,
+        .destroy = intel_dp_destroy,
+};
+static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
+        .get_modes = intel_dp_get_modes,
+        .mode_valid = intel_dp_mode_valid,
+        .best_encoder = intel_best_encoder,
+};
+static void intel_dp_enc_destroy(struct drm_encoder *encoder)
+{
+        drm_encoder_cleanup(encoder);
+}
+static const struct drm_encoder_funcs intel_dp_enc_funcs = {
+        .destroy = intel_dp_enc_destroy,
+};
+void
+intel_dp_hot_plug(struct intel_output *intel_output)
+{
+        struct intel_dp_priv *dp_priv = intel_output->dev_priv;
+        if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
+                intel_dp_check_link_status(intel_output);
+}
+void
+intel_dp_init(struct drm_device *dev, int output_reg)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct drm_connector *connector;
+        struct intel_output *intel_output;
+        struct intel_dp_priv *dp_priv;
+        intel_output = kcalloc(sizeof(struct intel_output) + 
+                               sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
+        if (!intel_output)
+                return;
+        dp_priv = (struct intel_dp_priv *)(intel_output + 1);
+        connector = &intel_output->base;
+        drm_connector_init(dev, connector, &intel_dp_connector_funcs,
+                           DRM_MODE_CONNECTOR_DisplayPort);
+        drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
+        intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
+        connector->interlace_allowed = true;
+        connector->doublescan_allowed = 0;
+        dp_priv->intel_output = intel_output;
+        dp_priv->output_reg = output_reg;
+        dp_priv->has_audio = false;
+        dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
+        intel_output->dev_priv = dp_priv;
+        drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs,
+                         DRM_MODE_ENCODER_TMDS);
+        drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs);
+        drm_mode_connector_attach_encoder(&intel_output->base,
+                                          &intel_output->enc);
+        drm_sysfs_connector_add(connector);
+        /* Set up the DDC bus. */
+        intel_dp_i2c_init(intel_output,
+                          (output_reg == DP_B) ? "DPDDC-B" :
+                          (output_reg == DP_C) ? "DPDDC-C" : "DPDDC-D");
+        intel_output->ddc_bus = &dp_priv->adapter;
+        intel_output->hot_plug = intel_dp_hot_plug;
+        /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
+         * 0xd.  Failure to do so will result in spurious interrupts being
+         * generated on the port when a cable is not attached.
+         */
+        if (IS_G4X(dev) && !IS_GM45(dev)) {
+                u32 temp = I915_READ(PEG_BAND_GAP_DATA);
+                I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
+        }
+}
diff --git a/drivers/gpu/drm/i915/intel_dp.h b/drivers/gpu/drm/i915/intel_dp.h
new file mode 100644
index 000000000000..2b38054d3b6d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright © 2008 Keith Packard
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission.  The copyright holders make no representations
+ * about the suitability of this software for any purpose.  It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+#ifndef _INTEL_DP_H_
+#define _INTEL_DP_H_
+/* From the VESA DisplayPort spec */
+#define AUX_NATIVE_WRITE        0x8
+#define AUX_NATIVE_READ         0x9
+#define AUX_I2C_WRITE           0x0
+#define AUX_I2C_READ            0x1
+#define AUX_I2C_STATUS          0x2
+#define AUX_I2C_MOT             0x4
+#define AUX_NATIVE_REPLY_ACK    (0x0 << 4)
+#define AUX_NATIVE_REPLY_NACK   (0x1 << 4)
+#define AUX_NATIVE_REPLY_DEFER  (0x2 << 4)
+#define AUX_NATIVE_REPLY_MASK   (0x3 << 4)
+#define AUX_I2C_REPLY_ACK       (0x0 << 6)
+#define AUX_I2C_REPLY_NACK      (0x1 << 6)
+#define AUX_I2C_REPLY_DEFER     (0x2 << 6)
+#define AUX_I2C_REPLY_MASK      (0x3 << 6)
+/* AUX CH addresses */
+#define DP_LINK_BW_SET          0x100
+# define DP_LINK_BW_1_62                    0x06
+# define DP_LINK_BW_2_7                     0x0a
+#define DP_LANE_COUNT_SET       0x101
+# define DP_LANE_COUNT_MASK                 0x0f
+# define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
+#define DP_TRAINING_PATTERN_SET 0x102
+# define DP_TRAINING_PATTERN_DISABLE        0
+# define DP_TRAINING_PATTERN_1              1
+# define DP_TRAINING_PATTERN_2              2
+# define DP_TRAINING_PATTERN_MASK           0x3
+# define DP_LINK_QUAL_PATTERN_DISABLE       (0 << 2)
+# define DP_LINK_QUAL_PATTERN_D10_2         (1 << 2)
+# define DP_LINK_QUAL_PATTERN_ERROR_RATE    (2 << 2)
+# define DP_LINK_QUAL_PATTERN_PRBS7         (3 << 2)
+# define DP_LINK_QUAL_PATTERN_MASK          (3 << 2)
+# define DP_RECOVERED_CLOCK_OUT_EN          (1 << 4)
+# define DP_LINK_SCRAMBLING_DISABLE         (1 << 5)
+# define DP_SYMBOL_ERROR_COUNT_BOTH         (0 << 6)
+# define DP_SYMBOL_ERROR_COUNT_DISPARITY    (1 << 6)
+# define DP_SYMBOL_ERROR_COUNT_SYMBOL       (2 << 6)
+# define DP_SYMBOL_ERROR_COUNT_MASK         (3 << 6)
+#define DP_TRAINING_LANE0_SET               0x103
+#define DP_TRAINING_LANE1_SET               0x104
+#define DP_TRAINING_LANE2_SET               0x105
+#define DP_TRAINING_LANE3_SET               0x106
+# define DP_TRAIN_VOLTAGE_SWING_MASK        0x3
+# define DP_TRAIN_VOLTAGE_SWING_SHIFT       0
+# define DP_TRAIN_MAX_SWING_REACHED         (1 << 2)
+# define DP_TRAIN_VOLTAGE_SWING_400         (0 << 0)
+# define DP_TRAIN_VOLTAGE_SWING_600         (1 << 0)
+# define DP_TRAIN_VOLTAGE_SWING_800         (2 << 0)
+# define DP_TRAIN_VOLTAGE_SWING_1200        (3 << 0)
+# define DP_TRAIN_PRE_EMPHASIS_MASK         (3 << 3)
+# define DP_TRAIN_PRE_EMPHASIS_0            (0 << 3)
+# define DP_TRAIN_PRE_EMPHASIS_3_5          (1 << 3)
+# define DP_TRAIN_PRE_EMPHASIS_6            (2 << 3)
+# define DP_TRAIN_PRE_EMPHASIS_9_5          (3 << 3)
+# define DP_TRAIN_PRE_EMPHASIS_SHIFT        3
+# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
+#define DP_DOWNSPREAD_CTRL                  0x107
+# define DP_SPREAD_AMP_0_5                  (1 << 4)
+#define DP_MAIN_LINK_CHANNEL_CODING_SET     0x108
+# define DP_SET_ANSI_8B10B                  (1 << 0)
+#define DP_LANE0_1_STATUS                   0x202
+#define DP_LANE2_3_STATUS                   0x203
+# define DP_LANE_CR_DONE                    (1 << 0)
+# define DP_LANE_CHANNEL_EQ_DONE            (1 << 1)
+# define DP_LANE_SYMBOL_LOCKED              (1 << 2)
+#define DP_LANE_ALIGN_STATUS_UPDATED        0x204
+#define DP_INTERLANE_ALIGN_DONE             (1 << 0)
+#define DP_DOWNSTREAM_PORT_STATUS_CHANGED   (1 << 6)
+#define DP_LINK_STATUS_UPDATED              (1 << 7)
+#define DP_SINK_STATUS                      0x205
+#define DP_RECEIVE_PORT_0_STATUS            (1 << 0)
+#define DP_RECEIVE_PORT_1_STATUS            (1 << 1)
+#define DP_ADJUST_REQUEST_LANE0_1           0x206
+#define DP_ADJUST_REQUEST_LANE2_3           0x207
+#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK  0x03
+#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
+#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK   0x0c
+#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT  2
+#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK  0x30
+#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
+#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
+#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
+struct i2c_algo_dp_aux_data {
+        bool running;
+        u16 address;
+        int (*aux_ch) (struct i2c_adapter *adapter,
+                       uint8_t *send, int send_bytes,
+                       uint8_t *recv, int recv_bytes);
+};
+int
+i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
+#endif /* _INTEL_DP_H_ */
diff --git a/drivers/gpu/drm/i915/intel_dp_i2c.c b/drivers/gpu/drm/i915/intel_dp_i2c.c
new file mode 100644
index 000000000000..a63b6f57d2d4
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_i2c.c
@@ -0,0 +1,273 @@
+/*
+ * Copyright © 2009 Keith Packard
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission.  The copyright holders make no representations
+ * about the suitability of this software for any purpose.  It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/i2c.h>
+#include "intel_dp.h"
+#include "drmP.h"
+/* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
+#define MODE_I2C_START  1
+#define MODE_I2C_WRITE  2
+#define MODE_I2C_READ   4
+#define MODE_I2C_STOP   8
+static int
+i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
+                            uint8_t write_byte, uint8_t *read_byte)
+{
+        struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+        uint16_t address = algo_data->address;
+        uint8_t msg[5];
+        uint8_t reply[2];
+        int msg_bytes;
+        int reply_bytes;
+        int ret;
+        /* Set up the command byte */
+        if (mode & MODE_I2C_READ)
+                msg[0] = AUX_I2C_READ << 4;
+        else
+                msg[0] = AUX_I2C_WRITE << 4;
+        if (!(mode & MODE_I2C_STOP))
+                msg[0] |= AUX_I2C_MOT << 4;
+        msg[1] = address >> 8;
+        msg[2] = address;
+        switch (mode) {
+        case MODE_I2C_WRITE:
+                msg[3] = 0;
+                msg[4] = write_byte;
+                msg_bytes = 5;
+                reply_bytes = 1;
+                break;
+        case MODE_I2C_READ:
+                msg[3] = 0;
+                msg_bytes = 4;
+                reply_bytes = 2;
+                break;
+        default:
+                msg_bytes = 3;
+                reply_bytes = 1;
+                break;
+        }
+        for (;;) {
+                ret = (*algo_data->aux_ch)(adapter,
+                                           msg, msg_bytes,
+                                           reply, reply_bytes);
+                if (ret < 0) {
+                        DRM_DEBUG("aux_ch failed %d\n", ret);
+                        return ret;
+                }
+                switch (reply[0] & AUX_I2C_REPLY_MASK) {
+                case AUX_I2C_REPLY_ACK:
+                        if (mode == MODE_I2C_READ) {
+                                *read_byte = reply[1];
+                        }
+                        return reply_bytes - 1;
+                case AUX_I2C_REPLY_NACK:
+                        DRM_DEBUG("aux_ch nack\n");
+                        return -EREMOTEIO;
+                case AUX_I2C_REPLY_DEFER:
+                        DRM_DEBUG("aux_ch defer\n");
+                        udelay(100);
+                        break;
+                default:
+                        DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
+                        return -EREMOTEIO;
+                }
+        }
+}
+/*
+ * I2C over AUX CH
+ */
+/*
+ * Send the address. If the I2C link is running, this 'restarts'
+ * the connection with the new address, this is used for doing
+ * a write followed by a read (as needed for DDC)
+ */
+static int
+i2c_algo_dp_aux_address(struct i2c_adapter *adapter, u16 address, bool reading)
+{
+        struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+        int mode = MODE_I2C_START;
+        int ret;
+        if (reading)
+                mode |= MODE_I2C_READ;
+        else
+                mode |= MODE_I2C_WRITE;
+        algo_data->address = address;
+        algo_data->running = true;
+        ret = i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
+        return ret;
+}
+/*
+ * Stop the I2C transaction. This closes out the link, sending
+ * a bare address packet with the MOT bit turned off
+ */
+static void
+i2c_algo_dp_aux_stop(struct i2c_adapter *adapter, bool reading)
+{
+        struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+        int mode = MODE_I2C_STOP;
+        if (reading)
+                mode |= MODE_I2C_READ;
+        else
+                mode |= MODE_I2C_WRITE;
+        if (algo_data->running) {
+                (void) i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
+                algo_data->running = false;
+        }
+}
+/*
+ * Write a single byte to the current I2C address, the
+ * the I2C link must be running or this returns -EIO
+ */
+static int
+i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter, u8 byte)
+{
+        struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+        int ret;
+        if (!algo_data->running)
+                return -EIO;
+        ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_WRITE, byte, NULL);
+        return ret;
+}
+/*
+ * Read a single byte from the current I2C address, the
+ * I2C link must be running or this returns -EIO
+ */
+static int
+i2c_algo_dp_aux_get_byte(struct i2c_adapter *adapter, u8 *byte_ret)
+{
+        struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+        int ret;
+        if (!algo_data->running)
+                return -EIO;
+        ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_READ, 0, byte_ret);
+        return ret;
+}
+static int
+i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
+                     struct i2c_msg *msgs,
+                     int num)
+{
+        int ret = 0;
+        bool reading = false;
+        int m;
+        int b;
+        for (m = 0; m < num; m++) {
+                u16 len = msgs[m].len;
+                u8 *buf = msgs[m].buf;
+                reading = (msgs[m].flags & I2C_M_RD) != 0;
+                ret = i2c_algo_dp_aux_address(adapter, msgs[m].addr, reading);
+                if (ret < 0)
+                        break;
+                if (reading) {
+                        for (b = 0; b < len; b++) {
+                                ret = i2c_algo_dp_aux_get_byte(adapter, &buf[b]);
+                                if (ret < 0)
+                                        break;
+                        }
+                } else {
+                        for (b = 0; b < len; b++) {
+                                ret = i2c_algo_dp_aux_put_byte(adapter, buf[b]);
+                                if (ret < 0)
+                                        break;
+                        }
+                }
+                if (ret < 0)
+                        break;
+        }
+        if (ret >= 0)
+                ret = num;
+        i2c_algo_dp_aux_stop(adapter, reading);
+        DRM_DEBUG("dp_aux_xfer return %d\n", ret);
+        return ret;
+}
+static u32
+i2c_algo_dp_aux_functionality(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
+               I2C_FUNC_SMBUS_READ_BLOCK_DATA |
+               I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
+               I2C_FUNC_10BIT_ADDR;
+}
+static const struct i2c_algorithm i2c_dp_aux_algo = {
+        .master_xfer    = i2c_algo_dp_aux_xfer,
+        .functionality  = i2c_algo_dp_aux_functionality,
+};
+static void
+i2c_dp_aux_reset_bus(struct i2c_adapter *adapter)
+{
+        (void) i2c_algo_dp_aux_address(adapter, 0, false);
+        (void) i2c_algo_dp_aux_stop(adapter, false);
+                                           
+}
+static int
+i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter)
+{
+        adapter->algo = &i2c_dp_aux_algo;
+        adapter->retries = 3;
+        i2c_dp_aux_reset_bus(adapter);
+        return 0;
+}
+int
+i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
+{
+        int error;
+        
+        error = i2c_dp_aux_prepare_bus(adapter);
+        if (error)
+                return error;
+        error = i2c_add_adapter(adapter);
+        return error;
+}
+EXPORT_SYMBOL(i2c_dp_aux_add_bus);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index cd4b9c5f715e..004541c935a8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -54,6 +54,7 @@
 #define INTEL_OUTPUT_LVDS 4
 #define INTEL_OUTPUT_TVOUT 5
 #define INTEL_OUTPUT_HDMI 6
+#define INTEL_OUTPUT_DISPLAYPORT 7
 #define INTEL_DVO_CHIP_NONE 0
 #define INTEL_DVO_CHIP_LVDS 1
@@ -65,7 +66,6 @@ struct intel_i2c_chan {
        u32 reg; /* GPIO reg */
        struct i2c_adapter adapter;
        struct i2c_algo_bit_data algo;
-        u8 slave_addr;
 };
 struct intel_framebuffer {
@@ -79,11 +79,12 @@ struct intel_output {
        struct drm_encoder enc;
        int type;
-        struct intel_i2c_chan *i2c_bus; /* for control functions */
+        struct i2c_adapter *i2c_bus;
-        struct intel_i2c_chan *ddc_bus; /* for DDC only stuff */
+        struct i2c_adapter *ddc_bus;
        bool load_detect_temp;
        bool needs_tv_clock;
        void *dev_priv;
+        void (*hot_plug)(struct intel_output *);
 };
 struct intel_crtc {
@@ -104,9 +105,9 @@ struct intel_crtc {
 #define enc_to_intel_output(x) container_of(x, struct intel_output, enc)
 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
-struct intel_i2c_chan *intel_i2c_create(struct drm_device *dev, const u32 reg,
+struct i2c_adapter *intel_i2c_create(struct drm_device *dev, const u32 reg,
-                                        const char *name);
+                                     const char *name);
-void intel_i2c_destroy(struct intel_i2c_chan *chan);
+void intel_i2c_destroy(struct i2c_adapter *adapter);
 int intel_ddc_get_modes(struct intel_output *intel_output);
 extern bool intel_ddc_probe(struct intel_output *intel_output);
 void intel_i2c_quirk_set(struct drm_device *dev, bool enable);
@@ -116,6 +117,10 @@ extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
 extern void intel_dvo_init(struct drm_device *dev);
 extern void intel_tv_init(struct drm_device *dev);
 extern void intel_lvds_init(struct drm_device *dev);
+extern void intel_dp_init(struct drm_device *dev, int dp_reg);
+void
+intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
+                 struct drm_display_mode *adjusted_mode);
 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
 extern void intel_encoder_prepare (struct drm_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 1ee3007d6ec0..13bff20930e8 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -384,10 +384,9 @@ void intel_dvo_init(struct drm_device *dev)
 {
        struct intel_output *intel_output;
        struct intel_dvo_device *dvo;
-        struct intel_i2c_chan *i2cbus = NULL;
+        struct i2c_adapter *i2cbus = NULL;
        int ret = 0;
        int i;
-        int gpio_inited = 0;
        int encoder_type = DRM_MODE_ENCODER_NONE;
        intel_output = kzalloc (sizeof(struct intel_output), GFP_KERNEL);
        if (!intel_output)
@@ -420,14 +419,11 @@ void intel_dvo_init(struct drm_device *dev)
                 * It appears that everything is on GPIOE except for panels
                 * on i830 laptops, which are on GPIOB (DVOA).
                 */
-                if (gpio_inited != gpio) {
+                if (i2cbus != NULL)
-                        if (i2cbus != NULL)
+                        intel_i2c_destroy(i2cbus);
-                                intel_i2c_destroy(i2cbus);
+                if (!(i2cbus = intel_i2c_create(dev, gpio,
-                        if (!(i2cbus = intel_i2c_create(dev, gpio,
+                        gpio == GPIOB ? "DVOI2C_B" : "DVOI2C_E"))) {
-                                gpio == GPIOB ? "DVOI2C_B" : "DVOI2C_E"))) {
+                        continue;
-                                continue;
-                        }
-                        gpio_inited = gpio;
                }
                if (dvo->dev_ops!= NULL)
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 1af7d68e3807..1d30802e773e 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -453,7 +453,7 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
        size = ALIGN(size, PAGE_SIZE);
        fbo = drm_gem_object_alloc(dev, size);
        if (!fbo) {
-                printk(KERN_ERR "failed to allocate framebuffer\n");
+                DRM_ERROR("failed to allocate framebuffer\n");
                ret = -ENOMEM;
                goto out;
        }
@@ -610,8 +610,8 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
        par->dev = dev;
        /* To allow resizeing without swapping buffers */
-        printk("allocated %dx%d fb: 0x%08x, bo %p\n", intel_fb->base.width,
+        DRM_DEBUG("allocated %dx%d fb: 0x%08x, bo %p\n", intel_fb->base.width,
-               intel_fb->base.height, obj_priv->gtt_offset, fbo);
+                  intel_fb->base.height, obj_priv->gtt_offset, fbo);
        mutex_unlock(&dev->struct_mutex);
        return 0;
@@ -698,13 +698,13 @@ static int intelfb_multi_fb_probe_crtc(struct drm_device *dev, struct drm_crtc *
        } else
                intelfb_set_par(info);
-        printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
+        DRM_INFO("fb%d: %s frame buffer device\n", info->node,
               info->fix.id);
        /* Switch back to kernel console on panic */
        kernelfb_mode = *modeset;
        atomic_notifier_chain_register(&panic_notifier_list, &paniced);
-        printk(KERN_INFO "registered panic notifier\n");
+        DRM_DEBUG("registered panic notifier\n");
        return 0;
 }
@@ -852,13 +852,13 @@ static int intelfb_single_fb_probe(struct drm_device *dev)
        } else
                intelfb_set_par(info);
-        printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
+        DRM_INFO("fb%d: %s frame buffer device\n", info->node,
               info->fix.id);
        /* Switch back to kernel console on panic */
        kernelfb_mode = *modeset;
        atomic_notifier_chain_register(&panic_notifier_list, &paniced);
-        printk(KERN_INFO "registered panic notifier\n");
+        DRM_DEBUG("registered panic notifier\n");
        return 0;
 }
@@ -872,8 +872,8 @@ void intelfb_restore(void)
 {
        int ret;
        if ((ret = drm_crtc_helper_set_config(&kernelfb_mode)) != 0) {
-                printk(KERN_ERR "Failed to restore crtc configuration: %d\n",
+                DRM_ERROR("Failed to restore crtc configuration: %d\n",
-                       ret);
+                          ret);
        }
 }
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 4ea2a651b92c..9e30daae37dc 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -31,6 +31,7 @@
 #include "drmP.h"
 #include "drm.h"
 #include "drm_crtc.h"
+#include "drm_edid.h"
 #include "intel_drv.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
@@ -56,8 +57,7 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
        sdvox = SDVO_ENCODING_HDMI |
                SDVO_BORDER_ENABLE |
                SDVO_VSYNC_ACTIVE_HIGH |
-                SDVO_HSYNC_ACTIVE_HIGH |
+                SDVO_HSYNC_ACTIVE_HIGH;
-                SDVO_NULL_PACKETS_DURING_VSYNC;
        if (hdmi_priv->has_hdmi_sink)
                sdvox |= SDVO_AUDIO_ENABLE;
@@ -129,20 +129,26 @@ static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
        return true;
 }
-static void
+static enum drm_connector_status
-intel_hdmi_sink_detect(struct drm_connector *connector)
+intel_hdmi_edid_detect(struct drm_connector *connector)
 {
        struct intel_output *intel_output = to_intel_output(connector);
        struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv;
        struct edid *edid = NULL;
+        enum drm_connector_status status = connector_status_disconnected;
        edid = drm_get_edid(&intel_output->base,
-                            &intel_output->ddc_bus->adapter);
+                            intel_output->ddc_bus);
-        if (edid != NULL) {
+        hdmi_priv->has_hdmi_sink = false;
-                hdmi_priv->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
+        if (edid) {
-                kfree(edid);
+                if (edid->input & DRM_EDID_INPUT_DIGITAL) {
+                        status = connector_status_connected;
+                        hdmi_priv->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
+                }
                intel_output->base.display_info.raw_edid = NULL;
+                kfree(edid);
        }
+        return status;
 }
 static enum drm_connector_status
@@ -154,11 +160,7 @@ igdng_hdmi_detect(struct drm_connector *connector)
        /* FIXME hotplug detect */
        hdmi_priv->has_hdmi_sink = false;
-        intel_hdmi_sink_detect(connector);
+        return intel_hdmi_edid_detect(connector);
-        if (hdmi_priv->has_hdmi_sink)
-                return connector_status_connected;
-        else
-                return connector_status_disconnected;
 }
 static enum drm_connector_status
@@ -201,10 +203,9 @@ intel_hdmi_detect(struct drm_connector *connector)
                return connector_status_unknown;
        }
-        if ((I915_READ(PORT_HOTPLUG_STAT) & bit) != 0) {
+        if ((I915_READ(PORT_HOTPLUG_STAT) & bit) != 0)
-                intel_hdmi_sink_detect(connector);
+                return intel_hdmi_edid_detect(connector);
-                return connector_status_connected;
+        else
-        } else
                return connector_status_disconnected;
 }
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index f7061f68d050..62b8bead7652 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -124,6 +124,7 @@ static void set_data(void *data, int state_high)
 * @output: driver specific output device
 * @reg: GPIO reg to use
 * @name: name for this bus
+ * @slave_addr: slave address (if fixed)
 *
 * Creates and registers a new i2c bus with the Linux i2c layer, for use
 * in output probing and control (e.g. DDC or SDVO control functions).
@@ -139,8 +140,8 @@ static void set_data(void *data, int state_high)
 *   %GPIOH
 * see PRM for details on how these different busses are used.
 */
-struct intel_i2c_chan *intel_i2c_create(struct drm_device *dev, const u32 reg,
+struct i2c_adapter *intel_i2c_create(struct drm_device *dev, const u32 reg,
-                                        const char *name)
+                                     const char *name)
 {
        struct intel_i2c_chan *chan;
@@ -174,7 +175,7 @@ struct intel_i2c_chan *intel_i2c_create(struct drm_device *dev, const u32 reg,
        intel_i2c_quirk_set(dev, false);
        udelay(20);
-        return chan;
+        return &chan->adapter;
 out_free:
        kfree(chan);
@@ -187,11 +188,16 @@ out_free:
 *
 * Unregister the adapter from the i2c layer, then free the structure.
 */
-void intel_i2c_destroy(struct intel_i2c_chan *chan)
+void intel_i2c_destroy(struct i2c_adapter *adapter)
 {
-        if (!chan)
+        struct intel_i2c_chan *chan;
+        if (!adapter)
                return;
+        chan = container_of(adapter,
+                            struct intel_i2c_chan,
+                            adapter);
        i2c_del_adapter(&chan->adapter);
        kfree(chan);
 }
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index f073ed8432e8..9ab38efffecf 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -36,9 +36,25 @@
 #include "intel_drv.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
+#include <linux/acpi.h>
 #define I915_LVDS "i915_lvds"
+/*
+ * the following four scaling options are defined.
+ * #define DRM_MODE_SCALE_NON_GPU       0
+ * #define DRM_MODE_SCALE_FULLSCREEN    1
+ * #define DRM_MODE_SCALE_NO_SCALE      2
+ * #define DRM_MODE_SCALE_ASPECT        3
+ */
+/* Private structure for the integrated LVDS support */
+struct intel_lvds_priv {
+        int fitting_mode;
+        u32 pfit_control;
+        u32 pfit_pgm_ratios;
+};
 /**
 * Sets the backlight level.
 *
@@ -213,26 +229,45 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
                                  struct drm_display_mode *mode,
                                  struct drm_display_mode *adjusted_mode)
 {
+        /*
+         * float point operation is not supported . So the PANEL_RATIO_FACTOR
+         * is defined, which can avoid the float point computation when
+         * calculating the panel ratio.
+         */
+#define PANEL_RATIO_FACTOR 8192
        struct drm_device *dev = encoder->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
        struct drm_encoder *tmp_encoder;
+        struct intel_output *intel_output = enc_to_intel_output(encoder);
+        struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
+        u32 pfit_control = 0, pfit_pgm_ratios = 0;
+        int left_border = 0, right_border = 0, top_border = 0;
+        int bottom_border = 0;
+        bool border = 0;
+        int panel_ratio, desired_ratio, vert_scale, horiz_scale;
+        int horiz_ratio, vert_ratio;
+        u32 hsync_width, vsync_width;
+        u32 hblank_width, vblank_width;
+        u32 hsync_pos, vsync_pos;
        /* Should never happen!! */
        if (!IS_I965G(dev) && intel_crtc->pipe == 0) {
-                printk(KERN_ERR "Can't support LVDS on pipe A\n");
+                DRM_ERROR("Can't support LVDS on pipe A\n");
                return false;
        }
        /* Should never happen!! */
        list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) {
                if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) {
-                        printk(KERN_ERR "Can't enable LVDS and another "
+                        DRM_ERROR("Can't enable LVDS and another "
                               "encoder on the same pipe\n");
                        return false;
                }
        }
+        /* If we don't have a panel mode, there is nothing we can do */
+        if (dev_priv->panel_fixed_mode == NULL)
+                return true;
        /*
         * If we have timings from the BIOS for the panel, put them in
         * to the adjusted mode.  The CRTC will be set up for this mode,
@@ -256,6 +291,243 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
                drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
        }
+        /* Make sure pre-965s set dither correctly */
+        if (!IS_I965G(dev)) {
+                if (dev_priv->panel_wants_dither || dev_priv->lvds_dither)
+                        pfit_control |= PANEL_8TO6_DITHER_ENABLE;
+        }
+        /* Native modes don't need fitting */
+        if (adjusted_mode->hdisplay == mode->hdisplay &&
+                        adjusted_mode->vdisplay == mode->vdisplay) {
+                pfit_pgm_ratios = 0;
+                border = 0;
+                goto out;
+        }
+        /* 965+ wants fuzzy fitting */
+        if (IS_I965G(dev))
+                pfit_control |= (intel_crtc->pipe << PFIT_PIPE_SHIFT) |
+                                        PFIT_FILTER_FUZZY;
+        hsync_width = adjusted_mode->crtc_hsync_end -
+                                        adjusted_mode->crtc_hsync_start;
+        vsync_width = adjusted_mode->crtc_vsync_end -
+                                        adjusted_mode->crtc_vsync_start;
+        hblank_width = adjusted_mode->crtc_hblank_end -
+                                        adjusted_mode->crtc_hblank_start;
+        vblank_width = adjusted_mode->crtc_vblank_end -
+                                        adjusted_mode->crtc_vblank_start;
+        /*
+         * Deal with panel fitting options. Figure out how to stretch the
+         * image based on its aspect ratio & the current panel fitting mode.
+         */
+        panel_ratio = adjusted_mode->hdisplay * PANEL_RATIO_FACTOR /
+                                adjusted_mode->vdisplay;
+        desired_ratio = mode->hdisplay * PANEL_RATIO_FACTOR /
+                                mode->vdisplay;
+        /*
+         * Enable automatic panel scaling for non-native modes so that they fill
+         * the screen.  Should be enabled before the pipe is enabled, according
+         * to register description and PRM.
+         * Change the value here to see the borders for debugging
+         */
+        I915_WRITE(BCLRPAT_A, 0);
+        I915_WRITE(BCLRPAT_B, 0);
+        switch (lvds_priv->fitting_mode) {
+        case DRM_MODE_SCALE_NO_SCALE:
+                /*
+                 * For centered modes, we have to calculate border widths &
+                 * heights and modify the values programmed into the CRTC.
+                 */
+                left_border = (adjusted_mode->hdisplay - mode->hdisplay) / 2;
+                right_border = left_border;
+                if (mode->hdisplay & 1)
+                        right_border++;
+                top_border = (adjusted_mode->vdisplay - mode->vdisplay) / 2;
+                bottom_border = top_border;
+                if (mode->vdisplay & 1)
+                        bottom_border++;
+                /* Set active & border values */
+                adjusted_mode->crtc_hdisplay = mode->hdisplay;
+                /* Keep the boder be even */
+                if (right_border & 1)
+                        right_border++;
+                /* use the border directly instead of border minuse one */
+                adjusted_mode->crtc_hblank_start = mode->hdisplay +
+                                                right_border;
+                /* keep the blank width constant */
+                adjusted_mode->crtc_hblank_end =
+                        adjusted_mode->crtc_hblank_start + hblank_width;
+                /* get the hsync pos relative to hblank start */
+                hsync_pos = (hblank_width - hsync_width) / 2;
+                /* keep the hsync pos be even */
+                if (hsync_pos & 1)
+                        hsync_pos++;
+                adjusted_mode->crtc_hsync_start =
+                                adjusted_mode->crtc_hblank_start + hsync_pos;
+                /* keep the hsync width constant */
+                adjusted_mode->crtc_hsync_end =
+                                adjusted_mode->crtc_hsync_start + hsync_width;
+                adjusted_mode->crtc_vdisplay = mode->vdisplay;
+                /* use the border instead of border minus one */
+                adjusted_mode->crtc_vblank_start = mode->vdisplay +
+                                                bottom_border;
+                /* keep the vblank width constant */
+                adjusted_mode->crtc_vblank_end =
+                                adjusted_mode->crtc_vblank_start + vblank_width;
+                /* get the vsync start postion relative to vblank start */
+                vsync_pos = (vblank_width - vsync_width) / 2;
+                adjusted_mode->crtc_vsync_start =
+                                adjusted_mode->crtc_vblank_start + vsync_pos;
+                /* keep the vsync width constant */
+                adjusted_mode->crtc_vsync_end =
+                                adjusted_mode->crtc_vblank_start + vsync_width;
+                border = 1;
+                break;
+        case DRM_MODE_SCALE_ASPECT:
+                /* Scale but preserve the spect ratio */
+                pfit_control |= PFIT_ENABLE;
+                if (IS_I965G(dev)) {
+                        /* 965+ is easy, it does everything in hw */
+                        if (panel_ratio > desired_ratio)
+                                pfit_control |= PFIT_SCALING_PILLAR;
+                        else if (panel_ratio < desired_ratio)
+                                pfit_control |= PFIT_SCALING_LETTER;
+                        else
+                                pfit_control |= PFIT_SCALING_AUTO;
+                } else {
+                        /*
+                         * For earlier chips we have to calculate the scaling
+                         * ratio by hand and program it into the
+                         * PFIT_PGM_RATIO register
+                         */
+                        u32 horiz_bits, vert_bits, bits = 12;
+                        horiz_ratio = mode->hdisplay * PANEL_RATIO_FACTOR/
+                                                adjusted_mode->hdisplay;
+                        vert_ratio = mode->vdisplay * PANEL_RATIO_FACTOR/
+                                                adjusted_mode->vdisplay;
+                        horiz_scale = adjusted_mode->hdisplay *
+                                        PANEL_RATIO_FACTOR / mode->hdisplay;
+                        vert_scale = adjusted_mode->vdisplay *
+                                        PANEL_RATIO_FACTOR / mode->vdisplay;
+                        /* retain aspect ratio */
+                        if (panel_ratio > desired_ratio) { /* Pillar */
+                                u32 scaled_width;
+                                scaled_width = mode->hdisplay * vert_scale /
+                                                PANEL_RATIO_FACTOR;
+                                horiz_ratio = vert_ratio;
+                                pfit_control |= (VERT_AUTO_SCALE |
+                                                 VERT_INTERP_BILINEAR |
+                                                 HORIZ_INTERP_BILINEAR);
+                                /* Pillar will have left/right borders */
+                                left_border = (adjusted_mode->hdisplay -
+                                                scaled_width) / 2;
+                                right_border = left_border;
+                                if (mode->hdisplay & 1) /* odd resolutions */
+                                        right_border++;
+                                /* keep the border be even */
+                                if (right_border & 1)
+                                        right_border++;
+                                adjusted_mode->crtc_hdisplay = scaled_width;
+                                /* use border instead of border minus one */
+                                adjusted_mode->crtc_hblank_start =
+                                        scaled_width + right_border;
+                                /* keep the hblank width constant */
+                                adjusted_mode->crtc_hblank_end =
+                                        adjusted_mode->crtc_hblank_start +
+                                                        hblank_width;
+                                /*
+                                 * get the hsync start pos relative to
+                                 * hblank start
+                                 */
+                                hsync_pos = (hblank_width - hsync_width) / 2;
+                                /* keep the hsync_pos be even */
+                                if (hsync_pos & 1)
+                                        hsync_pos++;
+                                adjusted_mode->crtc_hsync_start =
+                                        adjusted_mode->crtc_hblank_start +
+                                                        hsync_pos;
+                                /* keept hsync width constant */
+                                adjusted_mode->crtc_hsync_end =
+                                        adjusted_mode->crtc_hsync_start +
+                                                        hsync_width;
+                                border = 1;
+                        } else if (panel_ratio < desired_ratio) { /* letter */
+                                u32 scaled_height = mode->vdisplay *
+                                        horiz_scale / PANEL_RATIO_FACTOR;
+                                vert_ratio = horiz_ratio;
+                                pfit_control |= (HORIZ_AUTO_SCALE |
+                                                 VERT_INTERP_BILINEAR |
+                                                 HORIZ_INTERP_BILINEAR);
+                                /* Letterbox will have top/bottom border */
+                                top_border = (adjusted_mode->vdisplay -
+                                        scaled_height) / 2;
+                                bottom_border = top_border;
+                                if (mode->vdisplay & 1)
+                                        bottom_border++;
+                                adjusted_mode->crtc_vdisplay = scaled_height;
+                                /* use border instead of border minus one */
+                                adjusted_mode->crtc_vblank_start =
+                                        scaled_height + bottom_border;
+                                /* keep the vblank width constant */
+                                adjusted_mode->crtc_vblank_end =
+                                        adjusted_mode->crtc_vblank_start +
+                                                        vblank_width;
+                                /*
+                                 * get the vsync start pos relative to
+                                 * vblank start
+                                 */
+                                vsync_pos = (vblank_width - vsync_width) / 2;
+                                adjusted_mode->crtc_vsync_start =
+                                        adjusted_mode->crtc_vblank_start +
+                                                        vsync_pos;
+                                /* keep the vsync width constant */
+                                adjusted_mode->crtc_vsync_end =
+                                        adjusted_mode->crtc_vsync_start +
+                                                        vsync_width;
+                                border = 1;
+                        } else {
+                        /* Aspects match, Let hw scale both directions */
+                                pfit_control |= (VERT_AUTO_SCALE |
+                                                 HORIZ_AUTO_SCALE |
+                                                 VERT_INTERP_BILINEAR |
+                                                 HORIZ_INTERP_BILINEAR);
+                        }
+                        horiz_bits = (1 << bits) * horiz_ratio /
+                                        PANEL_RATIO_FACTOR;
+                        vert_bits = (1 << bits) * vert_ratio /
+                                        PANEL_RATIO_FACTOR;
+                        pfit_pgm_ratios =
+                                ((vert_bits << PFIT_VERT_SCALE_SHIFT) &
+                                                PFIT_VERT_SCALE_MASK) |
+                                ((horiz_bits << PFIT_HORIZ_SCALE_SHIFT) &
+                                                PFIT_HORIZ_SCALE_MASK);
+                }
+                break;
+        case DRM_MODE_SCALE_FULLSCREEN:
+                /*
+                 * Full scaling, even if it changes the aspect ratio.
+                 * Fortunately this is all done for us in hw.
+                 */
+                pfit_control |= PFIT_ENABLE;
+                if (IS_I965G(dev))
+                        pfit_control |= PFIT_SCALING_AUTO;
+                else
+                        pfit_control |= (VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
+                                         VERT_INTERP_BILINEAR |
+                                         HORIZ_INTERP_BILINEAR);
+                break;
+        default:
+                break;
+        }
+out:
+        lvds_priv->pfit_control = pfit_control;
+        lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios;
        /*
         * XXX: It would be nice to support lower refresh rates on the
         * panels to reduce power consumption, and perhaps match the
@@ -301,8 +573,8 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
 {
        struct drm_device *dev = encoder->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
-        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        struct intel_output *intel_output = enc_to_intel_output(encoder);
-        u32 pfit_control;
+        struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
        /*
         * The LVDS pin pair will already have been turned on in the
@@ -319,22 +591,8 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
         * screen.  Should be enabled before the pipe is enabled, according to
         * register description and PRM.
         */
-        if (mode->hdisplay != adjusted_mode->hdisplay ||
+        I915_WRITE(PFIT_PGM_RATIOS, lvds_priv->pfit_pgm_ratios);
-            mode->vdisplay != adjusted_mode->vdisplay)
+        I915_WRITE(PFIT_CONTROL, lvds_priv->pfit_control);
-                pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE |
-                                HORIZ_AUTO_SCALE | VERT_INTERP_BILINEAR |
-                                HORIZ_INTERP_BILINEAR);
-        else
-                pfit_control = 0;
-        if (!IS_I965G(dev)) {
-                if (dev_priv->panel_wants_dither || dev_priv->lvds_dither)
-                        pfit_control |= PANEL_8TO6_DITHER_ENABLE;
-        }
-        else
-                pfit_control |= intel_crtc->pipe << PFIT_PIPE_SHIFT;
-        I915_WRITE(PFIT_CONTROL, pfit_control);
 }
 /**
@@ -406,6 +664,34 @@ static int intel_lvds_set_property(struct drm_connector *connector,
                                   struct drm_property *property,
                                   uint64_t value)
 {
+        struct drm_device *dev = connector->dev;
+        struct intel_output *intel_output =
+                        to_intel_output(connector);
+        if (property == dev->mode_config.scaling_mode_property &&
+                                connector->encoder) {
+                struct drm_crtc *crtc = connector->encoder->crtc;
+                struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
+                if (value == DRM_MODE_SCALE_NON_GPU) {
+                        DRM_DEBUG_KMS(I915_LVDS,
+                                        "non_GPU property is unsupported\n");
+                        return 0;
+                }
+                if (lvds_priv->fitting_mode == value) {
+                        /* the LVDS scaling property is not changed */
+                        return 0;
+                }
+                lvds_priv->fitting_mode = value;
+                if (crtc && crtc->enabled) {
+                        /*
+                         * If the CRTC is enabled, the display will be changed
+                         * according to the new panel fitting mode.
+                         */
+                        drm_crtc_helper_set_mode(crtc, &crtc->mode,
+                                crtc->x, crtc->y, crtc->fb);
+                }
+        }
        return 0;
 }
@@ -456,7 +742,7 @@ static const struct dmi_system_id intel_no_lvds[] = {
                .callback = intel_no_lvds_dmi_callback,
                .ident = "Apple Mac Mini (Core series)",
                .matches = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+                        DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
                        DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
                },
        },
@@ -464,7 +750,7 @@ static const struct dmi_system_id intel_no_lvds[] = {
                .callback = intel_no_lvds_dmi_callback,
                .ident = "Apple Mac Mini (Core 2 series)",
                .matches = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+                        DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
                        DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
                },
        },
@@ -503,6 +789,65 @@ static const struct dmi_system_id intel_no_lvds[] = {
        { }     /* terminating entry */
 };
+#ifdef CONFIG_ACPI
+/*
+ * check_lid_device -- check whether @handle is an ACPI LID device.
+ * @handle: ACPI device handle
+ * @level : depth in the ACPI namespace tree
+ * @context: the number of LID device when we find the device
+ * @rv: a return value to fill if desired (Not use)
+ */
+static acpi_status
+check_lid_device(acpi_handle handle, u32 level, void *context,
+                        void **return_value)
+{
+        struct acpi_device *acpi_dev;
+        int *lid_present = context;
+        acpi_dev = NULL;
+        /* Get the acpi device for device handle */
+        if (acpi_bus_get_device(handle, &acpi_dev) || !acpi_dev) {
+                /* If there is no ACPI device for handle, return */
+                return AE_OK;
+        }
+        if (!strncmp(acpi_device_hid(acpi_dev), "PNP0C0D", 7))
+                *lid_present = 1;
+        return AE_OK;
+}
+/**
+ * check whether there exists the ACPI LID device by enumerating the ACPI
+ * device tree.
+ */
+static int intel_lid_present(void)
+{
+        int lid_present = 0;
+        if (acpi_disabled) {
+                /* If ACPI is disabled, there is no ACPI device tree to
+                 * check, so assume the LID device would have been present.
+                 */
+                return 1;
+        }
+        acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
+                                ACPI_UINT32_MAX,
+                                check_lid_device, &lid_present, NULL);
+        return lid_present;
+}
+#else
+static int intel_lid_present(void)
+{
+        /* In the absence of ACPI built in, assume that the LID device would
+         * have been present.
+         */
+        return 1;
+}
+#endif
 /**
 * intel_lvds_init - setup LVDS connectors on this device
 * @dev: drm device
@@ -518,6 +863,7 @@ void intel_lvds_init(struct drm_device *dev)
        struct drm_encoder *encoder;
        struct drm_display_mode *scan; /* *modes, *bios_mode; */
        struct drm_crtc *crtc;
+        struct intel_lvds_priv *lvds_priv;
        u32 lvds;
        int pipe, gpio = GPIOC;
@@ -525,13 +871,24 @@ void intel_lvds_init(struct drm_device *dev)
        if (dmi_check_system(intel_no_lvds))
                return;
+        /* Assume that any device without an ACPI LID device also doesn't
+         * have an integrated LVDS.  We would be better off parsing the BIOS
+         * to get a reliable indicator, but that code isn't written yet.
+         *
+         * In the case of all-in-one desktops using LVDS that we've seen,
+         * they're using SDVO LVDS.
+         */
+        if (!intel_lid_present())
+                return;
        if (IS_IGDNG(dev)) {
                if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
                        return;
                gpio = PCH_GPIOC;
        }
-        intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL);
+        intel_output = kzalloc(sizeof(struct intel_output) +
+                                sizeof(struct intel_lvds_priv), GFP_KERNEL);
        if (!intel_output) {
                return;
        }
@@ -553,7 +910,18 @@ void intel_lvds_init(struct drm_device *dev)
        connector->interlace_allowed = false;
        connector->doublescan_allowed = false;
+        lvds_priv = (struct intel_lvds_priv *)(intel_output + 1);
+        intel_output->dev_priv = lvds_priv;
+        /* create the scaling mode property */
+        drm_mode_create_scaling_mode_property(dev);
+        /*
+         * the initial panel fitting mode will be FULL_SCREEN.
+         */
+        drm_connector_attach_property(&intel_output->base,
+                                      dev->mode_config.scaling_mode_property,
+                                      DRM_MODE_SCALE_FULLSCREEN);
+        lvds_priv->fitting_mode = DRM_MODE_SCALE_FULLSCREEN;
        /*
         * LVDS discovery:
         * 1) check for EDID on DDC
@@ -649,5 +1017,5 @@ failed:
        if (intel_output->ddc_bus)
                intel_i2c_destroy(intel_output->ddc_bus);
        drm_connector_cleanup(connector);
-        kfree(connector);
+        kfree(intel_output);
 }
diff --git a/drivers/gpu/drm/i915/intel_modes.c b/drivers/gpu/drm/i915/intel_modes.c
index e0910fefce87..67e2f4632a24 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -53,10 +53,9 @@ bool intel_ddc_probe(struct intel_output *intel_output)
                }
        };
-        intel_i2c_quirk_set(intel_output->ddc_bus->drm_dev, true);
+        intel_i2c_quirk_set(intel_output->base.dev, true);
-        ret = i2c_transfer(&intel_output->ddc_bus->adapter, msgs, 2);
+        ret = i2c_transfer(intel_output->ddc_bus, msgs, 2);
-        intel_i2c_quirk_set(intel_output->ddc_bus->drm_dev, false);
+        intel_i2c_quirk_set(intel_output->base.dev, false);
        if (ret == 2)
                return true;
@@ -74,10 +73,9 @@ int intel_ddc_get_modes(struct intel_output *intel_output)
        struct edid *edid;
        int ret = 0;
-        intel_i2c_quirk_set(intel_output->ddc_bus->drm_dev, true);
+        intel_i2c_quirk_set(intel_output->base.dev, true);
-        edid = drm_get_edid(&intel_output->base,
+        edid = drm_get_edid(&intel_output->base, intel_output->ddc_bus);
-                            &intel_output->ddc_bus->adapter);
+        intel_i2c_quirk_set(intel_output->base.dev, false);
-        intel_i2c_quirk_set(intel_output->ddc_bus->drm_dev, false);
        if (edid) {
                drm_mode_connector_update_edid_property(&intel_output->base,
                                                        edid);
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 9a00adb3a508..4f0c30948bc4 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -38,8 +38,7 @@
 #undef SDVO_DEBUG
 #define I915_SDVO       "i915_sdvo"
 struct intel_sdvo_priv {
-        struct intel_i2c_chan *i2c_bus;
+        u8 slave_addr;
-        int slaveaddr;
        /* Register for the SDVO device: SDVOB or SDVOC */
        int output_device;
@@ -69,12 +68,23 @@ struct intel_sdvo_priv {
         * This is set if we treat the device as HDMI, instead of DVI.
         */
        bool is_hdmi;
        /**
         * This is set if we detect output of sdvo device as LVDS.
         */
        bool is_lvds;
        /**
+         * This is sdvo flags for input timing.
+         */
+        uint8_t sdvo_flags;
+        /**
+         * This is sdvo fixed pannel mode pointer
+         */
+        struct drm_display_mode *sdvo_lvds_fixed_mode;
+        /**
         * Returned SDTV resolutions allowed for the current format, if the
         * device reported it.
         */
@@ -146,13 +156,13 @@ static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
        struct i2c_msg msgs[] = {
                {
-                        .addr = sdvo_priv->i2c_bus->slave_addr,
+                        .addr = sdvo_priv->slave_addr >> 1,
                        .flags = 0,
                        .len = 1,
                        .buf = out_buf,
                },
                {
-                        .addr = sdvo_priv->i2c_bus->slave_addr,
+                        .addr = sdvo_priv->slave_addr >> 1,
                        .flags = I2C_M_RD,
                        .len = 1,
                        .buf = buf,
@@ -162,7 +172,7 @@ static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
        out_buf[0] = addr;
        out_buf[1] = 0;
-        if ((ret = i2c_transfer(&sdvo_priv->i2c_bus->adapter, msgs, 2)) == 2)
+        if ((ret = i2c_transfer(intel_output->i2c_bus, msgs, 2)) == 2)
        {
                *ch = buf[0];
                return true;
@@ -175,10 +185,11 @@ static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
                                  u8 ch)
 {
+        struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
        u8 out_buf[2];
        struct i2c_msg msgs[] = {
                {
-                        .addr = intel_output->i2c_bus->slave_addr,
+                        .addr = sdvo_priv->slave_addr >> 1,
                        .flags = 0,
                        .len = 2,
                        .buf = out_buf,
@@ -188,7 +199,7 @@ static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
        out_buf[0] = addr;
        out_buf[1] = ch;
-        if (i2c_transfer(&intel_output->i2c_bus->adapter, msgs, 1) == 1)
+        if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1)
        {
                return true;
        }
@@ -592,6 +603,7 @@ intel_sdvo_create_preferred_input_timing(struct intel_output *output,
                                         uint16_t height)
 {
        struct intel_sdvo_preferred_input_timing_args args;
+        struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
        uint8_t status;
        memset(&args, 0, sizeof(args));
@@ -599,7 +611,12 @@ intel_sdvo_create_preferred_input_timing(struct intel_output *output,
        args.width = width;
        args.height = height;
        args.interlace = 0;
-        args.scaled = 0;
+        if (sdvo_priv->is_lvds &&
+           (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
+            sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
+                args.scaled = 1;
        intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
                             &args, sizeof(args));
        status = intel_sdvo_read_response(output, NULL, 0);
@@ -944,12 +961,7 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
        struct intel_output *output = enc_to_intel_output(encoder);
        struct intel_sdvo_priv *dev_priv = output->dev_priv;
-        if (!dev_priv->is_tv) {
+        if (dev_priv->is_tv) {
-                /* Make the CRTC code factor in the SDVO pixel multiplier.  The
-                 * SDVO device will be told of the multiplier during mode_set.
-                 */
-                adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
-        } else {
                struct intel_sdvo_dtd output_dtd;
                bool success;
@@ -980,6 +992,7 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
                        intel_sdvo_get_preferred_input_timing(output,
                                                             &input_dtd);
                        intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
+                        dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
                        drm_mode_set_crtcinfo(adjusted_mode, 0);
@@ -990,6 +1003,52 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
                } else {
                        return false;
                }
+        } else if (dev_priv->is_lvds) {
+                struct intel_sdvo_dtd output_dtd;
+                bool success;
+                drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
+                /* Set output timings */
+                intel_sdvo_get_dtd_from_mode(&output_dtd,
+                                dev_priv->sdvo_lvds_fixed_mode);
+                intel_sdvo_set_target_output(output,
+                                             dev_priv->controlled_output);
+                intel_sdvo_set_output_timing(output, &output_dtd);
+                /* Set the input timing to the screen. Assume always input 0. */
+                intel_sdvo_set_target_input(output, true, false);
+                success = intel_sdvo_create_preferred_input_timing(
+                                output,
+                                mode->clock / 10,
+                                mode->hdisplay,
+                                mode->vdisplay);
+                if (success) {
+                        struct intel_sdvo_dtd input_dtd;
+                        intel_sdvo_get_preferred_input_timing(output,
+                                                             &input_dtd);
+                        intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
+                        dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
+                        drm_mode_set_crtcinfo(adjusted_mode, 0);
+                        mode->clock = adjusted_mode->clock;
+                        adjusted_mode->clock *=
+                                intel_sdvo_get_pixel_multiplier(mode);
+                } else {
+                        return false;
+                }
+        } else {
+                /* Make the CRTC code factor in the SDVO pixel multiplier.  The
+                 * SDVO device will be told of the multiplier during mode_set.
+                 */
+                adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
        }
        return true;
 }
@@ -1033,15 +1092,16 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
        /* We have tried to get input timing in mode_fixup, and filled into
           adjusted_mode */
-        if (sdvo_priv->is_tv)
+        if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
                intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
-        else
+                input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
+        } else
                intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
        /* If it's a TV, we already set the output timing in mode_fixup.
         * Otherwise, the output timing is equal to the input timing.
         */
-        if (!sdvo_priv->is_tv) {
+        if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
                /* Set the output timing to the screen */
                intel_sdvo_set_target_output(output,
                                             sdvo_priv->controlled_output);
@@ -1116,6 +1176,8 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
                sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
        }
+        if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
+                sdvox |= SDVO_STALL_SELECT;
        intel_sdvo_write_sdvox(output, sdvox);
 }
@@ -1276,6 +1338,17 @@ static int intel_sdvo_mode_valid(struct drm_connector *connector,
        if (sdvo_priv->pixel_clock_max < mode->clock)
                return MODE_CLOCK_HIGH;
+        if (sdvo_priv->is_lvds == true) {
+                if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
+                        return MODE_PANEL;
+                if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
+                        return MODE_PANEL;
+                if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
+                        return MODE_PANEL;
+        }
        return MODE_OK;
 }
@@ -1369,9 +1442,8 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
        struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
        struct edid *edid = NULL;
-        intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
        edid = drm_get_edid(&intel_output->base,
-                            &intel_output->ddc_bus->adapter);
+                            intel_output->ddc_bus);
        if (edid != NULL) {
                sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid);
                kfree(edid);
@@ -1549,23 +1621,21 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
 {
        struct intel_output *intel_output = to_intel_output(connector);
-        struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
        struct drm_i915_private *dev_priv = connector->dev->dev_private;
+        struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
+        struct drm_display_mode *newmode;
        /*
         * Attempt to get the mode list from DDC.
         * Assume that the preferred modes are
         * arranged in priority order.
         */
-        /* set the bus switch and get the modes */
-        intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
        intel_ddc_get_modes(intel_output);
        if (list_empty(&connector->probed_modes) == false)
-                return;
+                goto end;
        /* Fetch modes from VBT */
        if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
-                struct drm_display_mode *newmode;
                newmode = drm_mode_duplicate(connector->dev,
                                             dev_priv->sdvo_lvds_vbt_mode);
                if (newmode != NULL) {
@@ -1575,6 +1645,16 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
                        drm_mode_probed_add(connector, newmode);
                }
        }
+end:
+        list_for_each_entry(newmode, &connector->probed_modes, head) {
+                if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
+                        sdvo_priv->sdvo_lvds_fixed_mode =
+                                drm_mode_duplicate(connector->dev, newmode);
+                        break;
+                }
+        }
 }
 static int intel_sdvo_get_modes(struct drm_connector *connector)
@@ -1597,14 +1677,20 @@ static int intel_sdvo_get_modes(struct drm_connector *connector)
 static void intel_sdvo_destroy(struct drm_connector *connector)
 {
        struct intel_output *intel_output = to_intel_output(connector);
+        struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
        if (intel_output->i2c_bus)
                intel_i2c_destroy(intel_output->i2c_bus);
        if (intel_output->ddc_bus)
                intel_i2c_destroy(intel_output->ddc_bus);
+        if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
+                drm_mode_destroy(connector->dev,
+                                 sdvo_priv->sdvo_lvds_fixed_mode);
        drm_sysfs_connector_remove(connector);
        drm_connector_cleanup(connector);
        kfree(intel_output);
 }
@@ -1709,7 +1795,7 @@ intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
        list_for_each_entry(connector,
                        &dev->mode_config.connector_list, head) {
-                if (to_intel_output(connector)->ddc_bus == chan) {
+                if (to_intel_output(connector)->ddc_bus == &chan->adapter) {
                        intel_output = to_intel_output(connector);
                        break;
                }
@@ -1723,7 +1809,7 @@ static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
        struct intel_output *intel_output;
        struct intel_sdvo_priv *sdvo_priv;
        struct i2c_algo_bit_data *algo_data;
-        struct i2c_algorithm *algo;
+        const struct i2c_algorithm *algo;
        algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
        intel_output =
@@ -1733,7 +1819,7 @@ static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
                return -EINVAL;
        sdvo_priv = intel_output->dev_priv;
-        algo = (struct i2c_algorithm *)intel_output->i2c_bus->adapter.algo;
+        algo = intel_output->i2c_bus->algo;
        intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
        return algo->master_xfer(i2c_adap, msgs, num);
@@ -1785,13 +1871,11 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
        struct drm_connector *connector;
        struct intel_output *intel_output;
        struct intel_sdvo_priv *sdvo_priv;
-        struct intel_i2c_chan *i2cbus = NULL;
-        struct intel_i2c_chan *ddcbus = NULL;
        int connector_type;
        u8 ch[0x40];
        int i;
-        int encoder_type, output_id;
+        int encoder_type;
-        u8 slave_addr;
        intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
        if (!intel_output) {
@@ -1799,29 +1883,24 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
        }
        sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
+        sdvo_priv->output_device = output_device;
+        intel_output->dev_priv = sdvo_priv;
        intel_output->type = INTEL_OUTPUT_SDVO;
        /* setup the DDC bus. */
        if (output_device == SDVOB)
-                i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
+                intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
        else
-                i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
+                intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
-        if (!i2cbus)
+        if (!intel_output->i2c_bus)
                goto err_inteloutput;
-        slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
+        sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
-        sdvo_priv->i2c_bus = i2cbus;
-        if (output_device == SDVOB) {
+        /* Save the bit-banging i2c functionality for use by the DDC wrapper */
-                output_id = 1;
+        intel_sdvo_i2c_bit_algo.functionality = intel_output->i2c_bus->algo->functionality;
-        } else {
-                output_id = 2;
-        }
-        sdvo_priv->i2c_bus->slave_addr = slave_addr >> 1;
-        sdvo_priv->output_device = output_device;
-        intel_output->i2c_bus = i2cbus;
-        intel_output->dev_priv = sdvo_priv;
        /* Read the regs to test if we can talk to the device */
        for (i = 0; i < 0x40; i++) {
@@ -1835,17 +1914,15 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
        /* setup the DDC bus. */
        if (output_device == SDVOB)
-                ddcbus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
+                intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
        else
-                ddcbus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
+                intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
-        if (ddcbus == NULL)
+        if (intel_output->ddc_bus == NULL)
                goto err_i2c;
-        intel_sdvo_i2c_bit_algo.functionality =
+        /* Wrap with our custom algo which switches to DDC mode */
-                intel_output->i2c_bus->adapter.algo->functionality;
+        intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
-        ddcbus->adapter.algo = &intel_sdvo_i2c_bit_algo;
-        intel_output->ddc_bus = ddcbus;
        /* In defaut case sdvo lvds is false */
        sdvo_priv->is_lvds = false;
@@ -1965,9 +2042,10 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
        return true;
 err_i2c:
-        if (ddcbus != NULL)
+        if (intel_output->ddc_bus != NULL)
                intel_i2c_destroy(intel_output->ddc_bus);
-        intel_i2c_destroy(intel_output->i2c_bus);
+        if (intel_output->i2c_bus != NULL)
+                intel_i2c_destroy(intel_output->i2c_bus);
 err_inteloutput:
        kfree(intel_output);
diff --git a/drivers/gpu/drm/i915/intel_sdvo_regs.h b/drivers/gpu/drm/i915/intel_sdvo_regs.h
index 193938b7d7f9..ba5cdf8ae40b 100644
--- a/drivers/gpu/drm/i915/intel_sdvo_regs.h
+++ b/drivers/gpu/drm/i915/intel_sdvo_regs.h
@@ -715,6 +715,7 @@ struct intel_sdvo_enhancements_arg {
  #define SDVO_HBUF_TX_ONCE     (2 << 6)
  #define SDVO_HBUF_TX_VSYNC    (3 << 6)
 #define SDVO_CMD_GET_AUDIO_TX_INFO      0x9c
+#define SDVO_NEED_TO_STALL  (1 << 7)
 struct intel_sdvo_encode{
    u8 dvi_rev;
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index ea68992e4416..a43c98e3f077 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1383,34 +1383,31 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct intel_output *intel_output)
        /*
         * Detect TV by polling)
         */
-        if (intel_output->load_detect_temp) {
+        save_tv_dac = tv_dac;
-                /* TV not currently running, prod it with destructive detect */
+        tv_ctl = I915_READ(TV_CTL);
-                save_tv_dac = tv_dac;
+        save_tv_ctl = tv_ctl;
-                tv_ctl = I915_READ(TV_CTL);
+        tv_ctl &= ~TV_ENC_ENABLE;
-                save_tv_ctl = tv_ctl;
+        tv_ctl &= ~TV_TEST_MODE_MASK;
-                tv_ctl &= ~TV_ENC_ENABLE;
+        tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
-                tv_ctl &= ~TV_TEST_MODE_MASK;
+        tv_dac &= ~TVDAC_SENSE_MASK;
-                tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
+        tv_dac &= ~DAC_A_MASK;
-                tv_dac &= ~TVDAC_SENSE_MASK;
+        tv_dac &= ~DAC_B_MASK;
-                tv_dac &= ~DAC_A_MASK;
+        tv_dac &= ~DAC_C_MASK;
-                tv_dac &= ~DAC_B_MASK;
+        tv_dac |= (TVDAC_STATE_CHG_EN |
-                tv_dac &= ~DAC_C_MASK;
+                   TVDAC_A_SENSE_CTL |
-                tv_dac |= (TVDAC_STATE_CHG_EN |
+                   TVDAC_B_SENSE_CTL |
-                           TVDAC_A_SENSE_CTL |
+                   TVDAC_C_SENSE_CTL |
-                           TVDAC_B_SENSE_CTL |
+                   DAC_CTL_OVERRIDE |
-                           TVDAC_C_SENSE_CTL |
+                   DAC_A_0_7_V |
-                           DAC_CTL_OVERRIDE |
+                   DAC_B_0_7_V |
-                           DAC_A_0_7_V |
+                   DAC_C_0_7_V);
-                           DAC_B_0_7_V |
+        I915_WRITE(TV_CTL, tv_ctl);
-                           DAC_C_0_7_V);
+        I915_WRITE(TV_DAC, tv_dac);
-                I915_WRITE(TV_CTL, tv_ctl);
+        intel_wait_for_vblank(dev);
-                I915_WRITE(TV_DAC, tv_dac);
+        tv_dac = I915_READ(TV_DAC);
-                intel_wait_for_vblank(dev);
+        I915_WRITE(TV_DAC, save_tv_dac);
-                tv_dac = I915_READ(TV_DAC);
+        I915_WRITE(TV_CTL, save_tv_ctl);
-                I915_WRITE(TV_DAC, save_tv_dac);
+        intel_wait_for_vblank(dev);
-                I915_WRITE(TV_CTL, save_tv_ctl);
-                intel_wait_for_vblank(dev);
-        }
        /*
         *  A B C
         *  0 1 1 Composite
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index f30aa7274a54..f97563db4e59 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -35,6 +35,23 @@
 #include "atom.h"
 /*
+ * Clear GPU surface registers.
+ */
+static void radeon_surface_init(struct radeon_device *rdev)
+{
+        /* FIXME: check this out */
+        if (rdev->family < CHIP_R600) {
+                int i;
+                for (i = 0; i < 8; i++) {
+                        WREG32(RADEON_SURFACE0_INFO +
+                               i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
+                               0);
+                }
+        }
+}
+/*
 * GPU scratch registers helpers function.
 */
 static void radeon_scratch_init(struct radeon_device *rdev)
@@ -496,6 +513,8 @@ int radeon_device_init(struct radeon_device *rdev,
        radeon_errata(rdev);
        /* Initialize scratch registers */
        radeon_scratch_init(rdev);
+        /* Initialize surface registers */
+        radeon_surface_init(rdev);
        /* TODO: disable VGA need to use VGA request */
        /* BIOS*/
@@ -604,9 +623,6 @@ int radeon_device_init(struct radeon_device *rdev,
        if (r) {
                return r;
        }
-        if (rdev->fbdev_rfb && rdev->fbdev_rfb->obj) {
-                rdev->fbdev_robj = rdev->fbdev_rfb->obj->driver_private;
-        }
        if (!ret) {
                DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
        }
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 09c9fb9f6210..84ba69f48784 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -345,7 +345,7 @@ static void __exit radeon_exit(void)
        drm_exit(driver);
 }
-late_initcall(radeon_init);
+module_init(radeon_init);
 module_exit(radeon_exit);
 MODULE_AUTHOR(DRIVER_AUTHOR);
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index fa86d398945e..9e8f191eb64a 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -478,14 +478,16 @@ int radeonfb_create(struct radeon_device *rdev,
 {
        struct fb_info *info;
        struct radeon_fb_device *rfbdev;
-        struct drm_framebuffer *fb;
+        struct drm_framebuffer *fb = NULL;
        struct radeon_framebuffer *rfb;
        struct drm_mode_fb_cmd mode_cmd;
        struct drm_gem_object *gobj = NULL;
        struct radeon_object *robj = NULL;
        struct device *device = &rdev->pdev->dev;
        int size, aligned_size, ret;
+        u64 fb_gpuaddr;
        void *fbptr = NULL;
+        unsigned long tmp;
        mode_cmd.width = surface_width;
        mode_cmd.height = surface_height;
@@ -498,11 +500,12 @@ int radeonfb_create(struct radeon_device *rdev,
        aligned_size = ALIGN(size, PAGE_SIZE);
        ret = radeon_gem_object_create(rdev, aligned_size, 0,
-                                       RADEON_GEM_DOMAIN_VRAM,
+                        RADEON_GEM_DOMAIN_VRAM,
-                                       false, ttm_bo_type_kernel,
+                        false, ttm_bo_type_kernel,
-                                       false, &gobj);
+                        false, &gobj);
        if (ret) {
-                printk(KERN_ERR "failed to allocate framebuffer\n");
+                printk(KERN_ERR "failed to allocate framebuffer (%d %d)\n",
+                       surface_width, surface_height);
                ret = -ENOMEM;
                goto out;
        }
@@ -515,12 +518,19 @@ int radeonfb_create(struct radeon_device *rdev,
                ret = -ENOMEM;
                goto out_unref;
        }
+        ret = radeon_object_pin(robj, RADEON_GEM_DOMAIN_VRAM, &fb_gpuaddr);
+        if (ret) {
+                printk(KERN_ERR "failed to pin framebuffer\n");
+                ret = -ENOMEM;
+                goto out_unref;
+        }
        list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);
        rfb = to_radeon_framebuffer(fb);
        *rfb_p = rfb;
        rdev->fbdev_rfb = rfb;
+        rdev->fbdev_robj = robj;
        info = framebuffer_alloc(sizeof(struct radeon_fb_device), device);
        if (info == NULL) {
@@ -541,13 +551,13 @@ int radeonfb_create(struct radeon_device *rdev,
        info->fix.xpanstep = 1; /* doing it in hw */
        info->fix.ypanstep = 1; /* doing it in hw */
        info->fix.ywrapstep = 0;
-        info->fix.accel = FB_ACCEL_I830;
+        info->fix.accel = FB_ACCEL_NONE;
        info->fix.type_aux = 0;
        info->flags = FBINFO_DEFAULT;
        info->fbops = &radeonfb_ops;
        info->fix.line_length = fb->pitch;
-        info->screen_base = fbptr;
+        tmp = fb_gpuaddr - rdev->mc.vram_location;
-        info->fix.smem_start = (unsigned long)fbptr;
+        info->fix.smem_start = rdev->mc.aper_base + tmp;
        info->fix.smem_len = size;
        info->screen_base = fbptr;
        info->screen_size = size;
@@ -562,8 +572,8 @@ int radeonfb_create(struct radeon_device *rdev,
        info->var.width = -1;
        info->var.xres = fb_width;
        info->var.yres = fb_height;
-        info->fix.mmio_start = pci_resource_start(rdev->pdev, 2);
+        info->fix.mmio_start = 0;
-        info->fix.mmio_len = pci_resource_len(rdev->pdev, 2);
+        info->fix.mmio_len = 0;
        info->pixmap.size = 64*1024;
        info->pixmap.buf_align = 8;
        info->pixmap.access_align = 32;
@@ -644,7 +654,7 @@ out_unref:
        if (robj) {
                radeon_object_kunmap(robj);
        }
-        if (ret) {
+        if (fb && ret) {
                list_del(&fb->filp_head);
                drm_gem_object_unreference(gobj);
                drm_framebuffer_cleanup(fb);
@@ -813,6 +823,7 @@ int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
                robj = rfb->obj->driver_private;
                unregister_framebuffer(info);
                radeon_object_kunmap(robj);
+                radeon_object_unpin(robj);
                framebuffer_release(info);
        }
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 983e8df5e000..bac0d06c52ac 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -223,7 +223,6 @@ int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
 {
        uint32_t flags;
        uint32_t tmp;
-        void *fbptr;
        int r;
        flags = radeon_object_flags_from_domain(domain);
@@ -242,10 +241,6 @@ int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
                DRM_ERROR("radeon: failed to reserve object for pinning it.\n");
                return r;
        }
-        if (robj->rdev->fbdev_robj == robj) {
-                mutex_lock(&robj->rdev->fbdev_info->lock);
-                radeon_object_kunmap(robj);
-        }
        tmp = robj->tobj.mem.placement;
        ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM);
        robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING;
@@ -261,23 +256,12 @@ int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
                DRM_ERROR("radeon: failed to pin object.\n");
        }
        radeon_object_unreserve(robj);
-        if (robj->rdev->fbdev_robj == robj) {
-                if (!r) {
-                        r = radeon_object_kmap(robj, &fbptr);
-                }
-                if (!r) {
-                        robj->rdev->fbdev_info->screen_base = fbptr;
-                        robj->rdev->fbdev_info->fix.smem_start = (unsigned long)fbptr;
-                }
-                mutex_unlock(&robj->rdev->fbdev_info->lock);
-        }
        return r;
 }
 void radeon_object_unpin(struct radeon_object *robj)
 {
        uint32_t flags;
-        void *fbptr;
        int r;
        spin_lock(&robj->tobj.lock);
@@ -297,10 +281,6 @@ void radeon_object_unpin(struct radeon_object *robj)
                DRM_ERROR("radeon: failed to reserve object for unpinning it.\n");
                return;
        }
-        if (robj->rdev->fbdev_robj == robj) {
-                mutex_lock(&robj->rdev->fbdev_info->lock);
-                radeon_object_kunmap(robj);
-        }
        flags = robj->tobj.mem.placement;
        robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT;
        r = ttm_buffer_object_validate(&robj->tobj,
@@ -310,16 +290,6 @@ void radeon_object_unpin(struct radeon_object *robj)
                DRM_ERROR("radeon: failed to unpin buffer.\n");
        }
        radeon_object_unreserve(robj);
-        if (robj->rdev->fbdev_robj == robj) {
-                if (!r) {
-                        r = radeon_object_kmap(robj, &fbptr);
-                }
-                if (!r) {
-                        robj->rdev->fbdev_info->screen_base = fbptr;
-                        robj->rdev->fbdev_info->fix.smem_start = (unsigned long)fbptr;
-                }
-                mutex_unlock(&robj->rdev->fbdev_info->lock);
-        }
 }
 int radeon_object_wait(struct radeon_object *robj)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 517c84559633..bdec583901eb 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -34,7 +34,6 @@
 #include <linux/highmem.h>
 #include <linux/wait.h>
 #include <linux/vmalloc.h>
-#include <linux/version.h>
 #include <linux/module.h>
 void ttm_bo_free_old_node(struct ttm_buffer_object *bo)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
index 27b146c54fbc..40b75032ea47 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
@@ -32,7 +32,6 @@
 #include <ttm/ttm_bo_driver.h>
 #include <ttm/ttm_placement.h>
 #include <linux/mm.h>
-#include <linux/version.h>
 #include <linux/rbtree.h>
 #include <linux/module.h>
 #include <linux/uaccess.h>
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 0331fa74cd3f..75dc8bd24592 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -28,7 +28,6 @@
 * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
 */
-#include <linux/version.h>
 #include <linux/vmalloc.h>
 #include <linux/sched.h>
 #include <linux/highmem.h>