diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 7 |
2 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4058eaa19894..2102ff32ee20 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -3672,9 +3672,9 @@ | |||
3672 | #define _GAMMA_MODE_B 0x4ac80 | 3672 | #define _GAMMA_MODE_B 0x4ac80 |
3673 | #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) | 3673 | #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) |
3674 | #define GAMMA_MODE_MODE_MASK (3 << 0) | 3674 | #define GAMMA_MODE_MODE_MASK (3 << 0) |
3675 | #define GAMMA_MODE_MODE_8bit (0 << 0) | 3675 | #define GAMMA_MODE_MODE_8BIT (0 << 0) |
3676 | #define GAMMA_MODE_MODE_10bit (1 << 0) | 3676 | #define GAMMA_MODE_MODE_10BIT (1 << 0) |
3677 | #define GAMMA_MODE_MODE_12bit (2 << 0) | 3677 | #define GAMMA_MODE_MODE_12BIT (2 << 0) |
3678 | #define GAMMA_MODE_MODE_SPLIT (3 << 0) | 3678 | #define GAMMA_MODE_MODE_SPLIT (3 << 0) |
3679 | 3679 | ||
3680 | /* interrupts */ | 3680 | /* interrupts */ |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a6b4bee9034c..06b1180c4c16 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -5437,13 +5437,11 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc) | |||
5437 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | 5437 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
5438 | uint32_t val; | 5438 | uint32_t val; |
5439 | 5439 | ||
5440 | val = I915_READ(PIPECONF(cpu_transcoder)); | 5440 | val = 0; |
5441 | 5441 | ||
5442 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); | ||
5443 | if (intel_crtc->config.dither) | 5442 | if (intel_crtc->config.dither) |
5444 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); | 5443 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5445 | 5444 | ||
5446 | val &= ~PIPECONF_INTERLACE_MASK_HSW; | ||
5447 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | 5445 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
5448 | val |= PIPECONF_INTERLACED_ILK; | 5446 | val |= PIPECONF_INTERLACED_ILK; |
5449 | else | 5447 | else |
@@ -5451,6 +5449,9 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc) | |||
5451 | 5449 | ||
5452 | I915_WRITE(PIPECONF(cpu_transcoder), val); | 5450 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
5453 | POSTING_READ(PIPECONF(cpu_transcoder)); | 5451 | POSTING_READ(PIPECONF(cpu_transcoder)); |
5452 | |||
5453 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | ||
5454 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | ||
5454 | } | 5455 | } |
5455 | 5456 | ||
5456 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, | 5457 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |