19 files changed, 142 insertions, 69 deletions

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 1403b01e8216..318ade9bb5af 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1670,15 +1670,17 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
                 goto out_regs;
 
         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                ret = i915_kick_out_vgacon(dev_priv);
+                /* WARNING: Apparently we must kick fbdev drivers before vgacon,
+                 * otherwise the vga fbdev driver falls over. */
+                ret = i915_kick_out_firmware_fb(dev_priv);
                 if (ret) {
-                        DRM_ERROR("failed to remove conflicting VGA console\n");
+                        DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
                         goto out_gtt;
                 }
 
-                ret = i915_kick_out_firmware_fb(dev_priv);
+                ret = i915_kick_out_vgacon(dev_priv);
                 if (ret) {
-                        DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
+                        DRM_ERROR("failed to remove conflicting VGA console\n");
                         goto out_gtt;
                 }
         }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f0a1a56406eb..9cb5c95d5898 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4325,7 +4325,6 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
                 ironlake_fdi_disable(crtc);
 
                 ironlake_disable_pch_transcoder(dev_priv, pipe);
-                intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
 
                 if (HAS_PCH_CPT(dev)) {
                         /* disable TRANS_DP_CTL */
@@ -4389,7 +4388,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
         if (intel_crtc->config.has_pch_encoder) {
                 lpt_disable_pch_transcoder(dev_priv);
-                intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
                 intel_ddi_fdi_disable(crtc);
         }
 
@@ -9408,6 +9406,10 @@ static bool page_flip_finished(struct intel_crtc *crtc)
         struct drm_device *dev = crtc->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
 
+        if (i915_reset_in_progress(&dev_priv->gpu_error) ||
+            crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
+                return true;
+
         /*
          * The relevant registers doen't exist on pre-ctg.
          * As the flip done interrupt doesn't trigger for mmio
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5ad45bfff3fe..4bcd91757321 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4450,6 +4450,7 @@ static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
          * vdd might still be enabled do to the delayed vdd off.
          * Make sure vdd is actually turned off here.
          */
+        cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
         pps_lock(intel_dp);
         edp_panel_vdd_off_sync(intel_dp);
         pps_unlock(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index a6bd1422e38f..c0bbf2172446 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -899,6 +899,17 @@ void intel_lvds_init(struct drm_device *dev)
         int pipe;
         u8 pin;
 
+        /*
+         * Unlock registers and just leave them unlocked. Do this before
+         * checking quirk lists to avoid bogus WARNINGs.
+         */
+        if (HAS_PCH_SPLIT(dev)) {
+                I915_WRITE(PCH_PP_CONTROL,
+                           I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
+        } else {
+                I915_WRITE(PP_CONTROL,
+                           I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
+        }
         if (!intel_lvds_supported(dev))
                 return;
 
@@ -1097,17 +1108,6 @@ out:
         lvds_encoder->a3_power = I915_READ(lvds_encoder->reg) &
                                  LVDS_A3_POWER_MASK;
 
-        /*
-         * Unlock registers and just
-         * leave them unlocked
-         */
-        if (HAS_PCH_SPLIT(dev)) {
-                I915_WRITE(PCH_PP_CONTROL,
-                           I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
-        } else {
-                I915_WRITE(PP_CONTROL,
-                           I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
-        }
         lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
         if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
                 DRM_DEBUG_KMS("lid notifier registration failed\n");
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c27b6140bfd1..ad2fd605f76b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5469,11 +5469,6 @@ static void gen6_init_clock_gating(struct drm_device *dev)
         I915_WRITE(_3D_CHICKEN,
                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
 
-        /* WaSetupGtModeTdRowDispatch:snb */
-        if (IS_SNB_GT1(dev))
-                I915_WRITE(GEN6_GT_MODE,
-                           _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
-
         /* WaDisable_RenderCache_OperationalFlush:snb */
         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
index cd05677ad4b7..72a40f95d048 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
@@ -218,7 +218,6 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
-                device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
                 device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
                 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
                 break;
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
index 5ae6a43893b5..1931057f9962 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
@@ -551,8 +551,8 @@ nv04_fifo_intr(struct nouveau_subdev *subdev)
                         }
 
                         if (status & 0x40000000) {
-                                nouveau_fifo_uevent(&priv->base);
                                 nv_wr32(priv, 0x002100, 0x40000000);
+                                nouveau_fifo_uevent(&priv->base);
                                 status &= ~0x40000000;
                         }
                 }
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
index 1fe1f8fbda0c..074d434c3077 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
@@ -740,6 +740,8 @@ nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn)
         u32 inte = nv_rd32(priv, 0x002628);
         u32 unkn;
 
+        nv_wr32(priv, 0x0025a8 + (engn * 0x04), intr);
+
         for (unkn = 0; unkn < 8; unkn++) {
                 u32 ints = (intr >> (unkn * 0x04)) & inte;
                 if (ints & 0x1) {
@@ -751,8 +753,6 @@ nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn)
                         nv_mask(priv, 0x002628, ints, 0);
                 }
         }
-
-        nv_wr32(priv, 0x0025a8 + (engn * 0x04), intr);
 }
 
 static void
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
index d2f0fd39c145..f8734eb74eaa 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
@@ -952,8 +952,8 @@ nve0_fifo_intr(struct nouveau_subdev *subdev)
         }
 
         if (stat & 0x80000000) {
-                nve0_fifo_intr_engine(priv);
                 nv_wr32(priv, 0x002100, 0x80000000);
+                nve0_fifo_intr_engine(priv);
                 stat &= ~0x80000000;
         }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 57238076049f..62b97c4eef8d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -629,7 +629,6 @@ int nouveau_pmops_suspend(struct device *dev)
 
         pci_save_state(pdev);
         pci_disable_device(pdev);
-        pci_ignore_hotplug(pdev);
         pci_set_power_state(pdev, PCI_D3hot);
         return 0;
 }
@@ -933,6 +932,7 @@ static int nouveau_pmops_runtime_suspend(struct device *dev)
         ret = nouveau_do_suspend(drm_dev, true);
         pci_save_state(pdev);
         pci_disable_device(pdev);
+        pci_ignore_hotplug(pdev);
         pci_set_power_state(pdev, PCI_D3cold);
         drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
         return ret;
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index 515cd9aebb99..f32a434724e3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -52,20 +52,24 @@ nouveau_fctx(struct nouveau_fence *fence)
         return container_of(fence->base.lock, struct nouveau_fence_chan, lock);
 }
 
-static void
+static int
 nouveau_fence_signal(struct nouveau_fence *fence)
 {
+        int drop = 0;
+
         fence_signal_locked(&fence->base);
         list_del(&fence->head);
+        rcu_assign_pointer(fence->channel, NULL);
 
         if (test_bit(FENCE_FLAG_USER_BITS, &fence->base.flags)) {
                 struct nouveau_fence_chan *fctx = nouveau_fctx(fence);
 
                 if (!--fctx->notify_ref)
-                        nvif_notify_put(&fctx->notify);
+                        drop = 1;
         }
 
         fence_put(&fence->base);
+        return drop;
 }
 
 static struct nouveau_fence *
@@ -88,16 +92,23 @@ nouveau_fence_context_del(struct nouveau_fence_chan *fctx)
 {
         struct nouveau_fence *fence;
 
-        nvif_notify_fini(&fctx->notify);
-
         spin_lock_irq(&fctx->lock);
         while (!list_empty(&fctx->pending)) {
                 fence = list_entry(fctx->pending.next, typeof(*fence), head);
 
-                nouveau_fence_signal(fence);
-                fence->channel = NULL;
+                if (nouveau_fence_signal(fence))
+                        nvif_notify_put(&fctx->notify);
         }
         spin_unlock_irq(&fctx->lock);
+
+        nvif_notify_fini(&fctx->notify);
+        fctx->dead = 1;
+
+        /*
+         * Ensure that all accesses to fence->channel complete before freeing
+         * the channel.
+         */
+        synchronize_rcu();
 }
 
 static void
@@ -112,21 +123,23 @@ nouveau_fence_context_free(struct nouveau_fence_chan *fctx)
         kref_put(&fctx->fence_ref, nouveau_fence_context_put);
 }
 
-static void
+static int
 nouveau_fence_update(struct nouveau_channel *chan, struct nouveau_fence_chan *fctx)
 {
         struct nouveau_fence *fence;
-
+        int drop = 0;
         u32 seq = fctx->read(chan);
 
         while (!list_empty(&fctx->pending)) {
                 fence = list_entry(fctx->pending.next, typeof(*fence), head);
 
                 if ((int)(seq - fence->base.seqno) < 0)
-                        return;
+                        break;
 
-                nouveau_fence_signal(fence);
+                drop |= nouveau_fence_signal(fence);
         }
+
+        return drop;
 }
 
 static int
@@ -135,18 +148,21 @@ nouveau_fence_wait_uevent_handler(struct nvif_notify *notify)
         struct nouveau_fence_chan *fctx =
                 container_of(notify, typeof(*fctx), notify);
         unsigned long flags;
+        int ret = NVIF_NOTIFY_KEEP;
 
         spin_lock_irqsave(&fctx->lock, flags);
         if (!list_empty(&fctx->pending)) {
                 struct nouveau_fence *fence;
+                struct nouveau_channel *chan;
 
                 fence = list_entry(fctx->pending.next, typeof(*fence), head);
-                nouveau_fence_update(fence->channel, fctx);
+                chan = rcu_dereference_protected(fence->channel, lockdep_is_held(&fctx->lock));
+                if (nouveau_fence_update(fence->channel, fctx))
+                        ret = NVIF_NOTIFY_DROP;
         }
         spin_unlock_irqrestore(&fctx->lock, flags);
 
-        /* Always return keep here. NVIF refcount is handled with nouveau_fence_update */
-        return NVIF_NOTIFY_KEEP;
+        return ret;
 }
 
 void
@@ -262,7 +278,10 @@ nouveau_fence_emit(struct nouveau_fence *fence, struct nouveau_channel *chan)
         if (!ret) {
                 fence_get(&fence->base);
                 spin_lock_irq(&fctx->lock);
-                nouveau_fence_update(chan, fctx);
+
+                if (nouveau_fence_update(chan, fctx))
+                        nvif_notify_put(&fctx->notify);
+
                 list_add_tail(&fence->head, &fctx->pending);
                 spin_unlock_irq(&fctx->lock);
         }
@@ -276,13 +295,16 @@ nouveau_fence_done(struct nouveau_fence *fence)
         if (fence->base.ops == &nouveau_fence_ops_legacy ||
             fence->base.ops == &nouveau_fence_ops_uevent) {
                 struct nouveau_fence_chan *fctx = nouveau_fctx(fence);
+                struct nouveau_channel *chan;
                 unsigned long flags;
 
                 if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags))
                         return true;
 
                 spin_lock_irqsave(&fctx->lock, flags);
-                nouveau_fence_update(fence->channel, fctx);
+                chan = rcu_dereference_protected(fence->channel, lockdep_is_held(&fctx->lock));
+                if (chan && nouveau_fence_update(chan, fctx))
+                        nvif_notify_put(&fctx->notify);
                 spin_unlock_irqrestore(&fctx->lock, flags);
         }
         return fence_is_signaled(&fence->base);
@@ -387,12 +409,18 @@ nouveau_fence_sync(struct nouveau_bo *nvbo, struct nouveau_channel *chan, bool e
 
         if (fence && (!exclusive || !fobj || !fobj->shared_count)) {
                 struct nouveau_channel *prev = NULL;
+                bool must_wait = true;
 
                 f = nouveau_local_fence(fence, chan->drm);
-                if (f)
-                        prev = f->channel;
+                if (f) {
+                        rcu_read_lock();
+                        prev = rcu_dereference(f->channel);
+                        if (prev && (prev == chan || fctx->sync(f, prev, chan) == 0))
+                                must_wait = false;
+                        rcu_read_unlock();
+                }
 
-                if (!prev || (prev != chan && (ret = fctx->sync(f, prev, chan))))
+                if (must_wait)
                         ret = fence_wait(fence, intr);
 
                 return ret;
@@ -403,19 +431,22 @@ nouveau_fence_sync(struct nouveau_bo *nvbo, struct nouveau_channel *chan, bool e
 
         for (i = 0; i < fobj->shared_count && !ret; ++i) {
                 struct nouveau_channel *prev = NULL;
+                bool must_wait = true;
 
                 fence = rcu_dereference_protected(fobj->shared[i],
                                                 reservation_object_held(resv));
 
                 f = nouveau_local_fence(fence, chan->drm);
-                if (f)
-                        prev = f->channel;
+                if (f) {
+                        rcu_read_lock();
+                        prev = rcu_dereference(f->channel);
+                        if (prev && (prev == chan || fctx->sync(f, prev, chan) == 0))
+                                must_wait = false;
+                        rcu_read_unlock();
+                }
 
-                if (!prev || (prev != chan && (ret = fctx->sync(f, prev, chan))))
+                if (must_wait)
                         ret = fence_wait(fence, intr);
-
-                if (ret)
-                        break;
         }
 
         return ret;
@@ -463,7 +494,7 @@ static const char *nouveau_fence_get_timeline_name(struct fence *f)
         struct nouveau_fence *fence = from_fence(f);
         struct nouveau_fence_chan *fctx = nouveau_fctx(fence);
 
-        return fence->channel ? fctx->name : "dead channel";
+        return !fctx->dead ? fctx->name : "dead channel";
 }
 
 /*
@@ -476,9 +507,16 @@ static bool nouveau_fence_is_signaled(struct fence *f)
 {
         struct nouveau_fence *fence = from_fence(f);
         struct nouveau_fence_chan *fctx = nouveau_fctx(fence);
-        struct nouveau_channel *chan = fence->channel;
+        struct nouveau_channel *chan;
+        bool ret = false;
+
+        rcu_read_lock();
+        chan = rcu_dereference(fence->channel);
+        if (chan)
+                ret = (int)(fctx->read(chan) - fence->base.seqno) >= 0;
+        rcu_read_unlock();
 
-        return (int)(fctx->read(chan) - fence->base.seqno) >= 0;
+        return ret;
 }
 
 static bool nouveau_fence_no_signaling(struct fence *f)
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.h b/drivers/gpu/drm/nouveau/nouveau_fence.h
index 943b0b17b1fc..96e461c6f68f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.h
@@ -14,7 +14,7 @@ struct nouveau_fence {
 
         bool sysmem;
 
-        struct nouveau_channel *channel;
+        struct nouveau_channel __rcu *channel;
         unsigned long timeout;
 };
 
@@ -47,7 +47,7 @@ struct nouveau_fence_chan {
         char name[32];
 
         struct nvif_notify notify;
-        int notify_ref;
+        int notify_ref, dead;
 };
 
 struct nouveau_fence_priv {
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index f6309bd23e01..b5c73df8e202 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -1256,7 +1256,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev)
                                         (mode_info->atom_context->bios + data_offset +
                                          le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
                                 rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit =
-                                        ppt->usMaximumPowerDeliveryLimit;
+                                        le16_to_cpu(ppt->usMaximumPowerDeliveryLimit);
                                 pt = &ppt->power_tune_table;
                         } else {
                                 ATOM_PPLIB_POWERTUNE_Table *ppt = (ATOM_PPLIB_POWERTUNE_Table *)
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 300c4b3d4669..26baa9c05f6c 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -322,6 +322,12 @@ static void radeon_connector_get_edid(struct drm_connector *connector)
         }
 
         if (!radeon_connector->edid) {
+                /* don't fetch the edid from the vbios if ddc fails and runpm is
+                 * enabled so we report disconnected.
+                 */
+                if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0))
+                        return;
+
                 if (rdev->is_atom_bios) {
                         /* some laptops provide a hardcoded edid in rom for LCDs */
                         if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
@@ -826,6 +832,8 @@ static int radeon_lvds_mode_valid(struct drm_connector *connector,
 static enum drm_connector_status
 radeon_lvds_detect(struct drm_connector *connector, bool force)
 {
+        struct drm_device *dev = connector->dev;
+        struct radeon_device *rdev = dev->dev_private;
         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
         struct drm_encoder *encoder = radeon_best_single_encoder(connector);
         enum drm_connector_status ret = connector_status_disconnected;
@@ -842,7 +850,11 @@ radeon_lvds_detect(struct drm_connector *connector, bool force)
                 /* check if panel is valid */
                 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
                         ret = connector_status_connected;
-
+                /* don't fetch the edid from the vbios if ddc fails and runpm is
+                 * enabled so we report disconnected.
+                 */
+                if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0))
+                        ret = connector_status_disconnected;
         }
 
         /* check for edid as well */
@@ -1589,6 +1601,11 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
                         /* check if panel is valid */
                         if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
                                 ret = connector_status_connected;
+                        /* don't fetch the edid from the vbios if ddc fails and runpm is
+                         * enabled so we report disconnected.
+                         */
+                        if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0))
+                                ret = connector_status_disconnected;
                 }
                 /* eDP is always DP */
                 radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index a3e7aed7e680..6f377de099f9 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -251,22 +251,19 @@ static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority
 
 static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
 {
-        int i, r = 0;
+        struct radeon_cs_reloc *reloc;
+        int r;
 
-        for (i = 0; i < p->nrelocs; i++) {
+        list_for_each_entry(reloc, &p->validated, tv.head) {
                 struct reservation_object *resv;
 
-                if (!p->relocs[i].robj)
-                        continue;
-
-                resv = p->relocs[i].robj->tbo.resv;
+                resv = reloc->robj->tbo.resv;
                 r = radeon_semaphore_sync_resv(p->rdev, p->ib.semaphore, resv,
-                                               p->relocs[i].tv.shared);
-
+                                               reloc->tv.shared);
                 if (r)
-                        break;
+                        return r;
         }
-        return r;
+        return 0;
 }
 
 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 9a19e52cc655..6b670b0bc47b 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -179,6 +179,9 @@ static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder,
                     (rdev->pdev->subsystem_vendor == 0x1734) &&
                     (rdev->pdev->subsystem_device == 0x1107))
                         use_bl = false;
+                /* disable native backlight control on older asics */
+                else if (rdev->family < CHIP_R600)
+                        use_bl = false;
                 else
                         use_bl = true;
         }
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 7784911d78ef..00fc59762e0d 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -185,6 +185,16 @@ static bool radeon_msi_ok(struct radeon_device *rdev)
         if (rdev->flags & RADEON_IS_AGP)
                 return false;
 
+        /*
+         * Older chips have a HW limitation, they can only generate 40 bits
+         * of address for "64-bit" MSIs which breaks on some platforms, notably
+         * IBM POWER servers, so we limit them
+         */
+        if (rdev->family < CHIP_BONAIRE) {
+                dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");
+                rdev->pdev->no_64bit_msi = 1;
+        }
+
         /* force MSI on */
         if (radeon_msi == 1)
                 return true;
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 8309b11e674d..03586763ee86 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -795,6 +795,8 @@ int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
 
         /* Get associated drm_crtc: */
         drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
+        if (!drmcrtc)
+                return -EINVAL;
 
         /* Helper routine in DRM core does all the work: */
         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 99a960a4f302..4c0d786d5c7a 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -213,6 +213,13 @@ int radeon_bo_create(struct radeon_device *rdev,
         if (!(rdev->flags & RADEON_IS_PCIE))
                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 
+#ifdef CONFIG_X86_32
+        /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
+         * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
+         */
+        bo->flags &= ~RADEON_GEM_GTT_WC;
+#endif
+
         radeon_ttm_placement_from_domain(bo, domain);
         /* Kernel allocation are uninterruptible */
         down_read(&rdev->pm.mclk_lock);