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-rw-r--r--drivers/gpu/drm/drm_fb_cma_helper.c4
-rw-r--r--drivers/gpu/drm/i810/i810_dma.c2
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c22
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c1
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c16
-rw-r--r--drivers/gpu/drm/omapdrm/omap_crtc.c46
-rw-r--r--drivers/gpu/drm/omapdrm/omap_drv.c27
-rw-r--r--drivers/gpu/drm/omapdrm/omap_drv.h1
-rw-r--r--drivers/gpu/drm/qxl/qxl_ioctl.c5
-rw-r--r--drivers/gpu/drm/radeon/mkregtable.c13
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c2
12 files changed, 94 insertions, 47 deletions
diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c
index 0b5af7d0edb1..c385cc5e730e 100644
--- a/drivers/gpu/drm/drm_fb_cma_helper.c
+++ b/drivers/gpu/drm/drm_fb_cma_helper.c
@@ -92,7 +92,7 @@ static struct drm_fb_cma *drm_fb_cma_alloc(struct drm_device *dev,
92 92
93 ret = drm_framebuffer_init(dev, &fb_cma->fb, &drm_fb_cma_funcs); 93 ret = drm_framebuffer_init(dev, &fb_cma->fb, &drm_fb_cma_funcs);
94 if (ret) { 94 if (ret) {
95 dev_err(dev->dev, "Failed to initalize framebuffer: %d\n", ret); 95 dev_err(dev->dev, "Failed to initialize framebuffer: %d\n", ret);
96 kfree(fb_cma); 96 kfree(fb_cma);
97 return ERR_PTR(ret); 97 return ERR_PTR(ret);
98 } 98 }
@@ -376,7 +376,7 @@ struct drm_fbdev_cma *drm_fbdev_cma_init(struct drm_device *dev,
376 376
377 ret = drm_fb_helper_initial_config(helper, preferred_bpp); 377 ret = drm_fb_helper_initial_config(helper, preferred_bpp);
378 if (ret < 0) { 378 if (ret < 0) {
379 dev_err(dev->dev, "Failed to set inital hw configuration.\n"); 379 dev_err(dev->dev, "Failed to set initial hw configuration.\n");
380 goto err_drm_fb_helper_fini; 380 goto err_drm_fb_helper_fini;
381 } 381 }
382 382
diff --git a/drivers/gpu/drm/i810/i810_dma.c b/drivers/gpu/drm/i810/i810_dma.c
index 004ecdfe1b55..ada49eda489f 100644
--- a/drivers/gpu/drm/i810/i810_dma.c
+++ b/drivers/gpu/drm/i810/i810_dma.c
@@ -97,7 +97,7 @@ static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
97 buf = dev_priv->mmap_buffer; 97 buf = dev_priv->mmap_buffer;
98 buf_priv = buf->dev_private; 98 buf_priv = buf->dev_private;
99 99
100 vma->vm_flags |= (VM_IO | VM_DONTCOPY); 100 vma->vm_flags |= VM_DONTCOPY;
101 101
102 buf_priv->currently_mapped = I810_BUF_MAPPED; 102 buf_priv->currently_mapped = I810_BUF_MAPPED;
103 103
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cc1d6056ab70..a416645bcd23 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1806,6 +1806,8 @@ struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1806struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 1806struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1807 struct drm_gem_object *gem_obj, int flags); 1807 struct drm_gem_object *gem_obj, int flags);
1808 1808
1809void i915_gem_restore_fences(struct drm_device *dev);
1810
1809/* i915_gem_context.c */ 1811/* i915_gem_context.c */
1810void i915_gem_context_init(struct drm_device *dev); 1812void i915_gem_context_init(struct drm_device *dev);
1811void i915_gem_context_fini(struct drm_device *dev); 1813void i915_gem_context_fini(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 769f75262feb..4200c32407ec 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2247,25 +2247,15 @@ static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2247 } 2247 }
2248} 2248}
2249 2249
2250static void i915_gem_reset_fences(struct drm_device *dev) 2250void i915_gem_restore_fences(struct drm_device *dev)
2251{ 2251{
2252 struct drm_i915_private *dev_priv = dev->dev_private; 2252 struct drm_i915_private *dev_priv = dev->dev_private;
2253 int i; 2253 int i;
2254 2254
2255 for (i = 0; i < dev_priv->num_fence_regs; i++) { 2255 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2256 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; 2256 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2257 2257 i915_gem_write_fence(dev, i, reg->obj);
2258 if (reg->obj)
2259 i915_gem_object_fence_lost(reg->obj);
2260
2261 i915_gem_write_fence(dev, i, NULL);
2262
2263 reg->pin_count = 0;
2264 reg->obj = NULL;
2265 INIT_LIST_HEAD(&reg->lru_list);
2266 } 2258 }
2267
2268 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2269} 2259}
2270 2260
2271void i915_gem_reset(struct drm_device *dev) 2261void i915_gem_reset(struct drm_device *dev)
@@ -2288,8 +2278,7 @@ void i915_gem_reset(struct drm_device *dev)
2288 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; 2278 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2289 } 2279 }
2290 2280
2291 /* The fence registers are invalidated so clear them out */ 2281 i915_gem_restore_fences(dev);
2292 i915_gem_reset_fences(dev);
2293} 2282}
2294 2283
2295/** 2284/**
@@ -4020,8 +4009,6 @@ i915_gem_idle(struct drm_device *dev)
4020 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 4009 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4021 i915_gem_evict_everything(dev); 4010 i915_gem_evict_everything(dev);
4022 4011
4023 i915_gem_reset_fences(dev);
4024
4025 /* Hack! Don't let anybody do execbuf while we don't control the chip. 4012 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4026 * We need to replace this with a semaphore, or something. 4013 * We need to replace this with a semaphore, or something.
4027 * And not confound mm.suspended! 4014 * And not confound mm.suspended!
@@ -4357,7 +4344,8 @@ i915_gem_load(struct drm_device *dev)
4357 dev_priv->num_fence_regs = 8; 4344 dev_priv->num_fence_regs = 8;
4358 4345
4359 /* Initialize fence registers to zero */ 4346 /* Initialize fence registers to zero */
4360 i915_gem_reset_fences(dev); 4347 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4348 i915_gem_restore_fences(dev);
4361 4349
4362 i915_gem_detect_bit_6_swizzle(dev); 4350 i915_gem_detect_bit_6_swizzle(dev);
4363 init_waitqueue_head(&dev_priv->pending_flip_queue); 4351 init_waitqueue_head(&dev_priv->pending_flip_queue);
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 88b9a663944f..70db618989c4 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -394,6 +394,7 @@ int i915_restore_state(struct drm_device *dev)
394 394
395 mutex_lock(&dev->struct_mutex); 395 mutex_lock(&dev->struct_mutex);
396 396
397 i915_gem_restore_fences(dev);
397 i915_restore_display(dev); 398 i915_restore_display(dev);
398 399
399 if (!drm_core_check_feature(dev, DRIVER_MODESET)) { 400 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 2abb2d3c727b..021e8daa022d 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -690,6 +690,22 @@ static const struct dmi_system_id intel_no_lvds[] = {
690 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 690 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
691 }, 691 },
692 }, 692 },
693 {
694 .callback = intel_no_lvds_dmi_callback,
695 .ident = "Intel D510MO",
696 .matches = {
697 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
698 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
699 },
700 },
701 {
702 .callback = intel_no_lvds_dmi_callback,
703 .ident = "Intel D525MW",
704 .matches = {
705 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
706 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
707 },
708 },
693 709
694 { } /* terminating entry */ 710 { } /* terminating entry */
695}; 711};
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c
index ef161ea982e6..11a5263a5e9f 100644
--- a/drivers/gpu/drm/omapdrm/omap_crtc.c
+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c
@@ -40,7 +40,7 @@ struct omap_crtc {
40 * mgr->id.) Eventually this will be replaced w/ something 40 * mgr->id.) Eventually this will be replaced w/ something
41 * more common-panel-framework-y 41 * more common-panel-framework-y
42 */ 42 */
43 struct omap_overlay_manager mgr; 43 struct omap_overlay_manager *mgr;
44 44
45 struct omap_video_timings timings; 45 struct omap_video_timings timings;
46 bool enabled; 46 bool enabled;
@@ -90,7 +90,32 @@ uint32_t pipe2vbl(struct drm_crtc *crtc)
90 * job of sequencing the setup of the video pipe in the proper order 90 * job of sequencing the setup of the video pipe in the proper order
91 */ 91 */
92 92
93/* ovl-mgr-id -> crtc */
94static struct omap_crtc *omap_crtcs[8];
95
93/* we can probably ignore these until we support command-mode panels: */ 96/* we can probably ignore these until we support command-mode panels: */
97static int omap_crtc_connect(struct omap_overlay_manager *mgr,
98 struct omap_dss_device *dst)
99{
100 if (mgr->output)
101 return -EINVAL;
102
103 if ((mgr->supported_outputs & dst->id) == 0)
104 return -EINVAL;
105
106 dst->manager = mgr;
107 mgr->output = dst;
108
109 return 0;
110}
111
112static void omap_crtc_disconnect(struct omap_overlay_manager *mgr,
113 struct omap_dss_device *dst)
114{
115 mgr->output->manager = NULL;
116 mgr->output = NULL;
117}
118
94static void omap_crtc_start_update(struct omap_overlay_manager *mgr) 119static void omap_crtc_start_update(struct omap_overlay_manager *mgr)
95{ 120{
96} 121}
@@ -107,7 +132,7 @@ static void omap_crtc_disable(struct omap_overlay_manager *mgr)
107static void omap_crtc_set_timings(struct omap_overlay_manager *mgr, 132static void omap_crtc_set_timings(struct omap_overlay_manager *mgr,
108 const struct omap_video_timings *timings) 133 const struct omap_video_timings *timings)
109{ 134{
110 struct omap_crtc *omap_crtc = container_of(mgr, struct omap_crtc, mgr); 135 struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
111 DBG("%s", omap_crtc->name); 136 DBG("%s", omap_crtc->name);
112 omap_crtc->timings = *timings; 137 omap_crtc->timings = *timings;
113 omap_crtc->full_update = true; 138 omap_crtc->full_update = true;
@@ -116,7 +141,7 @@ static void omap_crtc_set_timings(struct omap_overlay_manager *mgr,
116static void omap_crtc_set_lcd_config(struct omap_overlay_manager *mgr, 141static void omap_crtc_set_lcd_config(struct omap_overlay_manager *mgr,
117 const struct dss_lcd_mgr_config *config) 142 const struct dss_lcd_mgr_config *config)
118{ 143{
119 struct omap_crtc *omap_crtc = container_of(mgr, struct omap_crtc, mgr); 144 struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
120 DBG("%s", omap_crtc->name); 145 DBG("%s", omap_crtc->name);
121 dispc_mgr_set_lcd_config(omap_crtc->channel, config); 146 dispc_mgr_set_lcd_config(omap_crtc->channel, config);
122} 147}
@@ -135,6 +160,8 @@ static void omap_crtc_unregister_framedone_handler(
135} 160}
136 161
137static const struct dss_mgr_ops mgr_ops = { 162static const struct dss_mgr_ops mgr_ops = {
163 .connect = omap_crtc_connect,
164 .disconnect = omap_crtc_disconnect,
138 .start_update = omap_crtc_start_update, 165 .start_update = omap_crtc_start_update,
139 .enable = omap_crtc_enable, 166 .enable = omap_crtc_enable,
140 .disable = omap_crtc_disable, 167 .disable = omap_crtc_disable,
@@ -564,7 +591,7 @@ static void omap_crtc_pre_apply(struct omap_drm_apply *apply)
564 } else { 591 } else {
565 if (encoder) { 592 if (encoder) {
566 omap_encoder_set_enabled(encoder, false); 593 omap_encoder_set_enabled(encoder, false);
567 omap_encoder_update(encoder, &omap_crtc->mgr, 594 omap_encoder_update(encoder, omap_crtc->mgr,
568 &omap_crtc->timings); 595 &omap_crtc->timings);
569 omap_encoder_set_enabled(encoder, true); 596 omap_encoder_set_enabled(encoder, true);
570 omap_crtc->full_update = false; 597 omap_crtc->full_update = false;
@@ -590,6 +617,11 @@ static const char *channel_names[] = {
590 [OMAP_DSS_CHANNEL_LCD2] = "lcd2", 617 [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
591}; 618};
592 619
620void omap_crtc_pre_init(void)
621{
622 dss_install_mgr_ops(&mgr_ops);
623}
624
593/* initialize crtc */ 625/* initialize crtc */
594struct drm_crtc *omap_crtc_init(struct drm_device *dev, 626struct drm_crtc *omap_crtc_init(struct drm_device *dev,
595 struct drm_plane *plane, enum omap_channel channel, int id) 627 struct drm_plane *plane, enum omap_channel channel, int id)
@@ -630,9 +662,7 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev,
630 omap_irq_register(dev, &omap_crtc->error_irq); 662 omap_irq_register(dev, &omap_crtc->error_irq);
631 663
632 /* temporary: */ 664 /* temporary: */
633 omap_crtc->mgr.id = channel; 665 omap_crtc->mgr = omap_dss_get_overlay_manager(channel);
634
635 dss_install_mgr_ops(&mgr_ops);
636 666
637 /* TODO: fix hard-coded setup.. add properties! */ 667 /* TODO: fix hard-coded setup.. add properties! */
638 info = &omap_crtc->info; 668 info = &omap_crtc->info;
@@ -646,6 +676,8 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev,
646 676
647 omap_plane_install_properties(omap_crtc->plane, &crtc->base); 677 omap_plane_install_properties(omap_crtc->plane, &crtc->base);
648 678
679 omap_crtcs[channel] = omap_crtc;
680
649 return crtc; 681 return crtc;
650 682
651fail: 683fail:
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c
index 826586ffbe83..a3004f12b9a3 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.c
+++ b/drivers/gpu/drm/omapdrm/omap_drv.c
@@ -65,10 +65,8 @@ static int get_connector_type(struct omap_dss_device *dssdev)
65 switch (dssdev->type) { 65 switch (dssdev->type) {
66 case OMAP_DISPLAY_TYPE_HDMI: 66 case OMAP_DISPLAY_TYPE_HDMI:
67 return DRM_MODE_CONNECTOR_HDMIA; 67 return DRM_MODE_CONNECTOR_HDMIA;
68 case OMAP_DISPLAY_TYPE_DPI: 68 case OMAP_DISPLAY_TYPE_DVI:
69 if (!strcmp(dssdev->name, "dvi")) 69 return DRM_MODE_CONNECTOR_DVID;
70 return DRM_MODE_CONNECTOR_DVID;
71 /* fallthrough */
72 default: 70 default:
73 return DRM_MODE_CONNECTOR_Unknown; 71 return DRM_MODE_CONNECTOR_Unknown;
74 } 72 }
@@ -97,6 +95,9 @@ static int omap_modeset_init(struct drm_device *dev)
97 int num_mgrs = dss_feat_get_num_mgrs(); 95 int num_mgrs = dss_feat_get_num_mgrs();
98 int num_crtcs; 96 int num_crtcs;
99 int i, id = 0; 97 int i, id = 0;
98 int r;
99
100 omap_crtc_pre_init();
100 101
101 drm_mode_config_init(dev); 102 drm_mode_config_init(dev);
102 103
@@ -116,6 +117,7 @@ static int omap_modeset_init(struct drm_device *dev)
116 struct drm_connector *connector; 117 struct drm_connector *connector;
117 struct drm_encoder *encoder; 118 struct drm_encoder *encoder;
118 enum omap_channel channel; 119 enum omap_channel channel;
120 struct omap_overlay_manager *mgr;
119 121
120 if (!dssdev->driver) { 122 if (!dssdev->driver) {
121 dev_warn(dev->dev, "%s has no driver.. skipping it\n", 123 dev_warn(dev->dev, "%s has no driver.. skipping it\n",
@@ -131,6 +133,13 @@ static int omap_modeset_init(struct drm_device *dev)
131 continue; 133 continue;
132 } 134 }
133 135
136 r = dssdev->driver->connect(dssdev);
137 if (r) {
138 dev_err(dev->dev, "could not connect display: %s\n",
139 dssdev->name);
140 continue;
141 }
142
134 encoder = omap_encoder_init(dev, dssdev); 143 encoder = omap_encoder_init(dev, dssdev);
135 144
136 if (!encoder) { 145 if (!encoder) {
@@ -172,8 +181,9 @@ static int omap_modeset_init(struct drm_device *dev)
172 * other possible channels to which the encoder can connect are 181 * other possible channels to which the encoder can connect are
173 * not considered. 182 * not considered.
174 */ 183 */
175 channel = dssdev->output->dispc_channel;
176 184
185 mgr = omapdss_find_mgr_from_display(dssdev);
186 channel = mgr->id;
177 /* 187 /*
178 * if this channel hasn't already been taken by a previously 188 * if this channel hasn't already been taken by a previously
179 * allocated crtc, we create a new crtc for it 189 * allocated crtc, we create a new crtc for it
@@ -247,6 +257,9 @@ static int omap_modeset_init(struct drm_device *dev)
247 struct drm_encoder *encoder = priv->encoders[i]; 257 struct drm_encoder *encoder = priv->encoders[i];
248 struct omap_dss_device *dssdev = 258 struct omap_dss_device *dssdev =
249 omap_encoder_get_dssdev(encoder); 259 omap_encoder_get_dssdev(encoder);
260 struct omap_dss_device *output;
261
262 output = omapdss_find_output_from_display(dssdev);
250 263
251 /* figure out which crtc's we can connect the encoder to: */ 264 /* figure out which crtc's we can connect the encoder to: */
252 encoder->possible_crtcs = 0; 265 encoder->possible_crtcs = 0;
@@ -259,9 +272,11 @@ static int omap_modeset_init(struct drm_device *dev)
259 supported_outputs = 272 supported_outputs =
260 dss_feat_get_supported_outputs(crtc_channel); 273 dss_feat_get_supported_outputs(crtc_channel);
261 274
262 if (supported_outputs & dssdev->output->id) 275 if (supported_outputs & output->id)
263 encoder->possible_crtcs |= (1 << id); 276 encoder->possible_crtcs |= (1 << id);
264 } 277 }
278
279 omap_dss_put_device(output);
265 } 280 }
266 281
267 DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n", 282 DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h
index 215a20dd340c..14f17da2ce25 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.h
+++ b/drivers/gpu/drm/omapdrm/omap_drv.h
@@ -157,6 +157,7 @@ const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc);
157enum omap_channel omap_crtc_channel(struct drm_crtc *crtc); 157enum omap_channel omap_crtc_channel(struct drm_crtc *crtc);
158int omap_crtc_apply(struct drm_crtc *crtc, 158int omap_crtc_apply(struct drm_crtc *crtc,
159 struct omap_drm_apply *apply); 159 struct omap_drm_apply *apply);
160void omap_crtc_pre_init(void);
160struct drm_crtc *omap_crtc_init(struct drm_device *dev, 161struct drm_crtc *omap_crtc_init(struct drm_device *dev,
161 struct drm_plane *plane, enum omap_channel channel, int id); 162 struct drm_plane *plane, enum omap_channel channel, int id);
162 163
diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c
index 6ba49d9922f2..27f45e49250d 100644
--- a/drivers/gpu/drm/qxl/qxl_ioctl.c
+++ b/drivers/gpu/drm/qxl/qxl_ioctl.c
@@ -171,6 +171,11 @@ static int qxl_execbuffer_ioctl(struct drm_device *dev, void *data,
171 if (user_cmd.command_size > PAGE_SIZE - sizeof(union qxl_release_info)) 171 if (user_cmd.command_size > PAGE_SIZE - sizeof(union qxl_release_info))
172 return -EINVAL; 172 return -EINVAL;
173 173
174 if (!access_ok(VERIFY_READ,
175 (void *)(unsigned long)user_cmd.command,
176 user_cmd.command_size))
177 return -EFAULT;
178
174 ret = qxl_alloc_release_reserved(qdev, 179 ret = qxl_alloc_release_reserved(qdev,
175 sizeof(union qxl_release_info) + 180 sizeof(union qxl_release_info) +
176 user_cmd.command_size, 181 user_cmd.command_size,
diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c
index 5a82b6b75849..af85299f2126 100644
--- a/drivers/gpu/drm/radeon/mkregtable.c
+++ b/drivers/gpu/drm/radeon/mkregtable.c
@@ -373,19 +373,6 @@ static inline void list_splice_tail_init(struct list_head *list,
373 pos = pos->next) 373 pos = pos->next)
374 374
375/** 375/**
376 * __list_for_each - iterate over a list
377 * @pos: the &struct list_head to use as a loop cursor.
378 * @head: the head for your list.
379 *
380 * This variant differs from list_for_each() in that it's the
381 * simplest possible list iteration code, no prefetching is done.
382 * Use this for code that knows the list to be very short (empty
383 * or 1 entry) most of the time.
384 */
385#define __list_for_each(pos, head) \
386 for (pos = (head)->next; pos != (head); pos = pos->next)
387
388/**
389 * list_for_each_prev - iterate over a list backwards 376 * list_for_each_prev - iterate over a list backwards
390 * @pos: the &struct list_head to use as a loop cursor. 377 * @pos: the &struct list_head to use as a loop cursor.
391 * @head: the head for your list. 378 * @head: the head for your list.
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index b1746741bc59..665ced3b7313 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -230,7 +230,7 @@ static int radeonfb_create(struct drm_fb_helper *helper,
230 230
231 ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj); 231 ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
232 if (ret) { 232 if (ret) {
233 DRM_ERROR("failed to initalise framebuffer %d\n", ret); 233 DRM_ERROR("failed to initialize framebuffer %d\n", ret);
234 goto out_unref; 234 goto out_unref;
235 } 235 }
236 236