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-rw-r--r--drivers/gpu/drm/armada/armada_drm.h1
-rw-r--r--drivers/gpu/drm/armada/armada_drv.c7
-rw-r--r--drivers/gpu/drm/armada/armada_fbdev.c20
-rw-r--r--drivers/gpu/drm/armada/armada_gem.c7
-rw-r--r--drivers/gpu/drm/drm_edid.c12
-rw-r--r--drivers/gpu/drm/drm_stub.c6
-rw-r--r--drivers/gpu/drm/drm_sysfs.c2
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_drv.c35
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fimd.c2
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c20
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c3
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h9
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c41
-rw-r--r--drivers/gpu/drm/i915/i915_gem_context.c16
-rw-r--r--drivers/gpu/drm/i915/i915_gem_dmabuf.c13
-rw-r--r--drivers/gpu/drm/i915/i915_gem_evict.c14
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c88
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c15
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c5
-rw-r--r--drivers/gpu/drm/i915/intel_display.c28
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c34
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h3
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c26
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c58
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c1
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c1
-rw-r--r--drivers/gpu/drm/nouveau/Makefile1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv50.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c3
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c3
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/software/nv50.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/clock.h4
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c7
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c445
-rw-r--r--drivers/gpu/drm/nouveau/dispnv04/overlay.c42
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_display.c3
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.c6
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_hwmon.c1
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c2
-rw-r--r--drivers/gpu/drm/qxl/Kconfig1
-rw-r--r--drivers/gpu/drm/qxl/qxl_display.c2
-rw-r--r--drivers/gpu/drm/qxl/qxl_release.c1
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c4
-rw-r--r--drivers/gpu/drm/radeon/atombios_i2c.c15
-rw-r--r--drivers/gpu/drm/radeon/cik_sdma.c2
-rw-r--r--drivers/gpu/drm/radeon/dce6_afmt.c20
-rw-r--r--drivers/gpu/drm/radeon/evergreen_hdmi.c4
-rw-r--r--drivers/gpu/drm/radeon/ni.c20
-rw-r--r--drivers/gpu/drm/radeon/ni_dpm.c28
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon.h8
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h3
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c16
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c55
-rw-r--r--drivers/gpu/drm/radeon/radeon_trace.h33
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/cayman4
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/evergreen4
-rw-r--r--drivers/gpu/drm/radeon/rs690.c10
-rw-r--r--drivers/gpu/drm/radeon/rv770_dpm.c6
-rw-r--r--drivers/gpu/drm/radeon/si.c11
-rw-r--r--drivers/gpu/drm/tegra/drm.c34
-rw-r--r--drivers/gpu/drm/tegra/drm.h2
-rw-r--r--drivers/gpu/drm/tegra/fb.c2
-rw-r--r--drivers/gpu/drm/tegra/rgb.c11
-rw-r--r--drivers/gpu/drm/ttm/ttm_bo_util.c3
-rw-r--r--drivers/gpu/drm/ttm/ttm_bo_vm.c6
-rw-r--r--drivers/gpu/drm/udl/udl_gem.c6
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c2
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.h1
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_kms.c1
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c4
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_resource.c118
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c5
-rw-r--r--drivers/gpu/host1x/bus.c5
-rw-r--r--drivers/gpu/host1x/hw/cdma_hw.c4
-rw-r--r--drivers/gpu/host1x/hw/debug_hw.c4
82 files changed, 1114 insertions, 363 deletions
diff --git a/drivers/gpu/drm/armada/armada_drm.h b/drivers/gpu/drm/armada/armada_drm.h
index eef09ec9a5ff..a72cae03b99b 100644
--- a/drivers/gpu/drm/armada/armada_drm.h
+++ b/drivers/gpu/drm/armada/armada_drm.h
@@ -103,6 +103,7 @@ void armada_drm_queue_unref_work(struct drm_device *,
103extern const struct drm_mode_config_funcs armada_drm_mode_config_funcs; 103extern const struct drm_mode_config_funcs armada_drm_mode_config_funcs;
104 104
105int armada_fbdev_init(struct drm_device *); 105int armada_fbdev_init(struct drm_device *);
106void armada_fbdev_lastclose(struct drm_device *);
106void armada_fbdev_fini(struct drm_device *); 107void armada_fbdev_fini(struct drm_device *);
107 108
108int armada_overlay_plane_create(struct drm_device *, unsigned long); 109int armada_overlay_plane_create(struct drm_device *, unsigned long);
diff --git a/drivers/gpu/drm/armada/armada_drv.c b/drivers/gpu/drm/armada/armada_drv.c
index 4f2b28354915..62d0ff3efddf 100644
--- a/drivers/gpu/drm/armada/armada_drv.c
+++ b/drivers/gpu/drm/armada/armada_drv.c
@@ -321,6 +321,11 @@ static struct drm_ioctl_desc armada_ioctls[] = {
321 DRM_UNLOCKED), 321 DRM_UNLOCKED),
322}; 322};
323 323
324static void armada_drm_lastclose(struct drm_device *dev)
325{
326 armada_fbdev_lastclose(dev);
327}
328
324static const struct file_operations armada_drm_fops = { 329static const struct file_operations armada_drm_fops = {
325 .owner = THIS_MODULE, 330 .owner = THIS_MODULE,
326 .llseek = no_llseek, 331 .llseek = no_llseek,
@@ -337,7 +342,7 @@ static struct drm_driver armada_drm_driver = {
337 .open = NULL, 342 .open = NULL,
338 .preclose = NULL, 343 .preclose = NULL,
339 .postclose = NULL, 344 .postclose = NULL,
340 .lastclose = NULL, 345 .lastclose = armada_drm_lastclose,
341 .unload = armada_drm_unload, 346 .unload = armada_drm_unload,
342 .get_vblank_counter = drm_vblank_count, 347 .get_vblank_counter = drm_vblank_count,
343 .enable_vblank = armada_drm_enable_vblank, 348 .enable_vblank = armada_drm_enable_vblank,
diff --git a/drivers/gpu/drm/armada/armada_fbdev.c b/drivers/gpu/drm/armada/armada_fbdev.c
index dd5ea77dac96..948cb14c561e 100644
--- a/drivers/gpu/drm/armada/armada_fbdev.c
+++ b/drivers/gpu/drm/armada/armada_fbdev.c
@@ -105,9 +105,9 @@ static int armada_fb_create(struct drm_fb_helper *fbh,
105 drm_fb_helper_fill_fix(info, dfb->fb.pitches[0], dfb->fb.depth); 105 drm_fb_helper_fill_fix(info, dfb->fb.pitches[0], dfb->fb.depth);
106 drm_fb_helper_fill_var(info, fbh, sizes->fb_width, sizes->fb_height); 106 drm_fb_helper_fill_var(info, fbh, sizes->fb_width, sizes->fb_height);
107 107
108 DRM_DEBUG_KMS("allocated %dx%d %dbpp fb: 0x%08x\n", 108 DRM_DEBUG_KMS("allocated %dx%d %dbpp fb: 0x%08llx\n",
109 dfb->fb.width, dfb->fb.height, 109 dfb->fb.width, dfb->fb.height, dfb->fb.bits_per_pixel,
110 dfb->fb.bits_per_pixel, obj->phys_addr); 110 (unsigned long long)obj->phys_addr);
111 111
112 return 0; 112 return 0;
113 113
@@ -177,6 +177,16 @@ int armada_fbdev_init(struct drm_device *dev)
177 return ret; 177 return ret;
178} 178}
179 179
180void armada_fbdev_lastclose(struct drm_device *dev)
181{
182 struct armada_private *priv = dev->dev_private;
183
184 drm_modeset_lock_all(dev);
185 if (priv->fbdev)
186 drm_fb_helper_restore_fbdev_mode(priv->fbdev);
187 drm_modeset_unlock_all(dev);
188}
189
180void armada_fbdev_fini(struct drm_device *dev) 190void armada_fbdev_fini(struct drm_device *dev)
181{ 191{
182 struct armada_private *priv = dev->dev_private; 192 struct armada_private *priv = dev->dev_private;
@@ -192,11 +202,11 @@ void armada_fbdev_fini(struct drm_device *dev)
192 framebuffer_release(info); 202 framebuffer_release(info);
193 } 203 }
194 204
205 drm_fb_helper_fini(fbh);
206
195 if (fbh->fb) 207 if (fbh->fb)
196 fbh->fb->funcs->destroy(fbh->fb); 208 fbh->fb->funcs->destroy(fbh->fb);
197 209
198 drm_fb_helper_fini(fbh);
199
200 priv->fbdev = NULL; 210 priv->fbdev = NULL;
201 } 211 }
202} 212}
diff --git a/drivers/gpu/drm/armada/armada_gem.c b/drivers/gpu/drm/armada/armada_gem.c
index 9f2356bae7fd..887816f43476 100644
--- a/drivers/gpu/drm/armada/armada_gem.c
+++ b/drivers/gpu/drm/armada/armada_gem.c
@@ -172,8 +172,9 @@ armada_gem_linear_back(struct drm_device *dev, struct armada_gem_object *obj)
172 obj->dev_addr = obj->linear->start; 172 obj->dev_addr = obj->linear->start;
173 } 173 }
174 174
175 DRM_DEBUG_DRIVER("obj %p phys %#x dev %#x\n", 175 DRM_DEBUG_DRIVER("obj %p phys %#llx dev %#llx\n", obj,
176 obj, obj->phys_addr, obj->dev_addr); 176 (unsigned long long)obj->phys_addr,
177 (unsigned long long)obj->dev_addr);
177 178
178 return 0; 179 return 0;
179} 180}
@@ -557,7 +558,6 @@ armada_gem_prime_import(struct drm_device *dev, struct dma_buf *buf)
557 * refcount on the gem object itself. 558 * refcount on the gem object itself.
558 */ 559 */
559 drm_gem_object_reference(obj); 560 drm_gem_object_reference(obj);
560 dma_buf_put(buf);
561 return obj; 561 return obj;
562 } 562 }
563 } 563 }
@@ -573,6 +573,7 @@ armada_gem_prime_import(struct drm_device *dev, struct dma_buf *buf)
573 } 573 }
574 574
575 dobj->obj.import_attach = attach; 575 dobj->obj.import_attach = attach;
576 get_dma_buf(buf);
576 577
577 /* 578 /*
578 * Don't call dma_buf_map_attachment() here - it maps the 579 * Don't call dma_buf_map_attachment() here - it maps the
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fb7cf0e796f6..8835dcddfac3 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -68,6 +68,8 @@
68#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 68#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
69/* Force reduced-blanking timings for detailed modes */ 69/* Force reduced-blanking timings for detailed modes */
70#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 70#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
71/* Force 8bpc */
72#define EDID_QUIRK_FORCE_8BPC (1 << 8)
71 73
72struct detailed_mode_closure { 74struct detailed_mode_closure {
73 struct drm_connector *connector; 75 struct drm_connector *connector;
@@ -128,6 +130,9 @@ static struct edid_quirk {
128 130
129 /* Medion MD 30217 PG */ 131 /* Medion MD 30217 PG */
130 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 132 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
133
134 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
135 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
131}; 136};
132 137
133/* 138/*
@@ -2674,7 +2679,7 @@ static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
2674 int modes = 0; 2679 int modes = 0;
2675 u8 cea_mode; 2680 u8 cea_mode;
2676 2681
2677 if (video_db == NULL || video_index > video_len) 2682 if (video_db == NULL || video_index >= video_len)
2678 return 0; 2683 return 0;
2679 2684
2680 /* CEA modes are numbered 1..127 */ 2685 /* CEA modes are numbered 1..127 */
@@ -2701,7 +2706,7 @@ static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
2701 if (structure & (1 << 8)) { 2706 if (structure & (1 << 8)) {
2702 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2707 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]);
2703 if (newmode) { 2708 if (newmode) {
2704 newmode->flags = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2709 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
2705 drm_mode_probed_add(connector, newmode); 2710 drm_mode_probed_add(connector, newmode);
2706 modes++; 2711 modes++;
2707 } 2712 }
@@ -3435,6 +3440,9 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
3435 3440
3436 drm_add_display_info(edid, &connector->display_info); 3441 drm_add_display_info(edid, &connector->display_info);
3437 3442
3443 if (quirks & EDID_QUIRK_FORCE_8BPC)
3444 connector->display_info.bpc = 8;
3445
3438 return num_modes; 3446 return num_modes;
3439} 3447}
3440EXPORT_SYMBOL(drm_add_edid_modes); 3448EXPORT_SYMBOL(drm_add_edid_modes);
diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c
index f53d5246979c..66dd3a001cf1 100644
--- a/drivers/gpu/drm/drm_stub.c
+++ b/drivers/gpu/drm/drm_stub.c
@@ -566,11 +566,11 @@ err_unload:
566 if (dev->driver->unload) 566 if (dev->driver->unload)
567 dev->driver->unload(dev); 567 dev->driver->unload(dev);
568err_primary_node: 568err_primary_node:
569 drm_put_minor(dev->primary); 569 drm_unplug_minor(dev->primary);
570err_render_node: 570err_render_node:
571 drm_put_minor(dev->render); 571 drm_unplug_minor(dev->render);
572err_control_node: 572err_control_node:
573 drm_put_minor(dev->control); 573 drm_unplug_minor(dev->control);
574err_agp: 574err_agp:
575 if (dev->driver->bus->agp_destroy) 575 if (dev->driver->bus->agp_destroy)
576 dev->driver->bus->agp_destroy(dev); 576 dev->driver->bus->agp_destroy(dev);
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index bd2bca395792..c22c3097c3e8 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -516,7 +516,7 @@ int drm_sysfs_device_add(struct drm_minor *minor)
516 minor_str = "card%d"; 516 minor_str = "card%d";
517 517
518 minor->kdev = kzalloc(sizeof(*minor->kdev), GFP_KERNEL); 518 minor->kdev = kzalloc(sizeof(*minor->kdev), GFP_KERNEL);
519 if (!minor->dev) { 519 if (!minor->kdev) {
520 r = -ENOMEM; 520 r = -ENOMEM;
521 goto error; 521 goto error;
522 } 522 }
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index b676006a95a0..22b8f5eced80 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -173,28 +173,37 @@ static int exynos_drm_open(struct drm_device *dev, struct drm_file *file)
173static void exynos_drm_preclose(struct drm_device *dev, 173static void exynos_drm_preclose(struct drm_device *dev,
174 struct drm_file *file) 174 struct drm_file *file)
175{ 175{
176 exynos_drm_subdrv_close(dev, file);
177}
178
179static void exynos_drm_postclose(struct drm_device *dev, struct drm_file *file)
180{
176 struct exynos_drm_private *private = dev->dev_private; 181 struct exynos_drm_private *private = dev->dev_private;
177 struct drm_pending_vblank_event *e, *t; 182 struct drm_pending_vblank_event *v, *vt;
183 struct drm_pending_event *e, *et;
178 unsigned long flags; 184 unsigned long flags;
179 185
180 /* release events of current file */ 186 if (!file->driver_priv)
187 return;
188
189 /* Release all events not unhandled by page flip handler. */
181 spin_lock_irqsave(&dev->event_lock, flags); 190 spin_lock_irqsave(&dev->event_lock, flags);
182 list_for_each_entry_safe(e, t, &private->pageflip_event_list, 191 list_for_each_entry_safe(v, vt, &private->pageflip_event_list,
183 base.link) { 192 base.link) {
184 if (e->base.file_priv == file) { 193 if (v->base.file_priv == file) {
185 list_del(&e->base.link); 194 list_del(&v->base.link);
186 e->base.destroy(&e->base); 195 drm_vblank_put(dev, v->pipe);
196 v->base.destroy(&v->base);
187 } 197 }
188 } 198 }
189 spin_unlock_irqrestore(&dev->event_lock, flags);
190 199
191 exynos_drm_subdrv_close(dev, file); 200 /* Release all events handled by page flip handler but not freed. */
192} 201 list_for_each_entry_safe(e, et, &file->event_list, link) {
202 list_del(&e->link);
203 e->destroy(e);
204 }
205 spin_unlock_irqrestore(&dev->event_lock, flags);
193 206
194static void exynos_drm_postclose(struct drm_device *dev, struct drm_file *file)
195{
196 if (!file->driver_priv)
197 return;
198 207
199 kfree(file->driver_priv); 208 kfree(file->driver_priv);
200 file->driver_priv = NULL; 209 file->driver_priv = NULL;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 23da72b5eae9..a61878bf5dcd 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -31,7 +31,7 @@
31#include "exynos_drm_iommu.h" 31#include "exynos_drm_iommu.h"
32 32
33/* 33/*
34 * FIMD is stand for Fully Interactive Mobile Display and 34 * FIMD stands for Fully Interactive Mobile Display and
35 * as a display controller, it transfers contents drawn on memory 35 * as a display controller, it transfers contents drawn on memory
36 * to a LCD Panel through Display Interfaces such as RGB or 36 * to a LCD Panel through Display Interfaces such as RGB or
37 * CPU Interface. 37 * CPU Interface.
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 0cab2d045135..5c648425c1e0 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -83,6 +83,14 @@ void i915_update_dri1_breadcrumb(struct drm_device *dev)
83 drm_i915_private_t *dev_priv = dev->dev_private; 83 drm_i915_private_t *dev_priv = dev->dev_private;
84 struct drm_i915_master_private *master_priv; 84 struct drm_i915_master_private *master_priv;
85 85
86 /*
87 * The dri breadcrumb update races against the drm master disappearing.
88 * Instead of trying to fix this (this is by far not the only ums issue)
89 * just don't do the update in kms mode.
90 */
91 if (drm_core_check_feature(dev, DRIVER_MODESET))
92 return;
93
86 if (dev->primary->master) { 94 if (dev->primary->master) {
87 master_priv = dev->primary->master->driver_priv; 95 master_priv = dev->primary->master->driver_priv;
88 if (master_priv->sarea_priv) 96 if (master_priv->sarea_priv)
@@ -1490,16 +1498,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1490 spin_lock_init(&dev_priv->uncore.lock); 1498 spin_lock_init(&dev_priv->uncore.lock);
1491 spin_lock_init(&dev_priv->mm.object_stat_lock); 1499 spin_lock_init(&dev_priv->mm.object_stat_lock);
1492 mutex_init(&dev_priv->dpio_lock); 1500 mutex_init(&dev_priv->dpio_lock);
1493 mutex_init(&dev_priv->rps.hw_lock);
1494 mutex_init(&dev_priv->modeset_restore_lock); 1501 mutex_init(&dev_priv->modeset_restore_lock);
1495 1502
1496 mutex_init(&dev_priv->pc8.lock); 1503 intel_pm_setup(dev);
1497 dev_priv->pc8.requirements_met = false;
1498 dev_priv->pc8.gpu_idle = false;
1499 dev_priv->pc8.irqs_disabled = false;
1500 dev_priv->pc8.enabled = false;
1501 dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
1502 INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
1503 1504
1504 intel_display_crc_init(dev); 1505 intel_display_crc_init(dev);
1505 1506
@@ -1603,7 +1604,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1603 } 1604 }
1604 1605
1605 intel_irq_init(dev); 1606 intel_irq_init(dev);
1606 intel_pm_init(dev);
1607 intel_uncore_sanitize(dev); 1607 intel_uncore_sanitize(dev);
1608 1608
1609 /* Try to make sure MCHBAR is enabled before poking at it */ 1609 /* Try to make sure MCHBAR is enabled before poking at it */
@@ -1848,8 +1848,10 @@ void i915_driver_lastclose(struct drm_device * dev)
1848 1848
1849void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) 1849void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1850{ 1850{
1851 mutex_lock(&dev->struct_mutex);
1851 i915_gem_context_close(dev, file_priv); 1852 i915_gem_context_close(dev, file_priv);
1852 i915_gem_release(dev, file_priv); 1853 i915_gem_release(dev, file_priv);
1854 mutex_unlock(&dev->struct_mutex);
1853} 1855}
1854 1856
1855void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1857void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 989be12cdd6e..5b7b7e06cb3a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -534,8 +534,10 @@ static int i915_drm_freeze(struct drm_device *dev)
534 * Disable CRTCs directly since we want to preserve sw state 534 * Disable CRTCs directly since we want to preserve sw state
535 * for _thaw. 535 * for _thaw.
536 */ 536 */
537 mutex_lock(&dev->mode_config.mutex);
537 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 538 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
538 dev_priv->display.crtc_disable(crtc); 539 dev_priv->display.crtc_disable(crtc);
540 mutex_unlock(&dev->mode_config.mutex);
539 541
540 intel_modeset_suspend_hw(dev); 542 intel_modeset_suspend_hw(dev);
541 } 543 }
@@ -649,6 +651,7 @@ static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
649 intel_modeset_init_hw(dev); 651 intel_modeset_init_hw(dev);
650 652
651 drm_modeset_lock_all(dev); 653 drm_modeset_lock_all(dev);
654 drm_mode_config_reset(dev);
652 intel_modeset_setup_hw_state(dev, true); 655 intel_modeset_setup_hw_state(dev, true);
653 drm_modeset_unlock_all(dev); 656 drm_modeset_unlock_all(dev);
654 657
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ccdbecca070d..90fcccba17b0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1755,8 +1755,13 @@ struct drm_i915_file_private {
1755#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1755#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1756#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 1756#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1757 ((dev)->pdev->device & 0xFF00) == 0x0C00) 1757 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1758#define IS_ULT(dev) (IS_HASWELL(dev) && \ 1758#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1759 (((dev)->pdev->device & 0xf) == 0x2 || \
1760 ((dev)->pdev->device & 0xf) == 0x6 || \
1761 ((dev)->pdev->device & 0xf) == 0xe))
1762#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1759 ((dev)->pdev->device & 0xFF00) == 0x0A00) 1763 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1764#define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1760#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 1765#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1761 ((dev)->pdev->device & 0x00F0) == 0x0020) 1766 ((dev)->pdev->device & 0x00F0) == 0x0020)
1762#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 1767#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
@@ -1901,9 +1906,7 @@ void i915_queue_hangcheck(struct drm_device *dev);
1901void i915_handle_error(struct drm_device *dev, bool wedged); 1906void i915_handle_error(struct drm_device *dev, bool wedged);
1902 1907
1903extern void intel_irq_init(struct drm_device *dev); 1908extern void intel_irq_init(struct drm_device *dev);
1904extern void intel_pm_init(struct drm_device *dev);
1905extern void intel_hpd_init(struct drm_device *dev); 1909extern void intel_hpd_init(struct drm_device *dev);
1906extern void intel_pm_init(struct drm_device *dev);
1907 1910
1908extern void intel_uncore_sanitize(struct drm_device *dev); 1911extern void intel_uncore_sanitize(struct drm_device *dev);
1909extern void intel_uncore_early_sanitize(struct drm_device *dev); 1912extern void intel_uncore_early_sanitize(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 12bbd5eac70d..76d3d1ab73c6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2343,15 +2343,24 @@ static void i915_gem_free_request(struct drm_i915_gem_request *request)
2343 kfree(request); 2343 kfree(request);
2344} 2344}
2345 2345
2346static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, 2346static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2347 struct intel_ring_buffer *ring) 2347 struct intel_ring_buffer *ring)
2348{ 2348{
2349 u32 completed_seqno; 2349 u32 completed_seqno = ring->get_seqno(ring, false);
2350 u32 acthd; 2350 u32 acthd = intel_ring_get_active_head(ring);
2351 struct drm_i915_gem_request *request;
2352
2353 list_for_each_entry(request, &ring->request_list, list) {
2354 if (i915_seqno_passed(completed_seqno, request->seqno))
2355 continue;
2351 2356
2352 acthd = intel_ring_get_active_head(ring); 2357 i915_set_reset_status(ring, request, acthd);
2353 completed_seqno = ring->get_seqno(ring, false); 2358 }
2359}
2354 2360
2361static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2362 struct intel_ring_buffer *ring)
2363{
2355 while (!list_empty(&ring->request_list)) { 2364 while (!list_empty(&ring->request_list)) {
2356 struct drm_i915_gem_request *request; 2365 struct drm_i915_gem_request *request;
2357 2366
@@ -2359,9 +2368,6 @@ static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2359 struct drm_i915_gem_request, 2368 struct drm_i915_gem_request,
2360 list); 2369 list);
2361 2370
2362 if (request->seqno > completed_seqno)
2363 i915_set_reset_status(ring, request, acthd);
2364
2365 i915_gem_free_request(request); 2371 i915_gem_free_request(request);
2366 } 2372 }
2367 2373
@@ -2403,8 +2409,16 @@ void i915_gem_reset(struct drm_device *dev)
2403 struct intel_ring_buffer *ring; 2409 struct intel_ring_buffer *ring;
2404 int i; 2410 int i;
2405 2411
2412 /*
2413 * Before we free the objects from the requests, we need to inspect
2414 * them for finding the guilty party. As the requests only borrow
2415 * their reference to the objects, the inspection must be done first.
2416 */
2417 for_each_ring(ring, dev_priv, i)
2418 i915_gem_reset_ring_status(dev_priv, ring);
2419
2406 for_each_ring(ring, dev_priv, i) 2420 for_each_ring(ring, dev_priv, i)
2407 i915_gem_reset_ring_lists(dev_priv, ring); 2421 i915_gem_reset_ring_cleanup(dev_priv, ring);
2408 2422
2409 i915_gem_cleanup_ringbuffer(dev); 2423 i915_gem_cleanup_ringbuffer(dev);
2410 2424
@@ -4442,10 +4456,9 @@ i915_gem_init_hw(struct drm_device *dev)
4442 if (dev_priv->ellc_size) 4456 if (dev_priv->ellc_size)
4443 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); 4457 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4444 4458
4445 if (IS_HSW_GT3(dev)) 4459 if (IS_HASWELL(dev))
4446 I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); 4460 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4447 else 4461 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4448 I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED);
4449 4462
4450 if (HAS_PCH_NOP(dev)) { 4463 if (HAS_PCH_NOP(dev)) {
4451 u32 temp = I915_READ(GEN7_MSG_CTL); 4464 u32 temp = I915_READ(GEN7_MSG_CTL);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 72a3df32292f..b0f42b9ca037 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -347,10 +347,8 @@ void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
347{ 347{
348 struct drm_i915_file_private *file_priv = file->driver_priv; 348 struct drm_i915_file_private *file_priv = file->driver_priv;
349 349
350 mutex_lock(&dev->struct_mutex);
351 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); 350 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
352 idr_destroy(&file_priv->context_idr); 351 idr_destroy(&file_priv->context_idr);
353 mutex_unlock(&dev->struct_mutex);
354} 352}
355 353
356static struct i915_hw_context * 354static struct i915_hw_context *
@@ -423,11 +421,21 @@ static int do_switch(struct i915_hw_context *to)
423 if (ret) 421 if (ret)
424 return ret; 422 return ret;
425 423
426 /* Clear this page out of any CPU caches for coherent swap-in/out. Note 424 /*
425 * Pin can switch back to the default context if we end up calling into
426 * evict_everything - as a last ditch gtt defrag effort that also
427 * switches to the default context. Hence we need to reload from here.
428 */
429 from = ring->last_context;
430
431 /*
432 * Clear this page out of any CPU caches for coherent swap-in/out. Note
427 * that thanks to write = false in this call and us not setting any gpu 433 * that thanks to write = false in this call and us not setting any gpu
428 * write domains when putting a context object onto the active list 434 * write domains when putting a context object onto the active list
429 * (when switching away from it), this won't block. 435 * (when switching away from it), this won't block.
430 * XXX: We need a real interface to do this instead of trickery. */ 436 *
437 * XXX: We need a real interface to do this instead of trickery.
438 */
431 ret = i915_gem_object_set_to_gtt_domain(to->obj, false); 439 ret = i915_gem_object_set_to_gtt_domain(to->obj, false);
432 if (ret) { 440 if (ret) {
433 i915_gem_object_unpin(to->obj); 441 i915_gem_object_unpin(to->obj);
diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
index 7d5752fda5f1..9bb533e0d762 100644
--- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
@@ -125,13 +125,15 @@ static void *i915_gem_dmabuf_vmap(struct dma_buf *dma_buf)
125 125
126 ret = i915_gem_object_get_pages(obj); 126 ret = i915_gem_object_get_pages(obj);
127 if (ret) 127 if (ret)
128 goto error; 128 goto err;
129
130 i915_gem_object_pin_pages(obj);
129 131
130 ret = -ENOMEM; 132 ret = -ENOMEM;
131 133
132 pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages)); 134 pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
133 if (pages == NULL) 135 if (pages == NULL)
134 goto error; 136 goto err_unpin;
135 137
136 i = 0; 138 i = 0;
137 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) 139 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
@@ -141,15 +143,16 @@ static void *i915_gem_dmabuf_vmap(struct dma_buf *dma_buf)
141 drm_free_large(pages); 143 drm_free_large(pages);
142 144
143 if (!obj->dma_buf_vmapping) 145 if (!obj->dma_buf_vmapping)
144 goto error; 146 goto err_unpin;
145 147
146 obj->vmapping_count = 1; 148 obj->vmapping_count = 1;
147 i915_gem_object_pin_pages(obj);
148out_unlock: 149out_unlock:
149 mutex_unlock(&dev->struct_mutex); 150 mutex_unlock(&dev->struct_mutex);
150 return obj->dma_buf_vmapping; 151 return obj->dma_buf_vmapping;
151 152
152error: 153err_unpin:
154 i915_gem_object_unpin_pages(obj);
155err:
153 mutex_unlock(&dev->struct_mutex); 156 mutex_unlock(&dev->struct_mutex);
154 return ERR_PTR(ret); 157 return ERR_PTR(ret);
155} 158}
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
index b7376533633d..8f3adc7d0dc8 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -88,6 +88,7 @@ i915_gem_evict_something(struct drm_device *dev, struct i915_address_space *vm,
88 } else 88 } else
89 drm_mm_init_scan(&vm->mm, min_size, alignment, cache_level); 89 drm_mm_init_scan(&vm->mm, min_size, alignment, cache_level);
90 90
91search_again:
91 /* First see if there is a large enough contiguous idle region... */ 92 /* First see if there is a large enough contiguous idle region... */
92 list_for_each_entry(vma, &vm->inactive_list, mm_list) { 93 list_for_each_entry(vma, &vm->inactive_list, mm_list) {
93 if (mark_free(vma, &unwind_list)) 94 if (mark_free(vma, &unwind_list))
@@ -115,10 +116,17 @@ none:
115 list_del_init(&vma->exec_list); 116 list_del_init(&vma->exec_list);
116 } 117 }
117 118
118 /* We expect the caller to unpin, evict all and try again, or give up. 119 /* Can we unpin some objects such as idle hw contents,
119 * So calling i915_gem_evict_vm() is unnecessary. 120 * or pending flips?
120 */ 121 */
121 return -ENOSPC; 122 ret = nonblocking ? -ENOSPC : i915_gpu_idle(dev);
123 if (ret)
124 return ret;
125
126 /* Only idle the GPU and repeat the search once */
127 i915_gem_retire_requests(dev);
128 nonblocking = true;
129 goto search_again;
122 130
123found: 131found:
124 /* drm_mm doesn't allow any other other operations while 132 /* drm_mm doesn't allow any other other operations while
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 885d595e0e02..a3ba9a8cd687 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -33,6 +33,9 @@
33#include "intel_drv.h" 33#include "intel_drv.h"
34#include <linux/dma_remapping.h> 34#include <linux/dma_remapping.h>
35 35
36#define __EXEC_OBJECT_HAS_PIN (1<<31)
37#define __EXEC_OBJECT_HAS_FENCE (1<<30)
38
36struct eb_vmas { 39struct eb_vmas {
37 struct list_head vmas; 40 struct list_head vmas;
38 int and; 41 int and;
@@ -90,7 +93,7 @@ eb_lookup_vmas(struct eb_vmas *eb,
90{ 93{
91 struct drm_i915_gem_object *obj; 94 struct drm_i915_gem_object *obj;
92 struct list_head objects; 95 struct list_head objects;
93 int i, ret = 0; 96 int i, ret;
94 97
95 INIT_LIST_HEAD(&objects); 98 INIT_LIST_HEAD(&objects);
96 spin_lock(&file->table_lock); 99 spin_lock(&file->table_lock);
@@ -103,7 +106,7 @@ eb_lookup_vmas(struct eb_vmas *eb,
103 DRM_DEBUG("Invalid object handle %d at index %d\n", 106 DRM_DEBUG("Invalid object handle %d at index %d\n",
104 exec[i].handle, i); 107 exec[i].handle, i);
105 ret = -ENOENT; 108 ret = -ENOENT;
106 goto out; 109 goto err;
107 } 110 }
108 111
109 if (!list_empty(&obj->obj_exec_link)) { 112 if (!list_empty(&obj->obj_exec_link)) {
@@ -111,7 +114,7 @@ eb_lookup_vmas(struct eb_vmas *eb,
111 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", 114 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
112 obj, exec[i].handle, i); 115 obj, exec[i].handle, i);
113 ret = -EINVAL; 116 ret = -EINVAL;
114 goto out; 117 goto err;
115 } 118 }
116 119
117 drm_gem_object_reference(&obj->base); 120 drm_gem_object_reference(&obj->base);
@@ -120,9 +123,13 @@ eb_lookup_vmas(struct eb_vmas *eb,
120 spin_unlock(&file->table_lock); 123 spin_unlock(&file->table_lock);
121 124
122 i = 0; 125 i = 0;
123 list_for_each_entry(obj, &objects, obj_exec_link) { 126 while (!list_empty(&objects)) {
124 struct i915_vma *vma; 127 struct i915_vma *vma;
125 128
129 obj = list_first_entry(&objects,
130 struct drm_i915_gem_object,
131 obj_exec_link);
132
126 /* 133 /*
127 * NOTE: We can leak any vmas created here when something fails 134 * NOTE: We can leak any vmas created here when something fails
128 * later on. But that's no issue since vma_unbind can deal with 135 * later on. But that's no issue since vma_unbind can deal with
@@ -135,10 +142,12 @@ eb_lookup_vmas(struct eb_vmas *eb,
135 if (IS_ERR(vma)) { 142 if (IS_ERR(vma)) {
136 DRM_DEBUG("Failed to lookup VMA\n"); 143 DRM_DEBUG("Failed to lookup VMA\n");
137 ret = PTR_ERR(vma); 144 ret = PTR_ERR(vma);
138 goto out; 145 goto err;
139 } 146 }
140 147
148 /* Transfer ownership from the objects list to the vmas list. */
141 list_add_tail(&vma->exec_list, &eb->vmas); 149 list_add_tail(&vma->exec_list, &eb->vmas);
150 list_del_init(&obj->obj_exec_link);
142 151
143 vma->exec_entry = &exec[i]; 152 vma->exec_entry = &exec[i];
144 if (eb->and < 0) { 153 if (eb->and < 0) {
@@ -152,16 +161,22 @@ eb_lookup_vmas(struct eb_vmas *eb,
152 ++i; 161 ++i;
153 } 162 }
154 163
164 return 0;
155 165
156out: 166
167err:
157 while (!list_empty(&objects)) { 168 while (!list_empty(&objects)) {
158 obj = list_first_entry(&objects, 169 obj = list_first_entry(&objects,
159 struct drm_i915_gem_object, 170 struct drm_i915_gem_object,
160 obj_exec_link); 171 obj_exec_link);
161 list_del_init(&obj->obj_exec_link); 172 list_del_init(&obj->obj_exec_link);
162 if (ret) 173 drm_gem_object_unreference(&obj->base);
163 drm_gem_object_unreference(&obj->base);
164 } 174 }
175 /*
176 * Objects already transfered to the vmas list will be unreferenced by
177 * eb_destroy.
178 */
179
165 return ret; 180 return ret;
166} 181}
167 182
@@ -187,7 +202,28 @@ static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
187 } 202 }
188} 203}
189 204
190static void eb_destroy(struct eb_vmas *eb) { 205static void
206i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
207{
208 struct drm_i915_gem_exec_object2 *entry;
209 struct drm_i915_gem_object *obj = vma->obj;
210
211 if (!drm_mm_node_allocated(&vma->node))
212 return;
213
214 entry = vma->exec_entry;
215
216 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
217 i915_gem_object_unpin_fence(obj);
218
219 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
220 i915_gem_object_unpin(obj);
221
222 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
223}
224
225static void eb_destroy(struct eb_vmas *eb)
226{
191 while (!list_empty(&eb->vmas)) { 227 while (!list_empty(&eb->vmas)) {
192 struct i915_vma *vma; 228 struct i915_vma *vma;
193 229
@@ -195,6 +231,7 @@ static void eb_destroy(struct eb_vmas *eb) {
195 struct i915_vma, 231 struct i915_vma,
196 exec_list); 232 exec_list);
197 list_del_init(&vma->exec_list); 233 list_del_init(&vma->exec_list);
234 i915_gem_execbuffer_unreserve_vma(vma);
198 drm_gem_object_unreference(&vma->obj->base); 235 drm_gem_object_unreference(&vma->obj->base);
199 } 236 }
200 kfree(eb); 237 kfree(eb);
@@ -478,9 +515,6 @@ i915_gem_execbuffer_relocate(struct eb_vmas *eb,
478 return ret; 515 return ret;
479} 516}
480 517
481#define __EXEC_OBJECT_HAS_PIN (1<<31)
482#define __EXEC_OBJECT_HAS_FENCE (1<<30)
483
484static int 518static int
485need_reloc_mappable(struct i915_vma *vma) 519need_reloc_mappable(struct i915_vma *vma)
486{ 520{
@@ -552,26 +586,6 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
552 return 0; 586 return 0;
553} 587}
554 588
555static void
556i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
557{
558 struct drm_i915_gem_exec_object2 *entry;
559 struct drm_i915_gem_object *obj = vma->obj;
560
561 if (!drm_mm_node_allocated(&vma->node))
562 return;
563
564 entry = vma->exec_entry;
565
566 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
567 i915_gem_object_unpin_fence(obj);
568
569 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
570 i915_gem_object_unpin(obj);
571
572 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
573}
574
575static int 589static int
576i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, 590i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
577 struct list_head *vmas, 591 struct list_head *vmas,
@@ -670,13 +684,14 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
670 goto err; 684 goto err;
671 } 685 }
672 686
673err: /* Decrement pin count for bound objects */ 687err:
674 list_for_each_entry(vma, vmas, exec_list)
675 i915_gem_execbuffer_unreserve_vma(vma);
676
677 if (ret != -ENOSPC || retry++) 688 if (ret != -ENOSPC || retry++)
678 return ret; 689 return ret;
679 690
691 /* Decrement pin count for bound objects */
692 list_for_each_entry(vma, vmas, exec_list)
693 i915_gem_execbuffer_unreserve_vma(vma);
694
680 ret = i915_gem_evict_vm(vm, true); 695 ret = i915_gem_evict_vm(vm, true);
681 if (ret) 696 if (ret)
682 return ret; 697 return ret;
@@ -708,6 +723,7 @@ i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
708 while (!list_empty(&eb->vmas)) { 723 while (!list_empty(&eb->vmas)) {
709 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); 724 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
710 list_del_init(&vma->exec_list); 725 list_del_init(&vma->exec_list);
726 i915_gem_execbuffer_unreserve_vma(vma);
711 drm_gem_object_unreference(&vma->obj->base); 727 drm_gem_object_unreference(&vma->obj->base);
712 } 728 }
713 729
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 3620a1b0a73c..c79dd2b1f70e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -57,7 +57,9 @@ typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
57#define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 57#define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
58#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 58#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
59#define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 59#define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
60#define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
60#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 61#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
62#define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
61 63
62#define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) 64#define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
63#define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) 65#define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
@@ -185,10 +187,10 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
185 case I915_CACHE_NONE: 187 case I915_CACHE_NONE:
186 break; 188 break;
187 case I915_CACHE_WT: 189 case I915_CACHE_WT:
188 pte |= HSW_WT_ELLC_LLC_AGE0; 190 pte |= HSW_WT_ELLC_LLC_AGE3;
189 break; 191 break;
190 default: 192 default:
191 pte |= HSW_WB_ELLC_LLC_AGE0; 193 pte |= HSW_WB_ELLC_LLC_AGE3;
192 break; 194 break;
193 } 195 }
194 196
@@ -335,8 +337,8 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
335 kfree(ppgtt->gen8_pt_dma_addr[i]); 337 kfree(ppgtt->gen8_pt_dma_addr[i]);
336 } 338 }
337 339
338 __free_pages(ppgtt->gen8_pt_pages, ppgtt->num_pt_pages << PAGE_SHIFT); 340 __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
339 __free_pages(ppgtt->pd_pages, ppgtt->num_pd_pages << PAGE_SHIFT); 341 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
340} 342}
341 343
342/** 344/**
@@ -1239,6 +1241,11 @@ static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1239 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; 1241 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1240 if (bdw_gmch_ctl) 1242 if (bdw_gmch_ctl)
1241 bdw_gmch_ctl = 1 << bdw_gmch_ctl; 1243 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1244 if (bdw_gmch_ctl > 4) {
1245 WARN_ON(!i915_preliminary_hw_support);
1246 return 4<<20;
1247 }
1248
1242 return bdw_gmch_ctl << 20; 1249 return bdw_gmch_ctl << 20;
1243} 1250}
1244 1251
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f9eafb6ed523..ee2742122a02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -235,6 +235,7 @@
235 */ 235 */
236#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) 236#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
237#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1) 237#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1)
238#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
238#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 239#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
239#define MI_FLUSH_DW_STORE_INDEX (1<<21) 240#define MI_FLUSH_DW_STORE_INDEX (1<<21)
240#define MI_INVALIDATE_TLB (1<<18) 241#define MI_INVALIDATE_TLB (1<<18)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 330077bcd0bd..526c8ded16b0 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -173,7 +173,7 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
173 ddi_translations = ddi_translations_dp; 173 ddi_translations = ddi_translations_dp;
174 break; 174 break;
175 case PORT_D: 175 case PORT_D:
176 if (intel_dpd_is_edp(dev)) 176 if (intel_dp_is_edp(dev, PORT_D))
177 ddi_translations = ddi_translations_edp; 177 ddi_translations = ddi_translations_edp;
178 else 178 else
179 ddi_translations = ddi_translations_dp; 179 ddi_translations = ddi_translations_dp;
@@ -1158,9 +1158,10 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1158 if (wait) 1158 if (wait)
1159 intel_wait_ddi_buf_idle(dev_priv, port); 1159 intel_wait_ddi_buf_idle(dev_priv, port);
1160 1160
1161 if (type == INTEL_OUTPUT_EDP) { 1161 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1162 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1162 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1163 ironlake_edp_panel_vdd_on(intel_dp); 1163 ironlake_edp_panel_vdd_on(intel_dp);
1164 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1164 ironlake_edp_panel_off(intel_dp); 1165 ironlake_edp_panel_off(intel_dp);
1165 } 1166 }
1166 1167
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7ec8b488bb1d..54e82a80cf50 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5815,7 +5815,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
5815 uint16_t postoff = 0; 5815 uint16_t postoff = 0;
5816 5816
5817 if (intel_crtc->config.limited_color_range) 5817 if (intel_crtc->config.limited_color_range)
5818 postoff = (16 * (1 << 13) / 255) & 0x1fff; 5818 postoff = (16 * (1 << 12) / 255) & 0x1fff;
5819 5819
5820 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); 5820 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5821 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); 5821 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
@@ -6303,7 +6303,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6303 uint32_t val; 6303 uint32_t val;
6304 6304
6305 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) 6305 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6306 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n", 6306 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6307 pipe_name(crtc->pipe)); 6307 pipe_name(crtc->pipe));
6308 6308
6309 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); 6309 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
@@ -6402,7 +6402,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6402 6402
6403 /* Make sure we're not on PC8 state before disabling PC8, otherwise 6403 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6404 * we'll hang the machine! */ 6404 * we'll hang the machine! */
6405 dev_priv->uncore.funcs.force_wake_get(dev_priv); 6405 gen6_gt_force_wake_get(dev_priv);
6406 6406
6407 if (val & LCPLL_POWER_DOWN_ALLOW) { 6407 if (val & LCPLL_POWER_DOWN_ALLOW) {
6408 val &= ~LCPLL_POWER_DOWN_ALLOW; 6408 val &= ~LCPLL_POWER_DOWN_ALLOW;
@@ -6436,7 +6436,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6436 DRM_ERROR("Switching back to LCPLL failed\n"); 6436 DRM_ERROR("Switching back to LCPLL failed\n");
6437 } 6437 }
6438 6438
6439 dev_priv->uncore.funcs.force_wake_put(dev_priv); 6439 gen6_gt_force_wake_put(dev_priv);
6440} 6440}
6441 6441
6442void hsw_enable_pc8_work(struct work_struct *__work) 6442void hsw_enable_pc8_work(struct work_struct *__work)
@@ -8354,7 +8354,8 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
8354 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | 8354 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8355 DERRMR_PIPEB_PRI_FLIP_DONE | 8355 DERRMR_PIPEB_PRI_FLIP_DONE |
8356 DERRMR_PIPEC_PRI_FLIP_DONE)); 8356 DERRMR_PIPEC_PRI_FLIP_DONE));
8357 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); 8357 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8358 MI_SRM_LRM_GLOBAL_GTT);
8358 intel_ring_emit(ring, DERRMR); 8359 intel_ring_emit(ring, DERRMR);
8359 intel_ring_emit(ring, ring->scratch.gtt_offset + 256); 8360 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8360 } 8361 }
@@ -9134,7 +9135,7 @@ intel_pipe_config_compare(struct drm_device *dev,
9134 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) 9135 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9135 PIPE_CONF_CHECK_I(pipe_bpp); 9136 PIPE_CONF_CHECK_I(pipe_bpp);
9136 9137
9137 if (!IS_HASWELL(dev)) { 9138 if (!HAS_DDI(dev)) {
9138 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); 9139 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9139 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 9140 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9140 } 9141 }
@@ -10049,7 +10050,7 @@ static void intel_setup_outputs(struct drm_device *dev)
10049 intel_ddi_init(dev, PORT_D); 10050 intel_ddi_init(dev, PORT_D);
10050 } else if (HAS_PCH_SPLIT(dev)) { 10051 } else if (HAS_PCH_SPLIT(dev)) {
10051 int found; 10052 int found;
10052 dpd_is_edp = intel_dpd_is_edp(dev); 10053 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10053 10054
10054 if (has_edp_a(dev)) 10055 if (has_edp_a(dev))
10055 intel_dp_init(dev, DP_A, PORT_A); 10056 intel_dp_init(dev, DP_A, PORT_A);
@@ -10086,8 +10087,7 @@ static void intel_setup_outputs(struct drm_device *dev)
10086 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, 10087 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10087 PORT_C); 10088 PORT_C);
10088 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) 10089 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10089 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, 10090 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10090 PORT_C);
10091 } 10091 }
10092 10092
10093 intel_dsi_init(dev); 10093 intel_dsi_init(dev);
@@ -11036,8 +11036,6 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
11036 } 11036 }
11037 11037
11038 intel_modeset_check_state(dev); 11038 intel_modeset_check_state(dev);
11039
11040 drm_mode_config_reset(dev);
11041} 11039}
11042 11040
11043void intel_modeset_gem_init(struct drm_device *dev) 11041void intel_modeset_gem_init(struct drm_device *dev)
@@ -11046,7 +11044,10 @@ void intel_modeset_gem_init(struct drm_device *dev)
11046 11044
11047 intel_setup_overlay(dev); 11045 intel_setup_overlay(dev);
11048 11046
11047 drm_modeset_lock_all(dev);
11048 drm_mode_config_reset(dev);
11049 intel_modeset_setup_hw_state(dev, false); 11049 intel_modeset_setup_hw_state(dev, false);
11050 drm_modeset_unlock_all(dev);
11050} 11051}
11051 11052
11052void intel_modeset_cleanup(struct drm_device *dev) 11053void intel_modeset_cleanup(struct drm_device *dev)
@@ -11125,14 +11126,15 @@ void intel_connector_attach_encoder(struct intel_connector *connector,
11125int intel_modeset_vga_set_state(struct drm_device *dev, bool state) 11126int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11126{ 11127{
11127 struct drm_i915_private *dev_priv = dev->dev_private; 11128 struct drm_i915_private *dev_priv = dev->dev_private;
11129 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11128 u16 gmch_ctrl; 11130 u16 gmch_ctrl;
11129 11131
11130 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); 11132 pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl);
11131 if (state) 11133 if (state)
11132 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 11134 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11133 else 11135 else
11134 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 11136 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11135 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); 11137 pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl);
11136 return 0; 11138 return 0;
11137} 11139}
11138 11140
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0b2e842fef01..30c627c7b7ba 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3326,11 +3326,19 @@ intel_trans_dp_port_sel(struct drm_crtc *crtc)
3326} 3326}
3327 3327
3328/* check the VBT to see whether the eDP is on DP-D port */ 3328/* check the VBT to see whether the eDP is on DP-D port */
3329bool intel_dpd_is_edp(struct drm_device *dev) 3329bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3330{ 3330{
3331 struct drm_i915_private *dev_priv = dev->dev_private; 3331 struct drm_i915_private *dev_priv = dev->dev_private;
3332 union child_device_config *p_child; 3332 union child_device_config *p_child;
3333 int i; 3333 int i;
3334 static const short port_mapping[] = {
3335 [PORT_B] = PORT_IDPB,
3336 [PORT_C] = PORT_IDPC,
3337 [PORT_D] = PORT_IDPD,
3338 };
3339
3340 if (port == PORT_A)
3341 return true;
3334 3342
3335 if (!dev_priv->vbt.child_dev_num) 3343 if (!dev_priv->vbt.child_dev_num)
3336 return false; 3344 return false;
@@ -3338,7 +3346,7 @@ bool intel_dpd_is_edp(struct drm_device *dev)
3338 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 3346 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3339 p_child = dev_priv->vbt.child_dev + i; 3347 p_child = dev_priv->vbt.child_dev + i;
3340 3348
3341 if (p_child->common.dvo_port == PORT_IDPD && 3349 if (p_child->common.dvo_port == port_mapping[port] &&
3342 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 3350 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3343 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 3351 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3344 return true; 3352 return true;
@@ -3616,26 +3624,10 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3616 intel_dp->DP = I915_READ(intel_dp->output_reg); 3624 intel_dp->DP = I915_READ(intel_dp->output_reg);
3617 intel_dp->attached_connector = intel_connector; 3625 intel_dp->attached_connector = intel_connector;
3618 3626
3619 type = DRM_MODE_CONNECTOR_DisplayPort; 3627 if (intel_dp_is_edp(dev, port))
3620 /*
3621 * FIXME : We need to initialize built-in panels before external panels.
3622 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3623 */
3624 switch (port) {
3625 case PORT_A:
3626 type = DRM_MODE_CONNECTOR_eDP; 3628 type = DRM_MODE_CONNECTOR_eDP;
3627 break; 3629 else
3628 case PORT_C: 3630 type = DRM_MODE_CONNECTOR_DisplayPort;
3629 if (IS_VALLEYVIEW(dev))
3630 type = DRM_MODE_CONNECTOR_eDP;
3631 break;
3632 case PORT_D:
3633 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3634 type = DRM_MODE_CONNECTOR_eDP;
3635 break;
3636 default: /* silence GCC warning */
3637 break;
3638 }
3639 3631
3640 /* 3632 /*
3641 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 3633 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1e49aa8f5377..79f91f26e288 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -708,7 +708,7 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder);
708void intel_dp_check_link_status(struct intel_dp *intel_dp); 708void intel_dp_check_link_status(struct intel_dp *intel_dp);
709bool intel_dp_compute_config(struct intel_encoder *encoder, 709bool intel_dp_compute_config(struct intel_encoder *encoder,
710 struct intel_crtc_config *pipe_config); 710 struct intel_crtc_config *pipe_config);
711bool intel_dpd_is_edp(struct drm_device *dev); 711bool intel_dp_is_edp(struct drm_device *dev, enum port port);
712void ironlake_edp_backlight_on(struct intel_dp *intel_dp); 712void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
713void ironlake_edp_backlight_off(struct intel_dp *intel_dp); 713void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
714void ironlake_edp_panel_on(struct intel_dp *intel_dp); 714void ironlake_edp_panel_on(struct intel_dp *intel_dp);
@@ -821,6 +821,7 @@ void intel_update_sprite_watermarks(struct drm_plane *plane,
821 uint32_t sprite_width, int pixel_size, 821 uint32_t sprite_width, int pixel_size,
822 bool enabled, bool scaled); 822 bool enabled, bool scaled);
823void intel_init_pm(struct drm_device *dev); 823void intel_init_pm(struct drm_device *dev);
824void intel_pm_setup(struct drm_device *dev);
824bool intel_fbc_enabled(struct drm_device *dev); 825bool intel_fbc_enabled(struct drm_device *dev);
825void intel_update_fbc(struct drm_device *dev); 826void intel_update_fbc(struct drm_device *dev);
826void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 827void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index f161ac02c4f6..e6f782d1c669 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -451,7 +451,9 @@ static u32 intel_panel_get_backlight(struct drm_device *dev,
451 451
452 spin_lock_irqsave(&dev_priv->backlight.lock, flags); 452 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
453 453
454 if (HAS_PCH_SPLIT(dev)) { 454 if (IS_BROADWELL(dev)) {
455 val = I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
456 } else if (HAS_PCH_SPLIT(dev)) {
455 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; 457 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
456 } else { 458 } else {
457 if (IS_VALLEYVIEW(dev)) 459 if (IS_VALLEYVIEW(dev))
@@ -479,6 +481,13 @@ static u32 intel_panel_get_backlight(struct drm_device *dev,
479 return val; 481 return val;
480} 482}
481 483
484static void intel_bdw_panel_set_backlight(struct drm_device *dev, u32 level)
485{
486 struct drm_i915_private *dev_priv = dev->dev_private;
487 u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
488 I915_WRITE(BLC_PWM_PCH_CTL2, val | level);
489}
490
482static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level) 491static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
483{ 492{
484 struct drm_i915_private *dev_priv = dev->dev_private; 493 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -496,7 +505,9 @@ static void intel_panel_actually_set_backlight(struct drm_device *dev,
496 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); 505 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
497 level = intel_panel_compute_brightness(dev, pipe, level); 506 level = intel_panel_compute_brightness(dev, pipe, level);
498 507
499 if (HAS_PCH_SPLIT(dev)) 508 if (IS_BROADWELL(dev))
509 return intel_bdw_panel_set_backlight(dev, level);
510 else if (HAS_PCH_SPLIT(dev))
500 return intel_pch_panel_set_backlight(dev, level); 511 return intel_pch_panel_set_backlight(dev, level);
501 512
502 if (is_backlight_combination_mode(dev)) { 513 if (is_backlight_combination_mode(dev)) {
@@ -666,7 +677,16 @@ void intel_panel_enable_backlight(struct intel_connector *connector)
666 POSTING_READ(reg); 677 POSTING_READ(reg);
667 I915_WRITE(reg, tmp | BLM_PWM_ENABLE); 678 I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
668 679
669 if (HAS_PCH_SPLIT(dev) && 680 if (IS_BROADWELL(dev)) {
681 /*
682 * Broadwell requires PCH override to drive the PCH
683 * backlight pin. The above will configure the CPU
684 * backlight pin, which we don't plan to use.
685 */
686 tmp = I915_READ(BLC_PWM_PCH_CTL1);
687 tmp |= BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE;
688 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
689 } else if (HAS_PCH_SPLIT(dev) &&
670 !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) { 690 !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
671 tmp = I915_READ(BLC_PWM_PCH_CTL1); 691 tmp = I915_READ(BLC_PWM_PCH_CTL1);
672 tmp |= BLM_PCH_PWM_ENABLE; 692 tmp |= BLM_PCH_PWM_ENABLE;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index caf2ee4e5441..26c29c173221 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1180,7 +1180,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
1180 1180
1181 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1181 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1182 clock = adjusted_mode->crtc_clock; 1182 clock = adjusted_mode->crtc_clock;
1183 htotal = adjusted_mode->htotal; 1183 htotal = adjusted_mode->crtc_htotal;
1184 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 1184 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1185 pixel_size = crtc->fb->bits_per_pixel / 8; 1185 pixel_size = crtc->fb->bits_per_pixel / 8;
1186 1186
@@ -1267,7 +1267,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
1267 crtc = intel_get_crtc_for_plane(dev, plane); 1267 crtc = intel_get_crtc_for_plane(dev, plane);
1268 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1268 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1269 clock = adjusted_mode->crtc_clock; 1269 clock = adjusted_mode->crtc_clock;
1270 htotal = adjusted_mode->htotal; 1270 htotal = adjusted_mode->crtc_htotal;
1271 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 1271 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1272 pixel_size = crtc->fb->bits_per_pixel / 8; 1272 pixel_size = crtc->fb->bits_per_pixel / 8;
1273 1273
@@ -1498,7 +1498,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
1498 const struct drm_display_mode *adjusted_mode = 1498 const struct drm_display_mode *adjusted_mode =
1499 &to_intel_crtc(crtc)->config.adjusted_mode; 1499 &to_intel_crtc(crtc)->config.adjusted_mode;
1500 int clock = adjusted_mode->crtc_clock; 1500 int clock = adjusted_mode->crtc_clock;
1501 int htotal = adjusted_mode->htotal; 1501 int htotal = adjusted_mode->crtc_htotal;
1502 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 1502 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1503 int pixel_size = crtc->fb->bits_per_pixel / 8; 1503 int pixel_size = crtc->fb->bits_per_pixel / 8;
1504 unsigned long line_time_us; 1504 unsigned long line_time_us;
@@ -1624,7 +1624,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1624 const struct drm_display_mode *adjusted_mode = 1624 const struct drm_display_mode *adjusted_mode =
1625 &to_intel_crtc(enabled)->config.adjusted_mode; 1625 &to_intel_crtc(enabled)->config.adjusted_mode;
1626 int clock = adjusted_mode->crtc_clock; 1626 int clock = adjusted_mode->crtc_clock;
1627 int htotal = adjusted_mode->htotal; 1627 int htotal = adjusted_mode->crtc_htotal;
1628 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; 1628 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1629 int pixel_size = enabled->fb->bits_per_pixel / 8; 1629 int pixel_size = enabled->fb->bits_per_pixel / 8;
1630 unsigned long line_time_us; 1630 unsigned long line_time_us;
@@ -1776,7 +1776,7 @@ static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1776 crtc = intel_get_crtc_for_plane(dev, plane); 1776 crtc = intel_get_crtc_for_plane(dev, plane);
1777 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1777 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1778 clock = adjusted_mode->crtc_clock; 1778 clock = adjusted_mode->crtc_clock;
1779 htotal = adjusted_mode->htotal; 1779 htotal = adjusted_mode->crtc_htotal;
1780 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 1780 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1781 pixel_size = crtc->fb->bits_per_pixel / 8; 1781 pixel_size = crtc->fb->bits_per_pixel / 8;
1782 1782
@@ -2469,8 +2469,9 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2469 /* The WM are computed with base on how long it takes to fill a single 2469 /* The WM are computed with base on how long it takes to fill a single
2470 * row at the given clock rate, multiplied by 8. 2470 * row at the given clock rate, multiplied by 8.
2471 * */ 2471 * */
2472 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock); 2472 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2473 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, 2473 mode->crtc_clock);
2474 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2474 intel_ddi_get_cdclk_freq(dev_priv)); 2475 intel_ddi_get_cdclk_freq(dev_priv));
2475 2476
2476 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | 2477 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
@@ -5684,8 +5685,11 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable)
5684{ 5685{
5685 struct drm_i915_private *dev_priv = dev->dev_private; 5686 struct drm_i915_private *dev_priv = dev->dev_private;
5686 bool is_enabled, enable_requested; 5687 bool is_enabled, enable_requested;
5688 unsigned long irqflags;
5687 uint32_t tmp; 5689 uint32_t tmp;
5688 5690
5691 WARN_ON(dev_priv->pc8.enabled);
5692
5689 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 5693 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5690 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 5694 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5691 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 5695 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
@@ -5701,9 +5705,24 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable)
5701 HSW_PWR_WELL_STATE_ENABLED), 20)) 5705 HSW_PWR_WELL_STATE_ENABLED), 20))
5702 DRM_ERROR("Timeout enabling power well\n"); 5706 DRM_ERROR("Timeout enabling power well\n");
5703 } 5707 }
5708
5709 if (IS_BROADWELL(dev)) {
5710 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5711 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5712 dev_priv->de_irq_mask[PIPE_B]);
5713 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5714 ~dev_priv->de_irq_mask[PIPE_B] |
5715 GEN8_PIPE_VBLANK);
5716 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5717 dev_priv->de_irq_mask[PIPE_C]);
5718 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5719 ~dev_priv->de_irq_mask[PIPE_C] |
5720 GEN8_PIPE_VBLANK);
5721 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5722 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5723 }
5704 } else { 5724 } else {
5705 if (enable_requested) { 5725 if (enable_requested) {
5706 unsigned long irqflags;
5707 enum pipe p; 5726 enum pipe p;
5708 5727
5709 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 5728 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
@@ -5730,16 +5749,24 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable)
5730static void __intel_power_well_get(struct drm_device *dev, 5749static void __intel_power_well_get(struct drm_device *dev,
5731 struct i915_power_well *power_well) 5750 struct i915_power_well *power_well)
5732{ 5751{
5733 if (!power_well->count++) 5752 struct drm_i915_private *dev_priv = dev->dev_private;
5753
5754 if (!power_well->count++) {
5755 hsw_disable_package_c8(dev_priv);
5734 __intel_set_power_well(dev, true); 5756 __intel_set_power_well(dev, true);
5757 }
5735} 5758}
5736 5759
5737static void __intel_power_well_put(struct drm_device *dev, 5760static void __intel_power_well_put(struct drm_device *dev,
5738 struct i915_power_well *power_well) 5761 struct i915_power_well *power_well)
5739{ 5762{
5763 struct drm_i915_private *dev_priv = dev->dev_private;
5764
5740 WARN_ON(!power_well->count); 5765 WARN_ON(!power_well->count);
5741 if (!--power_well->count && i915_disable_power_well) 5766 if (!--power_well->count && i915_disable_power_well) {
5742 __intel_set_power_well(dev, false); 5767 __intel_set_power_well(dev, false);
5768 hsw_enable_package_c8(dev_priv);
5769 }
5743} 5770}
5744 5771
5745void intel_display_power_get(struct drm_device *dev, 5772void intel_display_power_get(struct drm_device *dev,
@@ -6129,10 +6156,19 @@ int vlv_freq_opcode(int ddr_freq, int val)
6129 return val; 6156 return val;
6130} 6157}
6131 6158
6132void intel_pm_init(struct drm_device *dev) 6159void intel_pm_setup(struct drm_device *dev)
6133{ 6160{
6134 struct drm_i915_private *dev_priv = dev->dev_private; 6161 struct drm_i915_private *dev_priv = dev->dev_private;
6135 6162
6163 mutex_init(&dev_priv->rps.hw_lock);
6164
6165 mutex_init(&dev_priv->pc8.lock);
6166 dev_priv->pc8.requirements_met = false;
6167 dev_priv->pc8.gpu_idle = false;
6168 dev_priv->pc8.irqs_disabled = false;
6169 dev_priv->pc8.enabled = false;
6170 dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
6171 INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
6136 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 6172 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6137 intel_gen6_powersave_work); 6173 intel_gen6_powersave_work);
6138} 6174}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b620337e6d67..c2f09d456300 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -965,6 +965,7 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
965 } else if (IS_GEN6(ring->dev)) { 965 } else if (IS_GEN6(ring->dev)) {
966 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); 966 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
967 } else { 967 } else {
968 /* XXX: gen8 returns to sanity */
968 mmio = RING_HWS_PGA(ring->mmio_base); 969 mmio = RING_HWS_PGA(ring->mmio_base);
969 } 970 }
970 971
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 0b02078a0b84..25cbe073c388 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -784,6 +784,7 @@ static int gen6_do_reset(struct drm_device *dev)
784int intel_gpu_reset(struct drm_device *dev) 784int intel_gpu_reset(struct drm_device *dev)
785{ 785{
786 switch (INTEL_INFO(dev)->gen) { 786 switch (INTEL_INFO(dev)->gen) {
787 case 8:
787 case 7: 788 case 7:
788 case 6: return gen6_do_reset(dev); 789 case 6: return gen6_do_reset(dev);
789 case 5: return ironlake_do_reset(dev); 790 case 5: return ironlake_do_reset(dev);
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index edcf801613e6..b3fa1ba191b7 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -59,6 +59,7 @@ nouveau-y += core/subdev/clock/nv40.o
59nouveau-y += core/subdev/clock/nv50.o 59nouveau-y += core/subdev/clock/nv50.o
60nouveau-y += core/subdev/clock/nv84.o 60nouveau-y += core/subdev/clock/nv84.o
61nouveau-y += core/subdev/clock/nva3.o 61nouveau-y += core/subdev/clock/nva3.o
62nouveau-y += core/subdev/clock/nvaa.o
62nouveau-y += core/subdev/clock/nvc0.o 63nouveau-y += core/subdev/clock/nvc0.o
63nouveau-y += core/subdev/clock/nve0.o 64nouveau-y += core/subdev/clock/nve0.o
64nouveau-y += core/subdev/clock/pllnv04.o 65nouveau-y += core/subdev/clock/pllnv04.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
index db139827047c..db3fc7be856a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
@@ -283,7 +283,7 @@ nv50_identify(struct nouveau_device *device)
283 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 283 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
284 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 284 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
285 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; 285 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
286 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 286 device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
287 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 287 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
288 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 288 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
289 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 289 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
@@ -311,7 +311,7 @@ nv50_identify(struct nouveau_device *device)
311 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 311 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
312 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 312 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
313 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; 313 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
314 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 314 device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
315 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 315 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
316 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 316 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
317 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 317 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
index 5f555788121c..e6352bd5b4ff 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
@@ -33,6 +33,7 @@
33#include <engine/dmaobj.h> 33#include <engine/dmaobj.h>
34#include <engine/fifo.h> 34#include <engine/fifo.h>
35 35
36#include "nv04.h"
36#include "nv50.h" 37#include "nv50.h"
37 38
38/******************************************************************************* 39/*******************************************************************************
@@ -460,6 +461,8 @@ nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
460 nv_subdev(priv)->intr = nv04_fifo_intr; 461 nv_subdev(priv)->intr = nv04_fifo_intr;
461 nv_engine(priv)->cclass = &nv50_fifo_cclass; 462 nv_engine(priv)->cclass = &nv50_fifo_cclass;
462 nv_engine(priv)->sclass = nv50_fifo_sclass; 463 nv_engine(priv)->sclass = nv50_fifo_sclass;
464 priv->base.pause = nv04_fifo_pause;
465 priv->base.start = nv04_fifo_start;
463 return 0; 466 return 0;
464} 467}
465 468
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
index 0908dc834c84..fe0f41e65d9b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
@@ -35,6 +35,7 @@
35#include <engine/dmaobj.h> 35#include <engine/dmaobj.h>
36#include <engine/fifo.h> 36#include <engine/fifo.h>
37 37
38#include "nv04.h"
38#include "nv50.h" 39#include "nv50.h"
39 40
40/******************************************************************************* 41/*******************************************************************************
@@ -432,6 +433,8 @@ nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
432 nv_subdev(priv)->intr = nv04_fifo_intr; 433 nv_subdev(priv)->intr = nv04_fifo_intr;
433 nv_engine(priv)->cclass = &nv84_fifo_cclass; 434 nv_engine(priv)->cclass = &nv84_fifo_cclass;
434 nv_engine(priv)->sclass = nv84_fifo_sclass; 435 nv_engine(priv)->sclass = nv84_fifo_sclass;
436 priv->base.pause = nv04_fifo_pause;
437 priv->base.start = nv04_fifo_start;
435 return 0; 438 return 0;
436} 439}
437 440
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c b/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
index b574dd4bb828..5ce686ee729e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
@@ -176,7 +176,7 @@ nv50_software_context_ctor(struct nouveau_object *parent,
176 if (ret) 176 if (ret)
177 return ret; 177 return ret;
178 178
179 chan->vblank.nr_event = pdisp->vblank->index_nr; 179 chan->vblank.nr_event = pdisp ? pdisp->vblank->index_nr : 0;
180 chan->vblank.event = kzalloc(chan->vblank.nr_event * 180 chan->vblank.event = kzalloc(chan->vblank.nr_event *
181 sizeof(*chan->vblank.event), GFP_KERNEL); 181 sizeof(*chan->vblank.event), GFP_KERNEL);
182 if (!chan->vblank.event) 182 if (!chan->vblank.event)
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
index e2675bc0edba..8f4ced75444a 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
@@ -14,6 +14,9 @@ enum nv_clk_src {
14 nv_clk_src_hclk, 14 nv_clk_src_hclk,
15 nv_clk_src_hclkm3, 15 nv_clk_src_hclkm3,
16 nv_clk_src_hclkm3d2, 16 nv_clk_src_hclkm3d2,
17 nv_clk_src_hclkm2d3, /* NVAA */
18 nv_clk_src_hclkm4, /* NVAA */
19 nv_clk_src_cclk, /* NVAA */
17 20
18 nv_clk_src_host, 21 nv_clk_src_host,
19 22
@@ -127,6 +130,7 @@ extern struct nouveau_oclass nv04_clock_oclass;
127extern struct nouveau_oclass nv40_clock_oclass; 130extern struct nouveau_oclass nv40_clock_oclass;
128extern struct nouveau_oclass *nv50_clock_oclass; 131extern struct nouveau_oclass *nv50_clock_oclass;
129extern struct nouveau_oclass *nv84_clock_oclass; 132extern struct nouveau_oclass *nv84_clock_oclass;
133extern struct nouveau_oclass *nvaa_clock_oclass;
130extern struct nouveau_oclass nva3_clock_oclass; 134extern struct nouveau_oclass nva3_clock_oclass;
131extern struct nouveau_oclass nvc0_clock_oclass; 135extern struct nouveau_oclass nvc0_clock_oclass;
132extern struct nouveau_oclass nve0_clock_oclass; 136extern struct nouveau_oclass nve0_clock_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
index da50c1b12928..30c1f3a4158e 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
@@ -69,6 +69,11 @@ nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
69 return 0; 69 return 0;
70} 70}
71 71
72static struct nouveau_clocks
73nv04_domain[] = {
74 { nv_clk_src_max }
75};
76
72static int 77static int
73nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 78nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
74 struct nouveau_oclass *oclass, void *data, u32 size, 79 struct nouveau_oclass *oclass, void *data, u32 size,
@@ -77,7 +82,7 @@ nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
77 struct nv04_clock_priv *priv; 82 struct nv04_clock_priv *priv;
78 int ret; 83 int ret;
79 84
80 ret = nouveau_clock_create(parent, engine, oclass, NULL, &priv); 85 ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, &priv);
81 *pobject = nv_object(priv); 86 *pobject = nv_object(priv);
82 if (ret) 87 if (ret)
83 return ret; 88 return ret;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c
new file mode 100644
index 000000000000..7a723b4f564d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c
@@ -0,0 +1,445 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <engine/fifo.h>
26#include <subdev/bios.h>
27#include <subdev/bios/pll.h>
28#include <subdev/timer.h>
29#include <subdev/clock.h>
30
31#include "pll.h"
32
33struct nvaa_clock_priv {
34 struct nouveau_clock base;
35 enum nv_clk_src csrc, ssrc, vsrc;
36 u32 cctrl, sctrl;
37 u32 ccoef, scoef;
38 u32 cpost, spost;
39 u32 vdiv;
40};
41
42static u32
43read_div(struct nouveau_clock *clk)
44{
45 return nv_rd32(clk, 0x004600);
46}
47
48static u32
49read_pll(struct nouveau_clock *clk, u32 base)
50{
51 u32 ctrl = nv_rd32(clk, base + 0);
52 u32 coef = nv_rd32(clk, base + 4);
53 u32 ref = clk->read(clk, nv_clk_src_href);
54 u32 post_div = 0;
55 u32 clock = 0;
56 int N1, M1;
57
58 switch (base){
59 case 0x4020:
60 post_div = 1 << ((nv_rd32(clk, 0x4070) & 0x000f0000) >> 16);
61 break;
62 case 0x4028:
63 post_div = (nv_rd32(clk, 0x4040) & 0x000f0000) >> 16;
64 break;
65 default:
66 break;
67 }
68
69 N1 = (coef & 0x0000ff00) >> 8;
70 M1 = (coef & 0x000000ff);
71 if ((ctrl & 0x80000000) && M1) {
72 clock = ref * N1 / M1;
73 clock = clock / post_div;
74 }
75
76 return clock;
77}
78
79static int
80nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
81{
82 struct nvaa_clock_priv *priv = (void *)clk;
83 u32 mast = nv_rd32(clk, 0x00c054);
84 u32 P = 0;
85
86 switch (src) {
87 case nv_clk_src_crystal:
88 return nv_device(priv)->crystal;
89 case nv_clk_src_href:
90 return 100000; /* PCIE reference clock */
91 case nv_clk_src_hclkm4:
92 return clk->read(clk, nv_clk_src_href) * 4;
93 case nv_clk_src_hclkm2d3:
94 return clk->read(clk, nv_clk_src_href) * 2 / 3;
95 case nv_clk_src_host:
96 switch (mast & 0x000c0000) {
97 case 0x00000000: return clk->read(clk, nv_clk_src_hclkm2d3);
98 case 0x00040000: break;
99 case 0x00080000: return clk->read(clk, nv_clk_src_hclkm4);
100 case 0x000c0000: return clk->read(clk, nv_clk_src_cclk);
101 }
102 break;
103 case nv_clk_src_core:
104 P = (nv_rd32(clk, 0x004028) & 0x00070000) >> 16;
105
106 switch (mast & 0x00000003) {
107 case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P;
108 case 0x00000001: return 0;
109 case 0x00000002: return clk->read(clk, nv_clk_src_hclkm4) >> P;
110 case 0x00000003: return read_pll(clk, 0x004028) >> P;
111 }
112 break;
113 case nv_clk_src_cclk:
114 if ((mast & 0x03000000) != 0x03000000)
115 return clk->read(clk, nv_clk_src_core);
116
117 if ((mast & 0x00000200) == 0x00000000)
118 return clk->read(clk, nv_clk_src_core);
119
120 switch (mast & 0x00000c00) {
121 case 0x00000000: return clk->read(clk, nv_clk_src_href);
122 case 0x00000400: return clk->read(clk, nv_clk_src_hclkm4);
123 case 0x00000800: return clk->read(clk, nv_clk_src_hclkm2d3);
124 default: return 0;
125 }
126 case nv_clk_src_shader:
127 P = (nv_rd32(clk, 0x004020) & 0x00070000) >> 16;
128 switch (mast & 0x00000030) {
129 case 0x00000000:
130 if (mast & 0x00000040)
131 return clk->read(clk, nv_clk_src_href) >> P;
132 return clk->read(clk, nv_clk_src_crystal) >> P;
133 case 0x00000010: break;
134 case 0x00000020: return read_pll(clk, 0x004028) >> P;
135 case 0x00000030: return read_pll(clk, 0x004020) >> P;
136 }
137 break;
138 case nv_clk_src_mem:
139 return 0;
140 break;
141 case nv_clk_src_vdec:
142 P = (read_div(clk) & 0x00000700) >> 8;
143
144 switch (mast & 0x00400000) {
145 case 0x00400000:
146 return clk->read(clk, nv_clk_src_core) >> P;
147 break;
148 default:
149 return 500000 >> P;
150 break;
151 }
152 break;
153 default:
154 break;
155 }
156
157 nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
158 return 0;
159}
160
161static u32
162calc_pll(struct nvaa_clock_priv *priv, u32 reg,
163 u32 clock, int *N, int *M, int *P)
164{
165 struct nouveau_bios *bios = nouveau_bios(priv);
166 struct nvbios_pll pll;
167 struct nouveau_clock *clk = &priv->base;
168 int ret;
169
170 ret = nvbios_pll_parse(bios, reg, &pll);
171 if (ret)
172 return 0;
173
174 pll.vco2.max_freq = 0;
175 pll.refclk = clk->read(clk, nv_clk_src_href);
176 if (!pll.refclk)
177 return 0;
178
179 return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P);
180}
181
182static inline u32
183calc_P(u32 src, u32 target, int *div)
184{
185 u32 clk0 = src, clk1 = src;
186 for (*div = 0; *div <= 7; (*div)++) {
187 if (clk0 <= target) {
188 clk1 = clk0 << (*div ? 1 : 0);
189 break;
190 }
191 clk0 >>= 1;
192 }
193
194 if (target - clk0 <= clk1 - target)
195 return clk0;
196 (*div)--;
197 return clk1;
198}
199
200static int
201nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
202{
203 struct nvaa_clock_priv *priv = (void *)clk;
204 const int shader = cstate->domain[nv_clk_src_shader];
205 const int core = cstate->domain[nv_clk_src_core];
206 const int vdec = cstate->domain[nv_clk_src_vdec];
207 u32 out = 0, clock = 0;
208 int N, M, P1, P2 = 0;
209 int divs = 0;
210
211 /* cclk: find suitable source, disable PLL if we can */
212 if (core < clk->read(clk, nv_clk_src_hclkm4))
213 out = calc_P(clk->read(clk, nv_clk_src_hclkm4), core, &divs);
214
215 /* Calculate clock * 2, so shader clock can use it too */
216 clock = calc_pll(priv, 0x4028, (core << 1), &N, &M, &P1);
217
218 if (abs(core - out) <=
219 abs(core - (clock >> 1))) {
220 priv->csrc = nv_clk_src_hclkm4;
221 priv->cctrl = divs << 16;
222 } else {
223 /* NVCTRL is actually used _after_ NVPOST, and after what we
224 * call NVPLL. To make matters worse, NVPOST is an integer
225 * divider instead of a right-shift number. */
226 if(P1 > 2) {
227 P2 = P1 - 2;
228 P1 = 2;
229 }
230
231 priv->csrc = nv_clk_src_core;
232 priv->ccoef = (N << 8) | M;
233
234 priv->cctrl = (P2 + 1) << 16;
235 priv->cpost = (1 << P1) << 16;
236 }
237
238 /* sclk: nvpll + divisor, href or spll */
239 out = 0;
240 if (shader == clk->read(clk, nv_clk_src_href)) {
241 priv->ssrc = nv_clk_src_href;
242 } else {
243 clock = calc_pll(priv, 0x4020, shader, &N, &M, &P1);
244 if (priv->csrc == nv_clk_src_core) {
245 out = calc_P((core << 1), shader, &divs);
246 }
247
248 if (abs(shader - out) <=
249 abs(shader - clock) &&
250 (divs + P2) <= 7) {
251 priv->ssrc = nv_clk_src_core;
252 priv->sctrl = (divs + P2) << 16;
253 } else {
254 priv->ssrc = nv_clk_src_shader;
255 priv->scoef = (N << 8) | M;
256 priv->sctrl = P1 << 16;
257 }
258 }
259
260 /* vclk */
261 out = calc_P(core, vdec, &divs);
262 clock = calc_P(500000, vdec, &P1);
263 if(abs(vdec - out) <=
264 abs(vdec - clock)) {
265 priv->vsrc = nv_clk_src_cclk;
266 priv->vdiv = divs << 16;
267 } else {
268 priv->vsrc = nv_clk_src_vdec;
269 priv->vdiv = P1 << 16;
270 }
271
272 /* Print strategy! */
273 nv_debug(priv, "nvpll: %08x %08x %08x\n",
274 priv->ccoef, priv->cpost, priv->cctrl);
275 nv_debug(priv, " spll: %08x %08x %08x\n",
276 priv->scoef, priv->spost, priv->sctrl);
277 nv_debug(priv, " vdiv: %08x\n", priv->vdiv);
278 if (priv->csrc == nv_clk_src_hclkm4)
279 nv_debug(priv, "core: hrefm4\n");
280 else
281 nv_debug(priv, "core: nvpll\n");
282
283 if (priv->ssrc == nv_clk_src_hclkm4)
284 nv_debug(priv, "shader: hrefm4\n");
285 else if (priv->ssrc == nv_clk_src_core)
286 nv_debug(priv, "shader: nvpll\n");
287 else
288 nv_debug(priv, "shader: spll\n");
289
290 if (priv->vsrc == nv_clk_src_hclkm4)
291 nv_debug(priv, "vdec: 500MHz\n");
292 else
293 nv_debug(priv, "vdec: core\n");
294
295 return 0;
296}
297
298static int
299nvaa_clock_prog(struct nouveau_clock *clk)
300{
301 struct nvaa_clock_priv *priv = (void *)clk;
302 struct nouveau_fifo *pfifo = nouveau_fifo(clk);
303 unsigned long flags;
304 u32 pllmask = 0, mast, ptherm_gate;
305 int ret = -EBUSY;
306
307 /* halt and idle execution engines */
308 ptherm_gate = nv_mask(clk, 0x020060, 0x00070000, 0x00000000);
309 nv_mask(clk, 0x002504, 0x00000001, 0x00000001);
310 /* Wait until the interrupt handler is finished */
311 if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000))
312 goto resume;
313
314 if (pfifo)
315 pfifo->pause(pfifo, &flags);
316
317 if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010))
318 goto resume;
319 if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f))
320 goto resume;
321
322 /* First switch to safe clocks: href */
323 mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640);
324 mast &= ~0x00400e73;
325 mast |= 0x03000000;
326
327 switch (priv->csrc) {
328 case nv_clk_src_hclkm4:
329 nv_mask(clk, 0x4028, 0x00070000, priv->cctrl);
330 mast |= 0x00000002;
331 break;
332 case nv_clk_src_core:
333 nv_wr32(clk, 0x402c, priv->ccoef);
334 nv_wr32(clk, 0x4028, 0x80000000 | priv->cctrl);
335 nv_wr32(clk, 0x4040, priv->cpost);
336 pllmask |= (0x3 << 8);
337 mast |= 0x00000003;
338 break;
339 default:
340 nv_warn(priv,"Reclocking failed: unknown core clock\n");
341 goto resume;
342 }
343
344 switch (priv->ssrc) {
345 case nv_clk_src_href:
346 nv_mask(clk, 0x4020, 0x00070000, 0x00000000);
347 /* mast |= 0x00000000; */
348 break;
349 case nv_clk_src_core:
350 nv_mask(clk, 0x4020, 0x00070000, priv->sctrl);
351 mast |= 0x00000020;
352 break;
353 case nv_clk_src_shader:
354 nv_wr32(clk, 0x4024, priv->scoef);
355 nv_wr32(clk, 0x4020, 0x80000000 | priv->sctrl);
356 nv_wr32(clk, 0x4070, priv->spost);
357 pllmask |= (0x3 << 12);
358 mast |= 0x00000030;
359 break;
360 default:
361 nv_warn(priv,"Reclocking failed: unknown sclk clock\n");
362 goto resume;
363 }
364
365 if (!nv_wait(clk, 0x004080, pllmask, pllmask)) {
366 nv_warn(priv,"Reclocking failed: unstable PLLs\n");
367 goto resume;
368 }
369
370 switch (priv->vsrc) {
371 case nv_clk_src_cclk:
372 mast |= 0x00400000;
373 default:
374 nv_wr32(clk, 0x4600, priv->vdiv);
375 }
376
377 nv_wr32(clk, 0xc054, mast);
378 ret = 0;
379
380resume:
381 if (pfifo)
382 pfifo->start(pfifo, &flags);
383
384 nv_mask(clk, 0x002504, 0x00000001, 0x00000000);
385 nv_wr32(clk, 0x020060, ptherm_gate);
386
387 /* Disable some PLLs and dividers when unused */
388 if (priv->csrc != nv_clk_src_core) {
389 nv_wr32(clk, 0x4040, 0x00000000);
390 nv_mask(clk, 0x4028, 0x80000000, 0x00000000);
391 }
392
393 if (priv->ssrc != nv_clk_src_shader) {
394 nv_wr32(clk, 0x4070, 0x00000000);
395 nv_mask(clk, 0x4020, 0x80000000, 0x00000000);
396 }
397
398 return ret;
399}
400
401static void
402nvaa_clock_tidy(struct nouveau_clock *clk)
403{
404}
405
406static struct nouveau_clocks
407nvaa_domains[] = {
408 { nv_clk_src_crystal, 0xff },
409 { nv_clk_src_href , 0xff },
410 { nv_clk_src_core , 0xff, 0, "core", 1000 },
411 { nv_clk_src_shader , 0xff, 0, "shader", 1000 },
412 { nv_clk_src_vdec , 0xff, 0, "vdec", 1000 },
413 { nv_clk_src_max }
414};
415
416static int
417nvaa_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
418 struct nouveau_oclass *oclass, void *data, u32 size,
419 struct nouveau_object **pobject)
420{
421 struct nvaa_clock_priv *priv;
422 int ret;
423
424 ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, &priv);
425 *pobject = nv_object(priv);
426 if (ret)
427 return ret;
428
429 priv->base.read = nvaa_clock_read;
430 priv->base.calc = nvaa_clock_calc;
431 priv->base.prog = nvaa_clock_prog;
432 priv->base.tidy = nvaa_clock_tidy;
433 return 0;
434}
435
436struct nouveau_oclass *
437nvaa_clock_oclass = &(struct nouveau_oclass) {
438 .handle = NV_SUBDEV(CLOCK, 0xaa),
439 .ofuncs = &(struct nouveau_ofuncs) {
440 .ctor = nvaa_clock_ctor,
441 .dtor = _nouveau_clock_dtor,
442 .init = _nouveau_clock_init,
443 .fini = _nouveau_clock_fini,
444 },
445};
diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c
index 3618ac6b6316..32e7064b819b 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c
@@ -58,8 +58,8 @@ struct nouveau_plane {
58}; 58};
59 59
60static uint32_t formats[] = { 60static uint32_t formats[] = {
61 DRM_FORMAT_NV12,
62 DRM_FORMAT_UYVY, 61 DRM_FORMAT_UYVY,
62 DRM_FORMAT_NV12,
63}; 63};
64 64
65/* Sine can be approximated with 65/* Sine can be approximated with
@@ -99,13 +99,28 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
99 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 99 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
100 struct nouveau_bo *cur = nv_plane->cur; 100 struct nouveau_bo *cur = nv_plane->cur;
101 bool flip = nv_plane->flip; 101 bool flip = nv_plane->flip;
102 int format = ALIGN(src_w * 4, 0x100);
103 int soff = NV_PCRTC0_SIZE * nv_crtc->index; 102 int soff = NV_PCRTC0_SIZE * nv_crtc->index;
104 int soff2 = NV_PCRTC0_SIZE * !nv_crtc->index; 103 int soff2 = NV_PCRTC0_SIZE * !nv_crtc->index;
105 int ret; 104 int format, ret;
105
106 /* Source parameters given in 16.16 fixed point, ignore fractional. */
107 src_x >>= 16;
108 src_y >>= 16;
109 src_w >>= 16;
110 src_h >>= 16;
111
112 format = ALIGN(src_w * 4, 0x100);
106 113
107 if (format > 0xffff) 114 if (format > 0xffff)
108 return -EINVAL; 115 return -ERANGE;
116
117 if (dev->chipset >= 0x30) {
118 if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1))
119 return -ERANGE;
120 } else {
121 if (crtc_w < (src_w >> 3) || crtc_h < (src_h >> 3))
122 return -ERANGE;
123 }
109 124
110 ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM); 125 ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM);
111 if (ret) 126 if (ret)
@@ -113,12 +128,6 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
113 128
114 nv_plane->cur = nv_fb->nvbo; 129 nv_plane->cur = nv_fb->nvbo;
115 130
116 /* Source parameters given in 16.16 fixed point, ignore fractional. */
117 src_x = src_x >> 16;
118 src_y = src_y >> 16;
119 src_w = src_w >> 16;
120 src_h = src_h >> 16;
121
122 nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY); 131 nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY);
123 nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0); 132 nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0);
124 133
@@ -245,14 +254,25 @@ nv10_overlay_init(struct drm_device *device)
245{ 254{
246 struct nouveau_device *dev = nouveau_dev(device); 255 struct nouveau_device *dev = nouveau_dev(device);
247 struct nouveau_plane *plane = kzalloc(sizeof(struct nouveau_plane), GFP_KERNEL); 256 struct nouveau_plane *plane = kzalloc(sizeof(struct nouveau_plane), GFP_KERNEL);
257 int num_formats = ARRAY_SIZE(formats);
248 int ret; 258 int ret;
249 259
250 if (!plane) 260 if (!plane)
251 return; 261 return;
252 262
263 switch (dev->chipset) {
264 case 0x10:
265 case 0x11:
266 case 0x15:
267 case 0x1a:
268 case 0x20:
269 num_formats = 1;
270 break;
271 }
272
253 ret = drm_plane_init(device, &plane->base, 3 /* both crtc's */, 273 ret = drm_plane_init(device, &plane->base, 3 /* both crtc's */,
254 &nv10_plane_funcs, 274 &nv10_plane_funcs,
255 formats, ARRAY_SIZE(formats), false); 275 formats, num_formats, false);
256 if (ret) 276 if (ret)
257 goto err; 277 goto err;
258 278
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 7809d92183c4..29c3efdfc7dd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -608,6 +608,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
608 fence = nouveau_fence_ref(new_bo->bo.sync_obj); 608 fence = nouveau_fence_ref(new_bo->bo.sync_obj);
609 spin_unlock(&new_bo->bo.bdev->fence_lock); 609 spin_unlock(&new_bo->bo.bdev->fence_lock);
610 ret = nouveau_fence_sync(fence, chan); 610 ret = nouveau_fence_sync(fence, chan);
611 nouveau_fence_unref(&fence);
611 if (ret) 612 if (ret)
612 return ret; 613 return ret;
613 614
@@ -701,7 +702,7 @@ nouveau_finish_page_flip(struct nouveau_channel *chan,
701 702
702 s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head); 703 s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head);
703 if (s->event) 704 if (s->event)
704 drm_send_vblank_event(dev, -1, s->event); 705 drm_send_vblank_event(dev, s->crtc, s->event);
705 706
706 list_del(&s->head); 707 list_del(&s->head);
707 if (ps) 708 if (ps)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 7a3759f1c41a..98a22e6e27a1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -858,6 +858,12 @@ static int nouveau_pmops_runtime_suspend(struct device *dev)
858 if (nouveau_runtime_pm == 0) 858 if (nouveau_runtime_pm == 0)
859 return -EINVAL; 859 return -EINVAL;
860 860
861 /* are we optimus enabled? */
862 if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
863 DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
864 return -EINVAL;
865 }
866
861 nv_debug_level(SILENT); 867 nv_debug_level(SILENT);
862 drm_kms_helper_poll_disable(drm_dev); 868 drm_kms_helper_poll_disable(drm_dev);
863 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 869 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c b/drivers/gpu/drm/nouveau/nouveau_hwmon.c
index 38a4db5bfe21..4aff04fa483c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_hwmon.c
@@ -630,7 +630,6 @@ error:
630 hwmon->hwmon = NULL; 630 hwmon->hwmon = NULL;
631 return ret; 631 return ret;
632#else 632#else
633 hwmon->hwmon = NULL;
634 return 0; 633 return 0;
635#endif 634#endif
636} 635}
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index f8e66c08b11a..4e384a2f99c3 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -1265,7 +1265,7 @@ nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1265 uint32_t start, uint32_t size) 1265 uint32_t start, uint32_t size)
1266{ 1266{
1267 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 1267 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1268 u32 end = max(start + size, (u32)256); 1268 u32 end = min_t(u32, start + size, 256);
1269 u32 i; 1269 u32 i;
1270 1270
1271 for (i = start; i < end; i++) { 1271 for (i = start; i < end; i++) {
diff --git a/drivers/gpu/drm/qxl/Kconfig b/drivers/gpu/drm/qxl/Kconfig
index 037d324bf58f..66ac0ff95f5a 100644
--- a/drivers/gpu/drm/qxl/Kconfig
+++ b/drivers/gpu/drm/qxl/Kconfig
@@ -8,5 +8,6 @@ config DRM_QXL
8 select DRM_KMS_HELPER 8 select DRM_KMS_HELPER
9 select DRM_KMS_FB_HELPER 9 select DRM_KMS_FB_HELPER
10 select DRM_TTM 10 select DRM_TTM
11 select CRC32
11 help 12 help
12 QXL virtual GPU for Spice virtualization desktop integration. Do not enable this driver unless your distro ships a corresponding X.org QXL driver that can handle kernel modesetting. 13 QXL virtual GPU for Spice virtualization desktop integration. Do not enable this driver unless your distro ships a corresponding X.org QXL driver that can handle kernel modesetting.
diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c
index 5e827c29d194..d70aafb83307 100644
--- a/drivers/gpu/drm/qxl/qxl_display.c
+++ b/drivers/gpu/drm/qxl/qxl_display.c
@@ -24,7 +24,7 @@
24 */ 24 */
25 25
26 26
27#include "linux/crc32.h" 27#include <linux/crc32.h>
28 28
29#include "qxl_drv.h" 29#include "qxl_drv.h"
30#include "qxl_object.h" 30#include "qxl_object.h"
diff --git a/drivers/gpu/drm/qxl/qxl_release.c b/drivers/gpu/drm/qxl/qxl_release.c
index 0109a9644cb2..821ab7b9409b 100644
--- a/drivers/gpu/drm/qxl/qxl_release.c
+++ b/drivers/gpu/drm/qxl/qxl_release.c
@@ -92,6 +92,7 @@ qxl_release_free(struct qxl_device *qdev,
92 - DRM_FILE_OFFSET); 92 - DRM_FILE_OFFSET);
93 qxl_fence_remove_release(&bo->fence, release->id); 93 qxl_fence_remove_release(&bo->fence, release->id);
94 qxl_bo_unref(&bo); 94 qxl_bo_unref(&bo);
95 kfree(entry);
95 } 96 }
96 spin_lock(&qdev->release_idr_lock); 97 spin_lock(&qdev->release_idr_lock);
97 idr_remove(&qdev->release_idr, release->id); 98 idr_remove(&qdev->release_idr, release->id);
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 80a20120e625..b1970596a782 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1196,7 +1196,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1196 } else if ((rdev->family == CHIP_TAHITI) || 1196 } else if ((rdev->family == CHIP_TAHITI) ||
1197 (rdev->family == CHIP_PITCAIRN)) 1197 (rdev->family == CHIP_PITCAIRN))
1198 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); 1198 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1199 else if (rdev->family == CHIP_VERDE) 1199 else if ((rdev->family == CHIP_VERDE) ||
1200 (rdev->family == CHIP_OLAND) ||
1201 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1200 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); 1202 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1201 1203
1202 switch (radeon_crtc->crtc_id) { 1204 switch (radeon_crtc->crtc_id) {
diff --git a/drivers/gpu/drm/radeon/atombios_i2c.c b/drivers/gpu/drm/radeon/atombios_i2c.c
index 0652ee0a2098..f685035dbe39 100644
--- a/drivers/gpu/drm/radeon/atombios_i2c.c
+++ b/drivers/gpu/drm/radeon/atombios_i2c.c
@@ -44,7 +44,7 @@ static int radeon_process_i2c_ch(struct radeon_i2c_chan *chan,
44 PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args; 44 PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
45 int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction); 45 int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
46 unsigned char *base; 46 unsigned char *base;
47 u16 out; 47 u16 out = cpu_to_le16(0);
48 48
49 memset(&args, 0, sizeof(args)); 49 memset(&args, 0, sizeof(args));
50 50
@@ -55,11 +55,14 @@ static int radeon_process_i2c_ch(struct radeon_i2c_chan *chan,
55 DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 3)\n", num); 55 DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 3)\n", num);
56 return -EINVAL; 56 return -EINVAL;
57 } 57 }
58 args.ucRegIndex = buf[0]; 58 if (buf == NULL)
59 if (num > 1) { 59 args.ucRegIndex = 0;
60 else
61 args.ucRegIndex = buf[0];
62 if (num)
60 num--; 63 num--;
64 if (num)
61 memcpy(&out, &buf[1], num); 65 memcpy(&out, &buf[1], num);
62 }
63 args.lpI2CDataOut = cpu_to_le16(out); 66 args.lpI2CDataOut = cpu_to_le16(out);
64 } else { 67 } else {
65 if (num > ATOM_MAX_HW_I2C_READ) { 68 if (num > ATOM_MAX_HW_I2C_READ) {
@@ -96,14 +99,14 @@ int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
96 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 99 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
97 struct i2c_msg *p; 100 struct i2c_msg *p;
98 int i, remaining, current_count, buffer_offset, max_bytes, ret; 101 int i, remaining, current_count, buffer_offset, max_bytes, ret;
99 u8 buf = 0, flags; 102 u8 flags;
100 103
101 /* check for bus probe */ 104 /* check for bus probe */
102 p = &msgs[0]; 105 p = &msgs[0];
103 if ((num == 1) && (p->len == 0)) { 106 if ((num == 1) && (p->len == 0)) {
104 ret = radeon_process_i2c_ch(i2c, 107 ret = radeon_process_i2c_ch(i2c,
105 p->addr, HW_I2C_WRITE, 108 p->addr, HW_I2C_WRITE,
106 &buf, 1); 109 NULL, 0);
107 if (ret) 110 if (ret)
108 return ret; 111 return ret;
109 else 112 else
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 0300727a4f70..d08b83c6267b 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -458,7 +458,7 @@ int cik_copy_dma(struct radeon_device *rdev,
458 radeon_ring_write(ring, 0); /* src/dst endian swap */ 458 radeon_ring_write(ring, 0); /* src/dst endian swap */
459 radeon_ring_write(ring, src_offset & 0xffffffff); 459 radeon_ring_write(ring, src_offset & 0xffffffff);
460 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xffffffff); 460 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xffffffff);
461 radeon_ring_write(ring, dst_offset & 0xfffffffc); 461 radeon_ring_write(ring, dst_offset & 0xffffffff);
462 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xffffffff); 462 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xffffffff);
463 src_offset += cur_size_in_bytes; 463 src_offset += cur_size_in_bytes;
464 dst_offset += cur_size_in_bytes; 464 dst_offset += cur_size_in_bytes;
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c
index 009f46e0ce72..713a5d359901 100644
--- a/drivers/gpu/drm/radeon/dce6_afmt.c
+++ b/drivers/gpu/drm/radeon/dce6_afmt.c
@@ -93,11 +93,13 @@ void dce6_afmt_select_pin(struct drm_encoder *encoder)
93 struct radeon_device *rdev = encoder->dev->dev_private; 93 struct radeon_device *rdev = encoder->dev->dev_private;
94 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 94 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
95 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 95 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
96 u32 offset = dig->afmt->offset; 96 u32 offset;
97 97
98 if (!dig->afmt->pin) 98 if (!dig || !dig->afmt || !dig->afmt->pin)
99 return; 99 return;
100 100
101 offset = dig->afmt->offset;
102
101 WREG32(AFMT_AUDIO_SRC_CONTROL + offset, 103 WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
102 AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id)); 104 AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
103} 105}
@@ -112,7 +114,7 @@ void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
112 struct radeon_connector *radeon_connector = NULL; 114 struct radeon_connector *radeon_connector = NULL;
113 u32 tmp = 0, offset; 115 u32 tmp = 0, offset;
114 116
115 if (!dig->afmt->pin) 117 if (!dig || !dig->afmt || !dig->afmt->pin)
116 return; 118 return;
117 119
118 offset = dig->afmt->pin->offset; 120 offset = dig->afmt->pin->offset;
@@ -156,7 +158,7 @@ void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
156 u8 *sadb; 158 u8 *sadb;
157 int sad_count; 159 int sad_count;
158 160
159 if (!dig->afmt->pin) 161 if (!dig || !dig->afmt || !dig->afmt->pin)
160 return; 162 return;
161 163
162 offset = dig->afmt->pin->offset; 164 offset = dig->afmt->pin->offset;
@@ -172,7 +174,7 @@ void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
172 } 174 }
173 175
174 sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); 176 sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
175 if (sad_count < 0) { 177 if (sad_count <= 0) {
176 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 178 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
177 return; 179 return;
178 } 180 }
@@ -217,7 +219,7 @@ void dce6_afmt_write_sad_regs(struct drm_encoder *encoder)
217 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 219 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
218 }; 220 };
219 221
220 if (!dig->afmt->pin) 222 if (!dig || !dig->afmt || !dig->afmt->pin)
221 return; 223 return;
222 224
223 offset = dig->afmt->pin->offset; 225 offset = dig->afmt->pin->offset;
@@ -233,7 +235,7 @@ void dce6_afmt_write_sad_regs(struct drm_encoder *encoder)
233 } 235 }
234 236
235 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); 237 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
236 if (sad_count < 0) { 238 if (sad_count <= 0) {
237 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 239 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
238 return; 240 return;
239 } 241 }
@@ -306,7 +308,9 @@ int dce6_audio_init(struct radeon_device *rdev)
306 rdev->audio.enabled = true; 308 rdev->audio.enabled = true;
307 309
308 if (ASIC_IS_DCE8(rdev)) 310 if (ASIC_IS_DCE8(rdev))
309 rdev->audio.num_pins = 7; 311 rdev->audio.num_pins = 6;
312 else if (ASIC_IS_DCE61(rdev))
313 rdev->audio.num_pins = 4;
310 else 314 else
311 rdev->audio.num_pins = 6; 315 rdev->audio.num_pins = 6;
312 316
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index aa695c4feb3d..0c6d5cef4cf1 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -118,7 +118,7 @@ static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
118 } 118 }
119 119
120 sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); 120 sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
121 if (sad_count < 0) { 121 if (sad_count <= 0) {
122 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 122 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
123 return; 123 return;
124 } 124 }
@@ -173,7 +173,7 @@ static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
173 } 173 }
174 174
175 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); 175 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
176 if (sad_count < 0) { 176 if (sad_count <= 0) {
177 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 177 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
178 return; 178 return;
179 } 179 }
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 11aab2ab54ce..f59a9e9fccf8 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -895,6 +895,10 @@ static void cayman_gpu_init(struct radeon_device *rdev)
895 (rdev->pdev->device == 0x999C)) { 895 (rdev->pdev->device == 0x999C)) {
896 rdev->config.cayman.max_simds_per_se = 6; 896 rdev->config.cayman.max_simds_per_se = 6;
897 rdev->config.cayman.max_backends_per_se = 2; 897 rdev->config.cayman.max_backends_per_se = 2;
898 rdev->config.cayman.max_hw_contexts = 8;
899 rdev->config.cayman.sx_max_export_size = 256;
900 rdev->config.cayman.sx_max_export_pos_size = 64;
901 rdev->config.cayman.sx_max_export_smx_size = 192;
898 } else if ((rdev->pdev->device == 0x9903) || 902 } else if ((rdev->pdev->device == 0x9903) ||
899 (rdev->pdev->device == 0x9904) || 903 (rdev->pdev->device == 0x9904) ||
900 (rdev->pdev->device == 0x990A) || 904 (rdev->pdev->device == 0x990A) ||
@@ -905,6 +909,10 @@ static void cayman_gpu_init(struct radeon_device *rdev)
905 (rdev->pdev->device == 0x999D)) { 909 (rdev->pdev->device == 0x999D)) {
906 rdev->config.cayman.max_simds_per_se = 4; 910 rdev->config.cayman.max_simds_per_se = 4;
907 rdev->config.cayman.max_backends_per_se = 2; 911 rdev->config.cayman.max_backends_per_se = 2;
912 rdev->config.cayman.max_hw_contexts = 8;
913 rdev->config.cayman.sx_max_export_size = 256;
914 rdev->config.cayman.sx_max_export_pos_size = 64;
915 rdev->config.cayman.sx_max_export_smx_size = 192;
908 } else if ((rdev->pdev->device == 0x9919) || 916 } else if ((rdev->pdev->device == 0x9919) ||
909 (rdev->pdev->device == 0x9990) || 917 (rdev->pdev->device == 0x9990) ||
910 (rdev->pdev->device == 0x9991) || 918 (rdev->pdev->device == 0x9991) ||
@@ -915,9 +923,17 @@ static void cayman_gpu_init(struct radeon_device *rdev)
915 (rdev->pdev->device == 0x99A0)) { 923 (rdev->pdev->device == 0x99A0)) {
916 rdev->config.cayman.max_simds_per_se = 3; 924 rdev->config.cayman.max_simds_per_se = 3;
917 rdev->config.cayman.max_backends_per_se = 1; 925 rdev->config.cayman.max_backends_per_se = 1;
926 rdev->config.cayman.max_hw_contexts = 4;
927 rdev->config.cayman.sx_max_export_size = 128;
928 rdev->config.cayman.sx_max_export_pos_size = 32;
929 rdev->config.cayman.sx_max_export_smx_size = 96;
918 } else { 930 } else {
919 rdev->config.cayman.max_simds_per_se = 2; 931 rdev->config.cayman.max_simds_per_se = 2;
920 rdev->config.cayman.max_backends_per_se = 1; 932 rdev->config.cayman.max_backends_per_se = 1;
933 rdev->config.cayman.max_hw_contexts = 4;
934 rdev->config.cayman.sx_max_export_size = 128;
935 rdev->config.cayman.sx_max_export_pos_size = 32;
936 rdev->config.cayman.sx_max_export_smx_size = 96;
921 } 937 }
922 rdev->config.cayman.max_texture_channel_caches = 2; 938 rdev->config.cayman.max_texture_channel_caches = 2;
923 rdev->config.cayman.max_gprs = 256; 939 rdev->config.cayman.max_gprs = 256;
@@ -925,10 +941,6 @@ static void cayman_gpu_init(struct radeon_device *rdev)
925 rdev->config.cayman.max_gs_threads = 32; 941 rdev->config.cayman.max_gs_threads = 32;
926 rdev->config.cayman.max_stack_entries = 512; 942 rdev->config.cayman.max_stack_entries = 512;
927 rdev->config.cayman.sx_num_of_sets = 8; 943 rdev->config.cayman.sx_num_of_sets = 8;
928 rdev->config.cayman.sx_max_export_size = 256;
929 rdev->config.cayman.sx_max_export_pos_size = 64;
930 rdev->config.cayman.sx_max_export_smx_size = 192;
931 rdev->config.cayman.max_hw_contexts = 8;
932 rdev->config.cayman.sq_num_cf_insts = 2; 944 rdev->config.cayman.sq_num_cf_insts = 2;
933 945
934 rdev->config.cayman.sc_prim_fifo_size = 0x40; 946 rdev->config.cayman.sc_prim_fifo_size = 0x40;
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index cdc003085a76..49c4d48f54d6 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -785,8 +785,8 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
785 struct ni_ps *ps = ni_get_ps(rps); 785 struct ni_ps *ps = ni_get_ps(rps);
786 struct radeon_clock_and_voltage_limits *max_limits; 786 struct radeon_clock_and_voltage_limits *max_limits;
787 bool disable_mclk_switching; 787 bool disable_mclk_switching;
788 u32 mclk, sclk; 788 u32 mclk;
789 u16 vddc, vddci; 789 u16 vddci;
790 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 790 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
791 int i; 791 int i;
792 792
@@ -839,24 +839,14 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
839 839
840 /* XXX validate the min clocks required for display */ 840 /* XXX validate the min clocks required for display */
841 841
842 /* adjust low state */
842 if (disable_mclk_switching) { 843 if (disable_mclk_switching) {
843 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 844 ps->performance_levels[0].mclk =
844 sclk = ps->performance_levels[0].sclk; 845 ps->performance_levels[ps->performance_level_count - 1].mclk;
845 vddc = ps->performance_levels[0].vddc; 846 ps->performance_levels[0].vddci =
846 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 847 ps->performance_levels[ps->performance_level_count - 1].vddci;
847 } else {
848 sclk = ps->performance_levels[0].sclk;
849 mclk = ps->performance_levels[0].mclk;
850 vddc = ps->performance_levels[0].vddc;
851 vddci = ps->performance_levels[0].vddci;
852 } 848 }
853 849
854 /* adjusted low state */
855 ps->performance_levels[0].sclk = sclk;
856 ps->performance_levels[0].mclk = mclk;
857 ps->performance_levels[0].vddc = vddc;
858 ps->performance_levels[0].vddci = vddci;
859
860 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, 850 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
861 &ps->performance_levels[0].sclk, 851 &ps->performance_levels[0].sclk,
862 &ps->performance_levels[0].mclk); 852 &ps->performance_levels[0].mclk);
@@ -868,11 +858,15 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
868 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 858 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
869 } 859 }
870 860
861 /* adjust remaining states */
871 if (disable_mclk_switching) { 862 if (disable_mclk_switching) {
872 mclk = ps->performance_levels[0].mclk; 863 mclk = ps->performance_levels[0].mclk;
864 vddci = ps->performance_levels[0].vddci;
873 for (i = 1; i < ps->performance_level_count; i++) { 865 for (i = 1; i < ps->performance_level_count; i++) {
874 if (mclk < ps->performance_levels[i].mclk) 866 if (mclk < ps->performance_levels[i].mclk)
875 mclk = ps->performance_levels[i].mclk; 867 mclk = ps->performance_levels[i].mclk;
868 if (vddci < ps->performance_levels[i].vddci)
869 vddci = ps->performance_levels[i].vddci;
876 } 870 }
877 for (i = 0; i < ps->performance_level_count; i++) { 871 for (i = 0; i < ps->performance_level_count; i++) {
878 ps->performance_levels[i].mclk = mclk; 872 ps->performance_levels[i].mclk = mclk;
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 4b89262f3f0e..b7d3ecba43e3 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -304,9 +304,9 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
304 WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo); 304 WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
305 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ 305 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
306 } 306 }
307 } else if (ASIC_IS_DCE3(rdev)) { 307 } else {
308 /* according to the reg specs, this should DCE3.2 only, but in 308 /* according to the reg specs, this should DCE3.2 only, but in
309 * practice it seems to cover DCE3.0/3.1 as well. 309 * practice it seems to cover DCE2.0/3.0/3.1 as well.
310 */ 310 */
311 if (dig->dig_encoder == 0) { 311 if (dig->dig_encoder == 0) {
312 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); 312 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
@@ -317,10 +317,6 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
317 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); 317 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
318 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ 318 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
319 } 319 }
320 } else {
321 /* according to the reg specs, this should be DCE2.0 and DCE3.0/3.1 */
322 WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
323 AUDIO_DTO_MODULE(clock / 10));
324 } 320 }
325} 321}
326 322
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index ecf2a3960c07..b1f990d0eaa1 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2710,10 +2710,10 @@ void radeon_vm_fence(struct radeon_device *rdev,
2710 struct radeon_vm *vm, 2710 struct radeon_vm *vm,
2711 struct radeon_fence *fence); 2711 struct radeon_fence *fence);
2712uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2712uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2713int radeon_vm_bo_update_pte(struct radeon_device *rdev, 2713int radeon_vm_bo_update(struct radeon_device *rdev,
2714 struct radeon_vm *vm, 2714 struct radeon_vm *vm,
2715 struct radeon_bo *bo, 2715 struct radeon_bo *bo,
2716 struct ttm_mem_reg *mem); 2716 struct ttm_mem_reg *mem);
2717void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2717void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2718 struct radeon_bo *bo); 2718 struct radeon_bo *bo);
2719struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2719struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index e354ce94cdd1..c0425bb6223a 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -2021,7 +2021,7 @@ static struct radeon_asic ci_asic = {
2021 .hdmi_setmode = &evergreen_hdmi_setmode, 2021 .hdmi_setmode = &evergreen_hdmi_setmode,
2022 }, 2022 },
2023 .copy = { 2023 .copy = {
2024 .blit = NULL, 2024 .blit = &cik_copy_cpdma,
2025 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2025 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2026 .dma = &cik_copy_dma, 2026 .dma = &cik_copy_dma,
2027 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2027 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
@@ -2122,7 +2122,7 @@ static struct radeon_asic kv_asic = {
2122 .hdmi_setmode = &evergreen_hdmi_setmode, 2122 .hdmi_setmode = &evergreen_hdmi_setmode,
2123 }, 2123 },
2124 .copy = { 2124 .copy = {
2125 .blit = NULL, 2125 .blit = &cik_copy_cpdma,
2126 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2126 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2127 .dma = &cik_copy_dma, 2127 .dma = &cik_copy_dma,
2128 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2128 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index f79ee184ffd5..5c39bf7c3d88 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2918,7 +2918,7 @@ int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2918 mpll_param->dll_speed = args.ucDllSpeed; 2918 mpll_param->dll_speed = args.ucDllSpeed;
2919 mpll_param->bwcntl = args.ucBWCntl; 2919 mpll_param->bwcntl = args.ucBWCntl;
2920 mpll_param->vco_mode = 2920 mpll_param->vco_mode =
2921 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK) ? 1 : 0; 2921 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2922 mpll_param->yclk_sel = 2922 mpll_param->yclk_sel =
2923 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 2923 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2924 mpll_param->qdr = 2924 mpll_param->qdr =
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index f41594b2eeac..0b366169d64d 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -360,13 +360,13 @@ static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
360 struct radeon_bo *bo; 360 struct radeon_bo *bo;
361 int r; 361 int r;
362 362
363 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem); 363 r = radeon_vm_bo_update(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
364 if (r) { 364 if (r) {
365 return r; 365 return r;
366 } 366 }
367 list_for_each_entry(lobj, &parser->validated, tv.head) { 367 list_for_each_entry(lobj, &parser->validated, tv.head) {
368 bo = lobj->bo; 368 bo = lobj->bo;
369 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem); 369 r = radeon_vm_bo_update(parser->rdev, vm, bo, &bo->tbo.mem);
370 if (r) { 370 if (r) {
371 return r; 371 return r;
372 } 372 }
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 9f5ff28864f6..1958b36ad0e5 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -508,15 +508,6 @@ static const struct file_operations radeon_driver_kms_fops = {
508#endif 508#endif
509}; 509};
510 510
511
512static void
513radeon_pci_shutdown(struct pci_dev *pdev)
514{
515 struct drm_device *dev = pci_get_drvdata(pdev);
516
517 radeon_driver_unload_kms(dev);
518}
519
520static struct drm_driver kms_driver = { 511static struct drm_driver kms_driver = {
521 .driver_features = 512 .driver_features =
522 DRIVER_USE_AGP | 513 DRIVER_USE_AGP |
@@ -586,7 +577,6 @@ static struct pci_driver radeon_kms_pci_driver = {
586 .probe = radeon_pci_probe, 577 .probe = radeon_pci_probe,
587 .remove = radeon_pci_remove, 578 .remove = radeon_pci_remove,
588 .driver.pm = &radeon_pm_ops, 579 .driver.pm = &radeon_pm_ops,
589 .shutdown = radeon_pci_shutdown,
590}; 580};
591 581
592static int __init radeon_init(void) 582static int __init radeon_init(void)
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 543dcfae7e6f..00e0d449021c 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -108,9 +108,10 @@
108 * 1.31- Add support for num Z pipes from GET_PARAM 108 * 1.31- Add support for num Z pipes from GET_PARAM
109 * 1.32- fixes for rv740 setup 109 * 1.32- fixes for rv740 setup
110 * 1.33- Add r6xx/r7xx const buffer support 110 * 1.33- Add r6xx/r7xx const buffer support
111 * 1.34- fix evergreen/cayman GS register
111 */ 112 */
112#define DRIVER_MAJOR 1 113#define DRIVER_MAJOR 1
113#define DRIVER_MINOR 33 114#define DRIVER_MINOR 34
114#define DRIVER_PATCHLEVEL 0 115#define DRIVER_PATCHLEVEL 0
115 116
116long radeon_drm_ioctl(struct file *filp, 117long radeon_drm_ioctl(struct file *filp,
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index 3044e504f4ec..96e440061bdb 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -29,6 +29,7 @@
29#include <drm/radeon_drm.h> 29#include <drm/radeon_drm.h>
30#include "radeon.h" 30#include "radeon.h"
31#include "radeon_reg.h" 31#include "radeon_reg.h"
32#include "radeon_trace.h"
32 33
33/* 34/*
34 * GART 35 * GART
@@ -737,6 +738,7 @@ struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
737 for (i = 0; i < 2; ++i) { 738 for (i = 0; i < 2; ++i) {
738 if (choices[i]) { 739 if (choices[i]) {
739 vm->id = choices[i]; 740 vm->id = choices[i];
741 trace_radeon_vm_grab_id(vm->id, ring);
740 return rdev->vm_manager.active[choices[i]]; 742 return rdev->vm_manager.active[choices[i]];
741 } 743 }
742 } 744 }
@@ -1116,7 +1118,7 @@ static void radeon_vm_update_ptes(struct radeon_device *rdev,
1116} 1118}
1117 1119
1118/** 1120/**
1119 * radeon_vm_bo_update_pte - map a bo into the vm page table 1121 * radeon_vm_bo_update - map a bo into the vm page table
1120 * 1122 *
1121 * @rdev: radeon_device pointer 1123 * @rdev: radeon_device pointer
1122 * @vm: requested vm 1124 * @vm: requested vm
@@ -1128,10 +1130,10 @@ static void radeon_vm_update_ptes(struct radeon_device *rdev,
1128 * 1130 *
1129 * Object have to be reserved & global and local mutex must be locked! 1131 * Object have to be reserved & global and local mutex must be locked!
1130 */ 1132 */
1131int radeon_vm_bo_update_pte(struct radeon_device *rdev, 1133int radeon_vm_bo_update(struct radeon_device *rdev,
1132 struct radeon_vm *vm, 1134 struct radeon_vm *vm,
1133 struct radeon_bo *bo, 1135 struct radeon_bo *bo,
1134 struct ttm_mem_reg *mem) 1136 struct ttm_mem_reg *mem)
1135{ 1137{
1136 struct radeon_ib ib; 1138 struct radeon_ib ib;
1137 struct radeon_bo_va *bo_va; 1139 struct radeon_bo_va *bo_va;
@@ -1176,6 +1178,8 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1176 bo_va->valid = false; 1178 bo_va->valid = false;
1177 } 1179 }
1178 1180
1181 trace_radeon_vm_bo_update(bo_va);
1182
1179 nptes = radeon_bo_ngpu_pages(bo); 1183 nptes = radeon_bo_ngpu_pages(bo);
1180 1184
1181 /* assume two extra pdes in case the mapping overlaps the borders */ 1185 /* assume two extra pdes in case the mapping overlaps the borders */
@@ -1257,7 +1261,7 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev,
1257 mutex_lock(&rdev->vm_manager.lock); 1261 mutex_lock(&rdev->vm_manager.lock);
1258 mutex_lock(&bo_va->vm->mutex); 1262 mutex_lock(&bo_va->vm->mutex);
1259 if (bo_va->soffset) { 1263 if (bo_va->soffset) {
1260 r = radeon_vm_bo_update_pte(rdev, bo_va->vm, bo_va->bo, NULL); 1264 r = radeon_vm_bo_update(rdev, bo_va->vm, bo_va->bo, NULL);
1261 } 1265 }
1262 mutex_unlock(&rdev->vm_manager.lock); 1266 mutex_unlock(&rdev->vm_manager.lock);
1263 list_del(&bo_va->vm_list); 1267 list_del(&bo_va->vm_list);
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index d1385ccc672c..984097b907ef 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -537,8 +537,7 @@ static ssize_t radeon_hwmon_show_temp(struct device *dev,
537 struct device_attribute *attr, 537 struct device_attribute *attr,
538 char *buf) 538 char *buf)
539{ 539{
540 struct drm_device *ddev = dev_get_drvdata(dev); 540 struct radeon_device *rdev = dev_get_drvdata(dev);
541 struct radeon_device *rdev = ddev->dev_private;
542 int temp; 541 int temp;
543 542
544 if (rdev->asic->pm.get_temperature) 543 if (rdev->asic->pm.get_temperature)
@@ -553,8 +552,7 @@ static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
553 struct device_attribute *attr, 552 struct device_attribute *attr,
554 char *buf) 553 char *buf)
555{ 554{
556 struct drm_device *ddev = dev_get_drvdata(dev); 555 struct radeon_device *rdev = dev_get_drvdata(dev);
557 struct radeon_device *rdev = ddev->dev_private;
558 int hyst = to_sensor_dev_attr(attr)->index; 556 int hyst = to_sensor_dev_attr(attr)->index;
559 int temp; 557 int temp;
560 558
@@ -566,23 +564,14 @@ static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
566 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 564 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
567} 565}
568 566
569static ssize_t radeon_hwmon_show_name(struct device *dev,
570 struct device_attribute *attr,
571 char *buf)
572{
573 return sprintf(buf, "radeon\n");
574}
575
576static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 567static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
577static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0); 568static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
578static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1); 569static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
579static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
580 570
581static struct attribute *hwmon_attributes[] = { 571static struct attribute *hwmon_attributes[] = {
582 &sensor_dev_attr_temp1_input.dev_attr.attr, 572 &sensor_dev_attr_temp1_input.dev_attr.attr,
583 &sensor_dev_attr_temp1_crit.dev_attr.attr, 573 &sensor_dev_attr_temp1_crit.dev_attr.attr,
584 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 574 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
585 &sensor_dev_attr_name.dev_attr.attr,
586 NULL 575 NULL
587}; 576};
588 577
@@ -590,8 +579,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
590 struct attribute *attr, int index) 579 struct attribute *attr, int index)
591{ 580{
592 struct device *dev = container_of(kobj, struct device, kobj); 581 struct device *dev = container_of(kobj, struct device, kobj);
593 struct drm_device *ddev = dev_get_drvdata(dev); 582 struct radeon_device *rdev = dev_get_drvdata(dev);
594 struct radeon_device *rdev = ddev->dev_private;
595 583
596 /* Skip limit attributes if DPM is not enabled */ 584 /* Skip limit attributes if DPM is not enabled */
597 if (rdev->pm.pm_method != PM_METHOD_DPM && 585 if (rdev->pm.pm_method != PM_METHOD_DPM &&
@@ -607,11 +595,15 @@ static const struct attribute_group hwmon_attrgroup = {
607 .is_visible = hwmon_attributes_visible, 595 .is_visible = hwmon_attributes_visible,
608}; 596};
609 597
598static const struct attribute_group *hwmon_groups[] = {
599 &hwmon_attrgroup,
600 NULL
601};
602
610static int radeon_hwmon_init(struct radeon_device *rdev) 603static int radeon_hwmon_init(struct radeon_device *rdev)
611{ 604{
612 int err = 0; 605 int err = 0;
613 606 struct device *hwmon_dev;
614 rdev->pm.int_hwmon_dev = NULL;
615 607
616 switch (rdev->pm.int_thermal_type) { 608 switch (rdev->pm.int_thermal_type) {
617 case THERMAL_TYPE_RV6XX: 609 case THERMAL_TYPE_RV6XX:
@@ -624,20 +616,13 @@ static int radeon_hwmon_init(struct radeon_device *rdev)
624 case THERMAL_TYPE_KV: 616 case THERMAL_TYPE_KV:
625 if (rdev->asic->pm.get_temperature == NULL) 617 if (rdev->asic->pm.get_temperature == NULL)
626 return err; 618 return err;
627 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev); 619 hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
628 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 620 "radeon", rdev,
629 err = PTR_ERR(rdev->pm.int_hwmon_dev); 621 hwmon_groups);
622 if (IS_ERR(hwmon_dev)) {
623 err = PTR_ERR(hwmon_dev);
630 dev_err(rdev->dev, 624 dev_err(rdev->dev,
631 "Unable to register hwmon device: %d\n", err); 625 "Unable to register hwmon device: %d\n", err);
632 break;
633 }
634 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
635 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
636 &hwmon_attrgroup);
637 if (err) {
638 dev_err(rdev->dev,
639 "Unable to create hwmon sysfs file: %d\n", err);
640 hwmon_device_unregister(rdev->dev);
641 } 626 }
642 break; 627 break;
643 default: 628 default:
@@ -647,14 +632,6 @@ static int radeon_hwmon_init(struct radeon_device *rdev)
647 return err; 632 return err;
648} 633}
649 634
650static void radeon_hwmon_fini(struct radeon_device *rdev)
651{
652 if (rdev->pm.int_hwmon_dev) {
653 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
654 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
655 }
656}
657
658static void radeon_dpm_thermal_work_handler(struct work_struct *work) 635static void radeon_dpm_thermal_work_handler(struct work_struct *work)
659{ 636{
660 struct radeon_device *rdev = 637 struct radeon_device *rdev =
@@ -1337,8 +1314,6 @@ static void radeon_pm_fini_old(struct radeon_device *rdev)
1337 1314
1338 if (rdev->pm.power_state) 1315 if (rdev->pm.power_state)
1339 kfree(rdev->pm.power_state); 1316 kfree(rdev->pm.power_state);
1340
1341 radeon_hwmon_fini(rdev);
1342} 1317}
1343 1318
1344static void radeon_pm_fini_dpm(struct radeon_device *rdev) 1319static void radeon_pm_fini_dpm(struct radeon_device *rdev)
@@ -1358,8 +1333,6 @@ static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1358 1333
1359 if (rdev->pm.power_state) 1334 if (rdev->pm.power_state)
1360 kfree(rdev->pm.power_state); 1335 kfree(rdev->pm.power_state);
1361
1362 radeon_hwmon_fini(rdev);
1363} 1336}
1364 1337
1365void radeon_pm_fini(struct radeon_device *rdev) 1338void radeon_pm_fini(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/radeon_trace.h b/drivers/gpu/drm/radeon/radeon_trace.h
index 9f0e18172b6e..0473257d4078 100644
--- a/drivers/gpu/drm/radeon/radeon_trace.h
+++ b/drivers/gpu/drm/radeon/radeon_trace.h
@@ -47,6 +47,39 @@ TRACE_EVENT(radeon_cs,
47 __entry->fences) 47 __entry->fences)
48); 48);
49 49
50TRACE_EVENT(radeon_vm_grab_id,
51 TP_PROTO(unsigned vmid, int ring),
52 TP_ARGS(vmid, ring),
53 TP_STRUCT__entry(
54 __field(u32, vmid)
55 __field(u32, ring)
56 ),
57
58 TP_fast_assign(
59 __entry->vmid = vmid;
60 __entry->ring = ring;
61 ),
62 TP_printk("vmid=%u, ring=%u", __entry->vmid, __entry->ring)
63);
64
65TRACE_EVENT(radeon_vm_bo_update,
66 TP_PROTO(struct radeon_bo_va *bo_va),
67 TP_ARGS(bo_va),
68 TP_STRUCT__entry(
69 __field(u64, soffset)
70 __field(u64, eoffset)
71 __field(u32, flags)
72 ),
73
74 TP_fast_assign(
75 __entry->soffset = bo_va->soffset;
76 __entry->eoffset = bo_va->eoffset;
77 __entry->flags = bo_va->flags;
78 ),
79 TP_printk("soffs=%010llx, eoffs=%010llx, flags=%08x",
80 __entry->soffset, __entry->eoffset, __entry->flags)
81);
82
50TRACE_EVENT(radeon_vm_set_page, 83TRACE_EVENT(radeon_vm_set_page,
51 TP_PROTO(uint64_t pe, uint64_t addr, unsigned count, 84 TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
52 uint32_t incr, uint32_t flags), 85 uint32_t incr, uint32_t flags),
diff --git a/drivers/gpu/drm/radeon/reg_srcs/cayman b/drivers/gpu/drm/radeon/reg_srcs/cayman
index a072fa8c46b0..d46b58d078aa 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/cayman
+++ b/drivers/gpu/drm/radeon/reg_srcs/cayman
@@ -21,7 +21,7 @@ cayman 0x9400
210x000089AC VGT_COMPUTE_THREAD_GOURP_SIZE 210x000089AC VGT_COMPUTE_THREAD_GOURP_SIZE
220x000089B0 VGT_HS_OFFCHIP_PARAM 220x000089B0 VGT_HS_OFFCHIP_PARAM
230x00008A14 PA_CL_ENHANCE 230x00008A14 PA_CL_ENHANCE
240x00008A60 PA_SC_LINE_STIPPLE_VALUE 240x00008A60 PA_SU_LINE_STIPPLE_VALUE
250x00008B10 PA_SC_LINE_STIPPLE_STATE 250x00008B10 PA_SC_LINE_STIPPLE_STATE
260x00008BF0 PA_SC_ENHANCE 260x00008BF0 PA_SC_ENHANCE
270x00008D8C SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 270x00008D8C SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
@@ -532,7 +532,7 @@ cayman 0x9400
5320x00028B84 PA_SU_POLY_OFFSET_FRONT_OFFSET 5320x00028B84 PA_SU_POLY_OFFSET_FRONT_OFFSET
5330x00028B88 PA_SU_POLY_OFFSET_BACK_SCALE 5330x00028B88 PA_SU_POLY_OFFSET_BACK_SCALE
5340x00028B8C PA_SU_POLY_OFFSET_BACK_OFFSET 5340x00028B8C PA_SU_POLY_OFFSET_BACK_OFFSET
5350x00028B74 VGT_GS_INSTANCE_CNT 5350x00028B90 VGT_GS_INSTANCE_CNT
5360x00028BD4 PA_SC_CENTROID_PRIORITY_0 5360x00028BD4 PA_SC_CENTROID_PRIORITY_0
5370x00028BD8 PA_SC_CENTROID_PRIORITY_1 5370x00028BD8 PA_SC_CENTROID_PRIORITY_1
5380x00028BDC PA_SC_LINE_CNTL 5380x00028BDC PA_SC_LINE_CNTL
diff --git a/drivers/gpu/drm/radeon/reg_srcs/evergreen b/drivers/gpu/drm/radeon/reg_srcs/evergreen
index b912a37689bf..57745c8761c8 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/evergreen
+++ b/drivers/gpu/drm/radeon/reg_srcs/evergreen
@@ -22,7 +22,7 @@ evergreen 0x9400
220x000089A4 VGT_COMPUTE_START_Z 220x000089A4 VGT_COMPUTE_START_Z
230x000089AC VGT_COMPUTE_THREAD_GOURP_SIZE 230x000089AC VGT_COMPUTE_THREAD_GOURP_SIZE
240x00008A14 PA_CL_ENHANCE 240x00008A14 PA_CL_ENHANCE
250x00008A60 PA_SC_LINE_STIPPLE_VALUE 250x00008A60 PA_SU_LINE_STIPPLE_VALUE
260x00008B10 PA_SC_LINE_STIPPLE_STATE 260x00008B10 PA_SC_LINE_STIPPLE_STATE
270x00008BF0 PA_SC_ENHANCE 270x00008BF0 PA_SC_ENHANCE
280x00008D8C SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 280x00008D8C SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
@@ -545,7 +545,7 @@ evergreen 0x9400
5450x00028B84 PA_SU_POLY_OFFSET_FRONT_OFFSET 5450x00028B84 PA_SU_POLY_OFFSET_FRONT_OFFSET
5460x00028B88 PA_SU_POLY_OFFSET_BACK_SCALE 5460x00028B88 PA_SU_POLY_OFFSET_BACK_SCALE
5470x00028B8C PA_SU_POLY_OFFSET_BACK_OFFSET 5470x00028B8C PA_SU_POLY_OFFSET_BACK_OFFSET
5480x00028B74 VGT_GS_INSTANCE_CNT 5480x00028B90 VGT_GS_INSTANCE_CNT
5490x00028C00 PA_SC_LINE_CNTL 5490x00028C00 PA_SC_LINE_CNTL
5500x00028C08 PA_SU_VTX_CNTL 5500x00028C08 PA_SU_VTX_CNTL
5510x00028C0C PA_CL_GB_VERT_CLIP_ADJ 5510x00028C0C PA_CL_GB_VERT_CLIP_ADJ
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 1c560629575a..e7dab069cccf 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -162,6 +162,16 @@ static void rs690_mc_init(struct radeon_device *rdev)
162 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 162 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
163 base = G_000100_MC_FB_START(base) << 16; 163 base = G_000100_MC_FB_START(base) << 16;
164 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 164 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
165 /* Some boards seem to be configured for 128MB of sideport memory,
166 * but really only have 64MB. Just skip the sideport and use
167 * UMA memory.
168 */
169 if (rdev->mc.igp_sideport_enabled &&
170 (rdev->mc.real_vram_size == (384 * 1024 * 1024))) {
171 base += 128 * 1024 * 1024;
172 rdev->mc.real_vram_size -= 128 * 1024 * 1024;
173 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
174 }
165 175
166 /* Use K8 direct mapping for fast fb access. */ 176 /* Use K8 direct mapping for fast fb access. */
167 rdev->fastfb_working = false; 177 rdev->fastfb_working = false;
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
index 913b025ae9b3..374499db20c7 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -2328,6 +2328,12 @@ void rv770_get_engine_memory_ss(struct radeon_device *rdev)
2328 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss, 2328 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2329 ASIC_INTERNAL_MEMORY_SS, 0); 2329 ASIC_INTERNAL_MEMORY_SS, 0);
2330 2330
2331 /* disable ss, causes hangs on some cayman boards */
2332 if (rdev->family == CHIP_CAYMAN) {
2333 pi->sclk_ss = false;
2334 pi->mclk_ss = false;
2335 }
2336
2331 if (pi->sclk_ss || pi->mclk_ss) 2337 if (pi->sclk_ss || pi->mclk_ss)
2332 pi->dynamic_ss = true; 2338 pi->dynamic_ss = true;
2333 else 2339 else
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 6a64ccaa0695..a36736dab5e0 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3882,8 +3882,15 @@ static int si_mc_init(struct radeon_device *rdev)
3882 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 3882 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
3883 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 3883 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3884 /* size in MB on si */ 3884 /* size in MB on si */
3885 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; 3885 tmp = RREG32(CONFIG_MEMSIZE);
3886 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; 3886 /* some boards may have garbage in the upper 16 bits */
3887 if (tmp & 0xffff0000) {
3888 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
3889 if (tmp & 0xffff)
3890 tmp &= 0xffff;
3891 }
3892 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL;
3893 rdev->mc.real_vram_size = rdev->mc.mc_vram_size;
3887 rdev->mc.visible_vram_size = rdev->mc.aper_size; 3894 rdev->mc.visible_vram_size = rdev->mc.aper_size;
3888 si_vram_gtt_location(rdev, &rdev->mc); 3895 si_vram_gtt_location(rdev, &rdev->mc);
3889 radeon_update_bandwidth_info(rdev); 3896 radeon_update_bandwidth_info(rdev);
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 28e178137718..07eba596d458 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -135,11 +135,11 @@ int tegra_drm_submit(struct tegra_drm_context *context,
135 unsigned int num_relocs = args->num_relocs; 135 unsigned int num_relocs = args->num_relocs;
136 unsigned int num_waitchks = args->num_waitchks; 136 unsigned int num_waitchks = args->num_waitchks;
137 struct drm_tegra_cmdbuf __user *cmdbufs = 137 struct drm_tegra_cmdbuf __user *cmdbufs =
138 (void * __user)(uintptr_t)args->cmdbufs; 138 (void __user *)(uintptr_t)args->cmdbufs;
139 struct drm_tegra_reloc __user *relocs = 139 struct drm_tegra_reloc __user *relocs =
140 (void * __user)(uintptr_t)args->relocs; 140 (void __user *)(uintptr_t)args->relocs;
141 struct drm_tegra_waitchk __user *waitchks = 141 struct drm_tegra_waitchk __user *waitchks =
142 (void * __user)(uintptr_t)args->waitchks; 142 (void __user *)(uintptr_t)args->waitchks;
143 struct drm_tegra_syncpt syncpt; 143 struct drm_tegra_syncpt syncpt;
144 struct host1x_job *job; 144 struct host1x_job *job;
145 int err; 145 int err;
@@ -163,9 +163,10 @@ int tegra_drm_submit(struct tegra_drm_context *context,
163 struct drm_tegra_cmdbuf cmdbuf; 163 struct drm_tegra_cmdbuf cmdbuf;
164 struct host1x_bo *bo; 164 struct host1x_bo *bo;
165 165
166 err = copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf)); 166 if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
167 if (err) 167 err = -EFAULT;
168 goto fail; 168 goto fail;
169 }
169 170
170 bo = host1x_bo_lookup(drm, file, cmdbuf.handle); 171 bo = host1x_bo_lookup(drm, file, cmdbuf.handle);
171 if (!bo) { 172 if (!bo) {
@@ -178,10 +179,11 @@ int tegra_drm_submit(struct tegra_drm_context *context,
178 cmdbufs++; 179 cmdbufs++;
179 } 180 }
180 181
181 err = copy_from_user(job->relocarray, relocs, 182 if (copy_from_user(job->relocarray, relocs,
182 sizeof(*relocs) * num_relocs); 183 sizeof(*relocs) * num_relocs)) {
183 if (err) 184 err = -EFAULT;
184 goto fail; 185 goto fail;
186 }
185 187
186 while (num_relocs--) { 188 while (num_relocs--) {
187 struct host1x_reloc *reloc = &job->relocarray[num_relocs]; 189 struct host1x_reloc *reloc = &job->relocarray[num_relocs];
@@ -199,15 +201,17 @@ int tegra_drm_submit(struct tegra_drm_context *context,
199 } 201 }
200 } 202 }
201 203
202 err = copy_from_user(job->waitchk, waitchks, 204 if (copy_from_user(job->waitchk, waitchks,
203 sizeof(*waitchks) * num_waitchks); 205 sizeof(*waitchks) * num_waitchks)) {
204 if (err) 206 err = -EFAULT;
205 goto fail; 207 goto fail;
208 }
206 209
207 err = copy_from_user(&syncpt, (void * __user)(uintptr_t)args->syncpts, 210 if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts,
208 sizeof(syncpt)); 211 sizeof(syncpt))) {
209 if (err) 212 err = -EFAULT;
210 goto fail; 213 goto fail;
214 }
211 215
212 job->is_addr_reg = context->client->ops->is_addr_reg; 216 job->is_addr_reg = context->client->ops->is_addr_reg;
213 job->syncpt_incrs = syncpt.incrs; 217 job->syncpt_incrs = syncpt.incrs;
@@ -573,7 +577,7 @@ static void tegra_debugfs_cleanup(struct drm_minor *minor)
573} 577}
574#endif 578#endif
575 579
576struct drm_driver tegra_drm_driver = { 580static struct drm_driver tegra_drm_driver = {
577 .driver_features = DRIVER_MODESET | DRIVER_GEM, 581 .driver_features = DRIVER_MODESET | DRIVER_GEM,
578 .load = tegra_drm_load, 582 .load = tegra_drm_load,
579 .unload = tegra_drm_unload, 583 .unload = tegra_drm_unload,
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index fdfe259ed7f8..7da0b923131f 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -116,7 +116,7 @@ host1x_client_to_dc(struct host1x_client *client)
116 116
117static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) 117static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc)
118{ 118{
119 return container_of(crtc, struct tegra_dc, base); 119 return crtc ? container_of(crtc, struct tegra_dc, base) : NULL;
120} 120}
121 121
122static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long value, 122static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long value,
diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c
index 490f7719e317..a3835e7de184 100644
--- a/drivers/gpu/drm/tegra/fb.c
+++ b/drivers/gpu/drm/tegra/fb.c
@@ -247,7 +247,7 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper,
247 info->var.yoffset * fb->pitches[0]; 247 info->var.yoffset * fb->pitches[0];
248 248
249 drm->mode_config.fb_base = (resource_size_t)bo->paddr; 249 drm->mode_config.fb_base = (resource_size_t)bo->paddr;
250 info->screen_base = bo->vaddr + offset; 250 info->screen_base = (void __iomem *)bo->vaddr + offset;
251 info->screen_size = size; 251 info->screen_size = size;
252 info->fix.smem_start = (unsigned long)(bo->paddr + offset); 252 info->fix.smem_start = (unsigned long)(bo->paddr + offset);
253 info->fix.smem_len = size; 253 info->fix.smem_len = size;
diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c
index ba47ca4fb880..3b29018913a5 100644
--- a/drivers/gpu/drm/tegra/rgb.c
+++ b/drivers/gpu/drm/tegra/rgb.c
@@ -14,6 +14,8 @@
14 14
15struct tegra_rgb { 15struct tegra_rgb {
16 struct tegra_output output; 16 struct tegra_output output;
17 struct tegra_dc *dc;
18
17 struct clk *clk_parent; 19 struct clk *clk_parent;
18 struct clk *clk; 20 struct clk *clk;
19}; 21};
@@ -84,18 +86,18 @@ static void tegra_dc_write_regs(struct tegra_dc *dc,
84 86
85static int tegra_output_rgb_enable(struct tegra_output *output) 87static int tegra_output_rgb_enable(struct tegra_output *output)
86{ 88{
87 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 89 struct tegra_rgb *rgb = to_rgb(output);
88 90
89 tegra_dc_write_regs(dc, rgb_enable, ARRAY_SIZE(rgb_enable)); 91 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
90 92
91 return 0; 93 return 0;
92} 94}
93 95
94static int tegra_output_rgb_disable(struct tegra_output *output) 96static int tegra_output_rgb_disable(struct tegra_output *output)
95{ 97{
96 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 98 struct tegra_rgb *rgb = to_rgb(output);
97 99
98 tegra_dc_write_regs(dc, rgb_disable, ARRAY_SIZE(rgb_disable)); 100 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
99 101
100 return 0; 102 return 0;
101} 103}
@@ -146,6 +148,7 @@ int tegra_dc_rgb_probe(struct tegra_dc *dc)
146 148
147 rgb->output.dev = dc->dev; 149 rgb->output.dev = dc->dev;
148 rgb->output.of_node = np; 150 rgb->output.of_node = np;
151 rgb->dc = dc;
149 152
150 err = tegra_output_probe(&rgb->output); 153 err = tegra_output_probe(&rgb->output);
151 if (err < 0) 154 if (err < 0)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 15b86a94949d..406152152315 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -353,7 +353,8 @@ int ttm_bo_move_memcpy(struct ttm_buffer_object *bo,
353 * Don't move nonexistent data. Clear destination instead. 353 * Don't move nonexistent data. Clear destination instead.
354 */ 354 */
355 if (old_iomap == NULL && 355 if (old_iomap == NULL &&
356 (ttm == NULL || ttm->state == tt_unpopulated)) { 356 (ttm == NULL || (ttm->state == tt_unpopulated &&
357 !(ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)))) {
357 memset_io(new_iomap, 0, new_mem->num_pages*PAGE_SIZE); 358 memset_io(new_iomap, 0, new_mem->num_pages*PAGE_SIZE);
358 goto out2; 359 goto out2;
359 } 360 }
diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
index b249ab9b1eb2..6440eeac22d2 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
@@ -169,9 +169,9 @@ static int ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
169 } 169 }
170 170
171 page_offset = ((address - vma->vm_start) >> PAGE_SHIFT) + 171 page_offset = ((address - vma->vm_start) >> PAGE_SHIFT) +
172 drm_vma_node_start(&bo->vma_node) - vma->vm_pgoff; 172 vma->vm_pgoff - drm_vma_node_start(&bo->vma_node);
173 page_last = vma_pages(vma) + 173 page_last = vma_pages(vma) + vma->vm_pgoff -
174 drm_vma_node_start(&bo->vma_node) - vma->vm_pgoff; 174 drm_vma_node_start(&bo->vma_node);
175 175
176 if (unlikely(page_offset >= bo->num_pages)) { 176 if (unlikely(page_offset >= bo->num_pages)) {
177 retval = VM_FAULT_SIGBUS; 177 retval = VM_FAULT_SIGBUS;
diff --git a/drivers/gpu/drm/udl/udl_gem.c b/drivers/gpu/drm/udl/udl_gem.c
index 24ffbe990736..8d67b943ac05 100644
--- a/drivers/gpu/drm/udl/udl_gem.c
+++ b/drivers/gpu/drm/udl/udl_gem.c
@@ -125,6 +125,12 @@ static int udl_gem_get_pages(struct udl_gem_object *obj, gfp_t gfpmask)
125 125
126static void udl_gem_put_pages(struct udl_gem_object *obj) 126static void udl_gem_put_pages(struct udl_gem_object *obj)
127{ 127{
128 if (obj->base.import_attach) {
129 drm_free_large(obj->pages);
130 obj->pages = NULL;
131 return;
132 }
133
128 drm_gem_put_pages(&obj->base, obj->pages, false, false); 134 drm_gem_put_pages(&obj->base, obj->pages, false, false);
129 obj->pages = NULL; 135 obj->pages = NULL;
130} 136}
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c
index 7776e6f0aef6..0489c6152482 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c
@@ -150,6 +150,8 @@ struct vmw_ttm_tt {
150 bool mapped; 150 bool mapped;
151}; 151};
152 152
153const size_t vmw_tt_size = sizeof(struct vmw_ttm_tt);
154
153/** 155/**
154 * Helper functions to advance a struct vmw_piter iterator. 156 * Helper functions to advance a struct vmw_piter iterator.
155 * 157 *
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index db85985c7086..20890ad8408b 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -615,6 +615,7 @@ extern int vmw_mmap(struct file *filp, struct vm_area_struct *vma);
615 * TTM buffer object driver - vmwgfx_buffer.c 615 * TTM buffer object driver - vmwgfx_buffer.c
616 */ 616 */
617 617
618extern const size_t vmw_tt_size;
618extern struct ttm_placement vmw_vram_placement; 619extern struct ttm_placement vmw_vram_placement;
619extern struct ttm_placement vmw_vram_ne_placement; 620extern struct ttm_placement vmw_vram_ne_placement;
620extern struct ttm_placement vmw_vram_sys_placement; 621extern struct ttm_placement vmw_vram_sys_placement;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
index a51f48e3e917..45d5b5ab6ca9 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
@@ -68,6 +68,9 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
68 SVGA_FIFO_3D_HWVERSION)); 68 SVGA_FIFO_3D_HWVERSION));
69 break; 69 break;
70 } 70 }
71 case DRM_VMW_PARAM_MAX_SURF_MEMORY:
72 param->value = dev_priv->memory_size;
73 break;
71 default: 74 default:
72 DRM_ERROR("Illegal vmwgfx get param request: %d\n", 75 DRM_ERROR("Illegal vmwgfx get param request: %d\n",
73 param->param); 76 param->param);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index ecb3d867b426..03f1c2038631 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -75,6 +75,7 @@ void vmw_display_unit_cleanup(struct vmw_display_unit *du)
75 vmw_surface_unreference(&du->cursor_surface); 75 vmw_surface_unreference(&du->cursor_surface);
76 if (du->cursor_dmabuf) 76 if (du->cursor_dmabuf)
77 vmw_dmabuf_unreference(&du->cursor_dmabuf); 77 vmw_dmabuf_unreference(&du->cursor_dmabuf);
78 drm_sysfs_connector_remove(&du->connector);
78 drm_crtc_cleanup(&du->crtc); 79 drm_crtc_cleanup(&du->crtc);
79 drm_encoder_cleanup(&du->encoder); 80 drm_encoder_cleanup(&du->encoder);
80 drm_connector_cleanup(&du->connector); 81 drm_connector_cleanup(&du->connector);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
index 79f7e8e60529..a055a26819c2 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
@@ -260,6 +260,7 @@ static int vmw_ldu_crtc_set_config(struct drm_mode_set *set)
260 connector->encoder = NULL; 260 connector->encoder = NULL;
261 encoder->crtc = NULL; 261 encoder->crtc = NULL;
262 crtc->fb = NULL; 262 crtc->fb = NULL;
263 crtc->enabled = false;
263 264
264 vmw_ldu_del_active(dev_priv, ldu); 265 vmw_ldu_del_active(dev_priv, ldu);
265 266
@@ -285,6 +286,7 @@ static int vmw_ldu_crtc_set_config(struct drm_mode_set *set)
285 crtc->x = set->x; 286 crtc->x = set->x;
286 crtc->y = set->y; 287 crtc->y = set->y;
287 crtc->mode = *mode; 288 crtc->mode = *mode;
289 crtc->enabled = true;
288 290
289 vmw_ldu_add_active(dev_priv, ldu, vfb); 291 vmw_ldu_add_active(dev_priv, ldu, vfb);
290 292
@@ -369,6 +371,8 @@ static int vmw_ldu_init(struct vmw_private *dev_priv, unsigned unit)
369 encoder->possible_crtcs = (1 << unit); 371 encoder->possible_crtcs = (1 << unit);
370 encoder->possible_clones = 0; 372 encoder->possible_clones = 0;
371 373
374 (void) drm_sysfs_connector_add(connector);
375
372 drm_crtc_init(dev, crtc, &vmw_legacy_crtc_funcs); 376 drm_crtc_init(dev, crtc, &vmw_legacy_crtc_funcs);
373 377
374 drm_mode_crtc_set_gamma_size(crtc, 256); 378 drm_mode_crtc_set_gamma_size(crtc, 256);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index efe2b74c5eb1..9b5ea2ac7ddf 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
@@ -352,6 +352,38 @@ int vmw_user_lookup_handle(struct vmw_private *dev_priv,
352/** 352/**
353 * Buffer management. 353 * Buffer management.
354 */ 354 */
355
356/**
357 * vmw_dmabuf_acc_size - Calculate the pinned memory usage of buffers
358 *
359 * @dev_priv: Pointer to a struct vmw_private identifying the device.
360 * @size: The requested buffer size.
361 * @user: Whether this is an ordinary dma buffer or a user dma buffer.
362 */
363static size_t vmw_dmabuf_acc_size(struct vmw_private *dev_priv, size_t size,
364 bool user)
365{
366 static size_t struct_size, user_struct_size;
367 size_t num_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
368 size_t page_array_size = ttm_round_pot(num_pages * sizeof(void *));
369
370 if (unlikely(struct_size == 0)) {
371 size_t backend_size = ttm_round_pot(vmw_tt_size);
372
373 struct_size = backend_size +
374 ttm_round_pot(sizeof(struct vmw_dma_buffer));
375 user_struct_size = backend_size +
376 ttm_round_pot(sizeof(struct vmw_user_dma_buffer));
377 }
378
379 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
380 page_array_size +=
381 ttm_round_pot(num_pages * sizeof(dma_addr_t));
382
383 return ((user) ? user_struct_size : struct_size) +
384 page_array_size;
385}
386
355void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo) 387void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo)
356{ 388{
357 struct vmw_dma_buffer *vmw_bo = vmw_dma_buffer(bo); 389 struct vmw_dma_buffer *vmw_bo = vmw_dma_buffer(bo);
@@ -359,6 +391,13 @@ void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo)
359 kfree(vmw_bo); 391 kfree(vmw_bo);
360} 392}
361 393
394static void vmw_user_dmabuf_destroy(struct ttm_buffer_object *bo)
395{
396 struct vmw_user_dma_buffer *vmw_user_bo = vmw_user_dma_buffer(bo);
397
398 ttm_prime_object_kfree(vmw_user_bo, prime);
399}
400
362int vmw_dmabuf_init(struct vmw_private *dev_priv, 401int vmw_dmabuf_init(struct vmw_private *dev_priv,
363 struct vmw_dma_buffer *vmw_bo, 402 struct vmw_dma_buffer *vmw_bo,
364 size_t size, struct ttm_placement *placement, 403 size_t size, struct ttm_placement *placement,
@@ -368,28 +407,23 @@ int vmw_dmabuf_init(struct vmw_private *dev_priv,
368 struct ttm_bo_device *bdev = &dev_priv->bdev; 407 struct ttm_bo_device *bdev = &dev_priv->bdev;
369 size_t acc_size; 408 size_t acc_size;
370 int ret; 409 int ret;
410 bool user = (bo_free == &vmw_user_dmabuf_destroy);
371 411
372 BUG_ON(!bo_free); 412 BUG_ON(!bo_free && (!user && (bo_free != vmw_dmabuf_bo_free)));
373 413
374 acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct vmw_dma_buffer)); 414 acc_size = vmw_dmabuf_acc_size(dev_priv, size, user);
375 memset(vmw_bo, 0, sizeof(*vmw_bo)); 415 memset(vmw_bo, 0, sizeof(*vmw_bo));
376 416
377 INIT_LIST_HEAD(&vmw_bo->res_list); 417 INIT_LIST_HEAD(&vmw_bo->res_list);
378 418
379 ret = ttm_bo_init(bdev, &vmw_bo->base, size, 419 ret = ttm_bo_init(bdev, &vmw_bo->base, size,
380 ttm_bo_type_device, placement, 420 (user) ? ttm_bo_type_device :
421 ttm_bo_type_kernel, placement,
381 0, interruptible, 422 0, interruptible,
382 NULL, acc_size, NULL, bo_free); 423 NULL, acc_size, NULL, bo_free);
383 return ret; 424 return ret;
384} 425}
385 426
386static void vmw_user_dmabuf_destroy(struct ttm_buffer_object *bo)
387{
388 struct vmw_user_dma_buffer *vmw_user_bo = vmw_user_dma_buffer(bo);
389
390 ttm_prime_object_kfree(vmw_user_bo, prime);
391}
392
393static void vmw_user_dmabuf_release(struct ttm_base_object **p_base) 427static void vmw_user_dmabuf_release(struct ttm_base_object **p_base)
394{ 428{
395 struct vmw_user_dma_buffer *vmw_user_bo; 429 struct vmw_user_dma_buffer *vmw_user_bo;
@@ -781,54 +815,55 @@ err_ref:
781} 815}
782 816
783 817
818/**
819 * vmw_dumb_create - Create a dumb kms buffer
820 *
821 * @file_priv: Pointer to a struct drm_file identifying the caller.
822 * @dev: Pointer to the drm device.
823 * @args: Pointer to a struct drm_mode_create_dumb structure
824 *
825 * This is a driver callback for the core drm create_dumb functionality.
826 * Note that this is very similar to the vmw_dmabuf_alloc ioctl, except
827 * that the arguments have a different format.
828 */
784int vmw_dumb_create(struct drm_file *file_priv, 829int vmw_dumb_create(struct drm_file *file_priv,
785 struct drm_device *dev, 830 struct drm_device *dev,
786 struct drm_mode_create_dumb *args) 831 struct drm_mode_create_dumb *args)
787{ 832{
788 struct vmw_private *dev_priv = vmw_priv(dev); 833 struct vmw_private *dev_priv = vmw_priv(dev);
789 struct vmw_master *vmaster = vmw_master(file_priv->master); 834 struct vmw_master *vmaster = vmw_master(file_priv->master);
790 struct vmw_user_dma_buffer *vmw_user_bo; 835 struct vmw_dma_buffer *dma_buf;
791 struct ttm_buffer_object *tmp;
792 int ret; 836 int ret;
793 837
794 args->pitch = args->width * ((args->bpp + 7) / 8); 838 args->pitch = args->width * ((args->bpp + 7) / 8);
795 args->size = args->pitch * args->height; 839 args->size = args->pitch * args->height;
796 840
797 vmw_user_bo = kzalloc(sizeof(*vmw_user_bo), GFP_KERNEL);
798 if (vmw_user_bo == NULL)
799 return -ENOMEM;
800
801 ret = ttm_read_lock(&vmaster->lock, true); 841 ret = ttm_read_lock(&vmaster->lock, true);
802 if (ret != 0) { 842 if (unlikely(ret != 0))
803 kfree(vmw_user_bo);
804 return ret; 843 return ret;
805 }
806 844
807 ret = vmw_dmabuf_init(dev_priv, &vmw_user_bo->dma, args->size, 845 ret = vmw_user_dmabuf_alloc(dev_priv, vmw_fpriv(file_priv)->tfile,
808 &vmw_vram_sys_placement, true, 846 args->size, false, &args->handle,
809 &vmw_user_dmabuf_destroy); 847 &dma_buf);
810 if (ret != 0)
811 goto out_no_dmabuf;
812
813 tmp = ttm_bo_reference(&vmw_user_bo->dma.base);
814 ret = ttm_prime_object_init(vmw_fpriv(file_priv)->tfile,
815 args->size,
816 &vmw_user_bo->prime,
817 false,
818 ttm_buffer_type,
819 &vmw_user_dmabuf_release, NULL);
820 if (unlikely(ret != 0)) 848 if (unlikely(ret != 0))
821 goto out_no_base_object; 849 goto out_no_dmabuf;
822
823 args->handle = vmw_user_bo->prime.base.hash.key;
824 850
825out_no_base_object: 851 vmw_dmabuf_unreference(&dma_buf);
826 ttm_bo_unref(&tmp);
827out_no_dmabuf: 852out_no_dmabuf:
828 ttm_read_unlock(&vmaster->lock); 853 ttm_read_unlock(&vmaster->lock);
829 return ret; 854 return ret;
830} 855}
831 856
857/**
858 * vmw_dumb_map_offset - Return the address space offset of a dumb buffer
859 *
860 * @file_priv: Pointer to a struct drm_file identifying the caller.
861 * @dev: Pointer to the drm device.
862 * @handle: Handle identifying the dumb buffer.
863 * @offset: The address space offset returned.
864 *
865 * This is a driver callback for the core drm dumb_map_offset functionality.
866 */
832int vmw_dumb_map_offset(struct drm_file *file_priv, 867int vmw_dumb_map_offset(struct drm_file *file_priv,
833 struct drm_device *dev, uint32_t handle, 868 struct drm_device *dev, uint32_t handle,
834 uint64_t *offset) 869 uint64_t *offset)
@@ -846,6 +881,15 @@ int vmw_dumb_map_offset(struct drm_file *file_priv,
846 return 0; 881 return 0;
847} 882}
848 883
884/**
885 * vmw_dumb_destroy - Destroy a dumb boffer
886 *
887 * @file_priv: Pointer to a struct drm_file identifying the caller.
888 * @dev: Pointer to the drm device.
889 * @handle: Handle identifying the dumb buffer.
890 *
891 * This is a driver callback for the core drm dumb_destroy functionality.
892 */
849int vmw_dumb_destroy(struct drm_file *file_priv, 893int vmw_dumb_destroy(struct drm_file *file_priv,
850 struct drm_device *dev, 894 struct drm_device *dev,
851 uint32_t handle) 895 uint32_t handle)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
index 26387c3d5a21..22406c8651ea 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
@@ -310,6 +310,7 @@ static int vmw_sou_crtc_set_config(struct drm_mode_set *set)
310 crtc->fb = NULL; 310 crtc->fb = NULL;
311 crtc->x = 0; 311 crtc->x = 0;
312 crtc->y = 0; 312 crtc->y = 0;
313 crtc->enabled = false;
313 314
314 vmw_sou_del_active(dev_priv, sou); 315 vmw_sou_del_active(dev_priv, sou);
315 316
@@ -370,6 +371,7 @@ static int vmw_sou_crtc_set_config(struct drm_mode_set *set)
370 crtc->fb = NULL; 371 crtc->fb = NULL;
371 crtc->x = 0; 372 crtc->x = 0;
372 crtc->y = 0; 373 crtc->y = 0;
374 crtc->enabled = false;
373 375
374 return ret; 376 return ret;
375 } 377 }
@@ -382,6 +384,7 @@ static int vmw_sou_crtc_set_config(struct drm_mode_set *set)
382 crtc->fb = fb; 384 crtc->fb = fb;
383 crtc->x = set->x; 385 crtc->x = set->x;
384 crtc->y = set->y; 386 crtc->y = set->y;
387 crtc->enabled = true;
385 388
386 return 0; 389 return 0;
387} 390}
@@ -464,6 +467,8 @@ static int vmw_sou_init(struct vmw_private *dev_priv, unsigned unit)
464 encoder->possible_crtcs = (1 << unit); 467 encoder->possible_crtcs = (1 << unit);
465 encoder->possible_clones = 0; 468 encoder->possible_clones = 0;
466 469
470 (void) drm_sysfs_connector_add(connector);
471
467 drm_crtc_init(dev, crtc, &vmw_screen_object_crtc_funcs); 472 drm_crtc_init(dev, crtc, &vmw_screen_object_crtc_funcs);
468 473
469 drm_mode_crtc_set_gamma_size(crtc, 256); 474 drm_mode_crtc_set_gamma_size(crtc, 256);
diff --git a/drivers/gpu/host1x/bus.c b/drivers/gpu/host1x/bus.c
index 509383f8be03..6a929591aa73 100644
--- a/drivers/gpu/host1x/bus.c
+++ b/drivers/gpu/host1x/bus.c
@@ -19,6 +19,7 @@
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/slab.h> 20#include <linux/slab.h>
21 21
22#include "bus.h"
22#include "dev.h" 23#include "dev.h"
23 24
24static DEFINE_MUTEX(clients_lock); 25static DEFINE_MUTEX(clients_lock);
@@ -257,7 +258,7 @@ static int host1x_unregister_client(struct host1x *host1x,
257 return -ENODEV; 258 return -ENODEV;
258} 259}
259 260
260struct bus_type host1x_bus_type = { 261static struct bus_type host1x_bus_type = {
261 .name = "host1x", 262 .name = "host1x",
262}; 263};
263 264
@@ -301,7 +302,7 @@ static int host1x_device_add(struct host1x *host1x,
301 device->dev.coherent_dma_mask = host1x->dev->coherent_dma_mask; 302 device->dev.coherent_dma_mask = host1x->dev->coherent_dma_mask;
302 device->dev.dma_mask = &device->dev.coherent_dma_mask; 303 device->dev.dma_mask = &device->dev.coherent_dma_mask;
303 device->dev.release = host1x_device_release; 304 device->dev.release = host1x_device_release;
304 dev_set_name(&device->dev, driver->name); 305 dev_set_name(&device->dev, "%s", driver->name);
305 device->dev.bus = &host1x_bus_type; 306 device->dev.bus = &host1x_bus_type;
306 device->dev.parent = host1x->dev; 307 device->dev.parent = host1x->dev;
307 308
diff --git a/drivers/gpu/host1x/hw/cdma_hw.c b/drivers/gpu/host1x/hw/cdma_hw.c
index 37e2a63241a9..6b09b71940c2 100644
--- a/drivers/gpu/host1x/hw/cdma_hw.c
+++ b/drivers/gpu/host1x/hw/cdma_hw.c
@@ -54,8 +54,8 @@ static void cdma_timeout_cpu_incr(struct host1x_cdma *cdma, u32 getptr,
54 u32 *p = (u32 *)((u32)pb->mapped + getptr); 54 u32 *p = (u32 *)((u32)pb->mapped + getptr);
55 *(p++) = HOST1X_OPCODE_NOP; 55 *(p++) = HOST1X_OPCODE_NOP;
56 *(p++) = HOST1X_OPCODE_NOP; 56 *(p++) = HOST1X_OPCODE_NOP;
57 dev_dbg(host1x->dev, "%s: NOP at 0x%x\n", __func__, 57 dev_dbg(host1x->dev, "%s: NOP at %#llx\n", __func__,
58 pb->phys + getptr); 58 (u64)pb->phys + getptr);
59 getptr = (getptr + 8) & (pb->size_bytes - 1); 59 getptr = (getptr + 8) & (pb->size_bytes - 1);
60 } 60 }
61 wmb(); 61 wmb();
diff --git a/drivers/gpu/host1x/hw/debug_hw.c b/drivers/gpu/host1x/hw/debug_hw.c
index 640c75ca5a8b..f72c873eff81 100644
--- a/drivers/gpu/host1x/hw/debug_hw.c
+++ b/drivers/gpu/host1x/hw/debug_hw.c
@@ -163,8 +163,8 @@ static void show_channel_gathers(struct output *o, struct host1x_cdma *cdma)
163 continue; 163 continue;
164 } 164 }
165 165
166 host1x_debug_output(o, " GATHER at %08x+%04x, %d words\n", 166 host1x_debug_output(o, " GATHER at %#llx+%04x, %d words\n",
167 g->base, g->offset, g->words); 167 (u64)g->base, g->offset, g->words);
168 168
169 show_gather(o, g->base + g->offset, g->words, cdma, 169 show_gather(o, g->base + g->offset, g->words, cdma,
170 g->base, mapped); 170 g->base, mapped);