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-rw-r--r--drivers/gpu/drm/nouveau/nvc0_vm.c24
1 files changed, 15 insertions, 9 deletions
diff --git a/drivers/gpu/drm/nouveau/nvc0_vm.c b/drivers/gpu/drm/nouveau/nvc0_vm.c
index 69af0ba7edd3..a0a2a0277f73 100644
--- a/drivers/gpu/drm/nouveau/nvc0_vm.c
+++ b/drivers/gpu/drm/nouveau/nvc0_vm.c
@@ -104,20 +104,26 @@ nvc0_vm_flush(struct nouveau_vm *vm)
104 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; 104 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
105 struct drm_device *dev = vm->dev; 105 struct drm_device *dev = vm->dev;
106 struct nouveau_vm_pgd *vpgd; 106 struct nouveau_vm_pgd *vpgd;
107 u32 r100c80, engine; 107 u32 engine = (dev_priv->chan_vm == vm) ? 1 : 5;
108 108
109 pinstmem->flush(vm->dev); 109 pinstmem->flush(vm->dev);
110 110
111 if (vm == dev_priv->chan_vm) 111 spin_lock(&dev_priv->ramin_lock);
112 engine = 1;
113 else
114 engine = 5;
115
116 list_for_each_entry(vpgd, &vm->pgd_list, head) { 112 list_for_each_entry(vpgd, &vm->pgd_list, head) {
117 r100c80 = nv_rd32(dev, 0x100c80); 113 /* looks like maybe a "free flush slots" counter, the
114 * faster you write to 0x100cbc to more it decreases
115 */
116 if (!nv_wait_ne(dev, 0x100c80, 0x00ff0000, 0x00000000)) {
117 NV_ERROR(dev, "vm timeout 0: 0x%08x %d\n",
118 nv_rd32(dev, 0x100c80), engine);
119 }
118 nv_wr32(dev, 0x100cb8, vpgd->obj->vinst >> 8); 120 nv_wr32(dev, 0x100cb8, vpgd->obj->vinst >> 8);
119 nv_wr32(dev, 0x100cbc, 0x80000000 | engine); 121 nv_wr32(dev, 0x100cbc, 0x80000000 | engine);
120 if (!nv_wait(dev, 0x100c80, 0xffffffff, r100c80)) 122 /* wait for flush to be queued? */
121 NV_ERROR(dev, "vm flush timeout eng %d\n", engine); 123 if (!nv_wait(dev, 0x100c80, 0x00008000, 0x00008000)) {
124 NV_ERROR(dev, "vm timeout 1: 0x%08x %d\n",
125 nv_rd32(dev, 0x100c80), engine);
126 }
122 } 127 }
128 spin_unlock(&dev_priv->ramin_lock);
123} 129}