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-rw-r--r--drivers/gpu/drm/i915/i915_irq.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3201986bf25e..54bf54706d1d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3458,12 +3458,13 @@ static void gen8_irq_reset(struct drm_device *dev)
3458void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) 3458void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3459{ 3459{
3460 unsigned long irqflags; 3460 unsigned long irqflags;
3461 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3461 3462
3462 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3463 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3463 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], 3464 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3464 ~dev_priv->de_irq_mask[PIPE_B]); 3465 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3465 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], 3466 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3466 ~dev_priv->de_irq_mask[PIPE_C]); 3467 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3467 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3468 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3468} 3469}
3469 3470