diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/radeon/r300_cmdbuf.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r300_reg.h | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_cp.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_drv.h | 1 |
4 files changed, 11 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c index 3efa633966e8..cb2e470f97d4 100644 --- a/drivers/gpu/drm/radeon/r300_cmdbuf.c +++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c | |||
@@ -207,6 +207,10 @@ void r300_init_reg_flags(struct drm_device *dev) | |||
207 | ADD_RANGE(0x42C0, 2); | 207 | ADD_RANGE(0x42C0, 2); |
208 | ADD_RANGE(R300_RS_CNTL_0, 2); | 208 | ADD_RANGE(R300_RS_CNTL_0, 2); |
209 | 209 | ||
210 | ADD_RANGE(R300_SU_REG_DEST, 1); | ||
211 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) | ||
212 | ADD_RANGE(RV530_FG_ZBREG_DEST, 1); | ||
213 | |||
210 | ADD_RANGE(R300_SC_HYPERZ, 2); | 214 | ADD_RANGE(R300_SC_HYPERZ, 2); |
211 | ADD_RANGE(0x43E8, 1); | 215 | ADD_RANGE(0x43E8, 1); |
212 | 216 | ||
@@ -232,6 +236,7 @@ void r300_init_reg_flags(struct drm_device *dev) | |||
232 | ADD_RANGE(R300_ZB_DEPTHPITCH, 1); | 236 | ADD_RANGE(R300_ZB_DEPTHPITCH, 1); |
233 | ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1); | 237 | ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1); |
234 | ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13); | 238 | ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13); |
239 | ADD_RANGE(R300_ZB_ZPASS_DATA, 2); /* ZB_ZPASS_DATA, ZB_ZPASS_ADDR */ | ||
235 | 240 | ||
236 | ADD_RANGE(R300_TX_FILTER_0, 16); | 241 | ADD_RANGE(R300_TX_FILTER_0, 16); |
237 | ADD_RANGE(R300_TX_FILTER1_0, 16); | 242 | ADD_RANGE(R300_TX_FILTER1_0, 16); |
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h index ee6f811599a3..bdbc95fa6721 100644 --- a/drivers/gpu/drm/radeon/r300_reg.h +++ b/drivers/gpu/drm/radeon/r300_reg.h | |||
@@ -1770,4 +1770,9 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. | |||
1770 | #define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0 | 1770 | #define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0 |
1771 | #define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8 | 1771 | #define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8 |
1772 | 1772 | ||
1773 | #define R300_SU_REG_DEST 0x42c8 | ||
1774 | #define RV530_FG_ZBREG_DEST 0x4be8 | ||
1775 | #define R300_ZB_ZPASS_DATA 0x4f58 | ||
1776 | #define R300_ZB_ZPASS_ADDR 0x4f5c | ||
1777 | |||
1773 | #endif /* _R300_REG_H */ | 1778 | #endif /* _R300_REG_H */ |
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c index 6f579a8e5349..77a7a4d84650 100644 --- a/drivers/gpu/drm/radeon/radeon_cp.c +++ b/drivers/gpu/drm/radeon/radeon_cp.c | |||
@@ -434,7 +434,7 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv) | |||
434 | 434 | ||
435 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { | 435 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { |
436 | RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); | 436 | RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); |
437 | RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); | 437 | RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); |
438 | } | 438 | } |
439 | RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); | 439 | RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); |
440 | radeon_do_wait_for_idle(dev_priv); | 440 | radeon_do_wait_for_idle(dev_priv); |
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index 7091aafff196..ed4d27e6ee6f 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h | |||
@@ -687,7 +687,6 @@ extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pciga | |||
687 | /* pipe config regs */ | 687 | /* pipe config regs */ |
688 | #define R400_GB_PIPE_SELECT 0x402c | 688 | #define R400_GB_PIPE_SELECT 0x402c |
689 | #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ | 689 | #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ |
690 | #define R500_SU_REG_DEST 0x42c8 | ||
691 | #define R300_GB_TILE_CONFIG 0x4018 | 690 | #define R300_GB_TILE_CONFIG 0x4018 |
692 | # define R300_ENABLE_TILING (1 << 0) | 691 | # define R300_ENABLE_TILING (1 << 0) |
693 | # define R300_PIPE_COUNT_RV350 (0 << 1) | 692 | # define R300_PIPE_COUNT_RV350 (0 << 1) |