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-rw-r--r--drivers/gpu/drm/i915/i915_dma.c4
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c1
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c13
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h6
5 files changed, 24 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 0ded483d9ac7..81f1cff56fd5 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1112,6 +1112,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1112 dev_priv->has_gem = 1; 1112 dev_priv->has_gem = 1;
1113#endif 1113#endif
1114 1114
1115 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1116 if (IS_GM45(dev))
1117 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1118
1115 i915_gem_load(dev); 1119 i915_gem_load(dev);
1116 1120
1117 /* Init HWS */ 1121 /* Init HWS */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f8b3df0926c0..aac12ee31a46 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -112,7 +112,6 @@ static struct drm_driver driver = {
112 .suspend = i915_suspend, 112 .suspend = i915_suspend,
113 .resume = i915_resume, 113 .resume = i915_resume,
114 .device_is_agp = i915_driver_device_is_agp, 114 .device_is_agp = i915_driver_device_is_agp,
115 .get_vblank_counter = i915_get_vblank_counter,
116 .enable_vblank = i915_enable_vblank, 115 .enable_vblank = i915_enable_vblank,
117 .disable_vblank = i915_disable_vblank, 116 .disable_vblank = i915_disable_vblank,
118 .irq_preinstall = i915_driver_irq_preinstall, 117 .irq_preinstall = i915_driver_irq_preinstall,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a70bf77290fc..7325363164f8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -535,6 +535,7 @@ extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
535extern int i915_enable_vblank(struct drm_device *dev, int crtc); 535extern int i915_enable_vblank(struct drm_device *dev, int crtc);
536extern void i915_disable_vblank(struct drm_device *dev, int crtc); 536extern void i915_disable_vblank(struct drm_device *dev, int crtc);
537extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 537extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
538extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
538extern int i915_vblank_swap(struct drm_device *dev, void *data, 539extern int i915_vblank_swap(struct drm_device *dev, void *data,
539 struct drm_file *file_priv); 540 struct drm_file *file_priv);
540extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); 541extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6290219de6c8..548ff2c66431 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -174,6 +174,19 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
174 return count; 174 return count;
175} 175}
176 176
177u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
178{
179 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
180 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
181
182 if (!i915_pipe_enabled(dev, pipe)) {
183 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
184 return 0;
185 }
186
187 return I915_READ(reg);
188}
189
177irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 190irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
178{ 191{
179 struct drm_device *dev = (struct drm_device *) arg; 192 struct drm_device *dev = (struct drm_device *) arg;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 928e00462570..9d6539a868b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1371,6 +1371,9 @@
1371#define PIPE_FRAME_LOW_SHIFT 24 1371#define PIPE_FRAME_LOW_SHIFT 24
1372#define PIPE_PIXEL_MASK 0x00ffffff 1372#define PIPE_PIXEL_MASK 0x00ffffff
1373#define PIPE_PIXEL_SHIFT 0 1373#define PIPE_PIXEL_SHIFT 0
1374/* GM45+ just has to be different */
1375#define PIPEA_FRMCOUNT_GM45 0x70040
1376#define PIPEA_FLIPCOUNT_GM45 0x70044
1374 1377
1375/* Cursor A & B regs */ 1378/* Cursor A & B regs */
1376#define CURACNTR 0x70080 1379#define CURACNTR 0x70080
@@ -1439,6 +1442,9 @@
1439#define PIPEBSTAT 0x71024 1442#define PIPEBSTAT 0x71024
1440#define PIPEBFRAMEHIGH 0x71040 1443#define PIPEBFRAMEHIGH 0x71040
1441#define PIPEBFRAMEPIXEL 0x71044 1444#define PIPEBFRAMEPIXEL 0x71044
1445#define PIPEB_FRMCOUNT_GM45 0x71040
1446#define PIPEB_FLIPCOUNT_GM45 0x71044
1447
1442 1448
1443/* Display B control */ 1449/* Display B control */
1444#define DSPBCNTR 0x71180 1450#define DSPBCNTR 0x71180