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-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 6b3f1e4a34a1..e8b85ac4ca04 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -96,7 +96,8 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
96 */ 96 */
97 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 97 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
98 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 98 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
99 } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) { 99 } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev) ||
100 IS_GM45(dev)) {
100 uint32_t dcc; 101 uint32_t dcc;
101 102
102 /* On 915-945 and GM965, channel interleave by the CPU is 103 /* On 915-945 and GM965, channel interleave by the CPU is
@@ -118,7 +119,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
118 dcc & DCC_CHANNEL_XOR_DISABLE) { 119 dcc & DCC_CHANNEL_XOR_DISABLE) {
119 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 120 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
120 swizzle_y = I915_BIT_6_SWIZZLE_9; 121 swizzle_y = I915_BIT_6_SWIZZLE_9;
121 } else if (IS_I965GM(dev)) { 122 } else if (IS_I965GM(dev) || IS_GM45(dev)) {
122 /* GM965 only does bit 11-based channel 123 /* GM965 only does bit 11-based channel
123 * randomization 124 * randomization
124 */ 125 */